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sata_mv: fix pci_enable_msi() error handling
[linux-2.6/mini2440.git] / drivers / net / smc91x.h
blobd2767e6584a98c320d1ac88ff1a830b5b4131149
1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
3 .
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
9 .
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
14 .
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
19 .
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 .
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
27 .
28 . Authors
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
32 .
33 ---------------------------------------------------------------------------*/
34 #ifndef _SMC91X_H_
35 #define _SMC91X_H_
36
37
38 /*
39 * Define your architecture specific bus configuration parameters here.
40 */
41
42 #if defined(CONFIG_ARCH_LUBBOCK)
43
44 /* We can only do 16-bit reads and writes in the static memory space. */
45 #define SMC_CAN_USE_8BIT 0
46 #define SMC_CAN_USE_16BIT 1
47 #define SMC_CAN_USE_32BIT 0
48 #define SMC_NOWAIT 1
49
50 /* The first two address lines aren't connected... */
51 #define SMC_IO_SHIFT 2
52
53 #define SMC_inw(a, r) readw((a) + (r))
54 #define SMC_outw(v, a, r) writew(v, (a) + (r))
55 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
56 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
57
58 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
59
60 /* We can only do 16-bit reads and writes in the static memory space. */
61 #define SMC_CAN_USE_8BIT 0
62 #define SMC_CAN_USE_16BIT 1
63 #define SMC_CAN_USE_32BIT 0
64 #define SMC_NOWAIT 1
65
66 #define SMC_IO_SHIFT 0
67
68 #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
69 #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
70 #define SMC_insw(a, r, p, l) \
71 do { \
72 unsigned long __port = (a) + (r); \
73 u16 *__p = (u16 *)(p); \
74 int __l = (l); \
75 insw(__port, __p, __l); \
76 while (__l > 0) { \
77 *__p = swab16(*__p); \
78 __p++; \
79 __l--; \
80 } \
81 } while (0)
82 #define SMC_outsw(a, r, p, l) \
83 do { \
84 unsigned long __port = (a) + (r); \
85 u16 *__p = (u16 *)(p); \
86 int __l = (l); \
87 while (__l > 0) { \
88 /* Believe it or not, the swab isn't needed. */ \
89 outw( /* swab16 */ (*__p++), __port); \
90 __l--; \
91 } \
92 } while (0)
93 #define SMC_IRQ_FLAGS (0)
94
95 #elif defined(CONFIG_SA1100_PLEB)
96 /* We can only do 16-bit reads and writes in the static memory space. */
97 #define SMC_CAN_USE_8BIT 1
98 #define SMC_CAN_USE_16BIT 1
99 #define SMC_CAN_USE_32BIT 0
100 #define SMC_IO_SHIFT 0
101 #define SMC_NOWAIT 1
102
103 #define SMC_inb(a, r) readb((a) + (r))
104 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
105 #define SMC_inw(a, r) readw((a) + (r))
106 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
107 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
108 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
109 #define SMC_outw(v, a, r) writew(v, (a) + (r))
110 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
111
112 #define SMC_IRQ_FLAGS (0)
113
114 #elif defined(CONFIG_SA1100_ASSABET)
115
116 #include <asm/arch/neponset.h>
117
118 /* We can only do 8-bit reads and writes in the static memory space. */
119 #define SMC_CAN_USE_8BIT 1
120 #define SMC_CAN_USE_16BIT 0
121 #define SMC_CAN_USE_32BIT 0
122 #define SMC_NOWAIT 1
123
124 /* The first two address lines aren't connected... */
125 #define SMC_IO_SHIFT 2
126
127 #define SMC_inb(a, r) readb((a) + (r))
128 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
129 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
130 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
131
132 #elif defined(CONFIG_MACH_LOGICPD_PXA270)
133
134 #define SMC_CAN_USE_8BIT 0
135 #define SMC_CAN_USE_16BIT 1
136 #define SMC_CAN_USE_32BIT 0
137 #define SMC_IO_SHIFT 0
138 #define SMC_NOWAIT 1
139
140 #define SMC_inw(a, r) readw((a) + (r))
141 #define SMC_outw(v, a, r) writew(v, (a) + (r))
142 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
143 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
144
145 #elif defined(CONFIG_ARCH_INNOKOM) || \
146 defined(CONFIG_MACH_MAINSTONE) || \
147 defined(CONFIG_ARCH_PXA_IDP) || \
148 defined(CONFIG_ARCH_RAMSES)
149
150 #define SMC_CAN_USE_8BIT 1
151 #define SMC_CAN_USE_16BIT 1
152 #define SMC_CAN_USE_32BIT 1
153 #define SMC_IO_SHIFT 0
154 #define SMC_NOWAIT 1
155 #define SMC_USE_PXA_DMA 1
156
157 #define SMC_inb(a, r) readb((a) + (r))
158 #define SMC_inw(a, r) readw((a) + (r))
159 #define SMC_inl(a, r) readl((a) + (r))
160 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
161 #define SMC_outl(v, a, r) writel(v, (a) + (r))
162 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
163 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
164
165 /* We actually can't write halfwords properly if not word aligned */
166 static inline void
167 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
168 {
169 if (reg & 2) {
170 unsigned int v = val << 16;
171 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
172 writel(v, ioaddr + (reg & ~2));
173 } else {
174 writew(val, ioaddr + reg);
175 }
176 }
177
178 #elif defined(CONFIG_ARCH_OMAP)
179
180 /* We can only do 16-bit reads and writes in the static memory space. */
181 #define SMC_CAN_USE_8BIT 0
182 #define SMC_CAN_USE_16BIT 1
183 #define SMC_CAN_USE_32BIT 0
184 #define SMC_IO_SHIFT 0
185 #define SMC_NOWAIT 1
186
187 #define SMC_inw(a, r) readw((a) + (r))
188 #define SMC_outw(v, a, r) writew(v, (a) + (r))
189 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
190 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
191
192 #include <asm/mach-types.h>
193 #include <asm/arch/cpu.h>
194
195 #define SMC_IRQ_FLAGS (( \
196 machine_is_omap_h2() \
197 || machine_is_omap_h3() \
198 || machine_is_omap_h4() \
199 || (machine_is_omap_innovator() && !cpu_is_omap1510()) \
200 ) ? IRQF_TRIGGER_FALLING : IRQF_TRIGGER_RISING)
201
202
203 #elif defined(CONFIG_SH_SH4202_MICRODEV)
204
205 #define SMC_CAN_USE_8BIT 0
206 #define SMC_CAN_USE_16BIT 1
207 #define SMC_CAN_USE_32BIT 0
208
209 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
210 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
211 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
212 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
213 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
214 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
215 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
216 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
217 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
218 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
219
220 #define SMC_IRQ_FLAGS (0)
221
222 #elif defined(CONFIG_ISA)
223
224 #define SMC_CAN_USE_8BIT 1
225 #define SMC_CAN_USE_16BIT 1
226 #define SMC_CAN_USE_32BIT 0
227
228 #define SMC_inb(a, r) inb((a) + (r))
229 #define SMC_inw(a, r) inw((a) + (r))
230 #define SMC_outb(v, a, r) outb(v, (a) + (r))
231 #define SMC_outw(v, a, r) outw(v, (a) + (r))
232 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
233 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
234
235 #elif defined(CONFIG_M32R)
236
237 #define SMC_CAN_USE_8BIT 0
238 #define SMC_CAN_USE_16BIT 1
239 #define SMC_CAN_USE_32BIT 0
240
241 #define SMC_inb(a, r) inb(((u32)a) + (r))
242 #define SMC_inw(a, r) inw(((u32)a) + (r))
243 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
244 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
245 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
246 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
247
248 #define SMC_IRQ_FLAGS (0)
249
250 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
251 #define RPC_LSB_DEFAULT RPC_LED_100_10
252
253 #elif defined(CONFIG_MACH_LPD79520) \
254 || defined(CONFIG_MACH_LPD7A400) \
255 || defined(CONFIG_MACH_LPD7A404)
256
257 /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
258 * way that the CPU handles chip selects and the way that the SMC chip
259 * expects the chip select to operate. Refer to
260 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
261 * IOBARRIER is a byte, in order that we read the least-common
262 * denominator. It would be wasteful to read 32 bits from an 8-bit
263 * accessible region.
264 *
265 * There is no explicit protection against interrupts intervening
266 * between the writew and the IOBARRIER. In SMC ISR there is a
267 * preamble that performs an IOBARRIER in the extremely unlikely event
268 * that the driver interrupts itself between a writew to the chip an
269 * the IOBARRIER that follows *and* the cache is large enough that the
270 * first off-chip access while handing the interrupt is to the SMC
271 * chip. Other devices in the same address space as the SMC chip must
272 * be aware of the potential for trouble and perform a similar
273 * IOBARRIER on entry to their ISR.
274 */
275
276 #include <asm/arch/constants.h> /* IOBARRIER_VIRT */
277
278 #define SMC_CAN_USE_8BIT 0
279 #define SMC_CAN_USE_16BIT 1
280 #define SMC_CAN_USE_32BIT 0
281 #define SMC_NOWAIT 0
282 #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
283
284 #define SMC_inw(a,r)\
285 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
286 #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
287
288 #define SMC_insw LPD7_SMC_insw
289 static inline void LPD7_SMC_insw (unsigned char* a, int r,
290 unsigned char* p, int l)
291 {
292 unsigned short* ps = (unsigned short*) p;
293 while (l-- > 0) {
294 *ps++ = readw (a + r);
295 LPD7X_IOBARRIER;
296 }
297 }
298
299 #define SMC_outsw LPD7_SMC_outsw
300 static inline void LPD7_SMC_outsw (unsigned char* a, int r,
301 unsigned char* p, int l)
302 {
303 unsigned short* ps = (unsigned short*) p;
304 while (l-- > 0) {
305 writew (*ps++, a + r);
306 LPD7X_IOBARRIER;
307 }
308 }
309
310 #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
311
312 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
313 #define RPC_LSB_DEFAULT RPC_LED_100_10
314
315 #elif defined(CONFIG_SOC_AU1X00)
316
317 #include <au1xxx.h>
318
319 /* We can only do 16-bit reads and writes in the static memory space. */
320 #define SMC_CAN_USE_8BIT 0
321 #define SMC_CAN_USE_16BIT 1
322 #define SMC_CAN_USE_32BIT 0
323 #define SMC_IO_SHIFT 0
324 #define SMC_NOWAIT 1
325
326 #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
327 #define SMC_insw(a, r, p, l) \
328 do { \
329 unsigned long _a = (unsigned long)((a) + (r)); \
330 int _l = (l); \
331 u16 *_p = (u16 *)(p); \
332 while (_l-- > 0) \
333 *_p++ = au_readw(_a); \
334 } while(0)
335 #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
336 #define SMC_outsw(a, r, p, l) \
337 do { \
338 unsigned long _a = (unsigned long)((a) + (r)); \
339 int _l = (l); \
340 const u16 *_p = (const u16 *)(p); \
341 while (_l-- > 0) \
342 au_writew(*_p++ , _a); \
343 } while(0)
344
345 #define SMC_IRQ_FLAGS (0)
346
347 #elif defined(CONFIG_ARCH_VERSATILE)
348
349 #define SMC_CAN_USE_8BIT 1
350 #define SMC_CAN_USE_16BIT 1
351 #define SMC_CAN_USE_32BIT 1
352 #define SMC_NOWAIT 1
353
354 #define SMC_inb(a, r) readb((a) + (r))
355 #define SMC_inw(a, r) readw((a) + (r))
356 #define SMC_inl(a, r) readl((a) + (r))
357 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
358 #define SMC_outw(v, a, r) writew(v, (a) + (r))
359 #define SMC_outl(v, a, r) writel(v, (a) + (r))
360 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
361 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
362
363 #define SMC_IRQ_FLAGS (0)
364
365 #else
366
367 #define SMC_CAN_USE_8BIT 1
368 #define SMC_CAN_USE_16BIT 1
369 #define SMC_CAN_USE_32BIT 1
370 #define SMC_NOWAIT 1
371
372 #define SMC_inb(a, r) readb((a) + (r))
373 #define SMC_inw(a, r) readw((a) + (r))
374 #define SMC_inl(a, r) readl((a) + (r))
375 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
376 #define SMC_outw(v, a, r) writew(v, (a) + (r))
377 #define SMC_outl(v, a, r) writel(v, (a) + (r))
378 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
379 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
380
381 #define RPC_LSA_DEFAULT RPC_LED_100_10
382 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
383
384 #endif
385
386 #ifdef SMC_USE_PXA_DMA
387 /*
388 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
389 * always happening in irq context so no need to worry about races. TX is
390 * different and probably not worth it for that reason, and not as critical
391 * as RX which can overrun memory and lose packets.
392 */
393 #include <linux/dma-mapping.h>
394 #include <asm/dma.h>
395 #include <asm/arch/pxa-regs.h>
396
397 #ifdef SMC_insl
398 #undef SMC_insl
399 #define SMC_insl(a, r, p, l) \
400 smc_pxa_dma_insl(a, lp->physaddr, r, dev->dma, p, l)
401 static inline void
402 smc_pxa_dma_insl(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
403 u_char *buf, int len)
404 {
405 dma_addr_t dmabuf;
406
407 /* fallback if no DMA available */
408 if (dma == (unsigned char)-1) {
409 readsl(ioaddr + reg, buf, len);
410 return;
411 }
412
413 /* 64 bit alignment is required for memory to memory DMA */
414 if ((long)buf & 4) {
415 *((u32 *)buf) = SMC_inl(ioaddr, reg);
416 buf += 4;
417 len--;
418 }
419
420 len *= 4;
421 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
422 DCSR(dma) = DCSR_NODESC;
423 DTADR(dma) = dmabuf;
424 DSADR(dma) = physaddr + reg;
425 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
426 DCMD_WIDTH4 | (DCMD_LENGTH & len));
427 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
428 while (!(DCSR(dma) & DCSR_STOPSTATE))
429 cpu_relax();
430 DCSR(dma) = 0;
431 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
432 }
433 #endif
434
435 #ifdef SMC_insw
436 #undef SMC_insw
437 #define SMC_insw(a, r, p, l) \
438 smc_pxa_dma_insw(a, lp->physaddr, r, dev->dma, p, l)
439 static inline void
440 smc_pxa_dma_insw(void __iomem *ioaddr, u_long physaddr, int reg, int dma,
441 u_char *buf, int len)
442 {
443 dma_addr_t dmabuf;
444
445 /* fallback if no DMA available */
446 if (dma == (unsigned char)-1) {
447 readsw(ioaddr + reg, buf, len);
448 return;
449 }
450
451 /* 64 bit alignment is required for memory to memory DMA */
452 while ((long)buf & 6) {
453 *((u16 *)buf) = SMC_inw(ioaddr, reg);
454 buf += 2;
455 len--;
456 }
457
458 len *= 2;
459 dmabuf = dma_map_single(NULL, buf, len, DMA_FROM_DEVICE);
460 DCSR(dma) = DCSR_NODESC;
461 DTADR(dma) = dmabuf;
462 DSADR(dma) = physaddr + reg;
463 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
464 DCMD_WIDTH2 | (DCMD_LENGTH & len));
465 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
466 while (!(DCSR(dma) & DCSR_STOPSTATE))
467 cpu_relax();
468 DCSR(dma) = 0;
469 dma_unmap_single(NULL, dmabuf, len, DMA_FROM_DEVICE);
470 }
471 #endif
472
473 static void
474 smc_pxa_dma_irq(int dma, void *dummy)
475 {
476 DCSR(dma) = 0;
477 }
478 #endif /* SMC_USE_PXA_DMA */
479
480
481 /*
482 * Everything a particular hardware setup needs should have been defined
483 * at this point. Add stubs for the undefined cases, mainly to avoid
484 * compilation warnings since they'll be optimized away, or to prevent buggy
485 * use of them.
486 */
487
488 #if ! SMC_CAN_USE_32BIT
489 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
490 #define SMC_outl(x, ioaddr, reg) BUG()
491 #define SMC_insl(a, r, p, l) BUG()
492 #define SMC_outsl(a, r, p, l) BUG()
493 #endif
494
495 #if !defined(SMC_insl) || !defined(SMC_outsl)
496 #define SMC_insl(a, r, p, l) BUG()
497 #define SMC_outsl(a, r, p, l) BUG()
498 #endif
499
500 #if ! SMC_CAN_USE_16BIT
501
502 /*
503 * Any 16-bit access is performed with two 8-bit accesses if the hardware
504 * can't do it directly. Most registers are 16-bit so those are mandatory.
505 */
506 #define SMC_outw(x, ioaddr, reg) \
507 do { \
508 unsigned int __val16 = (x); \
509 SMC_outb( __val16, ioaddr, reg ); \
510 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
511 } while (0)
512 #define SMC_inw(ioaddr, reg) \
513 ({ \
514 unsigned int __val16; \
515 __val16 = SMC_inb( ioaddr, reg ); \
516 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
517 __val16; \
518 })
519
520 #define SMC_insw(a, r, p, l) BUG()
521 #define SMC_outsw(a, r, p, l) BUG()
522
523 #endif
524
525 #if !defined(SMC_insw) || !defined(SMC_outsw)
526 #define SMC_insw(a, r, p, l) BUG()
527 #define SMC_outsw(a, r, p, l) BUG()
528 #endif
529
530 #if ! SMC_CAN_USE_8BIT
531 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
532 #define SMC_outb(x, ioaddr, reg) BUG()
533 #define SMC_insb(a, r, p, l) BUG()
534 #define SMC_outsb(a, r, p, l) BUG()
535 #endif
536
537 #if !defined(SMC_insb) || !defined(SMC_outsb)
538 #define SMC_insb(a, r, p, l) BUG()
539 #define SMC_outsb(a, r, p, l) BUG()
540 #endif
541
542 #ifndef SMC_CAN_USE_DATACS
543 #define SMC_CAN_USE_DATACS 0
544 #endif
545
546 #ifndef SMC_IO_SHIFT
547 #define SMC_IO_SHIFT 0
548 #endif
549
550 #ifndef SMC_IRQ_FLAGS
551 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
552 #endif
553
554 #ifndef SMC_INTERRUPT_PREAMBLE
555 #define SMC_INTERRUPT_PREAMBLE
556 #endif
557
558
559 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
560 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
561 #define SMC_DATA_EXTENT (4)
562
563 /*
564 . Bank Select Register:
565 .
566 . yyyy yyyy 0000 00xx
567 . xx = bank number
568 . yyyy yyyy = 0x33, for identification purposes.
569 */
570 #define BANK_SELECT (14 << SMC_IO_SHIFT)
571
572
573 // Transmit Control Register
574 /* BANK 0 */
575 #define TCR_REG SMC_REG(0x0000, 0)
576 #define TCR_ENABLE 0x0001 // When 1 we can transmit
577 #define TCR_LOOP 0x0002 // Controls output pin LBK
578 #define TCR_FORCOL 0x0004 // When 1 will force a collision
579 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
580 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
581 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
582 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
583 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
584 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
585 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
586
587 #define TCR_CLEAR 0 /* do NOTHING */
588 /* the default settings for the TCR register : */
589 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
590
591
592 // EPH Status Register
593 /* BANK 0 */
594 #define EPH_STATUS_REG SMC_REG(0x0002, 0)
595 #define ES_TX_SUC 0x0001 // Last TX was successful
596 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
597 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
598 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
599 #define ES_16COL 0x0010 // 16 Collisions Reached
600 #define ES_SQET 0x0020 // Signal Quality Error Test
601 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
602 #define ES_TXDEFR 0x0080 // Transmit Deferred
603 #define ES_LATCOL 0x0200 // Late collision detected on last tx
604 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
605 #define ES_EXC_DEF 0x0800 // Excessive Deferral
606 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
607 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
608 #define ES_TXUNRN 0x8000 // Tx Underrun
609
610
611 // Receive Control Register
612 /* BANK 0 */
613 #define RCR_REG SMC_REG(0x0004, 0)
614 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
615 #define RCR_PRMS 0x0002 // Enable promiscuous mode
616 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
617 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
618 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
619 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
620 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
621 #define RCR_SOFTRST 0x8000 // resets the chip
622
623 /* the normal settings for the RCR register : */
624 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
625 #define RCR_CLEAR 0x0 // set it to a base state
626
627
628 // Counter Register
629 /* BANK 0 */
630 #define COUNTER_REG SMC_REG(0x0006, 0)
631
632
633 // Memory Information Register
634 /* BANK 0 */
635 #define MIR_REG SMC_REG(0x0008, 0)
636
637
638 // Receive/Phy Control Register
639 /* BANK 0 */
640 #define RPC_REG SMC_REG(0x000A, 0)
641 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
642 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
643 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
644 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
645 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
646 #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
647 #define RPC_LED_RES (0x01) // LED = Reserved
648 #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
649 #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
650 #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
651 #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
652 #define RPC_LED_TX (0x06) // LED = TX packet occurred
653 #define RPC_LED_RX (0x07) // LED = RX packet occurred
654
655 #ifndef RPC_LSA_DEFAULT
656 #define RPC_LSA_DEFAULT RPC_LED_100
657 #endif
658 #ifndef RPC_LSB_DEFAULT
659 #define RPC_LSB_DEFAULT RPC_LED_FD
660 #endif
661
662 #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
663
664
665 /* Bank 0 0x0C is reserved */
666
667 // Bank Select Register
668 /* All Banks */
669 #define BSR_REG 0x000E
670
671
672 // Configuration Reg
673 /* BANK 1 */
674 #define CONFIG_REG SMC_REG(0x0000, 1)
675 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
676 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
677 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
678 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
679
680 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
681 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
682
683
684 // Base Address Register
685 /* BANK 1 */
686 #define BASE_REG SMC_REG(0x0002, 1)
687
688
689 // Individual Address Registers
690 /* BANK 1 */
691 #define ADDR0_REG SMC_REG(0x0004, 1)
692 #define ADDR1_REG SMC_REG(0x0006, 1)
693 #define ADDR2_REG SMC_REG(0x0008, 1)
694
695
696 // General Purpose Register
697 /* BANK 1 */
698 #define GP_REG SMC_REG(0x000A, 1)
699
700
701 // Control Register
702 /* BANK 1 */
703 #define CTL_REG SMC_REG(0x000C, 1)
704 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
705 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
706 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
707 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
708 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
709 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
710 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
711 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
712
713
714 // MMU Command Register
715 /* BANK 2 */
716 #define MMU_CMD_REG SMC_REG(0x0000, 2)
717 #define MC_BUSY 1 // When 1 the last release has not completed
718 #define MC_NOP (0<<5) // No Op
719 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
720 #define MC_RESET (2<<5) // Reset MMU to initial state
721 #define MC_REMOVE (3<<5) // Remove the current rx packet
722 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
723 #define MC_FREEPKT (5<<5) // Release packet in PNR register
724 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
725 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
726
727
728 // Packet Number Register
729 /* BANK 2 */
730 #define PN_REG SMC_REG(0x0002, 2)
731
732
733 // Allocation Result Register
734 /* BANK 2 */
735 #define AR_REG SMC_REG(0x0003, 2)
736 #define AR_FAILED 0x80 // Alocation Failed
737
738
739 // TX FIFO Ports Register
740 /* BANK 2 */
741 #define TXFIFO_REG SMC_REG(0x0004, 2)
742 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
743
744 // RX FIFO Ports Register
745 /* BANK 2 */
746 #define RXFIFO_REG SMC_REG(0x0005, 2)
747 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
748
749 #define FIFO_REG SMC_REG(0x0004, 2)
750
751 // Pointer Register
752 /* BANK 2 */
753 #define PTR_REG SMC_REG(0x0006, 2)
754 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
755 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
756 #define PTR_READ 0x2000 // When 1 the operation is a read
757
758
759 // Data Register
760 /* BANK 2 */
761 #define DATA_REG SMC_REG(0x0008, 2)
762
763
764 // Interrupt Status/Acknowledge Register
765 /* BANK 2 */
766 #define INT_REG SMC_REG(0x000C, 2)
767
768
769 // Interrupt Mask Register
770 /* BANK 2 */
771 #define IM_REG SMC_REG(0x000D, 2)
772 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
773 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
774 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
775 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
776 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
777 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
778 #define IM_TX_INT 0x02 // Transmit Interrupt
779 #define IM_RCV_INT 0x01 // Receive Interrupt
780
781
782 // Multicast Table Registers
783 /* BANK 3 */
784 #define MCAST_REG1 SMC_REG(0x0000, 3)
785 #define MCAST_REG2 SMC_REG(0x0002, 3)
786 #define MCAST_REG3 SMC_REG(0x0004, 3)
787 #define MCAST_REG4 SMC_REG(0x0006, 3)
788
789
790 // Management Interface Register (MII)
791 /* BANK 3 */
792 #define MII_REG SMC_REG(0x0008, 3)
793 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
794 #define MII_MDOE 0x0008 // MII Output Enable
795 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
796 #define MII_MDI 0x0002 // MII Input, pin MDI
797 #define MII_MDO 0x0001 // MII Output, pin MDO
798
799
800 // Revision Register
801 /* BANK 3 */
802 /* ( hi: chip id low: rev # ) */
803 #define REV_REG SMC_REG(0x000A, 3)
804
805
806 // Early RCV Register
807 /* BANK 3 */
808 /* this is NOT on SMC9192 */
809 #define ERCV_REG SMC_REG(0x000C, 3)
810 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
811 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
812
813
814 // External Register
815 /* BANK 7 */
816 #define EXT_REG SMC_REG(0x0000, 7)
817
818
819 #define CHIP_9192 3
820 #define CHIP_9194 4
821 #define CHIP_9195 5
822 #define CHIP_9196 6
823 #define CHIP_91100 7
824 #define CHIP_91100FD 8
825 #define CHIP_91111FD 9
826
827 static const char * chip_ids[ 16 ] = {
828 NULL, NULL, NULL,
829 /* 3 */ "SMC91C90/91C92",
830 /* 4 */ "SMC91C94",
831 /* 5 */ "SMC91C95",
832 /* 6 */ "SMC91C96",
833 /* 7 */ "SMC91C100",
834 /* 8 */ "SMC91C100FD",
835 /* 9 */ "SMC91C11xFD",
836 NULL, NULL, NULL,
837 NULL, NULL, NULL};
838
839
840 /*
841 . Receive status bits
842 */
843 #define RS_ALGNERR 0x8000
844 #define RS_BRODCAST 0x4000
845 #define RS_BADCRC 0x2000
846 #define RS_ODDFRAME 0x1000
847 #define RS_TOOLONG 0x0800
848 #define RS_TOOSHORT 0x0400
849 #define RS_MULTICAST 0x0001
850 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
851
852
853 /*
854 * PHY IDs
855 * LAN83C183 == LAN91C111 Internal PHY
856 */
857 #define PHY_LAN83C183 0x0016f840
858 #define PHY_LAN83C180 0x02821c50
859
860 /*
861 * PHY Register Addresses (LAN91C111 Internal PHY)
862 *
863 * Generic PHY registers can be found in <linux/mii.h>
864 *
865 * These phy registers are specific to our on-board phy.
866 */
867
868 // PHY Configuration Register 1
869 #define PHY_CFG1_REG 0x10
870 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
871 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
872 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
873 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
874 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
875 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
876 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
877 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
878 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
879 #define PHY_CFG1_TLVL_MASK 0x003C
880 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
881
882
883 // PHY Configuration Register 2
884 #define PHY_CFG2_REG 0x11
885 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
886 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
887 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
888 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
889
890 // PHY Status Output (and Interrupt status) Register
891 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
892 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
893 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
894 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
895 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
896 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
897 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
898 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
899 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
900 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
901 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
902
903 // PHY Interrupt/Status Mask Register
904 #define PHY_MASK_REG 0x13 // Interrupt Mask
905 // Uses the same bit definitions as PHY_INT_REG
906
907
908 /*
909 * SMC91C96 ethernet config and status registers.
910 * These are in the "attribute" space.
911 */
912 #define ECOR 0x8000
913 #define ECOR_RESET 0x80
914 #define ECOR_LEVEL_IRQ 0x40
915 #define ECOR_WR_ATTRIB 0x04
916 #define ECOR_ENABLE 0x01
917
918 #define ECSR 0x8002
919 #define ECSR_IOIS8 0x20
920 #define ECSR_PWRDWN 0x04
921 #define ECSR_INT 0x02
922
923 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
924
925
926 /*
927 * Macros to abstract register access according to the data bus
928 * capabilities. Please use those and not the in/out primitives.
929 * Note: the following macros do *not* select the bank -- this must
930 * be done separately as needed in the main code. The SMC_REG() macro
931 * only uses the bank argument for debugging purposes (when enabled).
932 *
933 * Note: despite inline functions being safer, everything leading to this
934 * should preferably be macros to let BUG() display the line number in
935 * the core source code since we're interested in the top call site
936 * not in any inline function location.
937 */
938
939 #if SMC_DEBUG > 0
940 #define SMC_REG(reg, bank) \
941 ({ \
942 int __b = SMC_CURRENT_BANK(); \
943 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
944 printk( "%s: bank reg screwed (0x%04x)\n", \
945 CARDNAME, __b ); \
946 BUG(); \
947 } \
948 reg<<SMC_IO_SHIFT; \
949 })
950 #else
951 #define SMC_REG(reg, bank) (reg<<SMC_IO_SHIFT)
952 #endif
953
954 /*
955 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
956 * aligned to a 32 bit boundary. I tell you that does exist!
957 * Fortunately the affected register accesses can be easily worked around
958 * since we can write zeroes to the preceeding 16 bits without adverse
959 * effects and use a 32-bit access.
960 *
961 * Enforce it on any 32-bit capable setup for now.
962 */
963 #define SMC_MUST_ALIGN_WRITE SMC_CAN_USE_32BIT
964
965 #define SMC_GET_PN() \
966 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, PN_REG)) \
967 : (SMC_inw(ioaddr, PN_REG) & 0xFF) )
968
969 #define SMC_SET_PN(x) \
970 do { \
971 if (SMC_MUST_ALIGN_WRITE) \
972 SMC_outl((x)<<16, ioaddr, SMC_REG(0, 2)); \
973 else if (SMC_CAN_USE_8BIT) \
974 SMC_outb(x, ioaddr, PN_REG); \
975 else \
976 SMC_outw(x, ioaddr, PN_REG); \
977 } while (0)
978
979 #define SMC_GET_AR() \
980 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, AR_REG)) \
981 : (SMC_inw(ioaddr, PN_REG) >> 8) )
982
983 #define SMC_GET_TXFIFO() \
984 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, TXFIFO_REG)) \
985 : (SMC_inw(ioaddr, TXFIFO_REG) & 0xFF) )
986
987 #define SMC_GET_RXFIFO() \
988 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, RXFIFO_REG)) \
989 : (SMC_inw(ioaddr, TXFIFO_REG) >> 8) )
990
991 #define SMC_GET_INT() \
992 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, INT_REG)) \
993 : (SMC_inw(ioaddr, INT_REG) & 0xFF) )
994
995 #define SMC_ACK_INT(x) \
996 do { \
997 if (SMC_CAN_USE_8BIT) \
998 SMC_outb(x, ioaddr, INT_REG); \
999 else { \
1000 unsigned long __flags; \
1001 int __mask; \
1002 local_irq_save(__flags); \
1003 __mask = SMC_inw( ioaddr, INT_REG ) & ~0xff; \
1004 SMC_outw( __mask | (x), ioaddr, INT_REG ); \
1005 local_irq_restore(__flags); \
1006 } \
1007 } while (0)
1008
1009 #define SMC_GET_INT_MASK() \
1010 ( SMC_CAN_USE_8BIT ? (SMC_inb(ioaddr, IM_REG)) \
1011 : (SMC_inw( ioaddr, INT_REG ) >> 8) )
1012
1013 #define SMC_SET_INT_MASK(x) \
1014 do { \
1015 if (SMC_CAN_USE_8BIT) \
1016 SMC_outb(x, ioaddr, IM_REG); \
1017 else \
1018 SMC_outw((x) << 8, ioaddr, INT_REG); \
1019 } while (0)
1020
1021 #define SMC_CURRENT_BANK() SMC_inw(ioaddr, BANK_SELECT)
1022
1023 #define SMC_SELECT_BANK(x) \
1024 do { \
1025 if (SMC_MUST_ALIGN_WRITE) \
1026 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1027 else \
1028 SMC_outw(x, ioaddr, BANK_SELECT); \
1029 } while (0)
1030
1031 #define SMC_GET_BASE() SMC_inw(ioaddr, BASE_REG)
1032
1033 #define SMC_SET_BASE(x) SMC_outw(x, ioaddr, BASE_REG)
1034
1035 #define SMC_GET_CONFIG() SMC_inw(ioaddr, CONFIG_REG)
1036
1037 #define SMC_SET_CONFIG(x) SMC_outw(x, ioaddr, CONFIG_REG)
1038
1039 #define SMC_GET_COUNTER() SMC_inw(ioaddr, COUNTER_REG)
1040
1041 #define SMC_GET_CTL() SMC_inw(ioaddr, CTL_REG)
1042
1043 #define SMC_SET_CTL(x) SMC_outw(x, ioaddr, CTL_REG)
1044
1045 #define SMC_GET_MII() SMC_inw(ioaddr, MII_REG)
1046
1047 #define SMC_SET_MII(x) SMC_outw(x, ioaddr, MII_REG)
1048
1049 #define SMC_GET_MIR() SMC_inw(ioaddr, MIR_REG)
1050
1051 #define SMC_SET_MIR(x) SMC_outw(x, ioaddr, MIR_REG)
1052
1053 #define SMC_GET_MMU_CMD() SMC_inw(ioaddr, MMU_CMD_REG)
1054
1055 #define SMC_SET_MMU_CMD(x) SMC_outw(x, ioaddr, MMU_CMD_REG)
1056
1057 #define SMC_GET_FIFO() SMC_inw(ioaddr, FIFO_REG)
1058
1059 #define SMC_GET_PTR() SMC_inw(ioaddr, PTR_REG)
1060
1061 #define SMC_SET_PTR(x) \
1062 do { \
1063 if (SMC_MUST_ALIGN_WRITE) \
1064 SMC_outl((x)<<16, ioaddr, SMC_REG(4, 2)); \
1065 else \
1066 SMC_outw(x, ioaddr, PTR_REG); \
1067 } while (0)
1068
1069 #define SMC_GET_EPH_STATUS() SMC_inw(ioaddr, EPH_STATUS_REG)
1070
1071 #define SMC_GET_RCR() SMC_inw(ioaddr, RCR_REG)
1072
1073 #define SMC_SET_RCR(x) SMC_outw(x, ioaddr, RCR_REG)
1074
1075 #define SMC_GET_REV() SMC_inw(ioaddr, REV_REG)
1076
1077 #define SMC_GET_RPC() SMC_inw(ioaddr, RPC_REG)
1078
1079 #define SMC_SET_RPC(x) \
1080 do { \
1081 if (SMC_MUST_ALIGN_WRITE) \
1082 SMC_outl((x)<<16, ioaddr, SMC_REG(8, 0)); \
1083 else \
1084 SMC_outw(x, ioaddr, RPC_REG); \
1085 } while (0)
1086
1087 #define SMC_GET_TCR() SMC_inw(ioaddr, TCR_REG)
1088
1089 #define SMC_SET_TCR(x) SMC_outw(x, ioaddr, TCR_REG)
1090
1091 #ifndef SMC_GET_MAC_ADDR
1092 #define SMC_GET_MAC_ADDR(addr) \
1093 do { \
1094 unsigned int __v; \
1095 __v = SMC_inw( ioaddr, ADDR0_REG ); \
1096 addr[0] = __v; addr[1] = __v >> 8; \
1097 __v = SMC_inw( ioaddr, ADDR1_REG ); \
1098 addr[2] = __v; addr[3] = __v >> 8; \
1099 __v = SMC_inw( ioaddr, ADDR2_REG ); \
1100 addr[4] = __v; addr[5] = __v >> 8; \
1101 } while (0)
1102 #endif
1103
1104 #define SMC_SET_MAC_ADDR(addr) \
1105 do { \
1106 SMC_outw( addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG ); \
1107 SMC_outw( addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG ); \
1108 SMC_outw( addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG ); \
1109 } while (0)
1110
1111 #define SMC_SET_MCAST(x) \
1112 do { \
1113 const unsigned char *mt = (x); \
1114 SMC_outw( mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1 ); \
1115 SMC_outw( mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2 ); \
1116 SMC_outw( mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3 ); \
1117 SMC_outw( mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4 ); \
1118 } while (0)
1119
1120 #define SMC_PUT_PKT_HDR(status, length) \
1121 do { \
1122 if (SMC_CAN_USE_32BIT) \
1123 SMC_outl((status) | (length)<<16, ioaddr, DATA_REG); \
1124 else { \
1125 SMC_outw(status, ioaddr, DATA_REG); \
1126 SMC_outw(length, ioaddr, DATA_REG); \
1127 } \
1128 } while (0)
1129
1130 #define SMC_GET_PKT_HDR(status, length) \
1131 do { \
1132 if (SMC_CAN_USE_32BIT) { \
1133 unsigned int __val = SMC_inl(ioaddr, DATA_REG); \
1134 (status) = __val & 0xffff; \
1135 (length) = __val >> 16; \
1136 } else { \
1137 (status) = SMC_inw(ioaddr, DATA_REG); \
1138 (length) = SMC_inw(ioaddr, DATA_REG); \
1139 } \
1140 } while (0)
1141
1142 #define SMC_PUSH_DATA(p, l) \
1143 do { \
1144 if (SMC_CAN_USE_32BIT) { \
1145 void *__ptr = (p); \
1146 int __len = (l); \
1147 void __iomem *__ioaddr = ioaddr; \
1148 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1149 __len -= 2; \
1150 SMC_outw(*(u16 *)__ptr, ioaddr, DATA_REG); \
1151 __ptr += 2; \
1152 } \
1153 if (SMC_CAN_USE_DATACS && lp->datacs) \
1154 __ioaddr = lp->datacs; \
1155 SMC_outsl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1156 if (__len & 2) { \
1157 __ptr += (__len & ~3); \
1158 SMC_outw(*((u16 *)__ptr), ioaddr, DATA_REG); \
1159 } \
1160 } else if (SMC_CAN_USE_16BIT) \
1161 SMC_outsw(ioaddr, DATA_REG, p, (l) >> 1); \
1162 else if (SMC_CAN_USE_8BIT) \
1163 SMC_outsb(ioaddr, DATA_REG, p, l); \
1164 } while (0)
1165
1166 #define SMC_PULL_DATA(p, l) \
1167 do { \
1168 if (SMC_CAN_USE_32BIT) { \
1169 void *__ptr = (p); \
1170 int __len = (l); \
1171 void __iomem *__ioaddr = ioaddr; \
1172 if ((unsigned long)__ptr & 2) { \
1173 /* \
1174 * We want 32bit alignment here. \
1175 * Since some buses perform a full \
1176 * 32bit fetch even for 16bit data \
1177 * we can't use SMC_inw() here. \
1178 * Back both source (on-chip) and \
1179 * destination pointers of 2 bytes. \
1180 * This is possible since the call to \
1181 * SMC_GET_PKT_HDR() already advanced \
1182 * the source pointer of 4 bytes, and \
1183 * the skb_reserve(skb, 2) advanced \
1184 * the destination pointer of 2 bytes. \
1185 */ \
1186 __ptr -= 2; \
1187 __len += 2; \
1188 SMC_SET_PTR(2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1189 } \
1190 if (SMC_CAN_USE_DATACS && lp->datacs) \
1191 __ioaddr = lp->datacs; \
1192 __len += 2; \
1193 SMC_insl(__ioaddr, DATA_REG, __ptr, __len>>2); \
1194 } else if (SMC_CAN_USE_16BIT) \
1195 SMC_insw(ioaddr, DATA_REG, p, (l) >> 1); \
1196 else if (SMC_CAN_USE_8BIT) \
1197 SMC_insb(ioaddr, DATA_REG, p, l); \
1198 } while (0)
1199
1200 #endif /* _SMC91X_H_ */
Support for the Chinese Samsung S3C2440 based development boards