?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ixgbe: add support for 82599 KR device 0x1517
[linux-2.6/mini2440.git] / drivers / net / ixgbe / ixgbe_82599.c
blob9c4214993b8232b5e230f41ca52dd54900121edd
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2009 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34
35 #define IXGBE_82599_MAX_TX_QUEUES 128
36 #define IXGBE_82599_MAX_RX_QUEUES 128
37 #define IXGBE_82599_RAR_ENTRIES 128
38 #define IXGBE_82599_MC_TBL_SIZE 128
39 #define IXGBE_82599_VFT_TBL_SIZE 128
40
41 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
42 ixgbe_link_speed speed,
43 bool autoneg,
44 bool autoneg_wait_to_complete);
45 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
46 bool autoneg_wait_to_complete);
47 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
48 ixgbe_link_speed speed,
49 bool autoneg,
50 bool autoneg_wait_to_complete);
51 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
52 ixgbe_link_speed *speed,
53 bool *autoneg);
54 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
55 ixgbe_link_speed speed,
56 bool autoneg,
57 bool autoneg_wait_to_complete);
58 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
59
60 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
61 {
62 struct ixgbe_mac_info *mac = &hw->mac;
63 if (hw->phy.multispeed_fiber) {
64 /* Set up dual speed SFP+ support */
65 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
66 } else {
67 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
68 }
69 }
70
71 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
72 {
73 s32 ret_val = 0;
74 u16 list_offset, data_offset, data_value;
75
76 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
77 ixgbe_init_mac_link_ops_82599(hw);
78
79 hw->phy.ops.reset = NULL;
80
81 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
82 &data_offset);
83
84 if (ret_val != 0)
85 goto setup_sfp_out;
86
87 /* PHY config will finish before releasing the semaphore */
88 ret_val = ixgbe_acquire_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
89 if (ret_val != 0) {
90 ret_val = IXGBE_ERR_SWFW_SYNC;
91 goto setup_sfp_out;
92 }
93
94 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
95 while (data_value != 0xffff) {
96 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
97 IXGBE_WRITE_FLUSH(hw);
98 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
99 }
100 /* Now restart DSP by setting Restart_AN */
101 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
102 (IXGBE_READ_REG(hw, IXGBE_AUTOC) | IXGBE_AUTOC_AN_RESTART));
103
104 /* Release the semaphore */
105 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
106 /* Delay obtaining semaphore again to allow FW access */
107 msleep(hw->eeprom.semaphore_delay);
108 }
109
110 setup_sfp_out:
111 return ret_val;
112 }
113
114 /**
115 * ixgbe_get_pcie_msix_count_82599 - Gets MSI-X vector count
116 * @hw: pointer to hardware structure
117 *
118 * Read PCIe configuration space, and get the MSI-X vector count from
119 * the capabilities table.
120 **/
121 static u32 ixgbe_get_pcie_msix_count_82599(struct ixgbe_hw *hw)
122 {
123 struct ixgbe_adapter *adapter = hw->back;
124 u16 msix_count;
125 pci_read_config_word(adapter->pdev, IXGBE_PCIE_MSIX_82599_CAPS,
126 &msix_count);
127 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
128
129 /* MSI-X count is zero-based in HW, so increment to give proper value */
130 msix_count++;
131
132 return msix_count;
133 }
134
135 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
136 {
137 struct ixgbe_mac_info *mac = &hw->mac;
138
139 ixgbe_init_mac_link_ops_82599(hw);
140
141 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
142 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
143 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
144 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
145 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
146 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_82599(hw);
147
148 return 0;
149 }
150
151 /**
152 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
153 * @hw: pointer to hardware structure
154 *
155 * Initialize any function pointers that were not able to be
156 * set during get_invariants because the PHY/SFP type was
157 * not known. Perform the SFP init if necessary.
158 *
159 **/
160 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
161 {
162 struct ixgbe_mac_info *mac = &hw->mac;
163 struct ixgbe_phy_info *phy = &hw->phy;
164 s32 ret_val = 0;
165
166 /* Identify the PHY or SFP module */
167 ret_val = phy->ops.identify(hw);
168
169 /* Setup function pointers based on detected SFP module and speeds */
170 ixgbe_init_mac_link_ops_82599(hw);
171
172 /* If copper media, overwrite with copper function pointers */
173 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
174 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
175 mac->ops.get_link_capabilities =
176 &ixgbe_get_copper_link_capabilities_82599;
177 }
178
179 /* Set necessary function pointers based on phy type */
180 switch (hw->phy.type) {
181 case ixgbe_phy_tn:
182 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
183 phy->ops.get_firmware_version =
184 &ixgbe_get_phy_firmware_version_tnx;
185 break;
186 default:
187 break;
188 }
189
190 return ret_val;
191 }
192
193 /**
194 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
195 * @hw: pointer to hardware structure
196 * @speed: pointer to link speed
197 * @negotiation: true when autoneg or autotry is enabled
198 *
199 * Determines the link capabilities by reading the AUTOC register.
200 **/
201 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
202 ixgbe_link_speed *speed,
203 bool *negotiation)
204 {
205 s32 status = 0;
206 u32 autoc = 0;
207
208 /*
209 * Determine link capabilities based on the stored value of AUTOC,
210 * which represents EEPROM defaults. If AUTOC value has not been
211 * stored, use the current register value.
212 */
213 if (hw->mac.orig_link_settings_stored)
214 autoc = hw->mac.orig_autoc;
215 else
216 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
217
218 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
219 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
220 *speed = IXGBE_LINK_SPEED_1GB_FULL;
221 *negotiation = false;
222 break;
223
224 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
225 *speed = IXGBE_LINK_SPEED_10GB_FULL;
226 *negotiation = false;
227 break;
228
229 case IXGBE_AUTOC_LMS_1G_AN:
230 *speed = IXGBE_LINK_SPEED_1GB_FULL;
231 *negotiation = true;
232 break;
233
234 case IXGBE_AUTOC_LMS_10G_SERIAL:
235 *speed = IXGBE_LINK_SPEED_10GB_FULL;
236 *negotiation = false;
237 break;
238
239 case IXGBE_AUTOC_LMS_KX4_KX_KR:
240 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
241 *speed = IXGBE_LINK_SPEED_UNKNOWN;
242 if (autoc & IXGBE_AUTOC_KR_SUPP)
243 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
244 if (autoc & IXGBE_AUTOC_KX4_SUPP)
245 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
246 if (autoc & IXGBE_AUTOC_KX_SUPP)
247 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
248 *negotiation = true;
249 break;
250
251 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
252 *speed = IXGBE_LINK_SPEED_100_FULL;
253 if (autoc & IXGBE_AUTOC_KR_SUPP)
254 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
255 if (autoc & IXGBE_AUTOC_KX4_SUPP)
256 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
257 if (autoc & IXGBE_AUTOC_KX_SUPP)
258 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
259 *negotiation = true;
260 break;
261
262 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
263 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
264 *negotiation = false;
265 break;
266
267 default:
268 status = IXGBE_ERR_LINK_SETUP;
269 goto out;
270 break;
271 }
272
273 if (hw->phy.multispeed_fiber) {
274 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
275 IXGBE_LINK_SPEED_1GB_FULL;
276 *negotiation = true;
277 }
278
279 out:
280 return status;
281 }
282
283 /**
284 * ixgbe_get_copper_link_capabilities_82599 - Determines link capabilities
285 * @hw: pointer to hardware structure
286 * @speed: pointer to link speed
287 * @autoneg: boolean auto-negotiation value
288 *
289 * Determines the link capabilities by reading the AUTOC register.
290 **/
291 static s32 ixgbe_get_copper_link_capabilities_82599(struct ixgbe_hw *hw,
292 ixgbe_link_speed *speed,
293 bool *autoneg)
294 {
295 s32 status = IXGBE_ERR_LINK_SETUP;
296 u16 speed_ability;
297
298 *speed = 0;
299 *autoneg = true;
300
301 status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD,
302 &speed_ability);
303
304 if (status == 0) {
305 if (speed_ability & MDIO_SPEED_10G)
306 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
307 if (speed_ability & MDIO_PMA_SPEED_1000)
308 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
309 }
310
311 return status;
312 }
313
314 /**
315 * ixgbe_get_media_type_82599 - Get media type
316 * @hw: pointer to hardware structure
317 *
318 * Returns the media type (fiber, copper, backplane)
319 **/
320 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
321 {
322 enum ixgbe_media_type media_type;
323
324 /* Detect if there is a copper PHY attached. */
325 if (hw->phy.type == ixgbe_phy_cu_unknown ||
326 hw->phy.type == ixgbe_phy_tn) {
327 media_type = ixgbe_media_type_copper;
328 goto out;
329 }
330
331 switch (hw->device_id) {
332 case IXGBE_DEV_ID_82599_KX4:
333 case IXGBE_DEV_ID_82599_KX4_MEZZ:
334 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
335 case IXGBE_DEV_ID_82599_KR:
336 case IXGBE_DEV_ID_82599_XAUI_LOM:
337 /* Default device ID is mezzanine card KX/KX4 */
338 media_type = ixgbe_media_type_backplane;
339 break;
340 case IXGBE_DEV_ID_82599_SFP:
341 media_type = ixgbe_media_type_fiber;
342 break;
343 case IXGBE_DEV_ID_82599_CX4:
344 media_type = ixgbe_media_type_cx4;
345 break;
346 default:
347 media_type = ixgbe_media_type_unknown;
348 break;
349 }
350 out:
351 return media_type;
352 }
353
354 /**
355 * ixgbe_start_mac_link_82599 - Setup MAC link settings
356 * @hw: pointer to hardware structure
357 * @autoneg_wait_to_complete: true when waiting for completion is needed
358 *
359 * Configures link settings based on values in the ixgbe_hw struct.
360 * Restarts the link. Performs autonegotiation if needed.
361 **/
362 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
363 bool autoneg_wait_to_complete)
364 {
365 u32 autoc_reg;
366 u32 links_reg;
367 u32 i;
368 s32 status = 0;
369
370 /* Restart link */
371 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
372 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
373 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
374
375 /* Only poll for autoneg to complete if specified to do so */
376 if (autoneg_wait_to_complete) {
377 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
378 IXGBE_AUTOC_LMS_KX4_KX_KR ||
379 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
380 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
381 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
382 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
383 links_reg = 0; /* Just in case Autoneg time = 0 */
384 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
385 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
386 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
387 break;
388 msleep(100);
389 }
390 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
391 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
392 hw_dbg(hw, "Autoneg did not complete.\n");
393 }
394 }
395 }
396
397 /* Add delay to filter out noises during initial link setup */
398 msleep(50);
399
400 return status;
401 }
402
403 /**
404 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
405 * @hw: pointer to hardware structure
406 * @speed: new link speed
407 * @autoneg: true if autonegotiation enabled
408 * @autoneg_wait_to_complete: true when waiting for completion is needed
409 *
410 * Set the link speed in the AUTOC register and restarts link.
411 **/
412 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
413 ixgbe_link_speed speed,
414 bool autoneg,
415 bool autoneg_wait_to_complete)
416 {
417 s32 status = 0;
418 ixgbe_link_speed phy_link_speed;
419 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
420 u32 speedcnt = 0;
421 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
422 bool link_up = false;
423 bool negotiation;
424 int i;
425
426 /* Mask off requested but non-supported speeds */
427 hw->mac.ops.get_link_capabilities(hw, &phy_link_speed, &negotiation);
428 speed &= phy_link_speed;
429
430 /*
431 * When the driver changes the link speeds that it can support,
432 * it sets autotry_restart to true to indicate that we need to
433 * initiate a new autotry session with the link partner. To do
434 * so, we set the speed then disable and re-enable the tx laser, to
435 * alert the link partner that it also needs to restart autotry on its
436 * end. This is consistent with true clause 37 autoneg, which also
437 * involves a loss of signal.
438 */
439
440 /*
441 * Try each speed one by one, highest priority first. We do this in
442 * software because 10gb fiber doesn't support speed autonegotiation.
443 */
444 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
445 speedcnt++;
446 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
447
448 /* If we already have link at this speed, just jump out */
449 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
450
451 if ((phy_link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
452 goto out;
453
454 /* Set the module link speed */
455 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
456 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
457
458 /* Allow module to change analog characteristics (1G->10G) */
459 msleep(40);
460
461 status = ixgbe_setup_mac_link_82599(hw,
462 IXGBE_LINK_SPEED_10GB_FULL,
463 autoneg,
464 autoneg_wait_to_complete);
465 if (status != 0)
466 return status;
467
468 /* Flap the tx laser if it has not already been done */
469 if (hw->mac.autotry_restart) {
470 /* Disable tx laser; allow 100us to go dark per spec */
471 esdp_reg |= IXGBE_ESDP_SDP3;
472 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
473 udelay(100);
474
475 /* Enable tx laser; allow 2ms to light up per spec */
476 esdp_reg &= ~IXGBE_ESDP_SDP3;
477 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
478 msleep(2);
479
480 hw->mac.autotry_restart = false;
481 }
482
483 /* The controller may take up to 500ms at 10g to acquire link */
484 for (i = 0; i < 5; i++) {
485 /* Wait for the link partner to also set speed */
486 msleep(100);
487
488 /* If we have link, just jump out */
489 hw->mac.ops.check_link(hw, &phy_link_speed,
490 &link_up, false);
491 if (link_up)
492 goto out;
493 }
494 }
495
496 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
497 speedcnt++;
498 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
499 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
500
501 /* If we already have link at this speed, just jump out */
502 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
503
504 if ((phy_link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
505 goto out;
506
507 /* Set the module link speed */
508 esdp_reg &= ~IXGBE_ESDP_SDP5;
509 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
510 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
511
512 /* Allow module to change analog characteristics (10G->1G) */
513 msleep(40);
514
515 status = ixgbe_setup_mac_link_82599(hw,
516 IXGBE_LINK_SPEED_1GB_FULL,
517 autoneg,
518 autoneg_wait_to_complete);
519 if (status != 0)
520 return status;
521
522 /* Flap the tx laser if it has not already been done */
523 if (hw->mac.autotry_restart) {
524 /* Disable tx laser; allow 100us to go dark per spec */
525 esdp_reg |= IXGBE_ESDP_SDP3;
526 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
527 udelay(100);
528
529 /* Enable tx laser; allow 2ms to light up per spec */
530 esdp_reg &= ~IXGBE_ESDP_SDP3;
531 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
532 msleep(2);
533
534 hw->mac.autotry_restart = false;
535 }
536
537 /* Wait for the link partner to also set speed */
538 msleep(100);
539
540 /* If we have link, just jump out */
541 hw->mac.ops.check_link(hw, &phy_link_speed, &link_up, false);
542 if (link_up)
543 goto out;
544 }
545
546 /*
547 * We didn't get link. Configure back to the highest speed we tried,
548 * (if there was more than one). We call ourselves back with just the
549 * single highest speed that the user requested.
550 */
551 if (speedcnt > 1)
552 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
553 highest_link_speed,
554 autoneg,
555 autoneg_wait_to_complete);
556
557 out:
558 /* Set autoneg_advertised value based on input link speed */
559 hw->phy.autoneg_advertised = 0;
560
561 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
562 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
563
564 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
565 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
566
567 return status;
568 }
569
570 /**
571 * ixgbe_check_mac_link_82599 - Determine link and speed status
572 * @hw: pointer to hardware structure
573 * @speed: pointer to link speed
574 * @link_up: true when link is up
575 * @link_up_wait_to_complete: bool used to wait for link up or not
576 *
577 * Reads the links register to determine if link is up and the current speed
578 **/
579 static s32 ixgbe_check_mac_link_82599(struct ixgbe_hw *hw,
580 ixgbe_link_speed *speed,
581 bool *link_up,
582 bool link_up_wait_to_complete)
583 {
584 u32 links_reg;
585 u32 i;
586
587 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
588 if (link_up_wait_to_complete) {
589 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
590 if (links_reg & IXGBE_LINKS_UP) {
591 *link_up = true;
592 break;
593 } else {
594 *link_up = false;
595 }
596 msleep(100);
597 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
598 }
599 } else {
600 if (links_reg & IXGBE_LINKS_UP)
601 *link_up = true;
602 else
603 *link_up = false;
604 }
605
606 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
607 IXGBE_LINKS_SPEED_10G_82599)
608 *speed = IXGBE_LINK_SPEED_10GB_FULL;
609 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
610 IXGBE_LINKS_SPEED_1G_82599)
611 *speed = IXGBE_LINK_SPEED_1GB_FULL;
612 else
613 *speed = IXGBE_LINK_SPEED_100_FULL;
614
615 /* if link is down, zero out the current_mode */
616 if (*link_up == false) {
617 hw->fc.current_mode = ixgbe_fc_none;
618 hw->fc.fc_was_autonegged = false;
619 }
620
621 return 0;
622 }
623
624 /**
625 * ixgbe_setup_mac_link_82599 - Set MAC link speed
626 * @hw: pointer to hardware structure
627 * @speed: new link speed
628 * @autoneg: true if autonegotiation enabled
629 * @autoneg_wait_to_complete: true when waiting for completion is needed
630 *
631 * Set the link speed in the AUTOC register and restarts link.
632 **/
633 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
634 ixgbe_link_speed speed, bool autoneg,
635 bool autoneg_wait_to_complete)
636 {
637 s32 status = 0;
638 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
639 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
640 u32 start_autoc = autoc;
641 u32 orig_autoc = 0;
642 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
643 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
644 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
645 u32 links_reg;
646 u32 i;
647 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
648
649 /* Check to see if speed passed in is supported. */
650 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
651 speed &= link_capabilities;
652
653 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
654 status = IXGBE_ERR_LINK_SETUP;
655 goto out;
656 }
657
658 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
659 if (hw->mac.orig_link_settings_stored)
660 orig_autoc = hw->mac.orig_autoc;
661 else
662 orig_autoc = autoc;
663
664
665 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
666 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
667 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
668 /* Set KX4/KX/KR support according to speed requested */
669 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
670 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
671 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
672 autoc |= IXGBE_AUTOC_KX4_SUPP;
673 if (orig_autoc & IXGBE_AUTOC_KR_SUPP)
674 autoc |= IXGBE_AUTOC_KR_SUPP;
675 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
676 autoc |= IXGBE_AUTOC_KX_SUPP;
677 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
678 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
679 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
680 /* Switch from 1G SFI to 10G SFI if requested */
681 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
682 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
683 autoc &= ~IXGBE_AUTOC_LMS_MASK;
684 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
685 }
686 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
687 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
688 /* Switch from 10G SFI to 1G SFI if requested */
689 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
690 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
691 autoc &= ~IXGBE_AUTOC_LMS_MASK;
692 if (autoneg)
693 autoc |= IXGBE_AUTOC_LMS_1G_AN;
694 else
695 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
696 }
697 }
698
699 if (autoc != start_autoc) {
700 /* Restart link */
701 autoc |= IXGBE_AUTOC_AN_RESTART;
702 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
703
704 /* Only poll for autoneg to complete if specified to do so */
705 if (autoneg_wait_to_complete) {
706 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
707 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
708 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
709 links_reg = 0; /*Just in case Autoneg time=0*/
710 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
711 links_reg =
712 IXGBE_READ_REG(hw, IXGBE_LINKS);
713 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
714 break;
715 msleep(100);
716 }
717 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
718 status =
719 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
720 hw_dbg(hw, "Autoneg did not "
721 "complete.\n");
722 }
723 }
724 }
725
726 /* Add delay to filter out noises during initial link setup */
727 msleep(50);
728 }
729
730 out:
731 return status;
732 }
733
734 /**
735 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
736 * @hw: pointer to hardware structure
737 * @speed: new link speed
738 * @autoneg: true if autonegotiation enabled
739 * @autoneg_wait_to_complete: true if waiting is needed to complete
740 *
741 * Restarts link on PHY and MAC based on settings passed in.
742 **/
743 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
744 ixgbe_link_speed speed,
745 bool autoneg,
746 bool autoneg_wait_to_complete)
747 {
748 s32 status;
749
750 /* Setup the PHY according to input speed */
751 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
752 autoneg_wait_to_complete);
753 /* Set up MAC */
754 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
755
756 return status;
757 }
758
759 /**
760 * ixgbe_reset_hw_82599 - Perform hardware reset
761 * @hw: pointer to hardware structure
762 *
763 * Resets the hardware by resetting the transmit and receive units, masks
764 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
765 * reset.
766 **/
767 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
768 {
769 s32 status = 0;
770 u32 ctrl, ctrl_ext;
771 u32 i;
772 u32 autoc;
773 u32 autoc2;
774
775 /* Call adapter stop to disable tx/rx and clear interrupts */
776 hw->mac.ops.stop_adapter(hw);
777
778 /* PHY ops must be identified and initialized prior to reset */
779
780 /* Init PHY and function pointers, perform SFP setup */
781 status = hw->phy.ops.init(hw);
782
783 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
784 goto reset_hw_out;
785
786 /* Setup SFP module if there is one present. */
787 if (hw->phy.sfp_setup_needed) {
788 status = hw->mac.ops.setup_sfp(hw);
789 hw->phy.sfp_setup_needed = false;
790 }
791
792 /* Reset PHY */
793 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
794 hw->phy.ops.reset(hw);
795
796 /*
797 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
798 * access and verify no pending requests before reset
799 */
800 status = ixgbe_disable_pcie_master(hw);
801 if (status != 0) {
802 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
803 hw_dbg(hw, "PCI-E Master disable polling has failed.\n");
804 }
805
806 /*
807 * Issue global reset to the MAC. This needs to be a SW reset.
808 * If link reset is used, it might reset the MAC when mng is using it
809 */
810 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
811 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
812 IXGBE_WRITE_FLUSH(hw);
813
814 /* Poll for reset bit to self-clear indicating reset is complete */
815 for (i = 0; i < 10; i++) {
816 udelay(1);
817 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
818 if (!(ctrl & IXGBE_CTRL_RST))
819 break;
820 }
821 if (ctrl & IXGBE_CTRL_RST) {
822 status = IXGBE_ERR_RESET_FAILED;
823 hw_dbg(hw, "Reset polling failed to complete.\n");
824 }
825 /* Clear PF Reset Done bit so PF/VF Mail Ops can work */
826 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
827 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
828 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
829
830 msleep(50);
831
832
833
834 /*
835 * Store the original AUTOC/AUTOC2 values if they have not been
836 * stored off yet. Otherwise restore the stored original
837 * values since the reset operation sets back to defaults.
838 */
839 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
840 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
841 if (hw->mac.orig_link_settings_stored == false) {
842 hw->mac.orig_autoc = autoc;
843 hw->mac.orig_autoc2 = autoc2;
844 hw->mac.orig_link_settings_stored = true;
845 } else {
846 if (autoc != hw->mac.orig_autoc)
847 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
848 IXGBE_AUTOC_AN_RESTART));
849
850 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
851 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
852 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
853 autoc2 |= (hw->mac.orig_autoc2 &
854 IXGBE_AUTOC2_UPPER_MASK);
855 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
856 }
857 }
858
859 /*
860 * Store MAC address from RAR0, clear receive address registers, and
861 * clear the multicast table. Also reset num_rar_entries to 128,
862 * since we modify this value when programming the SAN MAC address.
863 */
864 hw->mac.num_rar_entries = 128;
865 hw->mac.ops.init_rx_addrs(hw);
866
867 /* Store the permanent mac address */
868 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
869
870 /* Store the permanent SAN mac address */
871 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
872
873 /* Add the SAN MAC address to the RAR only if it's a valid address */
874 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
875 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
876 hw->mac.san_addr, 0, IXGBE_RAH_AV);
877
878 /* Reserve the last RAR for the SAN MAC address */
879 hw->mac.num_rar_entries--;
880 }
881
882 reset_hw_out:
883 return status;
884 }
885
886 /**
887 * ixgbe_clear_vmdq_82599 - Disassociate a VMDq pool index from a rx address
888 * @hw: pointer to hardware struct
889 * @rar: receive address register index to disassociate
890 * @vmdq: VMDq pool index to remove from the rar
891 **/
892 static s32 ixgbe_clear_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
893 {
894 u32 mpsar_lo, mpsar_hi;
895 u32 rar_entries = hw->mac.num_rar_entries;
896
897 if (rar < rar_entries) {
898 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
899 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
900
901 if (!mpsar_lo && !mpsar_hi)
902 goto done;
903
904 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
905 if (mpsar_lo) {
906 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
907 mpsar_lo = 0;
908 }
909 if (mpsar_hi) {
910 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
911 mpsar_hi = 0;
912 }
913 } else if (vmdq < 32) {
914 mpsar_lo &= ~(1 << vmdq);
915 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
916 } else {
917 mpsar_hi &= ~(1 << (vmdq - 32));
918 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
919 }
920
921 /* was that the last pool using this rar? */
922 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
923 hw->mac.ops.clear_rar(hw, rar);
924 } else {
925 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
926 }
927
928 done:
929 return 0;
930 }
931
932 /**
933 * ixgbe_set_vmdq_82599 - Associate a VMDq pool index with a rx address
934 * @hw: pointer to hardware struct
935 * @rar: receive address register index to associate with a VMDq index
936 * @vmdq: VMDq pool index
937 **/
938 static s32 ixgbe_set_vmdq_82599(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
939 {
940 u32 mpsar;
941 u32 rar_entries = hw->mac.num_rar_entries;
942
943 if (rar < rar_entries) {
944 if (vmdq < 32) {
945 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
946 mpsar |= 1 << vmdq;
947 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
948 } else {
949 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
950 mpsar |= 1 << (vmdq - 32);
951 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
952 }
953 } else {
954 hw_dbg(hw, "RAR index %d is out of range.\n", rar);
955 }
956 return 0;
957 }
958
959 /**
960 * ixgbe_set_vfta_82599 - Set VLAN filter table
961 * @hw: pointer to hardware structure
962 * @vlan: VLAN id to write to VLAN filter
963 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
964 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
965 *
966 * Turn on/off specified VLAN in the VLAN filter table.
967 **/
968 static s32 ixgbe_set_vfta_82599(struct ixgbe_hw *hw, u32 vlan, u32 vind,
969 bool vlan_on)
970 {
971 u32 regindex;
972 u32 bitindex;
973 u32 bits;
974 u32 first_empty_slot;
975
976 if (vlan > 4095)
977 return IXGBE_ERR_PARAM;
978
979 /*
980 * this is a 2 part operation - first the VFTA, then the
981 * VLVF and VLVFB if vind is set
982 */
983
984 /* Part 1
985 * The VFTA is a bitstring made up of 128 32-bit registers
986 * that enable the particular VLAN id, much like the MTA:
987 * bits[11-5]: which register
988 * bits[4-0]: which bit in the register
989 */
990 regindex = (vlan >> 5) & 0x7F;
991 bitindex = vlan & 0x1F;
992 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
993 if (vlan_on)
994 bits |= (1 << bitindex);
995 else
996 bits &= ~(1 << bitindex);
997 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
998
999
1000 /* Part 2
1001 * If the vind is set
1002 * Either vlan_on
1003 * make sure the vlan is in VLVF
1004 * set the vind bit in the matching VLVFB
1005 * Or !vlan_on
1006 * clear the pool bit and possibly the vind
1007 */
1008 if (vind) {
1009 /* find the vlanid or the first empty slot */
1010 first_empty_slot = 0;
1011
1012 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
1013 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
1014 if (!bits && !first_empty_slot)
1015 first_empty_slot = regindex;
1016 else if ((bits & 0x0FFF) == vlan)
1017 break;
1018 }
1019
1020 if (regindex >= IXGBE_VLVF_ENTRIES) {
1021 if (first_empty_slot)
1022 regindex = first_empty_slot;
1023 else {
1024 hw_dbg(hw, "No space in VLVF.\n");
1025 goto out;
1026 }
1027 }
1028
1029 if (vlan_on) {
1030 /* set the pool bit */
1031 if (vind < 32) {
1032 bits = IXGBE_READ_REG(hw,
1033 IXGBE_VLVFB(regindex * 2));
1034 bits |= (1 << vind);
1035 IXGBE_WRITE_REG(hw,
1036 IXGBE_VLVFB(regindex * 2), bits);
1037 } else {
1038 bits = IXGBE_READ_REG(hw,
1039 IXGBE_VLVFB((regindex * 2) + 1));
1040 bits |= (1 << vind);
1041 IXGBE_WRITE_REG(hw,
1042 IXGBE_VLVFB((regindex * 2) + 1), bits);
1043 }
1044 } else {
1045 /* clear the pool bit */
1046 if (vind < 32) {
1047 bits = IXGBE_READ_REG(hw,
1048 IXGBE_VLVFB(regindex * 2));
1049 bits &= ~(1 << vind);
1050 IXGBE_WRITE_REG(hw,
1051 IXGBE_VLVFB(regindex * 2), bits);
1052 bits |= IXGBE_READ_REG(hw,
1053 IXGBE_VLVFB((regindex * 2) + 1));
1054 } else {
1055 bits = IXGBE_READ_REG(hw,
1056 IXGBE_VLVFB((regindex * 2) + 1));
1057 bits &= ~(1 << vind);
1058 IXGBE_WRITE_REG(hw,
1059 IXGBE_VLVFB((regindex * 2) + 1), bits);
1060 bits |= IXGBE_READ_REG(hw,
1061 IXGBE_VLVFB(regindex * 2));
1062 }
1063 }
1064
1065 if (bits)
1066 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex),
1067 (IXGBE_VLVF_VIEN | vlan));
1068 else
1069 IXGBE_WRITE_REG(hw, IXGBE_VLVF(regindex), 0);
1070 }
1071
1072 out:
1073 return 0;
1074 }
1075
1076 /**
1077 * ixgbe_clear_vfta_82599 - Clear VLAN filter table
1078 * @hw: pointer to hardware structure
1079 *
1080 * Clears the VLAN filer table, and the VMDq index associated with the filter
1081 **/
1082 static s32 ixgbe_clear_vfta_82599(struct ixgbe_hw *hw)
1083 {
1084 u32 offset;
1085
1086 for (offset = 0; offset < hw->mac.vft_size; offset++)
1087 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1088
1089 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
1090 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
1091 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
1092 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
1093 }
1094
1095 return 0;
1096 }
1097
1098 /**
1099 * ixgbe_init_uta_tables_82599 - Initialize the Unicast Table Array
1100 * @hw: pointer to hardware structure
1101 **/
1102 static s32 ixgbe_init_uta_tables_82599(struct ixgbe_hw *hw)
1103 {
1104 int i;
1105 hw_dbg(hw, " Clearing UTA\n");
1106
1107 for (i = 0; i < 128; i++)
1108 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
1109
1110 return 0;
1111 }
1112
1113 /**
1114 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1115 * @hw: pointer to hardware structure
1116 **/
1117 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1118 {
1119 int i;
1120 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1121 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1122
1123 /*
1124 * Before starting reinitialization process,
1125 * FDIRCMD.CMD must be zero.
1126 */
1127 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1128 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1129 IXGBE_FDIRCMD_CMD_MASK))
1130 break;
1131 udelay(10);
1132 }
1133 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1134 hw_dbg(hw ,"Flow Director previous command isn't complete, "
1135 "aborting table re-initialization. \n");
1136 return IXGBE_ERR_FDIR_REINIT_FAILED;
1137 }
1138
1139 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1140 IXGBE_WRITE_FLUSH(hw);
1141 /*
1142 * 82599 adapters flow director init flow cannot be restarted,
1143 * Workaround 82599 silicon errata by performing the following steps
1144 * before re-writing the FDIRCTRL control register with the same value.
1145 * - write 1 to bit 8 of FDIRCMD register &
1146 * - write 0 to bit 8 of FDIRCMD register
1147 */
1148 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1149 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1150 IXGBE_FDIRCMD_CLEARHT));
1151 IXGBE_WRITE_FLUSH(hw);
1152 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1153 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1154 ~IXGBE_FDIRCMD_CLEARHT));
1155 IXGBE_WRITE_FLUSH(hw);
1156 /*
1157 * Clear FDIR Hash register to clear any leftover hashes
1158 * waiting to be programmed.
1159 */
1160 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1161 IXGBE_WRITE_FLUSH(hw);
1162
1163 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1164 IXGBE_WRITE_FLUSH(hw);
1165
1166 /* Poll init-done after we write FDIRCTRL register */
1167 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1168 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1169 IXGBE_FDIRCTRL_INIT_DONE)
1170 break;
1171 udelay(10);
1172 }
1173 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1174 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1175 return IXGBE_ERR_FDIR_REINIT_FAILED;
1176 }
1177
1178 /* Clear FDIR statistics registers (read to clear) */
1179 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1180 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1181 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1182 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1183 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1184
1185 return 0;
1186 }
1187
1188 /**
1189 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1190 * @hw: pointer to hardware structure
1191 * @pballoc: which mode to allocate filters with
1192 **/
1193 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1194 {
1195 u32 fdirctrl = 0;
1196 u32 pbsize;
1197 int i;
1198
1199 /*
1200 * Before enabling Flow Director, the Rx Packet Buffer size
1201 * must be reduced. The new value is the current size minus
1202 * flow director memory usage size.
1203 */
1204 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1205 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1206 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1207
1208 /*
1209 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1210 * intialized to zero for non DCB mode otherwise actual total RX PB
1211 * would be bigger than programmed and filter space would run into
1212 * the PB 0 region.
1213 */
1214 for (i = 1; i < 8; i++)
1215 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1216
1217 /* Send interrupt when 64 filters are left */
1218 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1219
1220 /* Set the maximum length per hash bucket to 0xA filters */
1221 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1222
1223 switch (pballoc) {
1224 case IXGBE_FDIR_PBALLOC_64K:
1225 /* 8k - 1 signature filters */
1226 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1227 break;
1228 case IXGBE_FDIR_PBALLOC_128K:
1229 /* 16k - 1 signature filters */
1230 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1231 break;
1232 case IXGBE_FDIR_PBALLOC_256K:
1233 /* 32k - 1 signature filters */
1234 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1235 break;
1236 default:
1237 /* bad value */
1238 return IXGBE_ERR_CONFIG;
1239 };
1240
1241 /* Move the flexible bytes to use the ethertype - shift 6 words */
1242 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1243
1244 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1245
1246 /* Prime the keys for hashing */
1247 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1248 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1249 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1250 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1251
1252 /*
1253 * Poll init-done after we write the register. Estimated times:
1254 * 10G: PBALLOC = 11b, timing is 60us
1255 * 1G: PBALLOC = 11b, timing is 600us
1256 * 100M: PBALLOC = 11b, timing is 6ms
1257 *
1258 * Multiple these timings by 4 if under full Rx load
1259 *
1260 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1261 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1262 * this might not finish in our poll time, but we can live with that
1263 * for now.
1264 */
1265 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1266 IXGBE_WRITE_FLUSH(hw);
1267 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1268 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1269 IXGBE_FDIRCTRL_INIT_DONE)
1270 break;
1271 msleep(1);
1272 }
1273 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1274 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1275
1276 return 0;
1277 }
1278
1279 /**
1280 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1281 * @hw: pointer to hardware structure
1282 * @pballoc: which mode to allocate filters with
1283 **/
1284 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1285 {
1286 u32 fdirctrl = 0;
1287 u32 pbsize;
1288 int i;
1289
1290 /*
1291 * Before enabling Flow Director, the Rx Packet Buffer size
1292 * must be reduced. The new value is the current size minus
1293 * flow director memory usage size.
1294 */
1295 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1296 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1297 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1298
1299 /*
1300 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1301 * intialized to zero for non DCB mode otherwise actual total RX PB
1302 * would be bigger than programmed and filter space would run into
1303 * the PB 0 region.
1304 */
1305 for (i = 1; i < 8; i++)
1306 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1307
1308 /* Send interrupt when 64 filters are left */
1309 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1310
1311 switch (pballoc) {
1312 case IXGBE_FDIR_PBALLOC_64K:
1313 /* 2k - 1 perfect filters */
1314 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1315 break;
1316 case IXGBE_FDIR_PBALLOC_128K:
1317 /* 4k - 1 perfect filters */
1318 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1319 break;
1320 case IXGBE_FDIR_PBALLOC_256K:
1321 /* 8k - 1 perfect filters */
1322 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1323 break;
1324 default:
1325 /* bad value */
1326 return IXGBE_ERR_CONFIG;
1327 };
1328
1329 /* Turn perfect match filtering on */
1330 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1331 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1332
1333 /* Move the flexible bytes to use the ethertype - shift 6 words */
1334 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1335
1336 /* Prime the keys for hashing */
1337 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY,
1338 htonl(IXGBE_ATR_BUCKET_HASH_KEY));
1339 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY,
1340 htonl(IXGBE_ATR_SIGNATURE_HASH_KEY));
1341
1342 /*
1343 * Poll init-done after we write the register. Estimated times:
1344 * 10G: PBALLOC = 11b, timing is 60us
1345 * 1G: PBALLOC = 11b, timing is 600us
1346 * 100M: PBALLOC = 11b, timing is 6ms
1347 *
1348 * Multiple these timings by 4 if under full Rx load
1349 *
1350 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1351 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1352 * this might not finish in our poll time, but we can live with that
1353 * for now.
1354 */
1355
1356 /* Set the maximum length per hash bucket to 0xA filters */
1357 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1358
1359 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1360 IXGBE_WRITE_FLUSH(hw);
1361 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1362 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1363 IXGBE_FDIRCTRL_INIT_DONE)
1364 break;
1365 msleep(1);
1366 }
1367 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1368 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1369
1370 return 0;
1371 }
1372
1373
1374 /**
1375 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1376 * @stream: input bitstream to compute the hash on
1377 * @key: 32-bit hash key
1378 **/
1379 static u16 ixgbe_atr_compute_hash_82599(struct ixgbe_atr_input *atr_input,
1380 u32 key)
1381 {
1382 /*
1383 * The algorithm is as follows:
1384 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1385 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1386 * and A[n] x B[n] is bitwise AND between same length strings
1387 *
1388 * K[n] is 16 bits, defined as:
1389 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1390 * for n modulo 32 < 15, K[n] =
1391 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1392 *
1393 * S[n] is 16 bits, defined as:
1394 * for n >= 15, S[n] = S[n:n - 15]
1395 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1396 *
1397 * To simplify for programming, the algorithm is implemented
1398 * in software this way:
1399 *
1400 * Key[31:0], Stream[335:0]
1401 *
1402 * tmp_key[11 * 32 - 1:0] = 11{Key[31:0] = key concatenated 11 times
1403 * int_key[350:0] = tmp_key[351:1]
1404 * int_stream[365:0] = Stream[14:0] | Stream[335:0] | Stream[335:321]
1405 *
1406 * hash[15:0] = 0;
1407 * for (i = 0; i < 351; i++) {
1408 * if (int_key[i])
1409 * hash ^= int_stream[(i + 15):i];
1410 * }
1411 */
1412
1413 union {
1414 u64 fill[6];
1415 u32 key[11];
1416 u8 key_stream[44];
1417 } tmp_key;
1418
1419 u8 *stream = (u8 *)atr_input;
1420 u8 int_key[44]; /* upper-most bit unused */
1421 u8 hash_str[46]; /* upper-most 2 bits unused */
1422 u16 hash_result = 0;
1423 int i, j, k, h;
1424
1425 /*
1426 * Initialize the fill member to prevent warnings
1427 * on some compilers
1428 */
1429 tmp_key.fill[0] = 0;
1430
1431 /* First load the temporary key stream */
1432 for (i = 0; i < 6; i++) {
1433 u64 fillkey = ((u64)key << 32) | key;
1434 tmp_key.fill[i] = fillkey;
1435 }
1436
1437 /*
1438 * Set the interim key for the hashing. Bit 352 is unused, so we must
1439 * shift and compensate when building the key.
1440 */
1441
1442 int_key[0] = tmp_key.key_stream[0] >> 1;
1443 for (i = 1, j = 0; i < 44; i++) {
1444 unsigned int this_key = tmp_key.key_stream[j] << 7;
1445 j++;
1446 int_key[i] = (u8)(this_key | (tmp_key.key_stream[j] >> 1));
1447 }
1448
1449 /*
1450 * Set the interim bit string for the hashing. Bits 368 and 367 are
1451 * unused, so shift and compensate when building the string.
1452 */
1453 hash_str[0] = (stream[40] & 0x7f) >> 1;
1454 for (i = 1, j = 40; i < 46; i++) {
1455 unsigned int this_str = stream[j] << 7;
1456 j++;
1457 if (j > 41)
1458 j = 0;
1459 hash_str[i] = (u8)(this_str | (stream[j] >> 1));
1460 }
1461
1462 /*
1463 * Now compute the hash. i is the index into hash_str, j is into our
1464 * key stream, k is counting the number of bits, and h interates within
1465 * each byte.
1466 */
1467 for (i = 45, j = 43, k = 0; k < 351 && i >= 2 && j >= 0; i--, j--) {
1468 for (h = 0; h < 8 && k < 351; h++, k++) {
1469 if (int_key[j] & (1 << h)) {
1470 /*
1471 * Key bit is set, XOR in the current 16-bit
1472 * string. Example of processing:
1473 * h = 0,
1474 * tmp = (hash_str[i - 2] & 0 << 16) |
1475 * (hash_str[i - 1] & 0xff << 8) |
1476 * (hash_str[i] & 0xff >> 0)
1477 * So tmp = hash_str[15 + k:k], since the
1478 * i + 2 clause rolls off the 16-bit value
1479 * h = 7,
1480 * tmp = (hash_str[i - 2] & 0x7f << 9) |
1481 * (hash_str[i - 1] & 0xff << 1) |
1482 * (hash_str[i] & 0x80 >> 7)
1483 */
1484 int tmp = (hash_str[i] >> h);
1485 tmp |= (hash_str[i - 1] << (8 - h));
1486 tmp |= (int)(hash_str[i - 2] & ((1 << h) - 1))
1487 << (16 - h);
1488 hash_result ^= (u16)tmp;
1489 }
1490 }
1491 }
1492
1493 return hash_result;
1494 }
1495
1496 /**
1497 * ixgbe_atr_set_vlan_id_82599 - Sets the VLAN id in the ATR input stream
1498 * @input: input stream to modify
1499 * @vlan: the VLAN id to load
1500 **/
1501 s32 ixgbe_atr_set_vlan_id_82599(struct ixgbe_atr_input *input, u16 vlan)
1502 {
1503 input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] = vlan >> 8;
1504 input->byte_stream[IXGBE_ATR_VLAN_OFFSET] = vlan & 0xff;
1505
1506 return 0;
1507 }
1508
1509 /**
1510 * ixgbe_atr_set_src_ipv4_82599 - Sets the source IPv4 address
1511 * @input: input stream to modify
1512 * @src_addr: the IP address to load
1513 **/
1514 s32 ixgbe_atr_set_src_ipv4_82599(struct ixgbe_atr_input *input, u32 src_addr)
1515 {
1516 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] = src_addr >> 24;
1517 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] =
1518 (src_addr >> 16) & 0xff;
1519 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] =
1520 (src_addr >> 8) & 0xff;
1521 input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET] = src_addr & 0xff;
1522
1523 return 0;
1524 }
1525
1526 /**
1527 * ixgbe_atr_set_dst_ipv4_82599 - Sets the destination IPv4 address
1528 * @input: input stream to modify
1529 * @dst_addr: the IP address to load
1530 **/
1531 s32 ixgbe_atr_set_dst_ipv4_82599(struct ixgbe_atr_input *input, u32 dst_addr)
1532 {
1533 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] = dst_addr >> 24;
1534 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] =
1535 (dst_addr >> 16) & 0xff;
1536 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] =
1537 (dst_addr >> 8) & 0xff;
1538 input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET] = dst_addr & 0xff;
1539
1540 return 0;
1541 }
1542
1543 /**
1544 * ixgbe_atr_set_src_ipv6_82599 - Sets the source IPv6 address
1545 * @input: input stream to modify
1546 * @src_addr_1: the first 4 bytes of the IP address to load
1547 * @src_addr_2: the second 4 bytes of the IP address to load
1548 * @src_addr_3: the third 4 bytes of the IP address to load
1549 * @src_addr_4: the fourth 4 bytes of the IP address to load
1550 **/
1551 s32 ixgbe_atr_set_src_ipv6_82599(struct ixgbe_atr_input *input,
1552 u32 src_addr_1, u32 src_addr_2,
1553 u32 src_addr_3, u32 src_addr_4)
1554 {
1555 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET] = src_addr_4 & 0xff;
1556 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] =
1557 (src_addr_4 >> 8) & 0xff;
1558 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] =
1559 (src_addr_4 >> 16) & 0xff;
1560 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] = src_addr_4 >> 24;
1561
1562 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4] = src_addr_3 & 0xff;
1563 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] =
1564 (src_addr_3 >> 8) & 0xff;
1565 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] =
1566 (src_addr_3 >> 16) & 0xff;
1567 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] = src_addr_3 >> 24;
1568
1569 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8] = src_addr_2 & 0xff;
1570 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] =
1571 (src_addr_2 >> 8) & 0xff;
1572 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] =
1573 (src_addr_2 >> 16) & 0xff;
1574 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] = src_addr_2 >> 24;
1575
1576 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12] = src_addr_1 & 0xff;
1577 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] =
1578 (src_addr_1 >> 8) & 0xff;
1579 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] =
1580 (src_addr_1 >> 16) & 0xff;
1581 input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] = src_addr_1 >> 24;
1582
1583 return 0;
1584 }
1585
1586 /**
1587 * ixgbe_atr_set_dst_ipv6_82599 - Sets the destination IPv6 address
1588 * @input: input stream to modify
1589 * @dst_addr_1: the first 4 bytes of the IP address to load
1590 * @dst_addr_2: the second 4 bytes of the IP address to load
1591 * @dst_addr_3: the third 4 bytes of the IP address to load
1592 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1593 **/
1594 s32 ixgbe_atr_set_dst_ipv6_82599(struct ixgbe_atr_input *input,
1595 u32 dst_addr_1, u32 dst_addr_2,
1596 u32 dst_addr_3, u32 dst_addr_4)
1597 {
1598 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET] = dst_addr_4 & 0xff;
1599 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] =
1600 (dst_addr_4 >> 8) & 0xff;
1601 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] =
1602 (dst_addr_4 >> 16) & 0xff;
1603 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] = dst_addr_4 >> 24;
1604
1605 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4] = dst_addr_3 & 0xff;
1606 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] =
1607 (dst_addr_3 >> 8) & 0xff;
1608 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] =
1609 (dst_addr_3 >> 16) & 0xff;
1610 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] = dst_addr_3 >> 24;
1611
1612 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8] = dst_addr_2 & 0xff;
1613 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] =
1614 (dst_addr_2 >> 8) & 0xff;
1615 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] =
1616 (dst_addr_2 >> 16) & 0xff;
1617 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] = dst_addr_2 >> 24;
1618
1619 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12] = dst_addr_1 & 0xff;
1620 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] =
1621 (dst_addr_1 >> 8) & 0xff;
1622 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] =
1623 (dst_addr_1 >> 16) & 0xff;
1624 input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] = dst_addr_1 >> 24;
1625
1626 return 0;
1627 }
1628
1629 /**
1630 * ixgbe_atr_set_src_port_82599 - Sets the source port
1631 * @input: input stream to modify
1632 * @src_port: the source port to load
1633 **/
1634 s32 ixgbe_atr_set_src_port_82599(struct ixgbe_atr_input *input, u16 src_port)
1635 {
1636 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1] = src_port >> 8;
1637 input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] = src_port & 0xff;
1638
1639 return 0;
1640 }
1641
1642 /**
1643 * ixgbe_atr_set_dst_port_82599 - Sets the destination port
1644 * @input: input stream to modify
1645 * @dst_port: the destination port to load
1646 **/
1647 s32 ixgbe_atr_set_dst_port_82599(struct ixgbe_atr_input *input, u16 dst_port)
1648 {
1649 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1] = dst_port >> 8;
1650 input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] = dst_port & 0xff;
1651
1652 return 0;
1653 }
1654
1655 /**
1656 * ixgbe_atr_set_flex_byte_82599 - Sets the flexible bytes
1657 * @input: input stream to modify
1658 * @flex_bytes: the flexible bytes to load
1659 **/
1660 s32 ixgbe_atr_set_flex_byte_82599(struct ixgbe_atr_input *input, u16 flex_byte)
1661 {
1662 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] = flex_byte >> 8;
1663 input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET] = flex_byte & 0xff;
1664
1665 return 0;
1666 }
1667
1668 /**
1669 * ixgbe_atr_set_vm_pool_82599 - Sets the Virtual Machine pool
1670 * @input: input stream to modify
1671 * @vm_pool: the Virtual Machine pool to load
1672 **/
1673 s32 ixgbe_atr_set_vm_pool_82599(struct ixgbe_atr_input *input,
1674 u8 vm_pool)
1675 {
1676 input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET] = vm_pool;
1677
1678 return 0;
1679 }
1680
1681 /**
1682 * ixgbe_atr_set_l4type_82599 - Sets the layer 4 packet type
1683 * @input: input stream to modify
1684 * @l4type: the layer 4 type value to load
1685 **/
1686 s32 ixgbe_atr_set_l4type_82599(struct ixgbe_atr_input *input, u8 l4type)
1687 {
1688 input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET] = l4type;
1689
1690 return 0;
1691 }
1692
1693 /**
1694 * ixgbe_atr_get_vlan_id_82599 - Gets the VLAN id from the ATR input stream
1695 * @input: input stream to search
1696 * @vlan: the VLAN id to load
1697 **/
1698 static s32 ixgbe_atr_get_vlan_id_82599(struct ixgbe_atr_input *input,
1699 u16 *vlan)
1700 {
1701 *vlan = input->byte_stream[IXGBE_ATR_VLAN_OFFSET];
1702 *vlan |= input->byte_stream[IXGBE_ATR_VLAN_OFFSET + 1] << 8;
1703
1704 return 0;
1705 }
1706
1707 /**
1708 * ixgbe_atr_get_src_ipv4_82599 - Gets the source IPv4 address
1709 * @input: input stream to search
1710 * @src_addr: the IP address to load
1711 **/
1712 static s32 ixgbe_atr_get_src_ipv4_82599(struct ixgbe_atr_input *input,
1713 u32 *src_addr)
1714 {
1715 *src_addr = input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET];
1716 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 1] << 8;
1717 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 2] << 16;
1718 *src_addr |= input->byte_stream[IXGBE_ATR_SRC_IPV4_OFFSET + 3] << 24;
1719
1720 return 0;
1721 }
1722
1723 /**
1724 * ixgbe_atr_get_dst_ipv4_82599 - Gets the destination IPv4 address
1725 * @input: input stream to search
1726 * @dst_addr: the IP address to load
1727 **/
1728 static s32 ixgbe_atr_get_dst_ipv4_82599(struct ixgbe_atr_input *input,
1729 u32 *dst_addr)
1730 {
1731 *dst_addr = input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET];
1732 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 1] << 8;
1733 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 2] << 16;
1734 *dst_addr |= input->byte_stream[IXGBE_ATR_DST_IPV4_OFFSET + 3] << 24;
1735
1736 return 0;
1737 }
1738
1739 /**
1740 * ixgbe_atr_get_src_ipv6_82599 - Gets the source IPv6 address
1741 * @input: input stream to search
1742 * @src_addr_1: the first 4 bytes of the IP address to load
1743 * @src_addr_2: the second 4 bytes of the IP address to load
1744 * @src_addr_3: the third 4 bytes of the IP address to load
1745 * @src_addr_4: the fourth 4 bytes of the IP address to load
1746 **/
1747 static s32 ixgbe_atr_get_src_ipv6_82599(struct ixgbe_atr_input *input,
1748 u32 *src_addr_1, u32 *src_addr_2,
1749 u32 *src_addr_3, u32 *src_addr_4)
1750 {
1751 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 12];
1752 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 13] << 8;
1753 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 14] << 16;
1754 *src_addr_1 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 15] << 24;
1755
1756 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 8];
1757 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 9] << 8;
1758 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 10] << 16;
1759 *src_addr_2 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 11] << 24;
1760
1761 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 4];
1762 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 5] << 8;
1763 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 6] << 16;
1764 *src_addr_3 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 7] << 24;
1765
1766 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET];
1767 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 1] << 8;
1768 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 2] << 16;
1769 *src_addr_4 = input->byte_stream[IXGBE_ATR_SRC_IPV6_OFFSET + 3] << 24;
1770
1771 return 0;
1772 }
1773
1774 /**
1775 * ixgbe_atr_get_dst_ipv6_82599 - Gets the destination IPv6 address
1776 * @input: input stream to search
1777 * @dst_addr_1: the first 4 bytes of the IP address to load
1778 * @dst_addr_2: the second 4 bytes of the IP address to load
1779 * @dst_addr_3: the third 4 bytes of the IP address to load
1780 * @dst_addr_4: the fourth 4 bytes of the IP address to load
1781 **/
1782 s32 ixgbe_atr_get_dst_ipv6_82599(struct ixgbe_atr_input *input,
1783 u32 *dst_addr_1, u32 *dst_addr_2,
1784 u32 *dst_addr_3, u32 *dst_addr_4)
1785 {
1786 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 12];
1787 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 13] << 8;
1788 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 14] << 16;
1789 *dst_addr_1 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 15] << 24;
1790
1791 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 8];
1792 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 9] << 8;
1793 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 10] << 16;
1794 *dst_addr_2 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 11] << 24;
1795
1796 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 4];
1797 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 5] << 8;
1798 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 6] << 16;
1799 *dst_addr_3 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 7] << 24;
1800
1801 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET];
1802 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 1] << 8;
1803 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 2] << 16;
1804 *dst_addr_4 = input->byte_stream[IXGBE_ATR_DST_IPV6_OFFSET + 3] << 24;
1805
1806 return 0;
1807 }
1808
1809 /**
1810 * ixgbe_atr_get_src_port_82599 - Gets the source port
1811 * @input: input stream to modify
1812 * @src_port: the source port to load
1813 *
1814 * Even though the input is given in big-endian, the FDIRPORT registers
1815 * expect the ports to be programmed in little-endian. Hence the need to swap
1816 * endianness when retrieving the data. This can be confusing since the
1817 * internal hash engine expects it to be big-endian.
1818 **/
1819 static s32 ixgbe_atr_get_src_port_82599(struct ixgbe_atr_input *input,
1820 u16 *src_port)
1821 {
1822 *src_port = input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET] << 8;
1823 *src_port |= input->byte_stream[IXGBE_ATR_SRC_PORT_OFFSET + 1];
1824
1825 return 0;
1826 }
1827
1828 /**
1829 * ixgbe_atr_get_dst_port_82599 - Gets the destination port
1830 * @input: input stream to modify
1831 * @dst_port: the destination port to load
1832 *
1833 * Even though the input is given in big-endian, the FDIRPORT registers
1834 * expect the ports to be programmed in little-endian. Hence the need to swap
1835 * endianness when retrieving the data. This can be confusing since the
1836 * internal hash engine expects it to be big-endian.
1837 **/
1838 static s32 ixgbe_atr_get_dst_port_82599(struct ixgbe_atr_input *input,
1839 u16 *dst_port)
1840 {
1841 *dst_port = input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET] << 8;
1842 *dst_port |= input->byte_stream[IXGBE_ATR_DST_PORT_OFFSET + 1];
1843
1844 return 0;
1845 }
1846
1847 /**
1848 * ixgbe_atr_get_flex_byte_82599 - Gets the flexible bytes
1849 * @input: input stream to modify
1850 * @flex_bytes: the flexible bytes to load
1851 **/
1852 static s32 ixgbe_atr_get_flex_byte_82599(struct ixgbe_atr_input *input,
1853 u16 *flex_byte)
1854 {
1855 *flex_byte = input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET];
1856 *flex_byte |= input->byte_stream[IXGBE_ATR_FLEX_BYTE_OFFSET + 1] << 8;
1857
1858 return 0;
1859 }
1860
1861 /**
1862 * ixgbe_atr_get_vm_pool_82599 - Gets the Virtual Machine pool
1863 * @input: input stream to modify
1864 * @vm_pool: the Virtual Machine pool to load
1865 **/
1866 s32 ixgbe_atr_get_vm_pool_82599(struct ixgbe_atr_input *input,
1867 u8 *vm_pool)
1868 {
1869 *vm_pool = input->byte_stream[IXGBE_ATR_VM_POOL_OFFSET];
1870
1871 return 0;
1872 }
1873
1874 /**
1875 * ixgbe_atr_get_l4type_82599 - Gets the layer 4 packet type
1876 * @input: input stream to modify
1877 * @l4type: the layer 4 type value to load
1878 **/
1879 static s32 ixgbe_atr_get_l4type_82599(struct ixgbe_atr_input *input,
1880 u8 *l4type)
1881 {
1882 *l4type = input->byte_stream[IXGBE_ATR_L4TYPE_OFFSET];
1883
1884 return 0;
1885 }
1886
1887 /**
1888 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1889 * @hw: pointer to hardware structure
1890 * @stream: input bitstream
1891 * @queue: queue index to direct traffic to
1892 **/
1893 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1894 struct ixgbe_atr_input *input,
1895 u8 queue)
1896 {
1897 u64 fdirhashcmd;
1898 u64 fdircmd;
1899 u32 fdirhash;
1900 u16 bucket_hash, sig_hash;
1901 u8 l4type;
1902
1903 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1904 IXGBE_ATR_BUCKET_HASH_KEY);
1905
1906 /* bucket_hash is only 15 bits */
1907 bucket_hash &= IXGBE_ATR_HASH_MASK;
1908
1909 sig_hash = ixgbe_atr_compute_hash_82599(input,
1910 IXGBE_ATR_SIGNATURE_HASH_KEY);
1911
1912 /* Get the l4type in order to program FDIRCMD properly */
1913 /* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6 */
1914 ixgbe_atr_get_l4type_82599(input, &l4type);
1915
1916 /*
1917 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1918 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1919 */
1920 fdirhash = sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
1921
1922 fdircmd = (IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1923 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN);
1924
1925 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1926 case IXGBE_ATR_L4TYPE_TCP:
1927 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1928 break;
1929 case IXGBE_ATR_L4TYPE_UDP:
1930 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1931 break;
1932 case IXGBE_ATR_L4TYPE_SCTP:
1933 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1934 break;
1935 default:
1936 hw_dbg(hw, "Error on l4type input\n");
1937 return IXGBE_ERR_CONFIG;
1938 }
1939
1940 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK)
1941 fdircmd |= IXGBE_FDIRCMD_IPV6;
1942
1943 fdircmd |= ((u64)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT);
1944 fdirhashcmd = ((fdircmd << 32) | fdirhash);
1945
1946 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1947
1948 return 0;
1949 }
1950
1951 /**
1952 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1953 * @hw: pointer to hardware structure
1954 * @input: input bitstream
1955 * @queue: queue index to direct traffic to
1956 *
1957 * Note that the caller to this function must lock before calling, since the
1958 * hardware writes must be protected from one another.
1959 **/
1960 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1961 struct ixgbe_atr_input *input,
1962 u16 soft_id,
1963 u8 queue)
1964 {
1965 u32 fdircmd = 0;
1966 u32 fdirhash;
1967 u32 src_ipv4, dst_ipv4;
1968 u32 src_ipv6_1, src_ipv6_2, src_ipv6_3, src_ipv6_4;
1969 u16 src_port, dst_port, vlan_id, flex_bytes;
1970 u16 bucket_hash;
1971 u8 l4type;
1972
1973 /* Get our input values */
1974 ixgbe_atr_get_l4type_82599(input, &l4type);
1975
1976 /*
1977 * Check l4type formatting, and bail out before we touch the hardware
1978 * if there's a configuration issue
1979 */
1980 switch (l4type & IXGBE_ATR_L4TYPE_MASK) {
1981 case IXGBE_ATR_L4TYPE_TCP:
1982 fdircmd |= IXGBE_FDIRCMD_L4TYPE_TCP;
1983 break;
1984 case IXGBE_ATR_L4TYPE_UDP:
1985 fdircmd |= IXGBE_FDIRCMD_L4TYPE_UDP;
1986 break;
1987 case IXGBE_ATR_L4TYPE_SCTP:
1988 fdircmd |= IXGBE_FDIRCMD_L4TYPE_SCTP;
1989 break;
1990 default:
1991 hw_dbg(hw, "Error on l4type input\n");
1992 return IXGBE_ERR_CONFIG;
1993 }
1994
1995 bucket_hash = ixgbe_atr_compute_hash_82599(input,
1996 IXGBE_ATR_BUCKET_HASH_KEY);
1997
1998 /* bucket_hash is only 15 bits */
1999 bucket_hash &= IXGBE_ATR_HASH_MASK;
2000
2001 ixgbe_atr_get_vlan_id_82599(input, &vlan_id);
2002 ixgbe_atr_get_src_port_82599(input, &src_port);
2003 ixgbe_atr_get_dst_port_82599(input, &dst_port);
2004 ixgbe_atr_get_flex_byte_82599(input, &flex_bytes);
2005
2006 fdirhash = soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT | bucket_hash;
2007
2008 /* Now figure out if we're IPv4 or IPv6 */
2009 if (l4type & IXGBE_ATR_L4TYPE_IPV6_MASK) {
2010 /* IPv6 */
2011 ixgbe_atr_get_src_ipv6_82599(input, &src_ipv6_1, &src_ipv6_2,
2012 &src_ipv6_3, &src_ipv6_4);
2013
2014 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), src_ipv6_1);
2015 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), src_ipv6_2);
2016 IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), src_ipv6_3);
2017 /* The last 4 bytes is the same register as IPv4 */
2018 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv6_4);
2019
2020 fdircmd |= IXGBE_FDIRCMD_IPV6;
2021 fdircmd |= IXGBE_FDIRCMD_IPv6DMATCH;
2022 } else {
2023 /* IPv4 */
2024 ixgbe_atr_get_src_ipv4_82599(input, &src_ipv4);
2025 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPSA, src_ipv4);
2026
2027 }
2028
2029 ixgbe_atr_get_dst_ipv4_82599(input, &dst_ipv4);
2030 IXGBE_WRITE_REG(hw, IXGBE_FDIRIPDA, dst_ipv4);
2031
2032 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, (vlan_id |
2033 (flex_bytes << IXGBE_FDIRVLAN_FLEX_SHIFT)));
2034 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, (src_port |
2035 (dst_port << IXGBE_FDIRPORT_DESTINATION_SHIFT)));
2036
2037 fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW;
2038 fdircmd |= IXGBE_FDIRCMD_FILTER_UPDATE;
2039 fdircmd |= IXGBE_FDIRCMD_LAST;
2040 fdircmd |= IXGBE_FDIRCMD_QUEUE_EN;
2041 fdircmd |= queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
2042
2043 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
2044 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
2045
2046 return 0;
2047 }
2048 /**
2049 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2050 * @hw: pointer to hardware structure
2051 * @reg: analog register to read
2052 * @val: read value
2053 *
2054 * Performs read operation to Omer analog register specified.
2055 **/
2056 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
2057 {
2058 u32 core_ctl;
2059
2060 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2061 (reg << 8));
2062 IXGBE_WRITE_FLUSH(hw);
2063 udelay(10);
2064 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2065 *val = (u8)core_ctl;
2066
2067 return 0;
2068 }
2069
2070 /**
2071 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2072 * @hw: pointer to hardware structure
2073 * @reg: atlas register to write
2074 * @val: value to write
2075 *
2076 * Performs write operation to Omer analog register specified.
2077 **/
2078 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
2079 {
2080 u32 core_ctl;
2081
2082 core_ctl = (reg << 8) | val;
2083 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2084 IXGBE_WRITE_FLUSH(hw);
2085 udelay(10);
2086
2087 return 0;
2088 }
2089
2090 /**
2091 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2092 * @hw: pointer to hardware structure
2093 *
2094 * Starts the hardware using the generic start_hw function.
2095 * Then performs device-specific:
2096 * Clears the rate limiter registers.
2097 **/
2098 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
2099 {
2100 u32 q_num;
2101 s32 ret_val;
2102
2103 ret_val = ixgbe_start_hw_generic(hw);
2104
2105 /* Clear the rate limiters */
2106 for (q_num = 0; q_num < hw->mac.max_tx_queues; q_num++) {
2107 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, q_num);
2108 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
2109 }
2110 IXGBE_WRITE_FLUSH(hw);
2111
2112 /* We need to run link autotry after the driver loads */
2113 hw->mac.autotry_restart = true;
2114
2115 if (ret_val == 0)
2116 ret_val = ixgbe_verify_fw_version_82599(hw);
2117
2118 return ret_val;
2119 }
2120
2121 /**
2122 * ixgbe_identify_phy_82599 - Get physical layer module
2123 * @hw: pointer to hardware structure
2124 *
2125 * Determines the physical layer module found on the current adapter.
2126 **/
2127 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2128 {
2129 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
2130 status = ixgbe_identify_phy_generic(hw);
2131 if (status != 0)
2132 status = ixgbe_identify_sfp_module_generic(hw);
2133 return status;
2134 }
2135
2136 /**
2137 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2138 * @hw: pointer to hardware structure
2139 *
2140 * Determines physical layer capabilities of the current configuration.
2141 **/
2142 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2143 {
2144 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2145 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2146 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2147 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2148 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2149 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2150 u16 ext_ability = 0;
2151 u8 comp_codes_10g = 0;
2152
2153 hw->phy.ops.identify(hw);
2154
2155 if (hw->phy.type == ixgbe_phy_tn ||
2156 hw->phy.type == ixgbe_phy_cu_unknown) {
2157 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
2158 &ext_ability);
2159 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
2160 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2161 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
2162 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2163 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
2164 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2165 goto out;
2166 }
2167
2168 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2169 case IXGBE_AUTOC_LMS_1G_AN:
2170 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2171 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2172 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2173 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2174 goto out;
2175 } else
2176 /* SFI mode so read SFP module */
2177 goto sfp_check;
2178 break;
2179 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2180 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2181 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2182 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2183 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2184 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2185 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2186 goto out;
2187 break;
2188 case IXGBE_AUTOC_LMS_10G_SERIAL:
2189 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2190 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2191 goto out;
2192 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2193 goto sfp_check;
2194 break;
2195 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2196 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2197 if (autoc & IXGBE_AUTOC_KX_SUPP)
2198 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2199 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2200 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2201 if (autoc & IXGBE_AUTOC_KR_SUPP)
2202 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2203 goto out;
2204 break;
2205 default:
2206 goto out;
2207 break;
2208 }
2209
2210 sfp_check:
2211 /* SFP check must be done last since DA modules are sometimes used to
2212 * test KR mode - we need to id KR mode correctly before SFP module.
2213 * Call identify_sfp because the pluggable module may have changed */
2214 hw->phy.ops.identify_sfp(hw);
2215 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2216 goto out;
2217
2218 switch (hw->phy.type) {
2219 case ixgbe_phy_tw_tyco:
2220 case ixgbe_phy_tw_unknown:
2221 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2222 break;
2223 case ixgbe_phy_sfp_avago:
2224 case ixgbe_phy_sfp_ftl:
2225 case ixgbe_phy_sfp_intel:
2226 case ixgbe_phy_sfp_unknown:
2227 hw->phy.ops.read_i2c_eeprom(hw,
2228 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2229 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2230 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2231 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2232 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2233 break;
2234 default:
2235 break;
2236 }
2237
2238 out:
2239 return physical_layer;
2240 }
2241
2242 /**
2243 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2244 * @hw: pointer to hardware structure
2245 * @regval: register value to write to RXCTRL
2246 *
2247 * Enables the Rx DMA unit for 82599
2248 **/
2249 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2250 {
2251 #define IXGBE_MAX_SECRX_POLL 30
2252 int i;
2253 int secrxreg;
2254
2255 /*
2256 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2257 * If traffic is incoming before we enable the Rx unit, it could hang
2258 * the Rx DMA unit. Therefore, make sure the security engine is
2259 * completely disabled prior to enabling the Rx unit.
2260 */
2261 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2262 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2263 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2264 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2265 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2266 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2267 break;
2268 else
2269 udelay(10);
2270 }
2271
2272 /* For informational purposes only */
2273 if (i >= IXGBE_MAX_SECRX_POLL)
2274 hw_dbg(hw, "Rx unit being enabled before security "
2275 "path fully disabled. Continuing with init.\n");
2276
2277 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2278 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2279 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2280 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2281 IXGBE_WRITE_FLUSH(hw);
2282
2283 return 0;
2284 }
2285
2286 /**
2287 * ixgbe_get_device_caps_82599 - Get additional device capabilities
2288 * @hw: pointer to hardware structure
2289 * @device_caps: the EEPROM word with the extra device capabilities
2290 *
2291 * This function will read the EEPROM location for the device capabilities,
2292 * and return the word through device_caps.
2293 **/
2294 static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
2295 {
2296 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
2297
2298 return 0;
2299 }
2300
2301 /**
2302 * ixgbe_get_san_mac_addr_offset_82599 - SAN MAC address offset for 82599
2303 * @hw: pointer to hardware structure
2304 * @san_mac_offset: SAN MAC address offset
2305 *
2306 * This function will read the EEPROM location for the SAN MAC address
2307 * pointer, and returns the value at that location. This is used in both
2308 * get and set mac_addr routines.
2309 **/
2310 static s32 ixgbe_get_san_mac_addr_offset_82599(struct ixgbe_hw *hw,
2311 u16 *san_mac_offset)
2312 {
2313 /*
2314 * First read the EEPROM pointer to see if the MAC addresses are
2315 * available.
2316 */
2317 hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
2318
2319 return 0;
2320 }
2321
2322 /**
2323 * ixgbe_get_san_mac_addr_82599 - SAN MAC address retrieval for 82599
2324 * @hw: pointer to hardware structure
2325 * @san_mac_addr: SAN MAC address
2326 *
2327 * Reads the SAN MAC address from the EEPROM, if it's available. This is
2328 * per-port, so set_lan_id() must be called before reading the addresses.
2329 * set_lan_id() is called by identify_sfp(), but this cannot be relied
2330 * upon for non-SFP connections, so we must call it here.
2331 **/
2332 static s32 ixgbe_get_san_mac_addr_82599(struct ixgbe_hw *hw, u8 *san_mac_addr)
2333 {
2334 u16 san_mac_data, san_mac_offset;
2335 u8 i;
2336
2337 /*
2338 * First read the EEPROM pointer to see if the MAC addresses are
2339 * available. If they're not, no point in calling set_lan_id() here.
2340 */
2341 ixgbe_get_san_mac_addr_offset_82599(hw, &san_mac_offset);
2342
2343 if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
2344 /*
2345 * No addresses available in this EEPROM. It's not an
2346 * error though, so just wipe the local address and return.
2347 */
2348 for (i = 0; i < 6; i++)
2349 san_mac_addr[i] = 0xFF;
2350
2351 goto san_mac_addr_out;
2352 }
2353
2354 /* make sure we know which port we need to program */
2355 hw->mac.ops.set_lan_id(hw);
2356 /* apply the port offset to the address offset */
2357 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
2358 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
2359 for (i = 0; i < 3; i++) {
2360 hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
2361 san_mac_addr[i * 2] = (u8)(san_mac_data);
2362 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
2363 san_mac_offset++;
2364 }
2365
2366 san_mac_addr_out:
2367 return 0;
2368 }
2369
2370 /**
2371 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2372 * @hw: pointer to hardware structure
2373 *
2374 * Verifies that installed the firmware version is 0.6 or higher
2375 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2376 *
2377 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2378 * if the FW version is not supported.
2379 **/
2380 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2381 {
2382 s32 status = IXGBE_ERR_EEPROM_VERSION;
2383 u16 fw_offset, fw_ptp_cfg_offset;
2384 u16 fw_version = 0;
2385
2386 /* firmware check is only necessary for SFI devices */
2387 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2388 status = 0;
2389 goto fw_version_out;
2390 }
2391
2392 /* get the offset to the Firmware Module block */
2393 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2394
2395 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2396 goto fw_version_out;
2397
2398 /* get the offset to the Pass Through Patch Configuration block */
2399 hw->eeprom.ops.read(hw, (fw_offset +
2400 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2401 &fw_ptp_cfg_offset);
2402
2403 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2404 goto fw_version_out;
2405
2406 /* get the firmware version */
2407 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2408 IXGBE_FW_PATCH_VERSION_4),
2409 &fw_version);
2410
2411 if (fw_version > 0x5)
2412 status = 0;
2413
2414 fw_version_out:
2415 return status;
2416 }
2417
2418 static struct ixgbe_mac_operations mac_ops_82599 = {
2419 .init_hw = &ixgbe_init_hw_generic,
2420 .reset_hw = &ixgbe_reset_hw_82599,
2421 .start_hw = &ixgbe_start_hw_82599,
2422 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2423 .get_media_type = &ixgbe_get_media_type_82599,
2424 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2425 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2426 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2427 .get_san_mac_addr = &ixgbe_get_san_mac_addr_82599,
2428 .get_device_caps = &ixgbe_get_device_caps_82599,
2429 .stop_adapter = &ixgbe_stop_adapter_generic,
2430 .get_bus_info = &ixgbe_get_bus_info_generic,
2431 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2432 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2433 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2434 .setup_link = &ixgbe_setup_mac_link_82599,
2435 .check_link = &ixgbe_check_mac_link_82599,
2436 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2437 .led_on = &ixgbe_led_on_generic,
2438 .led_off = &ixgbe_led_off_generic,
2439 .blink_led_start = &ixgbe_blink_led_start_generic,
2440 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2441 .set_rar = &ixgbe_set_rar_generic,
2442 .clear_rar = &ixgbe_clear_rar_generic,
2443 .set_vmdq = &ixgbe_set_vmdq_82599,
2444 .clear_vmdq = &ixgbe_clear_vmdq_82599,
2445 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2446 .update_uc_addr_list = &ixgbe_update_uc_addr_list_generic,
2447 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2448 .enable_mc = &ixgbe_enable_mc_generic,
2449 .disable_mc = &ixgbe_disable_mc_generic,
2450 .clear_vfta = &ixgbe_clear_vfta_82599,
2451 .set_vfta = &ixgbe_set_vfta_82599,
2452 .fc_enable = &ixgbe_fc_enable_generic,
2453 .init_uta_tables = &ixgbe_init_uta_tables_82599,
2454 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2455 };
2456
2457 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2458 .init_params = &ixgbe_init_eeprom_params_generic,
2459 .read = &ixgbe_read_eeprom_generic,
2460 .write = &ixgbe_write_eeprom_generic,
2461 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2462 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2463 };
2464
2465 static struct ixgbe_phy_operations phy_ops_82599 = {
2466 .identify = &ixgbe_identify_phy_82599,
2467 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2468 .init = &ixgbe_init_phy_ops_82599,
2469 .reset = &ixgbe_reset_phy_generic,
2470 .read_reg = &ixgbe_read_phy_reg_generic,
2471 .write_reg = &ixgbe_write_phy_reg_generic,
2472 .setup_link = &ixgbe_setup_phy_link_generic,
2473 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2474 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2475 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2476 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2477 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2478 };
2479
2480 struct ixgbe_info ixgbe_82599_info = {
2481 .mac = ixgbe_mac_82599EB,
2482 .get_invariants = &ixgbe_get_invariants_82599,
2483 .mac_ops = &mac_ops_82599,
2484 .eeprom_ops = &eeprom_ops_82599,
2485 .phy_ops = &phy_ops_82599,
2486 };
Support for the Chinese Samsung S3C2440 based development boards