2 * Driver for C-Media CMI8338 and 8738 PCI soundcards.
3 * Copyright (c) 2000 by Takashi Iwai <tiwai@suse.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 /* Does not work. Warning may block system in capture mode */
21 /* #define USE_VAR48KRATE */
23 #include <sound/driver.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27 #include <linux/init.h>
28 #include <linux/pci.h>
29 #include <linux/slab.h>
30 #include <linux/gameport.h>
31 #include <linux/moduleparam.h>
32 #include <sound/core.h>
33 #include <sound/info.h>
34 #include <sound/control.h>
35 #include <sound/pcm.h>
36 #include <sound/rawmidi.h>
37 #include <sound/mpu401.h>
38 #include <sound/opl3.h>
40 #include <sound/asoundef.h>
41 #include <sound/initval.h>
43 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
44 MODULE_DESCRIPTION("C-Media CMI8x38 PCI");
45 MODULE_LICENSE("GPL");
46 MODULE_SUPPORTED_DEVICE("{{C-Media,CMI8738},"
49 "{C-Media,CMI8338B}}");
51 #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
52 #define SUPPORT_JOYSTICK 1
55 static int index
[SNDRV_CARDS
] = SNDRV_DEFAULT_IDX
; /* Index 0-MAX */
56 static char *id
[SNDRV_CARDS
] = SNDRV_DEFAULT_STR
; /* ID for this card */
57 static int enable
[SNDRV_CARDS
] = SNDRV_DEFAULT_ENABLE_PNP
; /* Enable switches */
58 static long mpu_port
[SNDRV_CARDS
];
59 static long fm_port
[SNDRV_CARDS
];
60 static int soft_ac3
[SNDRV_CARDS
] = {[0 ... (SNDRV_CARDS
-1)]=1};
61 #ifdef SUPPORT_JOYSTICK
62 static int joystick_port
[SNDRV_CARDS
];
65 module_param_array(index
, int, NULL
, 0444);
66 MODULE_PARM_DESC(index
, "Index value for C-Media PCI soundcard.");
67 module_param_array(id
, charp
, NULL
, 0444);
68 MODULE_PARM_DESC(id
, "ID string for C-Media PCI soundcard.");
69 module_param_array(enable
, bool, NULL
, 0444);
70 MODULE_PARM_DESC(enable
, "Enable C-Media PCI soundcard.");
71 module_param_array(mpu_port
, long, NULL
, 0444);
72 MODULE_PARM_DESC(mpu_port
, "MPU-401 port.");
73 module_param_array(fm_port
, long, NULL
, 0444);
74 MODULE_PARM_DESC(fm_port
, "FM port.");
75 module_param_array(soft_ac3
, bool, NULL
, 0444);
76 MODULE_PARM_DESC(soft_ac3
, "Sofware-conversion of raw SPDIF packets (model 033 only).");
77 #ifdef SUPPORT_JOYSTICK
78 module_param_array(joystick_port
, int, NULL
, 0444);
79 MODULE_PARM_DESC(joystick_port
, "Joystick port address.");
83 * CM8x38 registers definition
86 #define CM_REG_FUNCTRL0 0x00
87 #define CM_RST_CH1 0x00080000
88 #define CM_RST_CH0 0x00040000
89 #define CM_CHEN1 0x00020000 /* ch1: enable */
90 #define CM_CHEN0 0x00010000 /* ch0: enable */
91 #define CM_PAUSE1 0x00000008 /* ch1: pause */
92 #define CM_PAUSE0 0x00000004 /* ch0: pause */
93 #define CM_CHADC1 0x00000002 /* ch1, 0:playback, 1:record */
94 #define CM_CHADC0 0x00000001 /* ch0, 0:playback, 1:record */
96 #define CM_REG_FUNCTRL1 0x04
97 #define CM_ASFC_MASK 0x0000E000 /* ADC sampling frequency */
98 #define CM_ASFC_SHIFT 13
99 #define CM_DSFC_MASK 0x00001C00 /* DAC sampling frequency */
100 #define CM_DSFC_SHIFT 10
101 #define CM_SPDF_1 0x00000200 /* SPDIF IN/OUT at channel B */
102 #define CM_SPDF_0 0x00000100 /* SPDIF OUT only channel A */
103 #define CM_SPDFLOOP 0x00000080 /* ext. SPDIIF/OUT -> IN loopback */
104 #define CM_SPDO2DAC 0x00000040 /* SPDIF/OUT can be heard from internal DAC */
105 #define CM_INTRM 0x00000020 /* master control block (MCB) interrupt enabled */
106 #define CM_BREQ 0x00000010 /* bus master enabled */
107 #define CM_VOICE_EN 0x00000008 /* legacy voice (SB16,FM) */
108 #define CM_UART_EN 0x00000004 /* UART */
109 #define CM_JYSTK_EN 0x00000002 /* joy stick */
111 #define CM_REG_CHFORMAT 0x08
113 #define CM_CHB3D5C 0x80000000 /* 5,6 channels */
114 #define CM_CHB3D 0x20000000 /* 4 channels */
116 #define CM_CHIP_MASK1 0x1f000000
117 #define CM_CHIP_037 0x01000000
119 #define CM_SPDIF_SELECT1 0x00080000 /* for model <= 037 ? */
120 #define CM_AC3EN1 0x00100000 /* enable AC3: model 037 */
121 #define CM_SPD24SEL 0x00020000 /* 24bit spdif: model 037 */
122 /* #define CM_SPDIF_INVERSE 0x00010000 */ /* ??? */
124 #define CM_ADCBITLEN_MASK 0x0000C000
125 #define CM_ADCBITLEN_16 0x00000000
126 #define CM_ADCBITLEN_15 0x00004000
127 #define CM_ADCBITLEN_14 0x00008000
128 #define CM_ADCBITLEN_13 0x0000C000
130 #define CM_ADCDACLEN_MASK 0x00003000
131 #define CM_ADCDACLEN_060 0x00000000
132 #define CM_ADCDACLEN_066 0x00001000
133 #define CM_ADCDACLEN_130 0x00002000
134 #define CM_ADCDACLEN_280 0x00003000
136 #define CM_CH1_SRATE_176K 0x00000800
137 #define CM_CH1_SRATE_88K 0x00000400
138 #define CM_CH0_SRATE_176K 0x00000200
139 #define CM_CH0_SRATE_88K 0x00000100
141 #define CM_SPDIF_INVERSE2 0x00000080 /* model 055? */
143 #define CM_CH1FMT_MASK 0x0000000C
144 #define CM_CH1FMT_SHIFT 2
145 #define CM_CH0FMT_MASK 0x00000003
146 #define CM_CH0FMT_SHIFT 0
148 #define CM_REG_INT_HLDCLR 0x0C
149 #define CM_CHIP_MASK2 0xff000000
150 #define CM_CHIP_039 0x04000000
151 #define CM_CHIP_039_6CH 0x01000000
152 #define CM_CHIP_055 0x08000000
153 #define CM_CHIP_8768 0x20000000
154 #define CM_TDMA_INT_EN 0x00040000
155 #define CM_CH1_INT_EN 0x00020000
156 #define CM_CH0_INT_EN 0x00010000
157 #define CM_INT_HOLD 0x00000002
158 #define CM_INT_CLEAR 0x00000001
160 #define CM_REG_INT_STATUS 0x10
161 #define CM_INTR 0x80000000
162 #define CM_VCO 0x08000000 /* Voice Control? CMI8738 */
163 #define CM_MCBINT 0x04000000 /* Master Control Block abort cond.? */
164 #define CM_UARTINT 0x00010000
165 #define CM_LTDMAINT 0x00008000
166 #define CM_HTDMAINT 0x00004000
167 #define CM_XDO46 0x00000080 /* Modell 033? Direct programming EEPROM (read data register) */
168 #define CM_LHBTOG 0x00000040 /* High/Low status from DMA ctrl register */
169 #define CM_LEG_HDMA 0x00000020 /* Legacy is in High DMA channel */
170 #define CM_LEG_STEREO 0x00000010 /* Legacy is in Stereo mode */
171 #define CM_CH1BUSY 0x00000008
172 #define CM_CH0BUSY 0x00000004
173 #define CM_CHINT1 0x00000002
174 #define CM_CHINT0 0x00000001
176 #define CM_REG_LEGACY_CTRL 0x14
177 #define CM_NXCHG 0x80000000 /* h/w multi channels? */
178 #define CM_VMPU_MASK 0x60000000 /* MPU401 i/o port address */
179 #define CM_VMPU_330 0x00000000
180 #define CM_VMPU_320 0x20000000
181 #define CM_VMPU_310 0x40000000
182 #define CM_VMPU_300 0x60000000
183 #define CM_VSBSEL_MASK 0x0C000000 /* SB16 base address */
184 #define CM_VSBSEL_220 0x00000000
185 #define CM_VSBSEL_240 0x04000000
186 #define CM_VSBSEL_260 0x08000000
187 #define CM_VSBSEL_280 0x0C000000
188 #define CM_FMSEL_MASK 0x03000000 /* FM OPL3 base address */
189 #define CM_FMSEL_388 0x00000000
190 #define CM_FMSEL_3C8 0x01000000
191 #define CM_FMSEL_3E0 0x02000000
192 #define CM_FMSEL_3E8 0x03000000
193 #define CM_ENSPDOUT 0x00800000 /* enable XPDIF/OUT to I/O interface */
194 #define CM_SPDCOPYRHT 0x00400000 /* set copyright spdif in/out */
195 #define CM_DAC2SPDO 0x00200000 /* enable wave+fm_midi -> SPDIF/OUT */
196 #define CM_SETRETRY 0x00010000 /* 0: legacy i/o wait (default), 1: legacy i/o bus retry */
197 #define CM_CHB3D6C 0x00008000 /* 5.1 channels support */
198 #define CM_LINE_AS_BASS 0x00006000 /* use line-in as bass */
200 #define CM_REG_MISC_CTRL 0x18
201 #define CM_PWD 0x80000000
202 #define CM_RESET 0x40000000
203 #define CM_SFIL_MASK 0x30000000
204 #define CM_TXVX 0x08000000
205 #define CM_N4SPK3D 0x04000000 /* 4ch output */
206 #define CM_SPDO5V 0x02000000 /* 5V spdif output (1 = 0.5v (coax)) */
207 #define CM_SPDIF48K 0x01000000 /* write */
208 #define CM_SPATUS48K 0x01000000 /* read */
209 #define CM_ENDBDAC 0x00800000 /* enable dual dac */
210 #define CM_XCHGDAC 0x00400000 /* 0: front=ch0, 1: front=ch1 */
211 #define CM_SPD32SEL 0x00200000 /* 0: 16bit SPDIF, 1: 32bit */
212 #define CM_SPDFLOOPI 0x00100000 /* int. SPDIF-IN -> int. OUT */
213 #define CM_FM_EN 0x00080000 /* enalbe FM */
214 #define CM_AC3EN2 0x00040000 /* enable AC3: model 039 */
215 #define CM_VIDWPDSB 0x00010000
216 #define CM_SPDF_AC97 0x00008000 /* 0: SPDIF/OUT 44.1K, 1: 48K */
217 #define CM_MASK_EN 0x00004000
218 #define CM_VIDWPPRT 0x00002000
219 #define CM_SFILENB 0x00001000
220 #define CM_MMODE_MASK 0x00000E00
221 #define CM_SPDIF_SELECT2 0x00000100 /* for model > 039 ? */
222 #define CM_ENCENTER 0x00000080
223 #define CM_FLINKON 0x00000040
224 #define CM_FLINKOFF 0x00000020
225 #define CM_MIDSMP 0x00000010
226 #define CM_UPDDMA_MASK 0x0000000C
227 #define CM_TWAIT_MASK 0x00000003
230 #define CM_REG_MIXER0 0x20
232 #define CM_REG_SB16_DATA 0x22
233 #define CM_REG_SB16_ADDR 0x23
235 #define CM_REFFREQ_XIN (315*1000*1000)/22 /* 14.31818 Mhz reference clock frequency pin XIN */
236 #define CM_ADCMULT_XIN 512 /* Guessed (487 best for 44.1kHz, not for 88/176kHz) */
237 #define CM_TOLERANCE_RATE 0.001 /* Tolerance sample rate pitch (1000ppm) */
238 #define CM_MAXIMUM_RATE 80000000 /* Note more than 80MHz */
240 #define CM_REG_MIXER1 0x24
241 #define CM_FMMUTE 0x80 /* mute FM */
242 #define CM_FMMUTE_SHIFT 7
243 #define CM_WSMUTE 0x40 /* mute PCM */
244 #define CM_WSMUTE_SHIFT 6
245 #define CM_SPK4 0x20 /* lin-in -> rear line out */
246 #define CM_SPK4_SHIFT 5
247 #define CM_REAR2FRONT 0x10 /* exchange rear/front */
248 #define CM_REAR2FRONT_SHIFT 4
249 #define CM_WAVEINL 0x08 /* digital wave rec. left chan */
250 #define CM_WAVEINL_SHIFT 3
251 #define CM_WAVEINR 0x04 /* digical wave rec. right */
252 #define CM_WAVEINR_SHIFT 2
253 #define CM_X3DEN 0x02 /* 3D surround enable */
254 #define CM_X3DEN_SHIFT 1
255 #define CM_CDPLAY 0x01 /* enable SPDIF/IN PCM -> DAC */
256 #define CM_CDPLAY_SHIFT 0
258 #define CM_REG_MIXER2 0x25
259 #define CM_RAUXREN 0x80 /* AUX right capture */
260 #define CM_RAUXREN_SHIFT 7
261 #define CM_RAUXLEN 0x40 /* AUX left capture */
262 #define CM_RAUXLEN_SHIFT 6
263 #define CM_VAUXRM 0x20 /* AUX right mute */
264 #define CM_VAUXRM_SHIFT 5
265 #define CM_VAUXLM 0x10 /* AUX left mute */
266 #define CM_VAUXLM_SHIFT 4
267 #define CM_VADMIC_MASK 0x0e /* mic gain level (0-3) << 1 */
268 #define CM_VADMIC_SHIFT 1
269 #define CM_MICGAINZ 0x01 /* mic boost */
270 #define CM_MICGAINZ_SHIFT 0
272 #define CM_REG_AUX_VOL 0x26
273 #define CM_VAUXL_MASK 0xf0
274 #define CM_VAUXR_MASK 0x0f
276 #define CM_REG_MISC 0x27
277 #define CM_XGPO1 0x20
278 // #define CM_XGPBIO 0x04
279 #define CM_MIC_CENTER_LFE 0x04 /* mic as center/lfe out? (model 039 or later?) */
280 #define CM_SPDIF_INVERSE 0x04 /* spdif input phase inverse (model 037) */
281 #define CM_SPDVALID 0x02 /* spdif input valid check */
282 #define CM_DMAUTO 0x01
284 #define CM_REG_AC97 0x28 /* hmmm.. do we have ac97 link? */
286 * For CMI-8338 (0x28 - 0x2b) .. is this valid for CMI-8738
287 * or identical with AC97 codec?
289 #define CM_REG_EXTERN_CODEC CM_REG_AC97
292 * MPU401 pci port index address 0x40 - 0x4f (CMI-8738 spec ver. 0.6)
294 #define CM_REG_MPU_PCI 0x40
297 * FM pci port index address 0x50 - 0x5f (CMI-8738 spec ver. 0.6)
299 #define CM_REG_FM_PCI 0x50
302 * access from SB-mixer port
304 #define CM_REG_EXTENT_IND 0xf0
305 #define CM_VPHONE_MASK 0xe0 /* Phone volume control (0-3) << 5 */
306 #define CM_VPHONE_SHIFT 5
307 #define CM_VPHOM 0x10 /* Phone mute control */
308 #define CM_VSPKM 0x08 /* Speaker mute control, default high */
309 #define CM_RLOOPREN 0x04 /* Rec. R-channel enable */
310 #define CM_RLOOPLEN 0x02 /* Rec. L-channel enable */
311 #define CM_VADMIC3 0x01 /* Mic record boost */
314 * CMI-8338 spec ver 0.5 (this is not valid for CMI-8738):
315 * the 8 registers 0xf8 - 0xff are used for programming m/n counter by the PLL
318 #define CM_REG_PLL 0xf8
323 #define CM_REG_CH0_FRAME1 0x80 /* base address */
324 #define CM_REG_CH0_FRAME2 0x84
325 #define CM_REG_CH1_FRAME1 0x88 /* 0-15: count of samples at bus master; buffer size */
326 #define CM_REG_CH1_FRAME2 0x8C /* 16-31: count of samples at codec; fragment size */
327 #define CM_REG_MISC_CTRL_8768 0x92 /* reg. name the same as 0x18 */
328 #define CM_CHB3D8C 0x20 /* 7.1 channels support */
329 #define CM_SPD32FMT 0x10 /* SPDIF/IN 32k */
330 #define CM_ADC2SPDIF 0x08 /* ADC output to SPDIF/OUT */
331 #define CM_SHAREADC 0x04 /* DAC in ADC as Center/LFE */
332 #define CM_REALTCMP 0x02 /* monitor the CMPL/CMPR of ADC */
333 #define CM_INVLRCK 0x01 /* invert ZVPORT's LRCK */
338 #define CM_EXTENT_CODEC 0x100
339 #define CM_EXTENT_MIDI 0x2
340 #define CM_EXTENT_SYNTH 0x4
344 * channels for playback / capture
350 * flags to check device open/close
352 #define CM_OPEN_NONE 0
353 #define CM_OPEN_CH_MASK 0x01
354 #define CM_OPEN_DAC 0x10
355 #define CM_OPEN_ADC 0x20
356 #define CM_OPEN_SPDIF 0x40
357 #define CM_OPEN_MCHAN 0x80
358 #define CM_OPEN_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC)
359 #define CM_OPEN_PLAYBACK2 (CM_CH_CAPT | CM_OPEN_DAC)
360 #define CM_OPEN_PLAYBACK_MULTI (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_MCHAN)
361 #define CM_OPEN_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC)
362 #define CM_OPEN_SPDIF_PLAYBACK (CM_CH_PLAY | CM_OPEN_DAC | CM_OPEN_SPDIF)
363 #define CM_OPEN_SPDIF_CAPTURE (CM_CH_CAPT | CM_OPEN_ADC | CM_OPEN_SPDIF)
367 #define CM_PLAYBACK_SRATE_176K CM_CH1_SRATE_176K
368 #define CM_PLAYBACK_SPDF CM_SPDF_1
369 #define CM_CAPTURE_SPDF CM_SPDF_0
371 #define CM_PLAYBACK_SRATE_176K CM_CH0_SRATE_176K
372 #define CM_PLAYBACK_SPDF CM_SPDF_0
373 #define CM_CAPTURE_SPDF CM_SPDF_1
381 typedef struct snd_stru_cmipci cmipci_t
;
382 typedef struct snd_stru_cmipci_pcm cmipci_pcm_t
;
384 struct snd_stru_cmipci_pcm
{
385 snd_pcm_substream_t
*substream
;
386 int running
; /* dac/adc running? */
387 unsigned int dma_size
; /* in frames */
388 unsigned int period_size
; /* in frames */
389 unsigned int offset
; /* physical address of the buffer */
390 unsigned int fmt
; /* format bits */
391 int ch
; /* channel (0/1) */
392 unsigned int is_dac
; /* is dac? */
397 /* mixer elements toggled/resumed during ac3 playback */
398 struct cmipci_mixer_auto_switches
{
399 const char *name
; /* switch to toggle */
400 int toggle_on
; /* value to change when ac3 mode */
402 static const struct cmipci_mixer_auto_switches cm_saved_mixer
[] = {
403 {"PCM Playback Switch", 0},
404 {"IEC958 Output Switch", 1},
405 {"IEC958 Mix Analog", 0},
406 // {"IEC958 Out To DAC", 1}, // no longer used
409 #define CM_SAVED_MIXERS ARRAY_SIZE(cm_saved_mixer)
411 struct snd_stru_cmipci
{
415 unsigned int device
; /* device ID */
418 unsigned long iobase
;
419 unsigned int ctrl
; /* FUNCTRL0 current value */
421 snd_pcm_t
*pcm
; /* DAC/ADC PCM */
422 snd_pcm_t
*pcm2
; /* 2nd DAC */
423 snd_pcm_t
*pcm_spdif
; /* SPDIF */
427 unsigned int has_dual_dac
: 1;
428 unsigned int can_ac3_sw
: 1;
429 unsigned int can_ac3_hw
: 1;
430 unsigned int can_multi_ch
: 1;
431 unsigned int do_soft_ac3
: 1;
433 unsigned int spdif_playback_avail
: 1; /* spdif ready? */
434 unsigned int spdif_playback_enabled
: 1; /* spdif switch enabled? */
435 int spdif_counter
; /* for software AC3 */
437 unsigned int dig_status
;
438 unsigned int dig_pcm_status
;
440 snd_pcm_hardware_t
*hw_info
[3]; /* for playbacks */
442 int opened
[2]; /* open mode */
443 struct semaphore open_mutex
;
445 unsigned int mixer_insensitive
: 1;
446 snd_kcontrol_t
*mixer_res_ctl
[CM_SAVED_MIXERS
];
447 int mixer_res_status
[CM_SAVED_MIXERS
];
449 cmipci_pcm_t channel
[2]; /* ch0 - DAC, ch1 - ADC or 2nd DAC */
452 snd_rawmidi_t
*rmidi
;
454 #ifdef SUPPORT_JOYSTICK
455 struct gameport
*gameport
;
462 /* read/write operations for dword register */
463 static inline void snd_cmipci_write(cmipci_t
*cm
, unsigned int cmd
, unsigned int data
)
465 outl(data
, cm
->iobase
+ cmd
);
468 static inline unsigned int snd_cmipci_read(cmipci_t
*cm
, unsigned int cmd
)
470 return inl(cm
->iobase
+ cmd
);
473 /* read/write operations for word register */
474 static inline void snd_cmipci_write_w(cmipci_t
*cm
, unsigned int cmd
, unsigned short data
)
476 outw(data
, cm
->iobase
+ cmd
);
479 static inline unsigned short snd_cmipci_read_w(cmipci_t
*cm
, unsigned int cmd
)
481 return inw(cm
->iobase
+ cmd
);
484 /* read/write operations for byte register */
485 static inline void snd_cmipci_write_b(cmipci_t
*cm
, unsigned int cmd
, unsigned char data
)
487 outb(data
, cm
->iobase
+ cmd
);
490 static inline unsigned char snd_cmipci_read_b(cmipci_t
*cm
, unsigned int cmd
)
492 return inb(cm
->iobase
+ cmd
);
495 /* bit operations for dword register */
496 static int snd_cmipci_set_bit(cmipci_t
*cm
, unsigned int cmd
, unsigned int flag
)
498 unsigned int val
, oval
;
499 val
= oval
= inl(cm
->iobase
+ cmd
);
503 outl(val
, cm
->iobase
+ cmd
);
507 static int snd_cmipci_clear_bit(cmipci_t
*cm
, unsigned int cmd
, unsigned int flag
)
509 unsigned int val
, oval
;
510 val
= oval
= inl(cm
->iobase
+ cmd
);
514 outl(val
, cm
->iobase
+ cmd
);
518 /* bit operations for byte register */
519 static int snd_cmipci_set_bit_b(cmipci_t
*cm
, unsigned int cmd
, unsigned char flag
)
521 unsigned char val
, oval
;
522 val
= oval
= inb(cm
->iobase
+ cmd
);
526 outb(val
, cm
->iobase
+ cmd
);
530 static int snd_cmipci_clear_bit_b(cmipci_t
*cm
, unsigned int cmd
, unsigned char flag
)
532 unsigned char val
, oval
;
533 val
= oval
= inb(cm
->iobase
+ cmd
);
537 outb(val
, cm
->iobase
+ cmd
);
547 * calculate frequency
550 static unsigned int rates
[] = { 5512, 11025, 22050, 44100, 8000, 16000, 32000, 48000 };
552 static unsigned int snd_cmipci_rate_freq(unsigned int rate
)
555 for (i
= 0; i
< ARRAY_SIZE(rates
); i
++) {
556 if (rates
[i
] == rate
)
563 #ifdef USE_VAR48KRATE
565 * Determine PLL values for frequency setup, maybe the CMI8338 (CMI8738???)
566 * does it this way .. maybe not. Never get any information from C-Media about
567 * that <werner@suse.de>.
569 static int snd_cmipci_pll_rmn(unsigned int rate
, unsigned int adcmult
, int *r
, int *m
, int *n
)
571 unsigned int delta
, tolerance
;
574 for (*r
= 0; rate
< CM_MAXIMUM_RATE
/adcmult
; *r
+= (1<<5))
579 tolerance
= rate
*CM_TOLERANCE_RATE
;
581 for (xn
= (1+2); xn
< (0x1f+2); xn
++) {
582 for (xm
= (1+2); xm
< (0xff+2); xm
++) {
583 xr
= ((CM_REFFREQ_XIN
/adcmult
) * xm
) / xn
;
591 * If we found one, remember this,
592 * and try to find a closer one
594 if (delta
< tolerance
) {
606 * Program pll register bits, I assume that the 8 registers 0xf8 upto 0xff
607 * are mapped onto the 8 ADC/DAC sampling frequency which can be choosen
608 * at the register CM_REG_FUNCTRL1 (0x04).
609 * Problem: other ways are also possible (any information about that?)
611 static void snd_cmipci_set_pll(cmipci_t
*cm
, unsigned int rate
, unsigned int slot
)
613 unsigned int reg
= CM_REG_PLL
+ slot
;
615 * Guess that this programs at reg. 0x04 the pos 15:13/12:10
616 * for DSFC/ASFC (000 upto 111).
619 /* FIXME: Init (Do we've to set an other register first before programming?) */
621 /* FIXME: Is this correct? Or shouldn't the m/n/r values be used for that? */
622 snd_cmipci_write_b(cm
, reg
, rate
>>8);
623 snd_cmipci_write_b(cm
, reg
, rate
&0xff);
625 /* FIXME: Setup (Do we've to set an other register first to enable this?) */
627 #endif /* USE_VAR48KRATE */
629 static int snd_cmipci_hw_params(snd_pcm_substream_t
* substream
,
630 snd_pcm_hw_params_t
* hw_params
)
632 return snd_pcm_lib_malloc_pages(substream
, params_buffer_bytes(hw_params
));
635 static int snd_cmipci_playback2_hw_params(snd_pcm_substream_t
* substream
,
636 snd_pcm_hw_params_t
* hw_params
)
638 cmipci_t
*cm
= snd_pcm_substream_chip(substream
);
639 if (params_channels(hw_params
) > 2) {
640 down(&cm
->open_mutex
);
641 if (cm
->opened
[CM_CH_PLAY
]) {
645 /* reserve the channel A */
646 cm
->opened
[CM_CH_PLAY
] = CM_OPEN_PLAYBACK_MULTI
;
649 return snd_pcm_lib_malloc_pages(substream
, params_buffer_bytes(hw_params
));
652 static void snd_cmipci_ch_reset(cmipci_t
*cm
, int ch
)
654 int reset
= CM_RST_CH0
<< (cm
->channel
[ch
].ch
);
655 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
| reset
);
656 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
& ~reset
);
660 static int snd_cmipci_hw_free(snd_pcm_substream_t
* substream
)
662 return snd_pcm_lib_free_pages(substream
);
669 static unsigned int hw_channels
[] = {1, 2, 4, 5, 6, 8};
670 static snd_pcm_hw_constraint_list_t hw_constraints_channels_4
= {
675 static snd_pcm_hw_constraint_list_t hw_constraints_channels_6
= {
680 static snd_pcm_hw_constraint_list_t hw_constraints_channels_8
= {
686 static int set_dac_channels(cmipci_t
*cm
, cmipci_pcm_t
*rec
, int channels
)
689 if (! cm
->can_multi_ch
)
691 if (rec
->fmt
!= 0x03) /* stereo 16bit only */
694 spin_lock_irq(&cm
->reg_lock
);
695 snd_cmipci_set_bit(cm
, CM_REG_LEGACY_CTRL
, CM_NXCHG
);
696 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_XCHGDAC
);
698 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_CHB3D
);
699 snd_cmipci_set_bit(cm
, CM_REG_CHFORMAT
, CM_CHB3D5C
);
701 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_CHB3D5C
);
702 snd_cmipci_set_bit(cm
, CM_REG_CHFORMAT
, CM_CHB3D
);
705 snd_cmipci_set_bit(cm
, CM_REG_LEGACY_CTRL
, CM_CHB3D6C
);
706 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_ENCENTER
);
708 snd_cmipci_clear_bit(cm
, CM_REG_LEGACY_CTRL
, CM_CHB3D6C
);
709 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_ENCENTER
);
711 if (cm
->chip_version
== 68) {
713 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL_8768
, CM_CHB3D8C
);
715 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL_8768
, CM_CHB3D8C
);
718 spin_unlock_irq(&cm
->reg_lock
);
721 if (cm
->can_multi_ch
) {
722 spin_lock_irq(&cm
->reg_lock
);
723 snd_cmipci_clear_bit(cm
, CM_REG_LEGACY_CTRL
, CM_NXCHG
);
724 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_CHB3D
);
725 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_CHB3D5C
);
726 snd_cmipci_clear_bit(cm
, CM_REG_LEGACY_CTRL
, CM_CHB3D6C
);
727 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_ENCENTER
);
728 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_XCHGDAC
);
729 spin_unlock_irq(&cm
->reg_lock
);
737 * prepare playback/capture channel
738 * channel to be used must have been set in rec->ch.
740 static int snd_cmipci_pcm_prepare(cmipci_t
*cm
, cmipci_pcm_t
*rec
,
741 snd_pcm_substream_t
*substream
)
743 unsigned int reg
, freq
, val
;
744 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
748 if (snd_pcm_format_width(runtime
->format
) >= 16) {
750 if (snd_pcm_format_width(runtime
->format
) > 16)
751 rec
->shift
++; /* 24/32bit */
753 if (runtime
->channels
> 1)
755 if (rec
->is_dac
&& set_dac_channels(cm
, rec
, runtime
->channels
) < 0) {
756 snd_printd("cannot set dac channels\n");
760 rec
->offset
= runtime
->dma_addr
;
761 /* buffer and period sizes in frame */
762 rec
->dma_size
= runtime
->buffer_size
<< rec
->shift
;
763 rec
->period_size
= runtime
->period_size
<< rec
->shift
;
764 if (runtime
->channels
> 2) {
766 rec
->dma_size
= (rec
->dma_size
* runtime
->channels
) / 2;
767 rec
->period_size
= (rec
->period_size
* runtime
->channels
) / 2;
770 spin_lock_irq(&cm
->reg_lock
);
772 /* set buffer address */
773 reg
= rec
->ch
? CM_REG_CH1_FRAME1
: CM_REG_CH0_FRAME1
;
774 snd_cmipci_write(cm
, reg
, rec
->offset
);
775 /* program sample counts */
776 reg
= rec
->ch
? CM_REG_CH1_FRAME2
: CM_REG_CH0_FRAME2
;
777 snd_cmipci_write_w(cm
, reg
, rec
->dma_size
- 1);
778 snd_cmipci_write_w(cm
, reg
+ 2, rec
->period_size
- 1);
780 /* set adc/dac flag */
781 val
= rec
->ch
? CM_CHADC1
: CM_CHADC0
;
786 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
);
787 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
789 /* set sample rate */
790 freq
= snd_cmipci_rate_freq(runtime
->rate
);
791 val
= snd_cmipci_read(cm
, CM_REG_FUNCTRL1
);
793 val
&= ~CM_ASFC_MASK
;
794 val
|= (freq
<< CM_ASFC_SHIFT
) & CM_ASFC_MASK
;
796 val
&= ~CM_DSFC_MASK
;
797 val
|= (freq
<< CM_DSFC_SHIFT
) & CM_DSFC_MASK
;
799 snd_cmipci_write(cm
, CM_REG_FUNCTRL1
, val
);
800 //snd_printd("cmipci: functrl1 = %08x\n", val);
803 val
= snd_cmipci_read(cm
, CM_REG_CHFORMAT
);
805 val
&= ~CM_CH1FMT_MASK
;
806 val
|= rec
->fmt
<< CM_CH1FMT_SHIFT
;
808 val
&= ~CM_CH0FMT_MASK
;
809 val
|= rec
->fmt
<< CM_CH0FMT_SHIFT
;
811 snd_cmipci_write(cm
, CM_REG_CHFORMAT
, val
);
812 //snd_printd("cmipci: chformat = %08x\n", val);
815 spin_unlock_irq(&cm
->reg_lock
);
823 static int snd_cmipci_pcm_trigger(cmipci_t
*cm
, cmipci_pcm_t
*rec
,
824 snd_pcm_substream_t
*substream
, int cmd
)
826 unsigned int inthld
, chen
, reset
, pause
;
829 inthld
= CM_CH0_INT_EN
<< rec
->ch
;
830 chen
= CM_CHEN0
<< rec
->ch
;
831 reset
= CM_RST_CH0
<< rec
->ch
;
832 pause
= CM_PAUSE0
<< rec
->ch
;
834 spin_lock(&cm
->reg_lock
);
836 case SNDRV_PCM_TRIGGER_START
:
839 snd_cmipci_set_bit(cm
, CM_REG_INT_HLDCLR
, inthld
);
842 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
);
843 //snd_printd("cmipci: functrl0 = %08x\n", cm->ctrl);
845 case SNDRV_PCM_TRIGGER_STOP
:
847 /* disable interrupt */
848 snd_cmipci_clear_bit(cm
, CM_REG_INT_HLDCLR
, inthld
);
851 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
| reset
);
852 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
& ~reset
);
854 case SNDRV_PCM_TRIGGER_PAUSE_PUSH
:
856 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
);
858 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE
:
860 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, cm
->ctrl
);
866 spin_unlock(&cm
->reg_lock
);
871 * return the current pointer
873 static snd_pcm_uframes_t
snd_cmipci_pcm_pointer(cmipci_t
*cm
, cmipci_pcm_t
*rec
,
874 snd_pcm_substream_t
*substream
)
880 #if 1 // this seems better..
881 reg
= rec
->ch
? CM_REG_CH1_FRAME2
: CM_REG_CH0_FRAME2
;
882 ptr
= rec
->dma_size
- (snd_cmipci_read_w(cm
, reg
) + 1);
885 reg
= rec
->ch
? CM_REG_CH1_FRAME1
: CM_REG_CH0_FRAME1
;
886 ptr
= snd_cmipci_read(cm
, reg
) - rec
->offset
;
887 ptr
= bytes_to_frames(substream
->runtime
, ptr
);
889 if (substream
->runtime
->channels
> 2)
890 ptr
= (ptr
* 2) / substream
->runtime
->channels
;
898 static int snd_cmipci_playback_trigger(snd_pcm_substream_t
*substream
,
901 cmipci_t
*cm
= snd_pcm_substream_chip(substream
);
902 return snd_cmipci_pcm_trigger(cm
, &cm
->channel
[CM_CH_PLAY
], substream
, cmd
);
905 static snd_pcm_uframes_t
snd_cmipci_playback_pointer(snd_pcm_substream_t
*substream
)
907 cmipci_t
*cm
= snd_pcm_substream_chip(substream
);
908 return snd_cmipci_pcm_pointer(cm
, &cm
->channel
[CM_CH_PLAY
], substream
);
917 static int snd_cmipci_capture_trigger(snd_pcm_substream_t
*substream
,
920 cmipci_t
*cm
= snd_pcm_substream_chip(substream
);
921 return snd_cmipci_pcm_trigger(cm
, &cm
->channel
[CM_CH_CAPT
], substream
, cmd
);
924 static snd_pcm_uframes_t
snd_cmipci_capture_pointer(snd_pcm_substream_t
*substream
)
926 cmipci_t
*cm
= snd_pcm_substream_chip(substream
);
927 return snd_cmipci_pcm_pointer(cm
, &cm
->channel
[CM_CH_CAPT
], substream
);
932 * hw preparation for spdif
935 static int snd_cmipci_spdif_default_info(snd_kcontrol_t
*kcontrol
,
936 snd_ctl_elem_info_t
*uinfo
)
938 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
943 static int snd_cmipci_spdif_default_get(snd_kcontrol_t
*kcontrol
,
944 snd_ctl_elem_value_t
*ucontrol
)
946 cmipci_t
*chip
= snd_kcontrol_chip(kcontrol
);
949 spin_lock_irq(&chip
->reg_lock
);
950 for (i
= 0; i
< 4; i
++)
951 ucontrol
->value
.iec958
.status
[i
] = (chip
->dig_status
>> (i
* 8)) & 0xff;
952 spin_unlock_irq(&chip
->reg_lock
);
956 static int snd_cmipci_spdif_default_put(snd_kcontrol_t
* kcontrol
,
957 snd_ctl_elem_value_t
* ucontrol
)
959 cmipci_t
*chip
= snd_kcontrol_chip(kcontrol
);
964 spin_lock_irq(&chip
->reg_lock
);
965 for (i
= 0; i
< 4; i
++)
966 val
|= (unsigned int)ucontrol
->value
.iec958
.status
[i
] << (i
* 8);
967 change
= val
!= chip
->dig_status
;
968 chip
->dig_status
= val
;
969 spin_unlock_irq(&chip
->reg_lock
);
973 static snd_kcontrol_new_t snd_cmipci_spdif_default __devinitdata
=
975 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
976 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,DEFAULT
),
977 .info
= snd_cmipci_spdif_default_info
,
978 .get
= snd_cmipci_spdif_default_get
,
979 .put
= snd_cmipci_spdif_default_put
982 static int snd_cmipci_spdif_mask_info(snd_kcontrol_t
*kcontrol
,
983 snd_ctl_elem_info_t
*uinfo
)
985 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
990 static int snd_cmipci_spdif_mask_get(snd_kcontrol_t
* kcontrol
,
991 snd_ctl_elem_value_t
*ucontrol
)
993 ucontrol
->value
.iec958
.status
[0] = 0xff;
994 ucontrol
->value
.iec958
.status
[1] = 0xff;
995 ucontrol
->value
.iec958
.status
[2] = 0xff;
996 ucontrol
->value
.iec958
.status
[3] = 0xff;
1000 static snd_kcontrol_new_t snd_cmipci_spdif_mask __devinitdata
=
1002 .access
= SNDRV_CTL_ELEM_ACCESS_READ
,
1003 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
1004 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,CON_MASK
),
1005 .info
= snd_cmipci_spdif_mask_info
,
1006 .get
= snd_cmipci_spdif_mask_get
,
1009 static int snd_cmipci_spdif_stream_info(snd_kcontrol_t
*kcontrol
,
1010 snd_ctl_elem_info_t
*uinfo
)
1012 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_IEC958
;
1017 static int snd_cmipci_spdif_stream_get(snd_kcontrol_t
*kcontrol
,
1018 snd_ctl_elem_value_t
*ucontrol
)
1020 cmipci_t
*chip
= snd_kcontrol_chip(kcontrol
);
1023 spin_lock_irq(&chip
->reg_lock
);
1024 for (i
= 0; i
< 4; i
++)
1025 ucontrol
->value
.iec958
.status
[i
] = (chip
->dig_pcm_status
>> (i
* 8)) & 0xff;
1026 spin_unlock_irq(&chip
->reg_lock
);
1030 static int snd_cmipci_spdif_stream_put(snd_kcontrol_t
*kcontrol
,
1031 snd_ctl_elem_value_t
*ucontrol
)
1033 cmipci_t
*chip
= snd_kcontrol_chip(kcontrol
);
1038 spin_lock_irq(&chip
->reg_lock
);
1039 for (i
= 0; i
< 4; i
++)
1040 val
|= (unsigned int)ucontrol
->value
.iec958
.status
[i
] << (i
* 8);
1041 change
= val
!= chip
->dig_pcm_status
;
1042 chip
->dig_pcm_status
= val
;
1043 spin_unlock_irq(&chip
->reg_lock
);
1047 static snd_kcontrol_new_t snd_cmipci_spdif_stream __devinitdata
=
1049 .access
= SNDRV_CTL_ELEM_ACCESS_READWRITE
| SNDRV_CTL_ELEM_ACCESS_INACTIVE
,
1050 .iface
= SNDRV_CTL_ELEM_IFACE_PCM
,
1051 .name
= SNDRV_CTL_NAME_IEC958("",PLAYBACK
,PCM_STREAM
),
1052 .info
= snd_cmipci_spdif_stream_info
,
1053 .get
= snd_cmipci_spdif_stream_get
,
1054 .put
= snd_cmipci_spdif_stream_put
1060 /* save mixer setting and mute for AC3 playback */
1061 static int save_mixer_state(cmipci_t
*cm
)
1063 if (! cm
->mixer_insensitive
) {
1064 snd_ctl_elem_value_t
*val
;
1067 val
= kmalloc(sizeof(*val
), GFP_ATOMIC
);
1070 for (i
= 0; i
< CM_SAVED_MIXERS
; i
++) {
1071 snd_kcontrol_t
*ctl
= cm
->mixer_res_ctl
[i
];
1074 memset(val
, 0, sizeof(*val
));
1076 cm
->mixer_res_status
[i
] = val
->value
.integer
.value
[0];
1077 val
->value
.integer
.value
[0] = cm_saved_mixer
[i
].toggle_on
;
1078 event
= SNDRV_CTL_EVENT_MASK_INFO
;
1079 if (cm
->mixer_res_status
[i
] != val
->value
.integer
.value
[0]) {
1080 ctl
->put(ctl
, val
); /* toggle */
1081 event
|= SNDRV_CTL_EVENT_MASK_VALUE
;
1083 ctl
->vd
[0].access
|= SNDRV_CTL_ELEM_ACCESS_INACTIVE
;
1084 snd_ctl_notify(cm
->card
, event
, &ctl
->id
);
1088 cm
->mixer_insensitive
= 1;
1094 /* restore the previously saved mixer status */
1095 static void restore_mixer_state(cmipci_t
*cm
)
1097 if (cm
->mixer_insensitive
) {
1098 snd_ctl_elem_value_t
*val
;
1101 val
= kmalloc(sizeof(*val
), GFP_KERNEL
);
1104 cm
->mixer_insensitive
= 0; /* at first clear this;
1105 otherwise the changes will be ignored */
1106 for (i
= 0; i
< CM_SAVED_MIXERS
; i
++) {
1107 snd_kcontrol_t
*ctl
= cm
->mixer_res_ctl
[i
];
1111 memset(val
, 0, sizeof(*val
));
1112 ctl
->vd
[0].access
&= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE
;
1114 event
= SNDRV_CTL_EVENT_MASK_INFO
;
1115 if (val
->value
.integer
.value
[0] != cm
->mixer_res_status
[i
]) {
1116 val
->value
.integer
.value
[0] = cm
->mixer_res_status
[i
];
1118 event
|= SNDRV_CTL_EVENT_MASK_VALUE
;
1120 snd_ctl_notify(cm
->card
, event
, &ctl
->id
);
1127 /* spinlock held! */
1128 static void setup_ac3(cmipci_t
*cm
, snd_pcm_substream_t
*subs
, int do_ac3
, int rate
)
1132 snd_cmipci_set_bit(cm
, CM_REG_CHFORMAT
, CM_AC3EN1
);
1134 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_AC3EN2
);
1136 if (cm
->can_ac3_hw
) {
1137 /* SPD24SEL for 037, 0x02 */
1138 /* SPD24SEL for 039, 0x20, but cannot be set */
1139 snd_cmipci_set_bit(cm
, CM_REG_CHFORMAT
, CM_SPD24SEL
);
1140 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_SPD32SEL
);
1141 } else { /* can_ac3_sw */
1142 /* SPD32SEL for 037 & 039, 0x20 */
1143 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_SPD32SEL
);
1144 /* set 176K sample rate to fix 033 HW bug */
1145 if (cm
->chip_version
== 33) {
1146 if (rate
>= 48000) {
1147 snd_cmipci_set_bit(cm
, CM_REG_CHFORMAT
, CM_PLAYBACK_SRATE_176K
);
1149 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_PLAYBACK_SRATE_176K
);
1155 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_AC3EN1
);
1156 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_AC3EN2
);
1158 if (cm
->can_ac3_hw
) {
1159 /* chip model >= 37 */
1160 if (snd_pcm_format_width(subs
->runtime
->format
) > 16) {
1161 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_SPD32SEL
);
1162 snd_cmipci_set_bit(cm
, CM_REG_CHFORMAT
, CM_SPD24SEL
);
1164 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_SPD32SEL
);
1165 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_SPD24SEL
);
1168 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_SPD32SEL
);
1169 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_SPD24SEL
);
1170 snd_cmipci_clear_bit(cm
, CM_REG_CHFORMAT
, CM_PLAYBACK_SRATE_176K
);
1175 static int setup_spdif_playback(cmipci_t
*cm
, snd_pcm_substream_t
*subs
, int up
, int do_ac3
)
1179 rate
= subs
->runtime
->rate
;
1182 if ((err
= save_mixer_state(cm
)) < 0)
1185 spin_lock_irq(&cm
->reg_lock
);
1186 cm
->spdif_playback_avail
= up
;
1188 /* they are controlled via "IEC958 Output Switch" */
1189 /* snd_cmipci_set_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1190 /* snd_cmipci_set_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1191 if (cm
->spdif_playback_enabled
)
1192 snd_cmipci_set_bit(cm
, CM_REG_FUNCTRL1
, CM_PLAYBACK_SPDF
);
1193 setup_ac3(cm
, subs
, do_ac3
, rate
);
1196 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_SPDIF48K
| CM_SPDF_AC97
);
1198 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_SPDIF48K
| CM_SPDF_AC97
);
1201 /* they are controlled via "IEC958 Output Switch" */
1202 /* snd_cmipci_clear_bit(cm, CM_REG_LEGACY_CTRL, CM_ENSPDOUT); */
1203 /* snd_cmipci_clear_bit(cm, CM_REG_FUNCTRL1, CM_SPDO2DAC); */
1204 snd_cmipci_clear_bit(cm
, CM_REG_FUNCTRL1
, CM_PLAYBACK_SPDF
);
1205 setup_ac3(cm
, subs
, 0, 0);
1207 spin_unlock_irq(&cm
->reg_lock
);
1216 /* playback - enable spdif only on the certain condition */
1217 static int snd_cmipci_playback_prepare(snd_pcm_substream_t
*substream
)
1219 cmipci_t
*cm
= snd_pcm_substream_chip(substream
);
1220 int rate
= substream
->runtime
->rate
;
1221 int err
, do_spdif
, do_ac3
= 0;
1223 do_spdif
= ((rate
== 44100 || rate
== 48000) &&
1224 substream
->runtime
->format
== SNDRV_PCM_FORMAT_S16_LE
&&
1225 substream
->runtime
->channels
== 2);
1226 if (do_spdif
&& cm
->can_ac3_hw
)
1227 do_ac3
= cm
->dig_pcm_status
& IEC958_AES0_NONAUDIO
;
1228 if ((err
= setup_spdif_playback(cm
, substream
, do_spdif
, do_ac3
)) < 0)
1230 return snd_cmipci_pcm_prepare(cm
, &cm
->channel
[CM_CH_PLAY
], substream
);
1233 /* playback (via device #2) - enable spdif always */
1234 static int snd_cmipci_playback_spdif_prepare(snd_pcm_substream_t
*substream
)
1236 cmipci_t
*cm
= snd_pcm_substream_chip(substream
);
1240 do_ac3
= cm
->dig_pcm_status
& IEC958_AES0_NONAUDIO
;
1242 do_ac3
= 1; /* doesn't matter */
1243 if ((err
= setup_spdif_playback(cm
, substream
, 1, do_ac3
)) < 0)
1245 return snd_cmipci_pcm_prepare(cm
, &cm
->channel
[CM_CH_PLAY
], substream
);
1248 static int snd_cmipci_playback_hw_free(snd_pcm_substream_t
*substream
)
1250 cmipci_t
*cm
= snd_pcm_substream_chip(substream
);
1251 setup_spdif_playback(cm
, substream
, 0, 0);
1252 restore_mixer_state(cm
);
1253 return snd_cmipci_hw_free(substream
);
1257 static int snd_cmipci_capture_prepare(snd_pcm_substream_t
*substream
)
1259 cmipci_t
*cm
= snd_pcm_substream_chip(substream
);
1260 return snd_cmipci_pcm_prepare(cm
, &cm
->channel
[CM_CH_CAPT
], substream
);
1263 /* capture with spdif (via device #2) */
1264 static int snd_cmipci_capture_spdif_prepare(snd_pcm_substream_t
*substream
)
1266 cmipci_t
*cm
= snd_pcm_substream_chip(substream
);
1268 spin_lock_irq(&cm
->reg_lock
);
1269 snd_cmipci_set_bit(cm
, CM_REG_FUNCTRL1
, CM_CAPTURE_SPDF
);
1270 spin_unlock_irq(&cm
->reg_lock
);
1272 return snd_cmipci_pcm_prepare(cm
, &cm
->channel
[CM_CH_CAPT
], substream
);
1275 static int snd_cmipci_capture_spdif_hw_free(snd_pcm_substream_t
*subs
)
1277 cmipci_t
*cm
= snd_pcm_substream_chip(subs
);
1279 spin_lock_irq(&cm
->reg_lock
);
1280 snd_cmipci_clear_bit(cm
, CM_REG_FUNCTRL1
, CM_CAPTURE_SPDF
);
1281 spin_unlock_irq(&cm
->reg_lock
);
1283 return snd_cmipci_hw_free(subs
);
1290 static irqreturn_t
snd_cmipci_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
1292 cmipci_t
*cm
= dev_id
;
1293 unsigned int status
, mask
= 0;
1295 /* fastpath out, to ease interrupt sharing */
1296 status
= snd_cmipci_read(cm
, CM_REG_INT_STATUS
);
1297 if (!(status
& CM_INTR
))
1300 /* acknowledge interrupt */
1301 spin_lock(&cm
->reg_lock
);
1302 if (status
& CM_CHINT0
)
1303 mask
|= CM_CH0_INT_EN
;
1304 if (status
& CM_CHINT1
)
1305 mask
|= CM_CH1_INT_EN
;
1306 snd_cmipci_clear_bit(cm
, CM_REG_INT_HLDCLR
, mask
);
1307 snd_cmipci_set_bit(cm
, CM_REG_INT_HLDCLR
, mask
);
1308 spin_unlock(&cm
->reg_lock
);
1310 if (cm
->rmidi
&& (status
& CM_UARTINT
))
1311 snd_mpu401_uart_interrupt(irq
, cm
->rmidi
->private_data
, regs
);
1314 if ((status
& CM_CHINT0
) && cm
->channel
[0].running
)
1315 snd_pcm_period_elapsed(cm
->channel
[0].substream
);
1316 if ((status
& CM_CHINT1
) && cm
->channel
[1].running
)
1317 snd_pcm_period_elapsed(cm
->channel
[1].substream
);
1326 /* playback on channel A */
1327 static snd_pcm_hardware_t snd_cmipci_playback
=
1329 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1330 SNDRV_PCM_INFO_BLOCK_TRANSFER
| SNDRV_PCM_INFO_PAUSE
|
1331 SNDRV_PCM_INFO_MMAP_VALID
),
1332 .formats
= SNDRV_PCM_FMTBIT_U8
| SNDRV_PCM_FMTBIT_S16_LE
,
1333 .rates
= SNDRV_PCM_RATE_5512
| SNDRV_PCM_RATE_8000_48000
,
1338 .buffer_bytes_max
= (128*1024),
1339 .period_bytes_min
= 64,
1340 .period_bytes_max
= (128*1024),
1342 .periods_max
= 1024,
1346 /* capture on channel B */
1347 static snd_pcm_hardware_t snd_cmipci_capture
=
1349 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1350 SNDRV_PCM_INFO_BLOCK_TRANSFER
| SNDRV_PCM_INFO_PAUSE
|
1351 SNDRV_PCM_INFO_MMAP_VALID
),
1352 .formats
= SNDRV_PCM_FMTBIT_U8
| SNDRV_PCM_FMTBIT_S16_LE
,
1353 .rates
= SNDRV_PCM_RATE_5512
| SNDRV_PCM_RATE_8000_48000
,
1358 .buffer_bytes_max
= (128*1024),
1359 .period_bytes_min
= 64,
1360 .period_bytes_max
= (128*1024),
1362 .periods_max
= 1024,
1366 /* playback on channel B - stereo 16bit only? */
1367 static snd_pcm_hardware_t snd_cmipci_playback2
=
1369 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1370 SNDRV_PCM_INFO_BLOCK_TRANSFER
| SNDRV_PCM_INFO_PAUSE
|
1371 SNDRV_PCM_INFO_MMAP_VALID
),
1372 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1373 .rates
= SNDRV_PCM_RATE_5512
| SNDRV_PCM_RATE_8000_48000
,
1378 .buffer_bytes_max
= (128*1024),
1379 .period_bytes_min
= 64,
1380 .period_bytes_max
= (128*1024),
1382 .periods_max
= 1024,
1386 /* spdif playback on channel A */
1387 static snd_pcm_hardware_t snd_cmipci_playback_spdif
=
1389 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1390 SNDRV_PCM_INFO_BLOCK_TRANSFER
| SNDRV_PCM_INFO_PAUSE
|
1391 SNDRV_PCM_INFO_MMAP_VALID
),
1392 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1393 .rates
= SNDRV_PCM_RATE_44100
| SNDRV_PCM_RATE_48000
,
1398 .buffer_bytes_max
= (128*1024),
1399 .period_bytes_min
= 64,
1400 .period_bytes_max
= (128*1024),
1402 .periods_max
= 1024,
1406 /* spdif playback on channel A (32bit, IEC958 subframes) */
1407 static snd_pcm_hardware_t snd_cmipci_playback_iec958_subframe
=
1409 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1410 SNDRV_PCM_INFO_BLOCK_TRANSFER
| SNDRV_PCM_INFO_PAUSE
|
1411 SNDRV_PCM_INFO_MMAP_VALID
),
1412 .formats
= SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE
,
1413 .rates
= SNDRV_PCM_RATE_44100
| SNDRV_PCM_RATE_48000
,
1418 .buffer_bytes_max
= (128*1024),
1419 .period_bytes_min
= 64,
1420 .period_bytes_max
= (128*1024),
1422 .periods_max
= 1024,
1426 /* spdif capture on channel B */
1427 static snd_pcm_hardware_t snd_cmipci_capture_spdif
=
1429 .info
= (SNDRV_PCM_INFO_MMAP
| SNDRV_PCM_INFO_INTERLEAVED
|
1430 SNDRV_PCM_INFO_BLOCK_TRANSFER
| SNDRV_PCM_INFO_PAUSE
|
1431 SNDRV_PCM_INFO_MMAP_VALID
),
1432 .formats
= SNDRV_PCM_FMTBIT_S16_LE
,
1433 .rates
= SNDRV_PCM_RATE_44100
| SNDRV_PCM_RATE_48000
,
1438 .buffer_bytes_max
= (128*1024),
1439 .period_bytes_min
= 64,
1440 .period_bytes_max
= (128*1024),
1442 .periods_max
= 1024,
1447 * check device open/close
1449 static int open_device_check(cmipci_t
*cm
, int mode
, snd_pcm_substream_t
*subs
)
1451 int ch
= mode
& CM_OPEN_CH_MASK
;
1453 /* FIXME: a file should wait until the device becomes free
1454 * when it's opened on blocking mode. however, since the current
1455 * pcm framework doesn't pass file pointer before actually opened,
1456 * we can't know whether blocking mode or not in open callback..
1458 down(&cm
->open_mutex
);
1459 if (cm
->opened
[ch
]) {
1460 up(&cm
->open_mutex
);
1463 cm
->opened
[ch
] = mode
;
1464 cm
->channel
[ch
].substream
= subs
;
1465 if (! (mode
& CM_OPEN_DAC
)) {
1466 /* disable dual DAC mode */
1467 cm
->channel
[ch
].is_dac
= 0;
1468 spin_lock_irq(&cm
->reg_lock
);
1469 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_ENDBDAC
);
1470 spin_unlock_irq(&cm
->reg_lock
);
1472 up(&cm
->open_mutex
);
1476 static void close_device_check(cmipci_t
*cm
, int mode
)
1478 int ch
= mode
& CM_OPEN_CH_MASK
;
1480 down(&cm
->open_mutex
);
1481 if (cm
->opened
[ch
] == mode
) {
1482 if (cm
->channel
[ch
].substream
) {
1483 snd_cmipci_ch_reset(cm
, ch
);
1484 cm
->channel
[ch
].running
= 0;
1485 cm
->channel
[ch
].substream
= NULL
;
1488 if (! cm
->channel
[ch
].is_dac
) {
1489 /* enable dual DAC mode again */
1490 cm
->channel
[ch
].is_dac
= 1;
1491 spin_lock_irq(&cm
->reg_lock
);
1492 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_ENDBDAC
);
1493 spin_unlock_irq(&cm
->reg_lock
);
1496 up(&cm
->open_mutex
);
1502 static int snd_cmipci_playback_open(snd_pcm_substream_t
*substream
)
1504 cmipci_t
*cm
= snd_pcm_substream_chip(substream
);
1505 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
1508 if ((err
= open_device_check(cm
, CM_OPEN_PLAYBACK
, substream
)) < 0)
1510 runtime
->hw
= snd_cmipci_playback
;
1511 runtime
->hw
.channels_max
= cm
->max_channels
;
1512 snd_pcm_hw_constraint_minmax(runtime
, SNDRV_PCM_HW_PARAM_BUFFER_SIZE
, 0, 0x10000);
1513 cm
->dig_pcm_status
= cm
->dig_status
;
1517 static int snd_cmipci_capture_open(snd_pcm_substream_t
*substream
)
1519 cmipci_t
*cm
= snd_pcm_substream_chip(substream
);
1520 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
1523 if ((err
= open_device_check(cm
, CM_OPEN_CAPTURE
, substream
)) < 0)
1525 runtime
->hw
= snd_cmipci_capture
;
1526 if (cm
->chip_version
== 68) { // 8768 only supports 44k/48k recording
1527 runtime
->hw
.rate_min
= 41000;
1528 runtime
->hw
.rates
= SNDRV_PCM_RATE_44100
| SNDRV_PCM_RATE_48000
;
1530 snd_pcm_hw_constraint_minmax(runtime
, SNDRV_PCM_HW_PARAM_BUFFER_SIZE
, 0, 0x10000);
1534 static int snd_cmipci_playback2_open(snd_pcm_substream_t
*substream
)
1536 cmipci_t
*cm
= snd_pcm_substream_chip(substream
);
1537 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
1540 if ((err
= open_device_check(cm
, CM_OPEN_PLAYBACK2
, substream
)) < 0) /* use channel B */
1542 runtime
->hw
= snd_cmipci_playback2
;
1543 down(&cm
->open_mutex
);
1544 if (! cm
->opened
[CM_CH_PLAY
]) {
1545 if (cm
->can_multi_ch
) {
1546 runtime
->hw
.channels_max
= cm
->max_channels
;
1547 if (cm
->max_channels
== 4)
1548 snd_pcm_hw_constraint_list(runtime
, 0, SNDRV_PCM_HW_PARAM_CHANNELS
, &hw_constraints_channels_4
);
1549 else if (cm
->max_channels
== 6)
1550 snd_pcm_hw_constraint_list(runtime
, 0, SNDRV_PCM_HW_PARAM_CHANNELS
, &hw_constraints_channels_6
);
1551 else if (cm
->max_channels
== 8)
1552 snd_pcm_hw_constraint_list(runtime
, 0, SNDRV_PCM_HW_PARAM_CHANNELS
, &hw_constraints_channels_8
);
1554 snd_pcm_hw_constraint_minmax(runtime
, SNDRV_PCM_HW_PARAM_BUFFER_SIZE
, 0, 0x10000);
1556 up(&cm
->open_mutex
);
1560 static int snd_cmipci_playback_spdif_open(snd_pcm_substream_t
*substream
)
1562 cmipci_t
*cm
= snd_pcm_substream_chip(substream
);
1563 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
1566 if ((err
= open_device_check(cm
, CM_OPEN_SPDIF_PLAYBACK
, substream
)) < 0) /* use channel A */
1568 if (cm
->can_ac3_hw
) {
1569 runtime
->hw
= snd_cmipci_playback_spdif
;
1570 if (cm
->chip_version
>= 37)
1571 runtime
->hw
.formats
|= SNDRV_PCM_FMTBIT_S32_LE
;
1573 runtime
->hw
= snd_cmipci_playback_iec958_subframe
;
1575 snd_pcm_hw_constraint_minmax(runtime
, SNDRV_PCM_HW_PARAM_BUFFER_SIZE
, 0, 0x40000);
1576 cm
->dig_pcm_status
= cm
->dig_status
;
1580 static int snd_cmipci_capture_spdif_open(snd_pcm_substream_t
* substream
)
1582 cmipci_t
*cm
= snd_pcm_substream_chip(substream
);
1583 snd_pcm_runtime_t
*runtime
= substream
->runtime
;
1586 if ((err
= open_device_check(cm
, CM_OPEN_SPDIF_CAPTURE
, substream
)) < 0) /* use channel B */
1588 runtime
->hw
= snd_cmipci_capture_spdif
;
1589 snd_pcm_hw_constraint_minmax(runtime
, SNDRV_PCM_HW_PARAM_BUFFER_SIZE
, 0, 0x40000);
1597 static int snd_cmipci_playback_close(snd_pcm_substream_t
* substream
)
1599 cmipci_t
*cm
= snd_pcm_substream_chip(substream
);
1600 close_device_check(cm
, CM_OPEN_PLAYBACK
);
1604 static int snd_cmipci_capture_close(snd_pcm_substream_t
* substream
)
1606 cmipci_t
*cm
= snd_pcm_substream_chip(substream
);
1607 close_device_check(cm
, CM_OPEN_CAPTURE
);
1611 static int snd_cmipci_playback2_close(snd_pcm_substream_t
* substream
)
1613 cmipci_t
*cm
= snd_pcm_substream_chip(substream
);
1614 close_device_check(cm
, CM_OPEN_PLAYBACK2
);
1615 close_device_check(cm
, CM_OPEN_PLAYBACK_MULTI
);
1619 static int snd_cmipci_playback_spdif_close(snd_pcm_substream_t
* substream
)
1621 cmipci_t
*cm
= snd_pcm_substream_chip(substream
);
1622 close_device_check(cm
, CM_OPEN_SPDIF_PLAYBACK
);
1626 static int snd_cmipci_capture_spdif_close(snd_pcm_substream_t
* substream
)
1628 cmipci_t
*cm
= snd_pcm_substream_chip(substream
);
1629 close_device_check(cm
, CM_OPEN_SPDIF_CAPTURE
);
1637 static snd_pcm_ops_t snd_cmipci_playback_ops
= {
1638 .open
= snd_cmipci_playback_open
,
1639 .close
= snd_cmipci_playback_close
,
1640 .ioctl
= snd_pcm_lib_ioctl
,
1641 .hw_params
= snd_cmipci_hw_params
,
1642 .hw_free
= snd_cmipci_playback_hw_free
,
1643 .prepare
= snd_cmipci_playback_prepare
,
1644 .trigger
= snd_cmipci_playback_trigger
,
1645 .pointer
= snd_cmipci_playback_pointer
,
1648 static snd_pcm_ops_t snd_cmipci_capture_ops
= {
1649 .open
= snd_cmipci_capture_open
,
1650 .close
= snd_cmipci_capture_close
,
1651 .ioctl
= snd_pcm_lib_ioctl
,
1652 .hw_params
= snd_cmipci_hw_params
,
1653 .hw_free
= snd_cmipci_hw_free
,
1654 .prepare
= snd_cmipci_capture_prepare
,
1655 .trigger
= snd_cmipci_capture_trigger
,
1656 .pointer
= snd_cmipci_capture_pointer
,
1659 static snd_pcm_ops_t snd_cmipci_playback2_ops
= {
1660 .open
= snd_cmipci_playback2_open
,
1661 .close
= snd_cmipci_playback2_close
,
1662 .ioctl
= snd_pcm_lib_ioctl
,
1663 .hw_params
= snd_cmipci_playback2_hw_params
,
1664 .hw_free
= snd_cmipci_hw_free
,
1665 .prepare
= snd_cmipci_capture_prepare
, /* channel B */
1666 .trigger
= snd_cmipci_capture_trigger
, /* channel B */
1667 .pointer
= snd_cmipci_capture_pointer
, /* channel B */
1670 static snd_pcm_ops_t snd_cmipci_playback_spdif_ops
= {
1671 .open
= snd_cmipci_playback_spdif_open
,
1672 .close
= snd_cmipci_playback_spdif_close
,
1673 .ioctl
= snd_pcm_lib_ioctl
,
1674 .hw_params
= snd_cmipci_hw_params
,
1675 .hw_free
= snd_cmipci_playback_hw_free
,
1676 .prepare
= snd_cmipci_playback_spdif_prepare
, /* set up rate */
1677 .trigger
= snd_cmipci_playback_trigger
,
1678 .pointer
= snd_cmipci_playback_pointer
,
1681 static snd_pcm_ops_t snd_cmipci_capture_spdif_ops
= {
1682 .open
= snd_cmipci_capture_spdif_open
,
1683 .close
= snd_cmipci_capture_spdif_close
,
1684 .ioctl
= snd_pcm_lib_ioctl
,
1685 .hw_params
= snd_cmipci_hw_params
,
1686 .hw_free
= snd_cmipci_capture_spdif_hw_free
,
1687 .prepare
= snd_cmipci_capture_spdif_prepare
,
1688 .trigger
= snd_cmipci_capture_trigger
,
1689 .pointer
= snd_cmipci_capture_pointer
,
1696 static void snd_cmipci_pcm_free(snd_pcm_t
*pcm
)
1698 snd_pcm_lib_preallocate_free_for_all(pcm
);
1701 static int __devinit
snd_cmipci_pcm_new(cmipci_t
*cm
, int device
)
1706 err
= snd_pcm_new(cm
->card
, cm
->card
->driver
, device
, 1, 1, &pcm
);
1710 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_cmipci_playback_ops
);
1711 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_CAPTURE
, &snd_cmipci_capture_ops
);
1713 pcm
->private_data
= cm
;
1714 pcm
->private_free
= snd_cmipci_pcm_free
;
1715 pcm
->info_flags
= 0;
1716 strcpy(pcm
->name
, "C-Media PCI DAC/ADC");
1719 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1720 snd_dma_pci_data(cm
->pci
), 64*1024, 128*1024);
1725 static int __devinit
snd_cmipci_pcm2_new(cmipci_t
*cm
, int device
)
1730 err
= snd_pcm_new(cm
->card
, cm
->card
->driver
, device
, 1, 0, &pcm
);
1734 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_cmipci_playback2_ops
);
1736 pcm
->private_data
= cm
;
1737 pcm
->private_free
= snd_cmipci_pcm_free
;
1738 pcm
->info_flags
= 0;
1739 strcpy(pcm
->name
, "C-Media PCI 2nd DAC");
1742 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1743 snd_dma_pci_data(cm
->pci
), 64*1024, 128*1024);
1748 static int __devinit
snd_cmipci_pcm_spdif_new(cmipci_t
*cm
, int device
)
1753 err
= snd_pcm_new(cm
->card
, cm
->card
->driver
, device
, 1, 1, &pcm
);
1757 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_PLAYBACK
, &snd_cmipci_playback_spdif_ops
);
1758 snd_pcm_set_ops(pcm
, SNDRV_PCM_STREAM_CAPTURE
, &snd_cmipci_capture_spdif_ops
);
1760 pcm
->private_data
= cm
;
1761 pcm
->private_free
= snd_cmipci_pcm_free
;
1762 pcm
->info_flags
= 0;
1763 strcpy(pcm
->name
, "C-Media PCI IEC958");
1764 cm
->pcm_spdif
= pcm
;
1766 snd_pcm_lib_preallocate_pages_for_all(pcm
, SNDRV_DMA_TYPE_DEV
,
1767 snd_dma_pci_data(cm
->pci
), 64*1024, 128*1024);
1774 * - CM8338/8738 has a compatible mixer interface with SB16, but
1775 * lack of some elements like tone control, i/o gain and AGC.
1776 * - Access to native registers:
1778 * - Output mute switches
1781 static void snd_cmipci_mixer_write(cmipci_t
*s
, unsigned char idx
, unsigned char data
)
1783 outb(idx
, s
->iobase
+ CM_REG_SB16_ADDR
);
1784 outb(data
, s
->iobase
+ CM_REG_SB16_DATA
);
1787 static unsigned char snd_cmipci_mixer_read(cmipci_t
*s
, unsigned char idx
)
1791 outb(idx
, s
->iobase
+ CM_REG_SB16_ADDR
);
1792 v
= inb(s
->iobase
+ CM_REG_SB16_DATA
);
1797 * general mixer element
1799 typedef struct cmipci_sb_reg
{
1800 unsigned int left_reg
, right_reg
;
1801 unsigned int left_shift
, right_shift
;
1803 unsigned int invert
: 1;
1804 unsigned int stereo
: 1;
1807 #define COMPOSE_SB_REG(lreg,rreg,lshift,rshift,mask,invert,stereo) \
1808 ((lreg) | ((rreg) << 8) | (lshift << 16) | (rshift << 19) | (mask << 24) | (invert << 22) | (stereo << 23))
1810 #define CMIPCI_DOUBLE(xname, left_reg, right_reg, left_shift, right_shift, mask, invert, stereo) \
1811 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1812 .info = snd_cmipci_info_volume, \
1813 .get = snd_cmipci_get_volume, .put = snd_cmipci_put_volume, \
1814 .private_value = COMPOSE_SB_REG(left_reg, right_reg, left_shift, right_shift, mask, invert, stereo), \
1817 #define CMIPCI_SB_VOL_STEREO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg+1, shift, shift, mask, 0, 1)
1818 #define CMIPCI_SB_VOL_MONO(xname,reg,shift,mask) CMIPCI_DOUBLE(xname, reg, reg, shift, shift, mask, 0, 0)
1819 #define CMIPCI_SB_SW_STEREO(xname,lshift,rshift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, lshift, rshift, 1, 0, 1)
1820 #define CMIPCI_SB_SW_MONO(xname,shift) CMIPCI_DOUBLE(xname, SB_DSP4_OUTPUT_SW, SB_DSP4_OUTPUT_SW, shift, shift, 1, 0, 0)
1822 static void cmipci_sb_reg_decode(cmipci_sb_reg_t
*r
, unsigned long val
)
1824 r
->left_reg
= val
& 0xff;
1825 r
->right_reg
= (val
>> 8) & 0xff;
1826 r
->left_shift
= (val
>> 16) & 0x07;
1827 r
->right_shift
= (val
>> 19) & 0x07;
1828 r
->invert
= (val
>> 22) & 1;
1829 r
->stereo
= (val
>> 23) & 1;
1830 r
->mask
= (val
>> 24) & 0xff;
1833 static int snd_cmipci_info_volume(snd_kcontrol_t
* kcontrol
, snd_ctl_elem_info_t
* uinfo
)
1835 cmipci_sb_reg_t reg
;
1837 cmipci_sb_reg_decode(®
, kcontrol
->private_value
);
1838 uinfo
->type
= reg
.mask
== 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN
: SNDRV_CTL_ELEM_TYPE_INTEGER
;
1839 uinfo
->count
= reg
.stereo
+ 1;
1840 uinfo
->value
.integer
.min
= 0;
1841 uinfo
->value
.integer
.max
= reg
.mask
;
1845 static int snd_cmipci_get_volume(snd_kcontrol_t
* kcontrol
, snd_ctl_elem_value_t
* ucontrol
)
1847 cmipci_t
*cm
= snd_kcontrol_chip(kcontrol
);
1848 cmipci_sb_reg_t reg
;
1851 cmipci_sb_reg_decode(®
, kcontrol
->private_value
);
1852 spin_lock_irq(&cm
->reg_lock
);
1853 val
= (snd_cmipci_mixer_read(cm
, reg
.left_reg
) >> reg
.left_shift
) & reg
.mask
;
1855 val
= reg
.mask
- val
;
1856 ucontrol
->value
.integer
.value
[0] = val
;
1858 val
= (snd_cmipci_mixer_read(cm
, reg
.right_reg
) >> reg
.right_shift
) & reg
.mask
;
1860 val
= reg
.mask
- val
;
1861 ucontrol
->value
.integer
.value
[1] = val
;
1863 spin_unlock_irq(&cm
->reg_lock
);
1867 static int snd_cmipci_put_volume(snd_kcontrol_t
* kcontrol
, snd_ctl_elem_value_t
* ucontrol
)
1869 cmipci_t
*cm
= snd_kcontrol_chip(kcontrol
);
1870 cmipci_sb_reg_t reg
;
1872 int left
, right
, oleft
, oright
;
1874 cmipci_sb_reg_decode(®
, kcontrol
->private_value
);
1875 left
= ucontrol
->value
.integer
.value
[0] & reg
.mask
;
1877 left
= reg
.mask
- left
;
1878 left
<<= reg
.left_shift
;
1880 right
= ucontrol
->value
.integer
.value
[1] & reg
.mask
;
1882 right
= reg
.mask
- right
;
1883 right
<<= reg
.right_shift
;
1886 spin_lock_irq(&cm
->reg_lock
);
1887 oleft
= snd_cmipci_mixer_read(cm
, reg
.left_reg
);
1888 left
|= oleft
& ~(reg
.mask
<< reg
.left_shift
);
1889 change
= left
!= oleft
;
1891 if (reg
.left_reg
!= reg
.right_reg
) {
1892 snd_cmipci_mixer_write(cm
, reg
.left_reg
, left
);
1893 oright
= snd_cmipci_mixer_read(cm
, reg
.right_reg
);
1896 right
|= oright
& ~(reg
.mask
<< reg
.right_shift
);
1897 change
|= right
!= oright
;
1898 snd_cmipci_mixer_write(cm
, reg
.right_reg
, right
);
1900 snd_cmipci_mixer_write(cm
, reg
.left_reg
, left
);
1901 spin_unlock_irq(&cm
->reg_lock
);
1906 * input route (left,right) -> (left,right)
1908 #define CMIPCI_SB_INPUT_SW(xname, left_shift, right_shift) \
1909 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1910 .info = snd_cmipci_info_input_sw, \
1911 .get = snd_cmipci_get_input_sw, .put = snd_cmipci_put_input_sw, \
1912 .private_value = COMPOSE_SB_REG(SB_DSP4_INPUT_LEFT, SB_DSP4_INPUT_RIGHT, left_shift, right_shift, 1, 0, 1), \
1915 static int snd_cmipci_info_input_sw(snd_kcontrol_t
* kcontrol
, snd_ctl_elem_info_t
* uinfo
)
1917 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_BOOLEAN
;
1919 uinfo
->value
.integer
.min
= 0;
1920 uinfo
->value
.integer
.max
= 1;
1924 static int snd_cmipci_get_input_sw(snd_kcontrol_t
* kcontrol
, snd_ctl_elem_value_t
* ucontrol
)
1926 cmipci_t
*cm
= snd_kcontrol_chip(kcontrol
);
1927 cmipci_sb_reg_t reg
;
1930 cmipci_sb_reg_decode(®
, kcontrol
->private_value
);
1931 spin_lock_irq(&cm
->reg_lock
);
1932 val1
= snd_cmipci_mixer_read(cm
, reg
.left_reg
);
1933 val2
= snd_cmipci_mixer_read(cm
, reg
.right_reg
);
1934 spin_unlock_irq(&cm
->reg_lock
);
1935 ucontrol
->value
.integer
.value
[0] = (val1
>> reg
.left_shift
) & 1;
1936 ucontrol
->value
.integer
.value
[1] = (val2
>> reg
.left_shift
) & 1;
1937 ucontrol
->value
.integer
.value
[2] = (val1
>> reg
.right_shift
) & 1;
1938 ucontrol
->value
.integer
.value
[3] = (val2
>> reg
.right_shift
) & 1;
1942 static int snd_cmipci_put_input_sw(snd_kcontrol_t
* kcontrol
, snd_ctl_elem_value_t
* ucontrol
)
1944 cmipci_t
*cm
= snd_kcontrol_chip(kcontrol
);
1945 cmipci_sb_reg_t reg
;
1947 int val1
, val2
, oval1
, oval2
;
1949 cmipci_sb_reg_decode(®
, kcontrol
->private_value
);
1950 spin_lock_irq(&cm
->reg_lock
);
1951 oval1
= snd_cmipci_mixer_read(cm
, reg
.left_reg
);
1952 oval2
= snd_cmipci_mixer_read(cm
, reg
.right_reg
);
1953 val1
= oval1
& ~((1 << reg
.left_shift
) | (1 << reg
.right_shift
));
1954 val2
= oval2
& ~((1 << reg
.left_shift
) | (1 << reg
.right_shift
));
1955 val1
|= (ucontrol
->value
.integer
.value
[0] & 1) << reg
.left_shift
;
1956 val2
|= (ucontrol
->value
.integer
.value
[1] & 1) << reg
.left_shift
;
1957 val1
|= (ucontrol
->value
.integer
.value
[2] & 1) << reg
.right_shift
;
1958 val2
|= (ucontrol
->value
.integer
.value
[3] & 1) << reg
.right_shift
;
1959 change
= val1
!= oval1
|| val2
!= oval2
;
1960 snd_cmipci_mixer_write(cm
, reg
.left_reg
, val1
);
1961 snd_cmipci_mixer_write(cm
, reg
.right_reg
, val2
);
1962 spin_unlock_irq(&cm
->reg_lock
);
1967 * native mixer switches/volumes
1970 #define CMIPCI_MIXER_SW_STEREO(xname, reg, lshift, rshift, invert) \
1971 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1972 .info = snd_cmipci_info_native_mixer, \
1973 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1974 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, 1, invert, 1), \
1977 #define CMIPCI_MIXER_SW_MONO(xname, reg, shift, invert) \
1978 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1979 .info = snd_cmipci_info_native_mixer, \
1980 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1981 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, 1, invert, 0), \
1984 #define CMIPCI_MIXER_VOL_STEREO(xname, reg, lshift, rshift, mask) \
1985 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1986 .info = snd_cmipci_info_native_mixer, \
1987 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1988 .private_value = COMPOSE_SB_REG(reg, reg, lshift, rshift, mask, 0, 1), \
1991 #define CMIPCI_MIXER_VOL_MONO(xname, reg, shift, mask) \
1992 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
1993 .info = snd_cmipci_info_native_mixer, \
1994 .get = snd_cmipci_get_native_mixer, .put = snd_cmipci_put_native_mixer, \
1995 .private_value = COMPOSE_SB_REG(reg, reg, shift, shift, mask, 0, 0), \
1998 static int snd_cmipci_info_native_mixer(snd_kcontrol_t
*kcontrol
, snd_ctl_elem_info_t
*uinfo
)
2000 cmipci_sb_reg_t reg
;
2002 cmipci_sb_reg_decode(®
, kcontrol
->private_value
);
2003 uinfo
->type
= reg
.mask
== 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN
: SNDRV_CTL_ELEM_TYPE_INTEGER
;
2004 uinfo
->count
= reg
.stereo
+ 1;
2005 uinfo
->value
.integer
.min
= 0;
2006 uinfo
->value
.integer
.max
= reg
.mask
;
2011 static int snd_cmipci_get_native_mixer(snd_kcontrol_t
* kcontrol
, snd_ctl_elem_value_t
* ucontrol
)
2013 cmipci_t
*cm
= snd_kcontrol_chip(kcontrol
);
2014 cmipci_sb_reg_t reg
;
2015 unsigned char oreg
, val
;
2017 cmipci_sb_reg_decode(®
, kcontrol
->private_value
);
2018 spin_lock_irq(&cm
->reg_lock
);
2019 oreg
= inb(cm
->iobase
+ reg
.left_reg
);
2020 val
= (oreg
>> reg
.left_shift
) & reg
.mask
;
2022 val
= reg
.mask
- val
;
2023 ucontrol
->value
.integer
.value
[0] = val
;
2025 val
= (oreg
>> reg
.right_shift
) & reg
.mask
;
2027 val
= reg
.mask
- val
;
2028 ucontrol
->value
.integer
.value
[1] = val
;
2030 spin_unlock_irq(&cm
->reg_lock
);
2034 static int snd_cmipci_put_native_mixer(snd_kcontrol_t
* kcontrol
, snd_ctl_elem_value_t
* ucontrol
)
2036 cmipci_t
*cm
= snd_kcontrol_chip(kcontrol
);
2037 cmipci_sb_reg_t reg
;
2038 unsigned char oreg
, nreg
, val
;
2040 cmipci_sb_reg_decode(®
, kcontrol
->private_value
);
2041 spin_lock_irq(&cm
->reg_lock
);
2042 oreg
= inb(cm
->iobase
+ reg
.left_reg
);
2043 val
= ucontrol
->value
.integer
.value
[0] & reg
.mask
;
2045 val
= reg
.mask
- val
;
2046 nreg
= oreg
& ~(reg
.mask
<< reg
.left_shift
);
2047 nreg
|= (val
<< reg
.left_shift
);
2049 val
= ucontrol
->value
.integer
.value
[1] & reg
.mask
;
2051 val
= reg
.mask
- val
;
2052 nreg
&= ~(reg
.mask
<< reg
.right_shift
);
2053 nreg
|= (val
<< reg
.right_shift
);
2055 outb(nreg
, cm
->iobase
+ reg
.left_reg
);
2056 spin_unlock_irq(&cm
->reg_lock
);
2057 return (nreg
!= oreg
);
2061 * special case - check mixer sensitivity
2063 static int snd_cmipci_get_native_mixer_sensitive(snd_kcontrol_t
*kcontrol
, snd_ctl_elem_value_t
*ucontrol
)
2065 //cmipci_t *cm = snd_kcontrol_chip(kcontrol);
2066 return snd_cmipci_get_native_mixer(kcontrol
, ucontrol
);
2069 static int snd_cmipci_put_native_mixer_sensitive(snd_kcontrol_t
*kcontrol
, snd_ctl_elem_value_t
*ucontrol
)
2071 cmipci_t
*cm
= snd_kcontrol_chip(kcontrol
);
2072 if (cm
->mixer_insensitive
) {
2076 return snd_cmipci_put_native_mixer(kcontrol
, ucontrol
);
2080 static snd_kcontrol_new_t snd_cmipci_mixers
[] __devinitdata
= {
2081 CMIPCI_SB_VOL_STEREO("Master Playback Volume", SB_DSP4_MASTER_DEV
, 3, 31),
2082 CMIPCI_MIXER_SW_MONO("3D Control - Switch", CM_REG_MIXER1
, CM_X3DEN_SHIFT
, 0),
2083 CMIPCI_SB_VOL_STEREO("PCM Playback Volume", SB_DSP4_PCM_DEV
, 3, 31),
2084 //CMIPCI_MIXER_SW_MONO("PCM Playback Switch", CM_REG_MIXER1, CM_WSMUTE_SHIFT, 1),
2085 { /* switch with sensitivity */
2086 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2087 .name
= "PCM Playback Switch",
2088 .info
= snd_cmipci_info_native_mixer
,
2089 .get
= snd_cmipci_get_native_mixer_sensitive
,
2090 .put
= snd_cmipci_put_native_mixer_sensitive
,
2091 .private_value
= COMPOSE_SB_REG(CM_REG_MIXER1
, CM_REG_MIXER1
, CM_WSMUTE_SHIFT
, CM_WSMUTE_SHIFT
, 1, 1, 0),
2093 CMIPCI_MIXER_SW_STEREO("PCM Capture Switch", CM_REG_MIXER1
, CM_WAVEINL_SHIFT
, CM_WAVEINR_SHIFT
, 0),
2094 CMIPCI_SB_VOL_STEREO("Synth Playback Volume", SB_DSP4_SYNTH_DEV
, 3, 31),
2095 CMIPCI_MIXER_SW_MONO("Synth Playback Switch", CM_REG_MIXER1
, CM_FMMUTE_SHIFT
, 1),
2096 CMIPCI_SB_INPUT_SW("Synth Capture Route", 6, 5),
2097 CMIPCI_SB_VOL_STEREO("CD Playback Volume", SB_DSP4_CD_DEV
, 3, 31),
2098 CMIPCI_SB_SW_STEREO("CD Playback Switch", 2, 1),
2099 CMIPCI_SB_INPUT_SW("CD Capture Route", 2, 1),
2100 CMIPCI_SB_VOL_STEREO("Line Playback Volume", SB_DSP4_LINE_DEV
, 3, 31),
2101 CMIPCI_SB_SW_STEREO("Line Playback Switch", 4, 3),
2102 CMIPCI_SB_INPUT_SW("Line Capture Route", 4, 3),
2103 CMIPCI_SB_VOL_MONO("Mic Playback Volume", SB_DSP4_MIC_DEV
, 3, 31),
2104 CMIPCI_SB_SW_MONO("Mic Playback Switch", 0),
2105 CMIPCI_DOUBLE("Mic Capture Switch", SB_DSP4_INPUT_LEFT
, SB_DSP4_INPUT_RIGHT
, 0, 0, 1, 0, 0),
2106 CMIPCI_SB_VOL_MONO("PC Speaker Playback Volume", SB_DSP4_SPEAKER_DEV
, 6, 3),
2107 CMIPCI_MIXER_VOL_STEREO("Aux Playback Volume", CM_REG_AUX_VOL
, 4, 0, 15),
2108 CMIPCI_MIXER_SW_STEREO("Aux Playback Switch", CM_REG_MIXER2
, CM_VAUXLM_SHIFT
, CM_VAUXRM_SHIFT
, 0),
2109 CMIPCI_MIXER_SW_STEREO("Aux Capture Switch", CM_REG_MIXER2
, CM_RAUXLEN_SHIFT
, CM_RAUXREN_SHIFT
, 0),
2110 CMIPCI_MIXER_SW_MONO("Mic Boost Playback Switch", CM_REG_MIXER2
, CM_MICGAINZ_SHIFT
, 1),
2111 CMIPCI_MIXER_VOL_MONO("Mic Capture Volume", CM_REG_MIXER2
, CM_VADMIC_SHIFT
, 7),
2112 CMIPCI_SB_VOL_MONO("Phone Playback Volume", CM_REG_EXTENT_IND
, 5, 7),
2113 CMIPCI_DOUBLE("Phone Playback Switch", CM_REG_EXTENT_IND
, CM_REG_EXTENT_IND
, 4, 4, 1, 0, 0),
2114 CMIPCI_DOUBLE("PC Speaker Playnack Switch", CM_REG_EXTENT_IND
, CM_REG_EXTENT_IND
, 3, 3, 1, 0, 0),
2115 CMIPCI_DOUBLE("Mic Boost Capture Switch", CM_REG_EXTENT_IND
, CM_REG_EXTENT_IND
, 0, 0, 1, 0, 0),
2122 typedef struct snd_cmipci_switch_args
{
2123 int reg
; /* register index */
2124 unsigned int mask
; /* mask bits */
2125 unsigned int mask_on
; /* mask bits to turn on */
2126 unsigned int is_byte
: 1; /* byte access? */
2127 unsigned int ac3_sensitive
: 1; /* access forbidden during non-audio operation? */
2128 } snd_cmipci_switch_args_t
;
2130 static int snd_cmipci_uswitch_info(snd_kcontrol_t
*kcontrol
, snd_ctl_elem_info_t
*uinfo
)
2132 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_BOOLEAN
;
2134 uinfo
->value
.integer
.min
= 0;
2135 uinfo
->value
.integer
.max
= 1;
2139 static int _snd_cmipci_uswitch_get(snd_kcontrol_t
*kcontrol
, snd_ctl_elem_value_t
*ucontrol
, snd_cmipci_switch_args_t
*args
)
2142 cmipci_t
*cm
= snd_kcontrol_chip(kcontrol
);
2144 spin_lock_irq(&cm
->reg_lock
);
2145 if (args
->ac3_sensitive
&& cm
->mixer_insensitive
) {
2146 ucontrol
->value
.integer
.value
[0] = 0;
2147 spin_unlock_irq(&cm
->reg_lock
);
2151 val
= inb(cm
->iobase
+ args
->reg
);
2153 val
= snd_cmipci_read(cm
, args
->reg
);
2154 ucontrol
->value
.integer
.value
[0] = ((val
& args
->mask
) == args
->mask_on
) ? 1 : 0;
2155 spin_unlock_irq(&cm
->reg_lock
);
2159 static int snd_cmipci_uswitch_get(snd_kcontrol_t
*kcontrol
, snd_ctl_elem_value_t
*ucontrol
)
2161 snd_cmipci_switch_args_t
*args
= (snd_cmipci_switch_args_t
*)kcontrol
->private_value
;
2162 snd_assert(args
!= NULL
, return -EINVAL
);
2163 return _snd_cmipci_uswitch_get(kcontrol
, ucontrol
, args
);
2166 static int _snd_cmipci_uswitch_put(snd_kcontrol_t
*kcontrol
, snd_ctl_elem_value_t
*ucontrol
, snd_cmipci_switch_args_t
*args
)
2170 cmipci_t
*cm
= snd_kcontrol_chip(kcontrol
);
2172 spin_lock_irq(&cm
->reg_lock
);
2173 if (args
->ac3_sensitive
&& cm
->mixer_insensitive
) {
2175 spin_unlock_irq(&cm
->reg_lock
);
2179 val
= inb(cm
->iobase
+ args
->reg
);
2181 val
= snd_cmipci_read(cm
, args
->reg
);
2182 change
= (val
& args
->mask
) != (ucontrol
->value
.integer
.value
[0] ? args
->mask
: 0);
2185 if (ucontrol
->value
.integer
.value
[0])
2186 val
|= args
->mask_on
;
2188 val
|= (args
->mask
& ~args
->mask_on
);
2190 outb((unsigned char)val
, cm
->iobase
+ args
->reg
);
2192 snd_cmipci_write(cm
, args
->reg
, val
);
2194 spin_unlock_irq(&cm
->reg_lock
);
2198 static int snd_cmipci_uswitch_put(snd_kcontrol_t
*kcontrol
, snd_ctl_elem_value_t
*ucontrol
)
2200 snd_cmipci_switch_args_t
*args
= (snd_cmipci_switch_args_t
*)kcontrol
->private_value
;
2201 snd_assert(args
!= NULL
, return -EINVAL
);
2202 return _snd_cmipci_uswitch_put(kcontrol
, ucontrol
, args
);
2205 #define DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask_on, xis_byte, xac3) \
2206 static snd_cmipci_switch_args_t cmipci_switch_arg_##sname = { \
2209 .mask_on = xmask_on, \
2210 .is_byte = xis_byte, \
2211 .ac3_sensitive = xac3, \
2214 #define DEFINE_BIT_SWITCH_ARG(sname, xreg, xmask, xis_byte, xac3) \
2215 DEFINE_SWITCH_ARG(sname, xreg, xmask, xmask, xis_byte, xac3)
2217 #if 0 /* these will be controlled in pcm device */
2218 DEFINE_BIT_SWITCH_ARG(spdif_in
, CM_REG_FUNCTRL1
, CM_SPDF_1
, 0, 0);
2219 DEFINE_BIT_SWITCH_ARG(spdif_out
, CM_REG_FUNCTRL1
, CM_SPDF_0
, 0, 0);
2221 DEFINE_BIT_SWITCH_ARG(spdif_in_sel1
, CM_REG_CHFORMAT
, CM_SPDIF_SELECT1
, 0, 0);
2222 DEFINE_BIT_SWITCH_ARG(spdif_in_sel2
, CM_REG_MISC_CTRL
, CM_SPDIF_SELECT2
, 0, 0);
2223 DEFINE_BIT_SWITCH_ARG(spdif_enable
, CM_REG_LEGACY_CTRL
, CM_ENSPDOUT
, 0, 0);
2224 DEFINE_BIT_SWITCH_ARG(spdo2dac
, CM_REG_FUNCTRL1
, CM_SPDO2DAC
, 0, 1);
2225 DEFINE_BIT_SWITCH_ARG(spdi_valid
, CM_REG_MISC
, CM_SPDVALID
, 1, 0);
2226 DEFINE_BIT_SWITCH_ARG(spdif_copyright
, CM_REG_LEGACY_CTRL
, CM_SPDCOPYRHT
, 0, 0);
2227 DEFINE_BIT_SWITCH_ARG(spdif_dac_out
, CM_REG_LEGACY_CTRL
, CM_DAC2SPDO
, 0, 1);
2228 DEFINE_SWITCH_ARG(spdo_5v
, CM_REG_MISC_CTRL
, CM_SPDO5V
, 0, 0, 0); /* inverse: 0 = 5V */
2229 // DEFINE_BIT_SWITCH_ARG(spdo_48k, CM_REG_MISC_CTRL, CM_SPDF_AC97|CM_SPDIF48K, 0, 1);
2230 DEFINE_BIT_SWITCH_ARG(spdif_loop
, CM_REG_FUNCTRL1
, CM_SPDFLOOP
, 0, 1);
2231 DEFINE_BIT_SWITCH_ARG(spdi_monitor
, CM_REG_MIXER1
, CM_CDPLAY
, 1, 0);
2232 /* DEFINE_BIT_SWITCH_ARG(spdi_phase, CM_REG_CHFORMAT, CM_SPDIF_INVERSE, 0, 0); */
2233 DEFINE_BIT_SWITCH_ARG(spdi_phase
, CM_REG_MISC
, CM_SPDIF_INVERSE
, 1, 0);
2234 DEFINE_BIT_SWITCH_ARG(spdi_phase2
, CM_REG_CHFORMAT
, CM_SPDIF_INVERSE2
, 0, 0);
2236 DEFINE_SWITCH_ARG(exchange_dac
, CM_REG_MISC_CTRL
, CM_XCHGDAC
, 0, 0, 0); /* reversed */
2238 DEFINE_SWITCH_ARG(exchange_dac
, CM_REG_MISC_CTRL
, CM_XCHGDAC
, CM_XCHGDAC
, 0, 0);
2240 DEFINE_BIT_SWITCH_ARG(fourch
, CM_REG_MISC_CTRL
, CM_N4SPK3D
, 0, 0);
2241 // DEFINE_BIT_SWITCH_ARG(line_rear, CM_REG_MIXER1, CM_SPK4, 1, 0);
2242 // DEFINE_BIT_SWITCH_ARG(line_bass, CM_REG_LEGACY_CTRL, CM_LINE_AS_BASS, 0, 0);
2243 // DEFINE_BIT_SWITCH_ARG(joystick, CM_REG_FUNCTRL1, CM_JYSTK_EN, 0, 0); /* now module option */
2244 DEFINE_SWITCH_ARG(modem
, CM_REG_MISC_CTRL
, CM_FLINKON
|CM_FLINKOFF
, CM_FLINKON
, 0, 0);
2246 #define DEFINE_SWITCH(sname, stype, sarg) \
2249 .info = snd_cmipci_uswitch_info, \
2250 .get = snd_cmipci_uswitch_get, \
2251 .put = snd_cmipci_uswitch_put, \
2252 .private_value = (unsigned long)&cmipci_switch_arg_##sarg,\
2255 #define DEFINE_CARD_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_CARD, sarg)
2256 #define DEFINE_MIXER_SWITCH(sname, sarg) DEFINE_SWITCH(sname, SNDRV_CTL_ELEM_IFACE_MIXER, sarg)
2260 * callbacks for spdif output switch
2261 * needs toggle two registers..
2263 static int snd_cmipci_spdout_enable_get(snd_kcontrol_t
*kcontrol
, snd_ctl_elem_value_t
*ucontrol
)
2266 changed
= _snd_cmipci_uswitch_get(kcontrol
, ucontrol
, &cmipci_switch_arg_spdif_enable
);
2267 changed
|= _snd_cmipci_uswitch_get(kcontrol
, ucontrol
, &cmipci_switch_arg_spdo2dac
);
2271 static int snd_cmipci_spdout_enable_put(snd_kcontrol_t
*kcontrol
, snd_ctl_elem_value_t
*ucontrol
)
2273 cmipci_t
*chip
= snd_kcontrol_chip(kcontrol
);
2275 changed
= _snd_cmipci_uswitch_put(kcontrol
, ucontrol
, &cmipci_switch_arg_spdif_enable
);
2276 changed
|= _snd_cmipci_uswitch_put(kcontrol
, ucontrol
, &cmipci_switch_arg_spdo2dac
);
2278 if (ucontrol
->value
.integer
.value
[0]) {
2279 if (chip
->spdif_playback_avail
)
2280 snd_cmipci_set_bit(chip
, CM_REG_FUNCTRL1
, CM_PLAYBACK_SPDF
);
2282 if (chip
->spdif_playback_avail
)
2283 snd_cmipci_clear_bit(chip
, CM_REG_FUNCTRL1
, CM_PLAYBACK_SPDF
);
2286 chip
->spdif_playback_enabled
= ucontrol
->value
.integer
.value
[0];
2291 static int snd_cmipci_line_in_mode_info(snd_kcontrol_t
*kcontrol
,
2292 snd_ctl_elem_info_t
*uinfo
)
2294 cmipci_t
*cm
= snd_kcontrol_chip(kcontrol
);
2295 static char *texts
[3] = { "Line-In", "Rear Output", "Bass Output" };
2296 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_ENUMERATED
;
2298 uinfo
->value
.enumerated
.items
= cm
->chip_version
>= 39 ? 3 : 2;
2299 if (uinfo
->value
.enumerated
.item
>= uinfo
->value
.enumerated
.items
)
2300 uinfo
->value
.enumerated
.item
= uinfo
->value
.enumerated
.items
- 1;
2301 strcpy(uinfo
->value
.enumerated
.name
, texts
[uinfo
->value
.enumerated
.item
]);
2305 static inline unsigned int get_line_in_mode(cmipci_t
*cm
)
2308 if (cm
->chip_version
>= 39) {
2309 val
= snd_cmipci_read(cm
, CM_REG_LEGACY_CTRL
);
2310 if (val
& CM_LINE_AS_BASS
)
2313 val
= snd_cmipci_read_b(cm
, CM_REG_MIXER1
);
2319 static int snd_cmipci_line_in_mode_get(snd_kcontrol_t
*kcontrol
,
2320 snd_ctl_elem_value_t
*ucontrol
)
2322 cmipci_t
*cm
= snd_kcontrol_chip(kcontrol
);
2324 spin_lock_irq(&cm
->reg_lock
);
2325 ucontrol
->value
.enumerated
.item
[0] = get_line_in_mode(cm
);
2326 spin_unlock_irq(&cm
->reg_lock
);
2330 static int snd_cmipci_line_in_mode_put(snd_kcontrol_t
*kcontrol
,
2331 snd_ctl_elem_value_t
*ucontrol
)
2333 cmipci_t
*cm
= snd_kcontrol_chip(kcontrol
);
2336 spin_lock_irq(&cm
->reg_lock
);
2337 if (ucontrol
->value
.enumerated
.item
[0] == 2)
2338 change
= snd_cmipci_set_bit(cm
, CM_REG_LEGACY_CTRL
, CM_LINE_AS_BASS
);
2340 change
= snd_cmipci_clear_bit(cm
, CM_REG_LEGACY_CTRL
, CM_LINE_AS_BASS
);
2341 if (ucontrol
->value
.enumerated
.item
[0] == 1)
2342 change
|= snd_cmipci_set_bit_b(cm
, CM_REG_MIXER1
, CM_SPK4
);
2344 change
|= snd_cmipci_clear_bit_b(cm
, CM_REG_MIXER1
, CM_SPK4
);
2345 spin_unlock_irq(&cm
->reg_lock
);
2349 static int snd_cmipci_mic_in_mode_info(snd_kcontrol_t
*kcontrol
,
2350 snd_ctl_elem_info_t
*uinfo
)
2352 static char *texts
[2] = { "Mic-In", "Center/LFE Output" };
2353 uinfo
->type
= SNDRV_CTL_ELEM_TYPE_ENUMERATED
;
2355 uinfo
->value
.enumerated
.items
= 2;
2356 if (uinfo
->value
.enumerated
.item
>= uinfo
->value
.enumerated
.items
)
2357 uinfo
->value
.enumerated
.item
= uinfo
->value
.enumerated
.items
- 1;
2358 strcpy(uinfo
->value
.enumerated
.name
, texts
[uinfo
->value
.enumerated
.item
]);
2362 static int snd_cmipci_mic_in_mode_get(snd_kcontrol_t
*kcontrol
,
2363 snd_ctl_elem_value_t
*ucontrol
)
2365 cmipci_t
*cm
= snd_kcontrol_chip(kcontrol
);
2366 /* same bit as spdi_phase */
2367 spin_lock_irq(&cm
->reg_lock
);
2368 ucontrol
->value
.enumerated
.item
[0] =
2369 (snd_cmipci_read_b(cm
, CM_REG_MISC
) & CM_SPDIF_INVERSE
) ? 1 : 0;
2370 spin_unlock_irq(&cm
->reg_lock
);
2374 static int snd_cmipci_mic_in_mode_put(snd_kcontrol_t
*kcontrol
,
2375 snd_ctl_elem_value_t
*ucontrol
)
2377 cmipci_t
*cm
= snd_kcontrol_chip(kcontrol
);
2380 spin_lock_irq(&cm
->reg_lock
);
2381 if (ucontrol
->value
.enumerated
.item
[0])
2382 change
= snd_cmipci_set_bit_b(cm
, CM_REG_MISC
, CM_SPDIF_INVERSE
);
2384 change
= snd_cmipci_clear_bit_b(cm
, CM_REG_MISC
, CM_SPDIF_INVERSE
);
2385 spin_unlock_irq(&cm
->reg_lock
);
2389 /* both for CM8338/8738 */
2390 static snd_kcontrol_new_t snd_cmipci_mixer_switches
[] __devinitdata
= {
2391 DEFINE_MIXER_SWITCH("Four Channel Mode", fourch
),
2393 .name
= "Line-In Mode",
2394 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2395 .info
= snd_cmipci_line_in_mode_info
,
2396 .get
= snd_cmipci_line_in_mode_get
,
2397 .put
= snd_cmipci_line_in_mode_put
,
2401 /* for non-multichannel chips */
2402 static snd_kcontrol_new_t snd_cmipci_nomulti_switch __devinitdata
=
2403 DEFINE_MIXER_SWITCH("Exchange DAC", exchange_dac
);
2405 /* only for CM8738 */
2406 static snd_kcontrol_new_t snd_cmipci_8738_mixer_switches
[] __devinitdata
= {
2407 #if 0 /* controlled in pcm device */
2408 DEFINE_MIXER_SWITCH("IEC958 In Record", spdif_in
),
2409 DEFINE_MIXER_SWITCH("IEC958 Out", spdif_out
),
2410 DEFINE_MIXER_SWITCH("IEC958 Out To DAC", spdo2dac
),
2412 // DEFINE_MIXER_SWITCH("IEC958 Output Switch", spdif_enable),
2413 { .name
= "IEC958 Output Switch",
2414 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2415 .info
= snd_cmipci_uswitch_info
,
2416 .get
= snd_cmipci_spdout_enable_get
,
2417 .put
= snd_cmipci_spdout_enable_put
,
2419 DEFINE_MIXER_SWITCH("IEC958 In Valid", spdi_valid
),
2420 DEFINE_MIXER_SWITCH("IEC958 Copyright", spdif_copyright
),
2421 DEFINE_MIXER_SWITCH("IEC958 5V", spdo_5v
),
2422 // DEFINE_MIXER_SWITCH("IEC958 In/Out 48KHz", spdo_48k),
2423 DEFINE_MIXER_SWITCH("IEC958 Loop", spdif_loop
),
2424 DEFINE_MIXER_SWITCH("IEC958 In Monitor", spdi_monitor
),
2427 /* only for model 033/037 */
2428 static snd_kcontrol_new_t snd_cmipci_old_mixer_switches
[] __devinitdata
= {
2429 DEFINE_MIXER_SWITCH("IEC958 Mix Analog", spdif_dac_out
),
2430 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase
),
2431 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel1
),
2434 /* only for model 039 or later */
2435 static snd_kcontrol_new_t snd_cmipci_extra_mixer_switches
[] __devinitdata
= {
2436 DEFINE_MIXER_SWITCH("IEC958 In Select", spdif_in_sel2
),
2437 DEFINE_MIXER_SWITCH("IEC958 In Phase Inverse", spdi_phase2
),
2439 .name
= "Mic-In Mode",
2440 .iface
= SNDRV_CTL_ELEM_IFACE_MIXER
,
2441 .info
= snd_cmipci_mic_in_mode_info
,
2442 .get
= snd_cmipci_mic_in_mode_get
,
2443 .put
= snd_cmipci_mic_in_mode_put
,
2447 /* card control switches */
2448 static snd_kcontrol_new_t snd_cmipci_control_switches
[] __devinitdata
= {
2449 // DEFINE_CARD_SWITCH("Joystick", joystick), /* now module option */
2450 DEFINE_CARD_SWITCH("Modem", modem
),
2454 static int __devinit
snd_cmipci_mixer_new(cmipci_t
*cm
, int pcm_spdif_device
)
2457 snd_kcontrol_new_t
*sw
;
2458 snd_kcontrol_t
*kctl
;
2462 snd_assert(cm
!= NULL
&& cm
->card
!= NULL
, return -EINVAL
);
2466 strcpy(card
->mixername
, "CMedia PCI");
2468 spin_lock_irq(&cm
->reg_lock
);
2469 snd_cmipci_mixer_write(cm
, 0x00, 0x00); /* mixer reset */
2470 spin_unlock_irq(&cm
->reg_lock
);
2472 for (idx
= 0; idx
< ARRAY_SIZE(snd_cmipci_mixers
); idx
++) {
2473 if (cm
->chip_version
== 68) { // 8768 has no PCM volume
2474 if (!strcmp(snd_cmipci_mixers
[idx
].name
,
2475 "PCM Playback Volume"))
2478 if ((err
= snd_ctl_add(card
, snd_ctl_new1(&snd_cmipci_mixers
[idx
], cm
))) < 0)
2482 /* mixer switches */
2483 sw
= snd_cmipci_mixer_switches
;
2484 for (idx
= 0; idx
< ARRAY_SIZE(snd_cmipci_mixer_switches
); idx
++, sw
++) {
2485 err
= snd_ctl_add(cm
->card
, snd_ctl_new1(sw
, cm
));
2489 if (! cm
->can_multi_ch
) {
2490 err
= snd_ctl_add(cm
->card
, snd_ctl_new1(&snd_cmipci_nomulti_switch
, cm
));
2494 if (cm
->device
== PCI_DEVICE_ID_CMEDIA_CM8738
||
2495 cm
->device
== PCI_DEVICE_ID_CMEDIA_CM8738B
) {
2496 sw
= snd_cmipci_8738_mixer_switches
;
2497 for (idx
= 0; idx
< ARRAY_SIZE(snd_cmipci_8738_mixer_switches
); idx
++, sw
++) {
2498 err
= snd_ctl_add(cm
->card
, snd_ctl_new1(sw
, cm
));
2502 if (cm
->can_ac3_hw
) {
2503 if ((err
= snd_ctl_add(card
, kctl
= snd_ctl_new1(&snd_cmipci_spdif_default
, cm
))) < 0)
2505 kctl
->id
.device
= pcm_spdif_device
;
2506 if ((err
= snd_ctl_add(card
, kctl
= snd_ctl_new1(&snd_cmipci_spdif_mask
, cm
))) < 0)
2508 kctl
->id
.device
= pcm_spdif_device
;
2509 if ((err
= snd_ctl_add(card
, kctl
= snd_ctl_new1(&snd_cmipci_spdif_stream
, cm
))) < 0)
2511 kctl
->id
.device
= pcm_spdif_device
;
2513 if (cm
->chip_version
<= 37) {
2514 sw
= snd_cmipci_old_mixer_switches
;
2515 for (idx
= 0; idx
< ARRAY_SIZE(snd_cmipci_old_mixer_switches
); idx
++, sw
++) {
2516 err
= snd_ctl_add(cm
->card
, snd_ctl_new1(sw
, cm
));
2522 if (cm
->chip_version
>= 39) {
2523 sw
= snd_cmipci_extra_mixer_switches
;
2524 for (idx
= 0; idx
< ARRAY_SIZE(snd_cmipci_extra_mixer_switches
); idx
++, sw
++) {
2525 err
= snd_ctl_add(cm
->card
, snd_ctl_new1(sw
, cm
));
2532 sw
= snd_cmipci_control_switches
;
2533 for (idx
= 0; idx
< ARRAY_SIZE(snd_cmipci_control_switches
); idx
++, sw
++) {
2534 err
= snd_ctl_add(cm
->card
, snd_ctl_new1(sw
, cm
));
2539 for (idx
= 0; idx
< CM_SAVED_MIXERS
; idx
++) {
2540 snd_ctl_elem_id_t id
;
2541 snd_kcontrol_t
*ctl
;
2542 memset(&id
, 0, sizeof(id
));
2543 id
.iface
= SNDRV_CTL_ELEM_IFACE_MIXER
;
2544 strcpy(id
.name
, cm_saved_mixer
[idx
].name
);
2545 if ((ctl
= snd_ctl_find_id(cm
->card
, &id
)) != NULL
)
2546 cm
->mixer_res_ctl
[idx
] = ctl
;
2557 #ifdef CONFIG_PROC_FS
2558 static void snd_cmipci_proc_read(snd_info_entry_t
*entry
,
2559 snd_info_buffer_t
*buffer
)
2561 cmipci_t
*cm
= entry
->private_data
;
2564 snd_iprintf(buffer
, "%s\n\n", cm
->card
->longname
);
2565 for (i
= 0; i
< 0x40; i
++) {
2566 int v
= inb(cm
->iobase
+ i
);
2568 snd_iprintf(buffer
, "%02x: ", i
);
2569 snd_iprintf(buffer
, "%02x", v
);
2571 snd_iprintf(buffer
, "\n");
2573 snd_iprintf(buffer
, " ");
2577 static void __devinit
snd_cmipci_proc_init(cmipci_t
*cm
)
2579 snd_info_entry_t
*entry
;
2581 if (! snd_card_proc_new(cm
->card
, "cmipci", &entry
))
2582 snd_info_set_text_ops(entry
, cm
, 1024, snd_cmipci_proc_read
);
2584 #else /* !CONFIG_PROC_FS */
2585 static inline void snd_cmipci_proc_init(cmipci_t
*cm
) {}
2589 static struct pci_device_id snd_cmipci_ids
[] = {
2590 {PCI_VENDOR_ID_CMEDIA
, PCI_DEVICE_ID_CMEDIA_CM8338A
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
2591 {PCI_VENDOR_ID_CMEDIA
, PCI_DEVICE_ID_CMEDIA_CM8338B
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
2592 {PCI_VENDOR_ID_CMEDIA
, PCI_DEVICE_ID_CMEDIA_CM8738
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
2593 {PCI_VENDOR_ID_CMEDIA
, PCI_DEVICE_ID_CMEDIA_CM8738B
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
2594 {PCI_VENDOR_ID_AL
, PCI_DEVICE_ID_CMEDIA_CM8738
, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0},
2600 * check chip version and capabilities
2601 * driver name is modified according to the chip model
2603 static void __devinit
query_chip(cmipci_t
*cm
)
2605 unsigned int detect
;
2607 /* check reg 0Ch, bit 24-31 */
2608 detect
= snd_cmipci_read(cm
, CM_REG_INT_HLDCLR
) & CM_CHIP_MASK2
;
2610 /* check reg 08h, bit 24-28 */
2611 detect
= snd_cmipci_read(cm
, CM_REG_CHFORMAT
) & CM_CHIP_MASK1
;
2613 cm
->chip_version
= 33;
2614 cm
->max_channels
= 2;
2615 if (cm
->do_soft_ac3
)
2619 cm
->has_dual_dac
= 1;
2621 cm
->chip_version
= 37;
2622 cm
->max_channels
= 2;
2624 cm
->has_dual_dac
= 1;
2627 /* check reg 0Ch, bit 26 */
2628 if (detect
& CM_CHIP_8768
) {
2629 cm
->chip_version
= 68;
2630 cm
->max_channels
= 8;
2632 cm
->has_dual_dac
= 1;
2633 cm
->can_multi_ch
= 1;
2634 } else if (detect
& CM_CHIP_055
) {
2635 cm
->chip_version
= 55;
2636 cm
->max_channels
= 6;
2638 cm
->has_dual_dac
= 1;
2639 cm
->can_multi_ch
= 1;
2640 } else if (detect
& CM_CHIP_039
) {
2641 cm
->chip_version
= 39;
2642 if (detect
& CM_CHIP_039_6CH
) /* 4 or 6 channels */
2643 cm
->max_channels
= 6;
2645 cm
->max_channels
= 4;
2647 cm
->has_dual_dac
= 1;
2648 cm
->can_multi_ch
= 1;
2650 printk(KERN_ERR
"chip %x version not supported\n", detect
);
2655 #ifdef SUPPORT_JOYSTICK
2656 static int __devinit
snd_cmipci_create_gameport(cmipci_t
*cm
, int dev
)
2658 static int ports
[] = { 0x201, 0x200, 0 }; /* FIXME: majority is 0x201? */
2659 struct gameport
*gp
;
2660 struct resource
*r
= NULL
;
2663 if (joystick_port
[dev
] == 0)
2666 if (joystick_port
[dev
] == 1) { /* auto-detect */
2667 for (i
= 0; ports
[i
]; i
++) {
2669 r
= request_region(io_port
, 1, "CMIPCI gameport");
2674 io_port
= joystick_port
[dev
];
2675 r
= request_region(io_port
, 1, "CMIPCI gameport");
2679 printk(KERN_WARNING
"cmipci: cannot reserve joystick ports\n");
2683 cm
->gameport
= gp
= gameport_allocate_port();
2685 printk(KERN_ERR
"cmipci: cannot allocate memory for gameport\n");
2686 release_and_free_resource(r
);
2689 gameport_set_name(gp
, "C-Media Gameport");
2690 gameport_set_phys(gp
, "pci%s/gameport0", pci_name(cm
->pci
));
2691 gameport_set_dev_parent(gp
, &cm
->pci
->dev
);
2693 gameport_set_port_data(gp
, r
);
2695 snd_cmipci_set_bit(cm
, CM_REG_FUNCTRL1
, CM_JYSTK_EN
);
2697 gameport_register_port(cm
->gameport
);
2702 static void snd_cmipci_free_gameport(cmipci_t
*cm
)
2705 struct resource
*r
= gameport_get_port_data(cm
->gameport
);
2707 gameport_unregister_port(cm
->gameport
);
2708 cm
->gameport
= NULL
;
2710 snd_cmipci_clear_bit(cm
, CM_REG_FUNCTRL1
, CM_JYSTK_EN
);
2711 release_and_free_resource(r
);
2715 static inline int snd_cmipci_create_gameport(cmipci_t
*cm
, int dev
) { return -ENOSYS
; }
2716 static inline void snd_cmipci_free_gameport(cmipci_t
*cm
) { }
2719 static int snd_cmipci_free(cmipci_t
*cm
)
2722 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_FM_EN
);
2723 snd_cmipci_clear_bit(cm
, CM_REG_LEGACY_CTRL
, CM_ENSPDOUT
);
2724 snd_cmipci_write(cm
, CM_REG_INT_HLDCLR
, 0); /* disable ints */
2725 snd_cmipci_ch_reset(cm
, CM_CH_PLAY
);
2726 snd_cmipci_ch_reset(cm
, CM_CH_CAPT
);
2727 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, 0); /* disable channels */
2728 snd_cmipci_write(cm
, CM_REG_FUNCTRL1
, 0);
2731 snd_cmipci_mixer_write(cm
, 0, 0);
2733 synchronize_irq(cm
->irq
);
2735 free_irq(cm
->irq
, (void *)cm
);
2738 snd_cmipci_free_gameport(cm
);
2739 pci_release_regions(cm
->pci
);
2740 pci_disable_device(cm
->pci
);
2745 static int snd_cmipci_dev_free(snd_device_t
*device
)
2747 cmipci_t
*cm
= device
->device_data
;
2748 return snd_cmipci_free(cm
);
2751 static int __devinit
snd_cmipci_create_fm(cmipci_t
*cm
, long fm_port
)
2758 /* first try FM regs in PCI port range */
2759 iosynth
= cm
->iobase
+ CM_REG_FM_PCI
;
2760 err
= snd_opl3_create(cm
->card
, iosynth
, iosynth
+ 2,
2761 OPL3_HW_OPL3
, 1, &opl3
);
2763 /* then try legacy ports */
2764 val
= snd_cmipci_read(cm
, CM_REG_LEGACY_CTRL
) & ~CM_FMSEL_MASK
;
2767 case 0x3E8: val
|= CM_FMSEL_3E8
; break;
2768 case 0x3E0: val
|= CM_FMSEL_3E0
; break;
2769 case 0x3C8: val
|= CM_FMSEL_3C8
; break;
2770 case 0x388: val
|= CM_FMSEL_388
; break;
2774 snd_cmipci_write(cm
, CM_REG_LEGACY_CTRL
, val
);
2776 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_FM_EN
);
2778 if (snd_opl3_create(cm
->card
, iosynth
, iosynth
+ 2,
2779 OPL3_HW_OPL3
, 0, &opl3
) < 0) {
2780 printk(KERN_ERR
"cmipci: no OPL device at %#lx, "
2781 "skipping...\n", iosynth
);
2783 snd_cmipci_write(cm
, CM_REG_LEGACY_CTRL
,
2784 val
& ~CM_FMSEL_MASK
);
2785 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_FM_EN
);
2789 if ((err
= snd_opl3_hwdep_new(opl3
, 0, 1, NULL
)) < 0) {
2790 printk(KERN_ERR
"cmipci: cannot create OPL3 hwdep\n");
2796 static int __devinit
snd_cmipci_create(snd_card_t
*card
, struct pci_dev
*pci
,
2797 int dev
, cmipci_t
**rcmipci
)
2801 static snd_device_ops_t ops
= {
2802 .dev_free
= snd_cmipci_dev_free
,
2804 unsigned int val
= 0;
2806 int integrated_midi
;
2807 int pcm_index
, pcm_spdif_index
;
2808 static struct pci_device_id intel_82437vx
[] = {
2809 { PCI_DEVICE(PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82437VX
) },
2815 if ((err
= pci_enable_device(pci
)) < 0)
2818 cm
= kzalloc(sizeof(*cm
), GFP_KERNEL
);
2820 pci_disable_device(pci
);
2824 spin_lock_init(&cm
->reg_lock
);
2825 init_MUTEX(&cm
->open_mutex
);
2826 cm
->device
= pci
->device
;
2830 cm
->channel
[0].ch
= 0;
2831 cm
->channel
[1].ch
= 1;
2832 cm
->channel
[0].is_dac
= cm
->channel
[1].is_dac
= 1; /* dual DAC mode */
2834 if ((err
= pci_request_regions(pci
, card
->driver
)) < 0) {
2836 pci_disable_device(pci
);
2839 cm
->iobase
= pci_resource_start(pci
, 0);
2841 if (request_irq(pci
->irq
, snd_cmipci_interrupt
, SA_INTERRUPT
|SA_SHIRQ
, card
->driver
, (void *)cm
)) {
2842 snd_printk(KERN_ERR
"unable to grab IRQ %d\n", pci
->irq
);
2843 snd_cmipci_free(cm
);
2848 pci_set_master(cm
->pci
);
2851 * check chip version, max channels and capabilities
2854 cm
->chip_version
= 0;
2855 cm
->max_channels
= 2;
2856 cm
->do_soft_ac3
= soft_ac3
[dev
];
2858 if (pci
->device
!= PCI_DEVICE_ID_CMEDIA_CM8338A
&&
2859 pci
->device
!= PCI_DEVICE_ID_CMEDIA_CM8338B
)
2861 /* added -MCx suffix for chip supporting multi-channels */
2862 if (cm
->can_multi_ch
)
2863 sprintf(cm
->card
->driver
+ strlen(cm
->card
->driver
),
2864 "-MC%d", cm
->max_channels
);
2865 else if (cm
->can_ac3_sw
)
2866 strcpy(cm
->card
->driver
+ strlen(cm
->card
->driver
), "-SWIEC");
2868 cm
->dig_status
= SNDRV_PCM_DEFAULT_CON_SPDIF
;
2869 cm
->dig_pcm_status
= SNDRV_PCM_DEFAULT_CON_SPDIF
;
2872 cm
->ctrl
= CM_CHADC0
; /* default FUNCNTRL0 */
2874 cm
->ctrl
= CM_CHADC1
; /* default FUNCNTRL0 */
2877 /* initialize codec registers */
2878 snd_cmipci_write(cm
, CM_REG_INT_HLDCLR
, 0); /* disable ints */
2879 snd_cmipci_ch_reset(cm
, CM_CH_PLAY
);
2880 snd_cmipci_ch_reset(cm
, CM_CH_CAPT
);
2881 snd_cmipci_write(cm
, CM_REG_FUNCTRL0
, 0); /* disable channels */
2882 snd_cmipci_write(cm
, CM_REG_FUNCTRL1
, 0);
2884 snd_cmipci_write(cm
, CM_REG_CHFORMAT
, 0);
2885 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_ENDBDAC
|CM_N4SPK3D
);
2887 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_XCHGDAC
);
2889 snd_cmipci_clear_bit(cm
, CM_REG_MISC_CTRL
, CM_XCHGDAC
);
2891 /* Set Bus Master Request */
2892 snd_cmipci_set_bit(cm
, CM_REG_FUNCTRL1
, CM_BREQ
);
2894 /* Assume TX and compatible chip set (Autodetection required for VX chip sets) */
2895 switch (pci
->device
) {
2896 case PCI_DEVICE_ID_CMEDIA_CM8738
:
2897 case PCI_DEVICE_ID_CMEDIA_CM8738B
:
2898 if (!pci_dev_present(intel_82437vx
))
2899 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_TXVX
);
2905 if ((err
= snd_device_new(card
, SNDRV_DEV_LOWLEVEL
, cm
, &ops
)) < 0) {
2906 snd_cmipci_free(cm
);
2910 integrated_midi
= snd_cmipci_read_b(cm
, CM_REG_MPU_PCI
) != 0xff;
2911 if (integrated_midi
)
2912 iomidi
= cm
->iobase
+ CM_REG_MPU_PCI
;
2914 iomidi
= mpu_port
[dev
];
2916 case 0x320: val
= CM_VMPU_320
; break;
2917 case 0x310: val
= CM_VMPU_310
; break;
2918 case 0x300: val
= CM_VMPU_300
; break;
2919 case 0x330: val
= CM_VMPU_330
; break;
2924 snd_cmipci_write(cm
, CM_REG_LEGACY_CTRL
, val
);
2926 snd_cmipci_set_bit(cm
, CM_REG_FUNCTRL1
, CM_UART_EN
);
2930 if ((err
= snd_cmipci_create_fm(cm
, fm_port
[dev
])) < 0)
2934 snd_cmipci_mixer_write(cm
, 0, 0);
2936 snd_cmipci_proc_init(cm
);
2938 /* create pcm devices */
2939 pcm_index
= pcm_spdif_index
= 0;
2940 if ((err
= snd_cmipci_pcm_new(cm
, pcm_index
)) < 0)
2943 if (cm
->has_dual_dac
) {
2944 if ((err
= snd_cmipci_pcm2_new(cm
, pcm_index
)) < 0)
2948 if (cm
->can_ac3_hw
|| cm
->can_ac3_sw
) {
2949 pcm_spdif_index
= pcm_index
;
2950 if ((err
= snd_cmipci_pcm_spdif_new(cm
, pcm_index
)) < 0)
2954 /* create mixer interface & switches */
2955 if ((err
= snd_cmipci_mixer_new(cm
, pcm_spdif_index
)) < 0)
2959 if ((err
= snd_mpu401_uart_new(card
, 0, MPU401_HW_CMIPCI
,
2960 iomidi
, integrated_midi
,
2961 cm
->irq
, 0, &cm
->rmidi
)) < 0) {
2962 printk(KERN_ERR
"cmipci: no UART401 device at 0x%lx\n", iomidi
);
2966 #ifdef USE_VAR48KRATE
2967 for (val
= 0; val
< ARRAY_SIZE(rates
); val
++)
2968 snd_cmipci_set_pll(cm
, rates
[val
], val
);
2971 * (Re-)Enable external switch spdo_48k
2973 snd_cmipci_set_bit(cm
, CM_REG_MISC_CTRL
, CM_SPDIF48K
|CM_SPDF_AC97
);
2974 #endif /* USE_VAR48KRATE */
2976 if (snd_cmipci_create_gameport(cm
, dev
) < 0)
2977 snd_cmipci_clear_bit(cm
, CM_REG_FUNCTRL1
, CM_JYSTK_EN
);
2979 snd_card_set_dev(card
, &pci
->dev
);
2988 MODULE_DEVICE_TABLE(pci
, snd_cmipci_ids
);
2990 static int __devinit
snd_cmipci_probe(struct pci_dev
*pci
,
2991 const struct pci_device_id
*pci_id
)
2998 if (dev
>= SNDRV_CARDS
)
3000 if (! enable
[dev
]) {
3005 card
= snd_card_new(index
[dev
], id
[dev
], THIS_MODULE
, 0);
3009 switch (pci
->device
) {
3010 case PCI_DEVICE_ID_CMEDIA_CM8738
:
3011 case PCI_DEVICE_ID_CMEDIA_CM8738B
:
3012 strcpy(card
->driver
, "CMI8738");
3014 case PCI_DEVICE_ID_CMEDIA_CM8338A
:
3015 case PCI_DEVICE_ID_CMEDIA_CM8338B
:
3016 strcpy(card
->driver
, "CMI8338");
3019 strcpy(card
->driver
, "CMIPCI");
3023 if ((err
= snd_cmipci_create(card
, pci
, dev
, &cm
)) < 0) {
3024 snd_card_free(card
);
3028 sprintf(card
->shortname
, "C-Media PCI %s", card
->driver
);
3029 sprintf(card
->longname
, "%s (model %d) at 0x%lx, irq %i",
3035 //snd_printd("%s is detected\n", card->longname);
3037 if ((err
= snd_card_register(card
)) < 0) {
3038 snd_card_free(card
);
3041 pci_set_drvdata(pci
, card
);
3047 static void __devexit
snd_cmipci_remove(struct pci_dev
*pci
)
3049 snd_card_free(pci_get_drvdata(pci
));
3050 pci_set_drvdata(pci
, NULL
);
3054 static struct pci_driver driver
= {
3055 .name
= "C-Media PCI",
3056 .id_table
= snd_cmipci_ids
,
3057 .probe
= snd_cmipci_probe
,
3058 .remove
= __devexit_p(snd_cmipci_remove
),
3061 static int __init
alsa_card_cmipci_init(void)
3063 return pci_register_driver(&driver
);
3066 static void __exit
alsa_card_cmipci_exit(void)
3068 pci_unregister_driver(&driver
);
3071 module_init(alsa_card_cmipci_init
)
3072 module_exit(alsa_card_cmipci_exit
)