drivers/net/mv643xx_eth.h

   1 #ifndef __MV643XX_ETH_H__
   2 #define __MV643XX_ETH_H__
   3
   4 #include <linux/module.h>
   5 #include <linux/kernel.h>
   6 #include <linux/spinlock.h>
   7 #include <linux/workqueue.h>
   8
   9 #include <linux/mv643xx.h>
  10
  11 #define BIT0    0x00000001
  12 #define BIT1    0x00000002
  13 #define BIT2    0x00000004
  14 #define BIT3    0x00000008
  15 #define BIT4    0x00000010
  16 #define BIT5    0x00000020
  17 #define BIT6    0x00000040
  18 #define BIT7    0x00000080
  19 #define BIT8    0x00000100
  20 #define BIT9    0x00000200
  21 #define BIT10   0x00000400
  22 #define BIT11   0x00000800
  23 #define BIT12   0x00001000
  24 #define BIT13   0x00002000
  25 #define BIT14   0x00004000
  26 #define BIT15   0x00008000
  27 #define BIT16   0x00010000
  28 #define BIT17   0x00020000
  29 #define BIT18   0x00040000
  30 #define BIT19   0x00080000
  31 #define BIT20   0x00100000
  32 #define BIT21   0x00200000
  33 #define BIT22   0x00400000
  34 #define BIT23   0x00800000
  35 #define BIT24   0x01000000
  36 #define BIT25   0x02000000
  37 #define BIT26   0x04000000
  38 #define BIT27   0x08000000
  39 #define BIT28   0x10000000
  40 #define BIT29   0x20000000
  41 #define BIT30   0x40000000
  42 #define BIT31   0x80000000
  43
  44 /*
  45  *  The first part is the high level driver of the gigE ethernet ports.
  46  */
  47
  48 /* Checksum offload for Tx works for most packets, but
  49  * fails if previous packet sent did not use hw csum
  50  */
  51 #define MV643XX_CHECKSUM_OFFLOAD_TX
  52 #define MV643XX_NAPI
  53 #define MV643XX_TX_FAST_REFILL
  54 #undef  MV643XX_RX_QUEUE_FILL_ON_TASK   /* Does not work, yet */
  55 #undef  MV643XX_COAL
  56
  57 /*
  58  * Number of RX / TX descriptors on RX / TX rings.
  59  * Note that allocating RX descriptors is done by allocating the RX
  60  * ring AND a preallocated RX buffers (skb's) for each descriptor.
  61  * The TX descriptors only allocates the TX descriptors ring,
  62  * with no pre allocated TX buffers (skb's are allocated by higher layers.
  63  */
  64
  65 /* Default TX ring size is 1000 descriptors */
  66 #define MV643XX_DEFAULT_TX_QUEUE_SIZE 1000
  67
  68 /* Default RX ring size is 400 descriptors */
  69 #define MV643XX_DEFAULT_RX_QUEUE_SIZE 400
  70
  71 #define MV643XX_TX_COAL 100
  72 #ifdef MV643XX_COAL
  73 #define MV643XX_RX_COAL 100
  74 #endif
  75
  76 /*
  77  * The second part is the low level driver of the gigE ethernet ports.
  78  */
  79
  80 /*
  81  * Header File for : MV-643xx network interface header
  82  *
  83  * DESCRIPTION:
  84  *      This header file contains macros typedefs and function declaration for
  85  *      the Marvell Gig Bit Ethernet Controller.
  86  *
  87  * DEPENDENCIES:
  88  *      None.
  89  *
  90  */
  91
  92 /* MAC accepet/reject macros */
  93 #define ACCEPT_MAC_ADDR                         0
  94 #define REJECT_MAC_ADDR                         1
  95
  96 /* Buffer offset from buffer pointer */
  97 #define RX_BUF_OFFSET                           0x2
  98
  99 /* Gigabit Ethernet Unit Global Registers */
 100
 101 /* MIB Counters register definitions */
 102 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW        0x0
 103 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH       0x4
 104 #define ETH_MIB_BAD_OCTETS_RECEIVED             0x8
 105 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR       0xc
 106 #define ETH_MIB_GOOD_FRAMES_RECEIVED            0x10
 107 #define ETH_MIB_BAD_FRAMES_RECEIVED             0x14
 108 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED       0x18
 109 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED       0x1c
 110 #define ETH_MIB_FRAMES_64_OCTETS                0x20
 111 #define ETH_MIB_FRAMES_65_TO_127_OCTETS         0x24
 112 #define ETH_MIB_FRAMES_128_TO_255_OCTETS        0x28
 113 #define ETH_MIB_FRAMES_256_TO_511_OCTETS        0x2c
 114 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS       0x30
 115 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS       0x34
 116 #define ETH_MIB_GOOD_OCTETS_SENT_LOW            0x38
 117 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH           0x3c
 118 #define ETH_MIB_GOOD_FRAMES_SENT                0x40
 119 #define ETH_MIB_EXCESSIVE_COLLISION             0x44
 120 #define ETH_MIB_MULTICAST_FRAMES_SENT           0x48
 121 #define ETH_MIB_BROADCAST_FRAMES_SENT           0x4c
 122 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED      0x50
 123 #define ETH_MIB_FC_SENT                         0x54
 124 #define ETH_MIB_GOOD_FC_RECEIVED                0x58
 125 #define ETH_MIB_BAD_FC_RECEIVED                 0x5c
 126 #define ETH_MIB_UNDERSIZE_RECEIVED              0x60
 127 #define ETH_MIB_FRAGMENTS_RECEIVED              0x64
 128 #define ETH_MIB_OVERSIZE_RECEIVED               0x68
 129 #define ETH_MIB_JABBER_RECEIVED                 0x6c
 130 #define ETH_MIB_MAC_RECEIVE_ERROR               0x70
 131 #define ETH_MIB_BAD_CRC_EVENT                   0x74
 132 #define ETH_MIB_COLLISION                       0x78
 133 #define ETH_MIB_LATE_COLLISION                  0x7c
 134
 135 /* Port serial status reg (PSR) */
 136 #define ETH_INTERFACE_GMII_MII                  0
 137 #define ETH_INTERFACE_PCM                       BIT0
 138 #define ETH_LINK_IS_DOWN                        0
 139 #define ETH_LINK_IS_UP                          BIT1
 140 #define ETH_PORT_AT_HALF_DUPLEX                 0
 141 #define ETH_PORT_AT_FULL_DUPLEX                 BIT2
 142 #define ETH_RX_FLOW_CTRL_DISABLED               0
 143 #define ETH_RX_FLOW_CTRL_ENBALED                BIT3
 144 #define ETH_GMII_SPEED_100_10                   0
 145 #define ETH_GMII_SPEED_1000                     BIT4
 146 #define ETH_MII_SPEED_10                        0
 147 #define ETH_MII_SPEED_100                       BIT5
 148 #define ETH_NO_TX                               0
 149 #define ETH_TX_IN_PROGRESS                      BIT7
 150 #define ETH_BYPASS_NO_ACTIVE                    0
 151 #define ETH_BYPASS_ACTIVE                       BIT8
 152 #define ETH_PORT_NOT_AT_PARTITION_STATE         0
 153 #define ETH_PORT_AT_PARTITION_STATE             BIT9
 154 #define ETH_PORT_TX_FIFO_NOT_EMPTY              0
 155 #define ETH_PORT_TX_FIFO_EMPTY                  BIT10
 156
 157 #define ETH_DEFAULT_RX_BPDU_QUEUE_3             (BIT23 | BIT22)
 158 #define ETH_DEFAULT_RX_BPDU_QUEUE_4             BIT24
 159 #define ETH_DEFAULT_RX_BPDU_QUEUE_5             (BIT24 | BIT22)
 160 #define ETH_DEFAULT_RX_BPDU_QUEUE_6             (BIT24 | BIT23)
 161 #define ETH_DEFAULT_RX_BPDU_QUEUE_7             (BIT24 | BIT23 | BIT22)
 162
 163 /* SMI reg */
 164 #define ETH_SMI_BUSY            BIT28   /* 0 - Write, 1 - Read          */
 165 #define ETH_SMI_READ_VALID      BIT27   /* 0 - Write, 1 - Read          */
 166 #define ETH_SMI_OPCODE_WRITE    0       /* Completion of Read operation */
 167 #define ETH_SMI_OPCODE_READ     BIT26   /* Operation is in progress     */
 168
 169 /* SDMA command status fields macros */
 170
 171 /* Tx & Rx descriptors status */
 172 #define ETH_ERROR_SUMMARY                       (BIT0)
 173
 174 /* Tx & Rx descriptors command */
 175 #define ETH_BUFFER_OWNED_BY_DMA                 (BIT31)
 176
 177 /* Tx descriptors status */
 178 #define ETH_LC_ERROR                            (0    )
 179 #define ETH_UR_ERROR                            (BIT1 )
 180 #define ETH_RL_ERROR                            (BIT2 )
 181 #define ETH_LLC_SNAP_FORMAT                     (BIT9 )
 182
 183 /* Rx descriptors status */
 184 #define ETH_CRC_ERROR                           (0    )
 185 #define ETH_OVERRUN_ERROR                       (BIT1 )
 186 #define ETH_MAX_FRAME_LENGTH_ERROR              (BIT2 )
 187 #define ETH_RESOURCE_ERROR                      ((BIT2 | BIT1))
 188 #define ETH_VLAN_TAGGED                         (BIT19)
 189 #define ETH_BPDU_FRAME                          (BIT20)
 190 #define ETH_TCP_FRAME_OVER_IP_V_4               (0    )
 191 #define ETH_UDP_FRAME_OVER_IP_V_4               (BIT21)
 192 #define ETH_OTHER_FRAME_TYPE                    (BIT22)
 193 #define ETH_LAYER_2_IS_ETH_V_2                  (BIT23)
 194 #define ETH_FRAME_TYPE_IP_V_4                   (BIT24)
 195 #define ETH_FRAME_HEADER_OK                     (BIT25)
 196 #define ETH_RX_LAST_DESC                        (BIT26)
 197 #define ETH_RX_FIRST_DESC                       (BIT27)
 198 #define ETH_UNKNOWN_DESTINATION_ADDR            (BIT28)
 199 #define ETH_RX_ENABLE_INTERRUPT                 (BIT29)
 200 #define ETH_LAYER_4_CHECKSUM_OK                 (BIT30)
 201
 202 /* Rx descriptors byte count */
 203 #define ETH_FRAME_FRAGMENTED                    (BIT2)
 204
 205 /* Tx descriptors command */
 206 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC         (BIT10)
 207 #define ETH_FRAME_SET_TO_VLAN                   (BIT15)
 208 #define ETH_TCP_FRAME                           (0    )
 209 #define ETH_UDP_FRAME                           (BIT16)
 210 #define ETH_GEN_TCP_UDP_CHECKSUM                (BIT17)
 211 #define ETH_GEN_IP_V_4_CHECKSUM                 (BIT18)
 212 #define ETH_ZERO_PADDING                        (BIT19)
 213 #define ETH_TX_LAST_DESC                        (BIT20)
 214 #define ETH_TX_FIRST_DESC                       (BIT21)
 215 #define ETH_GEN_CRC                             (BIT22)
 216 #define ETH_TX_ENABLE_INTERRUPT                 (BIT23)
 217 #define ETH_AUTO_MODE                           (BIT30)
 218
 219 #define ETH_TX_IHL_SHIFT                        11
 220
 221 /* typedefs */
 222
 223 typedef enum _eth_func_ret_status {
 224         ETH_OK,                 /* Returned as expected.                */
 225         ETH_ERROR,              /* Fundamental error.                   */
 226         ETH_RETRY,              /* Could not process request. Try later.*/
 227         ETH_END_OF_JOB,         /* Ring has nothing to process.         */
 228         ETH_QUEUE_FULL,         /* Ring resource error.                 */
 229         ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust.     */
 230 } ETH_FUNC_RET_STATUS;
 231
 232 typedef enum _eth_target {
 233         ETH_TARGET_DRAM,
 234         ETH_TARGET_DEVICE,
 235         ETH_TARGET_CBS,
 236         ETH_TARGET_PCI0,
 237         ETH_TARGET_PCI1
 238 } ETH_TARGET;
 239
 240 /* These are for big-endian machines.  Little endian needs different
 241  * definitions.
 242  */
 243 #if defined(__BIG_ENDIAN)
 244 struct eth_rx_desc {
 245         u16 byte_cnt;           /* Descriptor buffer byte count         */
 246         u16 buf_size;           /* Buffer size                          */
 247         u32 cmd_sts;            /* Descriptor command status            */
 248         u32 next_desc_ptr;      /* Next descriptor pointer              */
 249         u32 buf_ptr;            /* Descriptor buffer pointer            */
 250 };
 251
 252 struct eth_tx_desc {
 253         u16 byte_cnt;           /* buffer byte count                    */
 254         u16 l4i_chk;            /* CPU provided TCP checksum            */
 255         u32 cmd_sts;            /* Command/status field                 */
 256         u32 next_desc_ptr;      /* Pointer to next descriptor           */
 257         u32 buf_ptr;            /* pointer to buffer for this descriptor*/
 258 };
 259
 260 #elif defined(__LITTLE_ENDIAN)
 261 struct eth_rx_desc {
 262         u32 cmd_sts;            /* Descriptor command status            */
 263         u16 buf_size;           /* Buffer size                          */
 264         u16 byte_cnt;           /* Descriptor buffer byte count         */
 265         u32 buf_ptr;            /* Descriptor buffer pointer            */
 266         u32 next_desc_ptr;      /* Next descriptor pointer              */
 267 };
 268
 269 struct eth_tx_desc {
 270         u32 cmd_sts;            /* Command/status field                 */
 271         u16 l4i_chk;            /* CPU provided TCP checksum            */
 272         u16 byte_cnt;           /* buffer byte count                    */
 273         u32 buf_ptr;            /* pointer to buffer for this descriptor*/
 274         u32 next_desc_ptr;      /* Pointer to next descriptor           */
 275 };
 276 #else
 277 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
 278 #endif
 279
 280 /* Unified struct for Rx and Tx operations. The user is not required to */
 281 /* be familier with neither Tx nor Rx descriptors.                      */
 282 struct pkt_info {
 283         unsigned short byte_cnt;        /* Descriptor buffer byte count */
 284         unsigned short l4i_chk;         /* Tx CPU provided TCP Checksum */
 285         unsigned int cmd_sts;           /* Descriptor command status    */
 286         dma_addr_t buf_ptr;             /* Descriptor buffer pointer    */
 287         struct sk_buff *return_info;    /* User resource return information */
 288 };
 289
 290 /* Ethernet port specific infomation */
 291
 292 struct mv643xx_mib_counters {
 293         u64 good_octets_received;
 294         u32 bad_octets_received;
 295         u32 internal_mac_transmit_err;
 296         u32 good_frames_received;
 297         u32 bad_frames_received;
 298         u32 broadcast_frames_received;
 299         u32 multicast_frames_received;
 300         u32 frames_64_octets;
 301         u32 frames_65_to_127_octets;
 302         u32 frames_128_to_255_octets;
 303         u32 frames_256_to_511_octets;
 304         u32 frames_512_to_1023_octets;
 305         u32 frames_1024_to_max_octets;
 306         u64 good_octets_sent;
 307         u32 good_frames_sent;
 308         u32 excessive_collision;
 309         u32 multicast_frames_sent;
 310         u32 broadcast_frames_sent;
 311         u32 unrec_mac_control_received;
 312         u32 fc_sent;
 313         u32 good_fc_received;
 314         u32 bad_fc_received;
 315         u32 undersize_received;
 316         u32 fragments_received;
 317         u32 oversize_received;
 318         u32 jabber_received;
 319         u32 mac_receive_error;
 320         u32 bad_crc_event;
 321         u32 collision;
 322         u32 late_collision;
 323 };
 324
 325 struct mv643xx_private {
 326         int port_num;                   /* User Ethernet port number    */
 327         u8 port_mac_addr[6];            /* User defined port MAC address.*/
 328         u32 port_config;                /* User port configuration value*/
 329         u32 port_config_extend;         /* User port config extend value*/
 330         u32 port_sdma_config;           /* User port SDMA config value  */
 331         u32 port_serial_control;        /* User port serial control value */
 332         u32 port_tx_queue_command;      /* Port active Tx queues summary*/
 333         u32 port_rx_queue_command;      /* Port active Rx queues summary*/
 334
 335         u32 rx_sram_addr;               /* Base address of rx sram area */
 336         u32 rx_sram_size;               /* Size of rx sram area         */
 337         u32 tx_sram_addr;               /* Base address of tx sram area */
 338         u32 tx_sram_size;               /* Size of tx sram area         */
 339
 340         int rx_resource_err;            /* Rx ring resource error flag */
 341         int tx_resource_err;            /* Tx ring resource error flag */
 342
 343         /* Tx/Rx rings managment indexes fields. For driver use */
 344
 345         /* Next available and first returning Rx resource */
 346         int rx_curr_desc_q, rx_used_desc_q;
 347
 348         /* Next available and first returning Tx resource */
 349         int tx_curr_desc_q, tx_used_desc_q;
 350 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
 351         int tx_first_desc_q;
 352         u32 tx_first_command;
 353 #endif
 354
 355 #ifdef MV643XX_TX_FAST_REFILL
 356         u32 tx_clean_threshold;
 357 #endif
 358
 359         struct eth_rx_desc *p_rx_desc_area;
 360         dma_addr_t rx_desc_dma;
 361         unsigned int rx_desc_area_size;
 362         struct sk_buff **rx_skb;
 363
 364         struct eth_tx_desc *p_tx_desc_area;
 365         dma_addr_t tx_desc_dma;
 366         unsigned int tx_desc_area_size;
 367         struct sk_buff **tx_skb;
 368
 369         struct work_struct tx_timeout_task;
 370
 371         /*
 372          * Former struct mv643xx_eth_priv members start here
 373          */
 374         struct net_device_stats stats;
 375         struct mv643xx_mib_counters mib_counters;
 376         spinlock_t lock;
 377         /* Size of Tx Ring per queue */
 378         unsigned int tx_ring_size;
 379         /* Ammont of SKBs outstanding on Tx queue */
 380         unsigned int tx_ring_skbs;
 381         /* Size of Rx Ring per queue */
 382         unsigned int rx_ring_size;
 383         /* Ammount of SKBs allocated to Rx Ring per queue */
 384         unsigned int rx_ring_skbs;
 385
 386         /*
 387          * rx_task used to fill RX ring out of bottom half context
 388          */
 389         struct work_struct rx_task;
 390
 391         /*
 392          * Used in case RX Ring is empty, which can be caused when
 393          * system does not have resources (skb's)
 394          */
 395         struct timer_list timeout;
 396         long rx_task_busy __attribute__ ((aligned(SMP_CACHE_BYTES)));
 397         unsigned rx_timer_flag;
 398
 399         u32 rx_int_coal;
 400         u32 tx_int_coal;
 401 };
 402
 403 /* ethernet.h API list */
 404
 405 /* Port operation control routines */
 406 static void eth_port_init(struct mv643xx_private *mp);
 407 static void eth_port_reset(unsigned int eth_port_num);
 408 static void eth_port_start(struct mv643xx_private *mp);
 409
 410 /* Port MAC address routines */
 411 static void eth_port_uc_addr_set(unsigned int eth_port_num,
 412                                  unsigned char *p_addr);
 413
 414 /* PHY and MIB routines */
 415 static void ethernet_phy_reset(unsigned int eth_port_num);
 416
 417 static void eth_port_write_smi_reg(unsigned int eth_port_num,
 418                                    unsigned int phy_reg, unsigned int value);
 419
 420 static void eth_port_read_smi_reg(unsigned int eth_port_num,
 421                                   unsigned int phy_reg, unsigned int *value);
 422
 423 static void eth_clear_mib_counters(unsigned int eth_port_num);
 424
 425 /* Port data flow control routines */
 426 static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
 427                                          struct pkt_info *p_pkt_info);
 428 static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
 429                                               struct pkt_info *p_pkt_info);
 430 static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
 431                                             struct pkt_info *p_pkt_info);
 432 static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
 433                                               struct pkt_info *p_pkt_info);
 434
 435 #endif                          /* __MV643XX_ETH_H__ */