include/asm-x86/gart.h

   1 #ifndef _ASM_X8664_IOMMU_H
   2 #define _ASM_X8664_IOMMU_H 1
   3
   4 #include <asm/e820.h>
   5
   6 extern void pci_iommu_shutdown(void);
   7 extern void no_iommu_init(void);
   8 extern int force_iommu, no_iommu;
   9 extern int iommu_detected;
  10 extern int agp_amd64_init(void);
  11 #ifdef CONFIG_GART_IOMMU
  12 extern void gart_iommu_init(void);
  13 extern void gart_iommu_shutdown(void);
  14 extern void __init gart_parse_options(char *);
  15 extern void early_gart_iommu_check(void);
  16 extern void gart_iommu_hole_init(void);
  17 extern void set_up_gart_resume(u32, u32);
  18 extern int fallback_aper_order;
  19 extern int fallback_aper_force;
  20 extern int gart_iommu_aperture;
  21 extern int gart_iommu_aperture_allowed;
  22 extern int gart_iommu_aperture_disabled;
  23 extern int fix_aperture;
  24 #else
  25 #define gart_iommu_aperture 0
  26 #define gart_iommu_aperture_allowed 0
  27
  28 static inline void early_gart_iommu_check(void)
  29 {
  30 }
  31
  32 static inline void gart_iommu_shutdown(void)
  33 {
  34 }
  35
  36 #endif
  37
  38 /* PTE bits. */
  39 #define GPTE_VALID      1
  40 #define GPTE_COHERENT   2
  41
  42 /* Aperture control register bits. */
  43 #define GARTEN          (1<<0)
  44 #define DISGARTCPU      (1<<4)
  45 #define DISGARTIO       (1<<5)
  46
  47 /* GART cache control register bits. */
  48 #define INVGART         (1<<0)
  49 #define GARTPTEERR      (1<<1)
  50
  51 /* K8 On-cpu GART registers */
  52 #define AMD64_GARTAPERTURECTL   0x90
  53 #define AMD64_GARTAPERTUREBASE  0x94
  54 #define AMD64_GARTTABLEBASE     0x98
  55 #define AMD64_GARTCACHECTL      0x9c
  56 #define AMD64_GARTEN            (1<<0)
  57
  58 static inline void enable_gart_translation(struct pci_dev *dev, u64 addr)
  59 {
  60         u32 tmp, ctl;
  61
  62         /* address of the mappings table */
  63         addr >>= 12;
  64         tmp = (u32) addr<<4;
  65         tmp &= ~0xf;
  66         pci_write_config_dword(dev, AMD64_GARTTABLEBASE, tmp);
  67
  68         /* Enable GART translation for this hammer. */
  69         pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
  70         ctl |= GARTEN;
  71         ctl &= ~(DISGARTCPU | DISGARTIO);
  72         pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
  73 }
  74
  75 static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size)
  76 {
  77         if (!aper_base)
  78                 return 0;
  79
  80         if (aper_base + aper_size > 0x100000000ULL) {
  81                 printk(KERN_ERR "Aperture beyond 4GB. Ignoring.\n");
  82                 return 0;
  83         }
  84         if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) {
  85                 printk(KERN_ERR "Aperture pointing to e820 RAM. Ignoring.\n");
  86                 return 0;
  87         }
  88         if (aper_size < min_size) {
  89                 printk(KERN_ERR "Aperture too small (%d MB) than (%d MB)\n",
  90                                  aper_size>>20, min_size>>20);
  91                 return 0;
  92         }
  93
  94         return 1;
  95 }
  96
  97 #endif