5 * GCC defines register number like this:
6 * -----------------------------
7 * 0 - 7 are data registers R0-R7
8 * 8 - 15 are address registers P0-P7
9 * 16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
10 * 32 - 33 A registers A0 & A1
11 * 34 - status register
12 * -----------------------------
14 * We follows above, except:
15 * 32-33 --- Low 32-bit of A0&1
16 * 34-35 --- High 8-bit of A0&1
21 /* this struct defines the way the registers are stored on the
22 stack during a system call. */
31 long pc
; /* PC == RETI */
33 long reserved
; /* Used as scratch during system calls */
82 /* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
83 #define PTRACE_GETREGS 12
84 #define PTRACE_SETREGS 13 /* ptrace signal */
86 #ifdef CONFIG_BINFMT_ELF_FDPIC
87 #define PTRACE_GETFDPIC 31
88 #define PTRACE_GETFDPIC_EXEC 0
89 #define PTRACE_GETFDPIC_INTERP 1
94 /* user_mode returns true if only one bit is set in IPEND, other than the
95 master interrupt enable. */
96 #define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
97 #define instruction_pointer(regs) ((regs)->pc)
98 #define profile_pc(regs) instruction_pointer(regs)
99 extern void show_regs(struct pt_regs
*);
101 #endif /* __ASSEMBLY__ */
104 * Offsets used by 'ptrace' system call interface.
150 #define PT_RESERVED 32
159 #define PT_SYSCFG 216
160 #define PT_TEXT_ADDR 220
161 #define PT_TEXT_END_ADDR 224
162 #define PT_DATA_ADDR 228
163 #define PT_FDPIC_EXEC 232
164 #define PT_FDPIC_INTERP 236
166 #endif /* _BFIN_PTRACE_H */