2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/i2c.h>
28 #include <linux/kernel.h>
30 #include "intel_drv.h"
35 #include "drm_crtc_helper.h"
37 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
39 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
);
40 static void intel_update_watermarks(struct drm_device
*dev
);
63 #define INTEL_P2_NUM 2
64 typedef struct intel_limit intel_limit_t
;
66 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
68 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
69 int, int, intel_clock_t
*);
72 #define I8XX_DOT_MIN 25000
73 #define I8XX_DOT_MAX 350000
74 #define I8XX_VCO_MIN 930000
75 #define I8XX_VCO_MAX 1400000
79 #define I8XX_M_MAX 140
80 #define I8XX_M1_MIN 18
81 #define I8XX_M1_MAX 26
83 #define I8XX_M2_MAX 16
85 #define I8XX_P_MAX 128
87 #define I8XX_P1_MAX 33
88 #define I8XX_P1_LVDS_MIN 1
89 #define I8XX_P1_LVDS_MAX 6
90 #define I8XX_P2_SLOW 4
91 #define I8XX_P2_FAST 2
92 #define I8XX_P2_LVDS_SLOW 14
93 #define I8XX_P2_LVDS_FAST 7
94 #define I8XX_P2_SLOW_LIMIT 165000
96 #define I9XX_DOT_MIN 20000
97 #define I9XX_DOT_MAX 400000
98 #define I9XX_VCO_MIN 1400000
99 #define I9XX_VCO_MAX 2800000
100 #define IGD_VCO_MIN 1700000
101 #define IGD_VCO_MAX 3500000
104 /* IGD's Ncounter is a ring counter */
107 #define I9XX_M_MIN 70
108 #define I9XX_M_MAX 120
110 #define IGD_M_MAX 256
111 #define I9XX_M1_MIN 10
112 #define I9XX_M1_MAX 22
113 #define I9XX_M2_MIN 5
114 #define I9XX_M2_MAX 9
115 /* IGD M1 is reserved, and must be 0 */
119 #define IGD_M2_MAX 254
120 #define I9XX_P_SDVO_DAC_MIN 5
121 #define I9XX_P_SDVO_DAC_MAX 80
122 #define I9XX_P_LVDS_MIN 7
123 #define I9XX_P_LVDS_MAX 98
124 #define IGD_P_LVDS_MIN 7
125 #define IGD_P_LVDS_MAX 112
126 #define I9XX_P1_MIN 1
127 #define I9XX_P1_MAX 8
128 #define I9XX_P2_SDVO_DAC_SLOW 10
129 #define I9XX_P2_SDVO_DAC_FAST 5
130 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
131 #define I9XX_P2_LVDS_SLOW 14
132 #define I9XX_P2_LVDS_FAST 7
133 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
135 /*The parameter is for SDVO on G4x platform*/
136 #define G4X_DOT_SDVO_MIN 25000
137 #define G4X_DOT_SDVO_MAX 270000
138 #define G4X_VCO_MIN 1750000
139 #define G4X_VCO_MAX 3500000
140 #define G4X_N_SDVO_MIN 1
141 #define G4X_N_SDVO_MAX 4
142 #define G4X_M_SDVO_MIN 104
143 #define G4X_M_SDVO_MAX 138
144 #define G4X_M1_SDVO_MIN 17
145 #define G4X_M1_SDVO_MAX 23
146 #define G4X_M2_SDVO_MIN 5
147 #define G4X_M2_SDVO_MAX 11
148 #define G4X_P_SDVO_MIN 10
149 #define G4X_P_SDVO_MAX 30
150 #define G4X_P1_SDVO_MIN 1
151 #define G4X_P1_SDVO_MAX 3
152 #define G4X_P2_SDVO_SLOW 10
153 #define G4X_P2_SDVO_FAST 10
154 #define G4X_P2_SDVO_LIMIT 270000
156 /*The parameter is for HDMI_DAC on G4x platform*/
157 #define G4X_DOT_HDMI_DAC_MIN 22000
158 #define G4X_DOT_HDMI_DAC_MAX 400000
159 #define G4X_N_HDMI_DAC_MIN 1
160 #define G4X_N_HDMI_DAC_MAX 4
161 #define G4X_M_HDMI_DAC_MIN 104
162 #define G4X_M_HDMI_DAC_MAX 138
163 #define G4X_M1_HDMI_DAC_MIN 16
164 #define G4X_M1_HDMI_DAC_MAX 23
165 #define G4X_M2_HDMI_DAC_MIN 5
166 #define G4X_M2_HDMI_DAC_MAX 11
167 #define G4X_P_HDMI_DAC_MIN 5
168 #define G4X_P_HDMI_DAC_MAX 80
169 #define G4X_P1_HDMI_DAC_MIN 1
170 #define G4X_P1_HDMI_DAC_MAX 8
171 #define G4X_P2_HDMI_DAC_SLOW 10
172 #define G4X_P2_HDMI_DAC_FAST 5
173 #define G4X_P2_HDMI_DAC_LIMIT 165000
175 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
176 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
177 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
178 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
179 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
180 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
181 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
182 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
183 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
184 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
185 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
186 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
187 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
188 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
189 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
190 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
191 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
192 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
194 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
195 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
196 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
197 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
198 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
199 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
200 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
201 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
202 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
203 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
204 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
205 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
206 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
207 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
208 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
209 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
210 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
211 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
213 /*The parameter is for DISPLAY PORT on G4x platform*/
214 #define G4X_DOT_DISPLAY_PORT_MIN 161670
215 #define G4X_DOT_DISPLAY_PORT_MAX 227000
216 #define G4X_N_DISPLAY_PORT_MIN 1
217 #define G4X_N_DISPLAY_PORT_MAX 2
218 #define G4X_M_DISPLAY_PORT_MIN 97
219 #define G4X_M_DISPLAY_PORT_MAX 108
220 #define G4X_M1_DISPLAY_PORT_MIN 0x10
221 #define G4X_M1_DISPLAY_PORT_MAX 0x12
222 #define G4X_M2_DISPLAY_PORT_MIN 0x05
223 #define G4X_M2_DISPLAY_PORT_MAX 0x06
224 #define G4X_P_DISPLAY_PORT_MIN 10
225 #define G4X_P_DISPLAY_PORT_MAX 20
226 #define G4X_P1_DISPLAY_PORT_MIN 1
227 #define G4X_P1_DISPLAY_PORT_MAX 2
228 #define G4X_P2_DISPLAY_PORT_SLOW 10
229 #define G4X_P2_DISPLAY_PORT_FAST 10
230 #define G4X_P2_DISPLAY_PORT_LIMIT 0
233 /* as we calculate clock using (register_value + 2) for
234 N/M1/M2, so here the range value for them is (actual_value-2).
236 #define IGDNG_DOT_MIN 25000
237 #define IGDNG_DOT_MAX 350000
238 #define IGDNG_VCO_MIN 1760000
239 #define IGDNG_VCO_MAX 3510000
240 #define IGDNG_N_MIN 1
241 #define IGDNG_N_MAX 5
242 #define IGDNG_M_MIN 79
243 #define IGDNG_M_MAX 118
244 #define IGDNG_M1_MIN 12
245 #define IGDNG_M1_MAX 23
246 #define IGDNG_M2_MIN 5
247 #define IGDNG_M2_MAX 9
248 #define IGDNG_P_SDVO_DAC_MIN 5
249 #define IGDNG_P_SDVO_DAC_MAX 80
250 #define IGDNG_P_LVDS_MIN 28
251 #define IGDNG_P_LVDS_MAX 112
252 #define IGDNG_P1_MIN 1
253 #define IGDNG_P1_MAX 8
254 #define IGDNG_P2_SDVO_DAC_SLOW 10
255 #define IGDNG_P2_SDVO_DAC_FAST 5
256 #define IGDNG_P2_LVDS_SLOW 14 /* single channel */
257 #define IGDNG_P2_LVDS_FAST 7 /* double channel */
258 #define IGDNG_P2_DOT_LIMIT 225000 /* 225Mhz */
261 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
262 int target
, int refclk
, intel_clock_t
*best_clock
);
264 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
265 int target
, int refclk
, intel_clock_t
*best_clock
);
267 intel_igdng_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
268 int target
, int refclk
, intel_clock_t
*best_clock
);
271 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
272 int target
, int refclk
, intel_clock_t
*best_clock
);
274 intel_find_pll_igdng_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
275 int target
, int refclk
, intel_clock_t
*best_clock
);
277 static const intel_limit_t intel_limits_i8xx_dvo
= {
278 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
279 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
280 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
281 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
282 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
283 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
284 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
285 .p1
= { .min
= I8XX_P1_MIN
, .max
= I8XX_P1_MAX
},
286 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
287 .p2_slow
= I8XX_P2_SLOW
, .p2_fast
= I8XX_P2_FAST
},
288 .find_pll
= intel_find_best_PLL
,
291 static const intel_limit_t intel_limits_i8xx_lvds
= {
292 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
293 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
294 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
295 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
296 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
297 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
298 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
299 .p1
= { .min
= I8XX_P1_LVDS_MIN
, .max
= I8XX_P1_LVDS_MAX
},
300 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
301 .p2_slow
= I8XX_P2_LVDS_SLOW
, .p2_fast
= I8XX_P2_LVDS_FAST
},
302 .find_pll
= intel_find_best_PLL
,
305 static const intel_limit_t intel_limits_i9xx_sdvo
= {
306 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
307 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
308 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
309 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
310 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
311 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
312 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
313 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
314 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
315 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
316 .find_pll
= intel_find_best_PLL
,
319 static const intel_limit_t intel_limits_i9xx_lvds
= {
320 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
321 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
322 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
323 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
324 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
325 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
326 .p
= { .min
= I9XX_P_LVDS_MIN
, .max
= I9XX_P_LVDS_MAX
},
327 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
328 /* The single-channel range is 25-112Mhz, and dual-channel
329 * is 80-224Mhz. Prefer single channel as much as possible.
331 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
332 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_FAST
},
333 .find_pll
= intel_find_best_PLL
,
336 /* below parameter and function is for G4X Chipset Family*/
337 static const intel_limit_t intel_limits_g4x_sdvo
= {
338 .dot
= { .min
= G4X_DOT_SDVO_MIN
, .max
= G4X_DOT_SDVO_MAX
},
339 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
340 .n
= { .min
= G4X_N_SDVO_MIN
, .max
= G4X_N_SDVO_MAX
},
341 .m
= { .min
= G4X_M_SDVO_MIN
, .max
= G4X_M_SDVO_MAX
},
342 .m1
= { .min
= G4X_M1_SDVO_MIN
, .max
= G4X_M1_SDVO_MAX
},
343 .m2
= { .min
= G4X_M2_SDVO_MIN
, .max
= G4X_M2_SDVO_MAX
},
344 .p
= { .min
= G4X_P_SDVO_MIN
, .max
= G4X_P_SDVO_MAX
},
345 .p1
= { .min
= G4X_P1_SDVO_MIN
, .max
= G4X_P1_SDVO_MAX
},
346 .p2
= { .dot_limit
= G4X_P2_SDVO_LIMIT
,
347 .p2_slow
= G4X_P2_SDVO_SLOW
,
348 .p2_fast
= G4X_P2_SDVO_FAST
350 .find_pll
= intel_g4x_find_best_PLL
,
353 static const intel_limit_t intel_limits_g4x_hdmi
= {
354 .dot
= { .min
= G4X_DOT_HDMI_DAC_MIN
, .max
= G4X_DOT_HDMI_DAC_MAX
},
355 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
356 .n
= { .min
= G4X_N_HDMI_DAC_MIN
, .max
= G4X_N_HDMI_DAC_MAX
},
357 .m
= { .min
= G4X_M_HDMI_DAC_MIN
, .max
= G4X_M_HDMI_DAC_MAX
},
358 .m1
= { .min
= G4X_M1_HDMI_DAC_MIN
, .max
= G4X_M1_HDMI_DAC_MAX
},
359 .m2
= { .min
= G4X_M2_HDMI_DAC_MIN
, .max
= G4X_M2_HDMI_DAC_MAX
},
360 .p
= { .min
= G4X_P_HDMI_DAC_MIN
, .max
= G4X_P_HDMI_DAC_MAX
},
361 .p1
= { .min
= G4X_P1_HDMI_DAC_MIN
, .max
= G4X_P1_HDMI_DAC_MAX
},
362 .p2
= { .dot_limit
= G4X_P2_HDMI_DAC_LIMIT
,
363 .p2_slow
= G4X_P2_HDMI_DAC_SLOW
,
364 .p2_fast
= G4X_P2_HDMI_DAC_FAST
366 .find_pll
= intel_g4x_find_best_PLL
,
369 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
370 .dot
= { .min
= G4X_DOT_SINGLE_CHANNEL_LVDS_MIN
,
371 .max
= G4X_DOT_SINGLE_CHANNEL_LVDS_MAX
},
372 .vco
= { .min
= G4X_VCO_MIN
,
373 .max
= G4X_VCO_MAX
},
374 .n
= { .min
= G4X_N_SINGLE_CHANNEL_LVDS_MIN
,
375 .max
= G4X_N_SINGLE_CHANNEL_LVDS_MAX
},
376 .m
= { .min
= G4X_M_SINGLE_CHANNEL_LVDS_MIN
,
377 .max
= G4X_M_SINGLE_CHANNEL_LVDS_MAX
},
378 .m1
= { .min
= G4X_M1_SINGLE_CHANNEL_LVDS_MIN
,
379 .max
= G4X_M1_SINGLE_CHANNEL_LVDS_MAX
},
380 .m2
= { .min
= G4X_M2_SINGLE_CHANNEL_LVDS_MIN
,
381 .max
= G4X_M2_SINGLE_CHANNEL_LVDS_MAX
},
382 .p
= { .min
= G4X_P_SINGLE_CHANNEL_LVDS_MIN
,
383 .max
= G4X_P_SINGLE_CHANNEL_LVDS_MAX
},
384 .p1
= { .min
= G4X_P1_SINGLE_CHANNEL_LVDS_MIN
,
385 .max
= G4X_P1_SINGLE_CHANNEL_LVDS_MAX
},
386 .p2
= { .dot_limit
= G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT
,
387 .p2_slow
= G4X_P2_SINGLE_CHANNEL_LVDS_SLOW
,
388 .p2_fast
= G4X_P2_SINGLE_CHANNEL_LVDS_FAST
390 .find_pll
= intel_g4x_find_best_PLL
,
393 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
394 .dot
= { .min
= G4X_DOT_DUAL_CHANNEL_LVDS_MIN
,
395 .max
= G4X_DOT_DUAL_CHANNEL_LVDS_MAX
},
396 .vco
= { .min
= G4X_VCO_MIN
,
397 .max
= G4X_VCO_MAX
},
398 .n
= { .min
= G4X_N_DUAL_CHANNEL_LVDS_MIN
,
399 .max
= G4X_N_DUAL_CHANNEL_LVDS_MAX
},
400 .m
= { .min
= G4X_M_DUAL_CHANNEL_LVDS_MIN
,
401 .max
= G4X_M_DUAL_CHANNEL_LVDS_MAX
},
402 .m1
= { .min
= G4X_M1_DUAL_CHANNEL_LVDS_MIN
,
403 .max
= G4X_M1_DUAL_CHANNEL_LVDS_MAX
},
404 .m2
= { .min
= G4X_M2_DUAL_CHANNEL_LVDS_MIN
,
405 .max
= G4X_M2_DUAL_CHANNEL_LVDS_MAX
},
406 .p
= { .min
= G4X_P_DUAL_CHANNEL_LVDS_MIN
,
407 .max
= G4X_P_DUAL_CHANNEL_LVDS_MAX
},
408 .p1
= { .min
= G4X_P1_DUAL_CHANNEL_LVDS_MIN
,
409 .max
= G4X_P1_DUAL_CHANNEL_LVDS_MAX
},
410 .p2
= { .dot_limit
= G4X_P2_DUAL_CHANNEL_LVDS_LIMIT
,
411 .p2_slow
= G4X_P2_DUAL_CHANNEL_LVDS_SLOW
,
412 .p2_fast
= G4X_P2_DUAL_CHANNEL_LVDS_FAST
414 .find_pll
= intel_g4x_find_best_PLL
,
417 static const intel_limit_t intel_limits_g4x_display_port
= {
418 .dot
= { .min
= G4X_DOT_DISPLAY_PORT_MIN
,
419 .max
= G4X_DOT_DISPLAY_PORT_MAX
},
420 .vco
= { .min
= G4X_VCO_MIN
,
422 .n
= { .min
= G4X_N_DISPLAY_PORT_MIN
,
423 .max
= G4X_N_DISPLAY_PORT_MAX
},
424 .m
= { .min
= G4X_M_DISPLAY_PORT_MIN
,
425 .max
= G4X_M_DISPLAY_PORT_MAX
},
426 .m1
= { .min
= G4X_M1_DISPLAY_PORT_MIN
,
427 .max
= G4X_M1_DISPLAY_PORT_MAX
},
428 .m2
= { .min
= G4X_M2_DISPLAY_PORT_MIN
,
429 .max
= G4X_M2_DISPLAY_PORT_MAX
},
430 .p
= { .min
= G4X_P_DISPLAY_PORT_MIN
,
431 .max
= G4X_P_DISPLAY_PORT_MAX
},
432 .p1
= { .min
= G4X_P1_DISPLAY_PORT_MIN
,
433 .max
= G4X_P1_DISPLAY_PORT_MAX
},
434 .p2
= { .dot_limit
= G4X_P2_DISPLAY_PORT_LIMIT
,
435 .p2_slow
= G4X_P2_DISPLAY_PORT_SLOW
,
436 .p2_fast
= G4X_P2_DISPLAY_PORT_FAST
},
437 .find_pll
= intel_find_pll_g4x_dp
,
440 static const intel_limit_t intel_limits_igd_sdvo
= {
441 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
442 .vco
= { .min
= IGD_VCO_MIN
, .max
= IGD_VCO_MAX
},
443 .n
= { .min
= IGD_N_MIN
, .max
= IGD_N_MAX
},
444 .m
= { .min
= IGD_M_MIN
, .max
= IGD_M_MAX
},
445 .m1
= { .min
= IGD_M1_MIN
, .max
= IGD_M1_MAX
},
446 .m2
= { .min
= IGD_M2_MIN
, .max
= IGD_M2_MAX
},
447 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
448 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
449 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
450 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
451 .find_pll
= intel_find_best_PLL
,
454 static const intel_limit_t intel_limits_igd_lvds
= {
455 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
456 .vco
= { .min
= IGD_VCO_MIN
, .max
= IGD_VCO_MAX
},
457 .n
= { .min
= IGD_N_MIN
, .max
= IGD_N_MAX
},
458 .m
= { .min
= IGD_M_MIN
, .max
= IGD_M_MAX
},
459 .m1
= { .min
= IGD_M1_MIN
, .max
= IGD_M1_MAX
},
460 .m2
= { .min
= IGD_M2_MIN
, .max
= IGD_M2_MAX
},
461 .p
= { .min
= IGD_P_LVDS_MIN
, .max
= IGD_P_LVDS_MAX
},
462 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
463 /* IGD only supports single-channel mode. */
464 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
465 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_SLOW
},
466 .find_pll
= intel_find_best_PLL
,
469 static const intel_limit_t intel_limits_igdng_sdvo
= {
470 .dot
= { .min
= IGDNG_DOT_MIN
, .max
= IGDNG_DOT_MAX
},
471 .vco
= { .min
= IGDNG_VCO_MIN
, .max
= IGDNG_VCO_MAX
},
472 .n
= { .min
= IGDNG_N_MIN
, .max
= IGDNG_N_MAX
},
473 .m
= { .min
= IGDNG_M_MIN
, .max
= IGDNG_M_MAX
},
474 .m1
= { .min
= IGDNG_M1_MIN
, .max
= IGDNG_M1_MAX
},
475 .m2
= { .min
= IGDNG_M2_MIN
, .max
= IGDNG_M2_MAX
},
476 .p
= { .min
= IGDNG_P_SDVO_DAC_MIN
, .max
= IGDNG_P_SDVO_DAC_MAX
},
477 .p1
= { .min
= IGDNG_P1_MIN
, .max
= IGDNG_P1_MAX
},
478 .p2
= { .dot_limit
= IGDNG_P2_DOT_LIMIT
,
479 .p2_slow
= IGDNG_P2_SDVO_DAC_SLOW
,
480 .p2_fast
= IGDNG_P2_SDVO_DAC_FAST
},
481 .find_pll
= intel_igdng_find_best_PLL
,
484 static const intel_limit_t intel_limits_igdng_lvds
= {
485 .dot
= { .min
= IGDNG_DOT_MIN
, .max
= IGDNG_DOT_MAX
},
486 .vco
= { .min
= IGDNG_VCO_MIN
, .max
= IGDNG_VCO_MAX
},
487 .n
= { .min
= IGDNG_N_MIN
, .max
= IGDNG_N_MAX
},
488 .m
= { .min
= IGDNG_M_MIN
, .max
= IGDNG_M_MAX
},
489 .m1
= { .min
= IGDNG_M1_MIN
, .max
= IGDNG_M1_MAX
},
490 .m2
= { .min
= IGDNG_M2_MIN
, .max
= IGDNG_M2_MAX
},
491 .p
= { .min
= IGDNG_P_LVDS_MIN
, .max
= IGDNG_P_LVDS_MAX
},
492 .p1
= { .min
= IGDNG_P1_MIN
, .max
= IGDNG_P1_MAX
},
493 .p2
= { .dot_limit
= IGDNG_P2_DOT_LIMIT
,
494 .p2_slow
= IGDNG_P2_LVDS_SLOW
,
495 .p2_fast
= IGDNG_P2_LVDS_FAST
},
496 .find_pll
= intel_igdng_find_best_PLL
,
499 static const intel_limit_t
*intel_igdng_limit(struct drm_crtc
*crtc
)
501 const intel_limit_t
*limit
;
502 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
503 limit
= &intel_limits_igdng_lvds
;
505 limit
= &intel_limits_igdng_sdvo
;
510 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
512 struct drm_device
*dev
= crtc
->dev
;
513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
514 const intel_limit_t
*limit
;
516 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
517 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
519 /* LVDS with dual channel */
520 limit
= &intel_limits_g4x_dual_channel_lvds
;
522 /* LVDS with dual channel */
523 limit
= &intel_limits_g4x_single_channel_lvds
;
524 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
525 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
526 limit
= &intel_limits_g4x_hdmi
;
527 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
528 limit
= &intel_limits_g4x_sdvo
;
529 } else if (intel_pipe_has_type (crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
530 limit
= &intel_limits_g4x_display_port
;
531 } else /* The option is for other outputs */
532 limit
= &intel_limits_i9xx_sdvo
;
537 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
)
539 struct drm_device
*dev
= crtc
->dev
;
540 const intel_limit_t
*limit
;
543 limit
= intel_igdng_limit(crtc
);
544 else if (IS_G4X(dev
)) {
545 limit
= intel_g4x_limit(crtc
);
546 } else if (IS_I9XX(dev
) && !IS_IGD(dev
)) {
547 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
548 limit
= &intel_limits_i9xx_lvds
;
550 limit
= &intel_limits_i9xx_sdvo
;
551 } else if (IS_IGD(dev
)) {
552 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
553 limit
= &intel_limits_igd_lvds
;
555 limit
= &intel_limits_igd_sdvo
;
557 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
558 limit
= &intel_limits_i8xx_lvds
;
560 limit
= &intel_limits_i8xx_dvo
;
565 /* m1 is reserved as 0 in IGD, n is a ring counter */
566 static void igd_clock(int refclk
, intel_clock_t
*clock
)
568 clock
->m
= clock
->m2
+ 2;
569 clock
->p
= clock
->p1
* clock
->p2
;
570 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
571 clock
->dot
= clock
->vco
/ clock
->p
;
574 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
577 igd_clock(refclk
, clock
);
580 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
581 clock
->p
= clock
->p1
* clock
->p2
;
582 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
583 clock
->dot
= clock
->vco
/ clock
->p
;
587 * Returns whether any output on the specified pipe is of the specified type
589 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
)
591 struct drm_device
*dev
= crtc
->dev
;
592 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
593 struct drm_connector
*l_entry
;
595 list_for_each_entry(l_entry
, &mode_config
->connector_list
, head
) {
596 if (l_entry
->encoder
&&
597 l_entry
->encoder
->crtc
== crtc
) {
598 struct intel_output
*intel_output
= to_intel_output(l_entry
);
599 if (intel_output
->type
== type
)
606 struct drm_connector
*
607 intel_pipe_get_output (struct drm_crtc
*crtc
)
609 struct drm_device
*dev
= crtc
->dev
;
610 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
611 struct drm_connector
*l_entry
, *ret
= NULL
;
613 list_for_each_entry(l_entry
, &mode_config
->connector_list
, head
) {
614 if (l_entry
->encoder
&&
615 l_entry
->encoder
->crtc
== crtc
) {
623 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
625 * Returns whether the given set of divisors are valid for a given refclk with
626 * the given connectors.
629 static bool intel_PLL_is_valid(struct drm_crtc
*crtc
, intel_clock_t
*clock
)
631 const intel_limit_t
*limit
= intel_limit (crtc
);
632 struct drm_device
*dev
= crtc
->dev
;
634 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
635 INTELPllInvalid ("p1 out of range\n");
636 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
637 INTELPllInvalid ("p out of range\n");
638 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
639 INTELPllInvalid ("m2 out of range\n");
640 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
641 INTELPllInvalid ("m1 out of range\n");
642 if (clock
->m1
<= clock
->m2
&& !IS_IGD(dev
))
643 INTELPllInvalid ("m1 <= m2\n");
644 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
645 INTELPllInvalid ("m out of range\n");
646 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
647 INTELPllInvalid ("n out of range\n");
648 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
649 INTELPllInvalid ("vco out of range\n");
650 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
651 * connector, etc., rather than just a single range.
653 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
654 INTELPllInvalid ("dot out of range\n");
660 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
661 int target
, int refclk
, intel_clock_t
*best_clock
)
664 struct drm_device
*dev
= crtc
->dev
;
665 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
669 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
670 (I915_READ(LVDS
)) != 0) {
672 * For LVDS, if the panel is on, just rely on its current
673 * settings for dual-channel. We haven't figured out how to
674 * reliably set up different single/dual channel state, if we
677 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
679 clock
.p2
= limit
->p2
.p2_fast
;
681 clock
.p2
= limit
->p2
.p2_slow
;
683 if (target
< limit
->p2
.dot_limit
)
684 clock
.p2
= limit
->p2
.p2_slow
;
686 clock
.p2
= limit
->p2
.p2_fast
;
689 memset (best_clock
, 0, sizeof (*best_clock
));
691 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
692 for (clock
.m2
= limit
->m2
.min
; clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
693 /* m1 is always 0 in IGD */
694 if (clock
.m2
>= clock
.m1
&& !IS_IGD(dev
))
696 for (clock
.n
= limit
->n
.min
; clock
.n
<= limit
->n
.max
;
698 for (clock
.p1
= limit
->p1
.min
;
699 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
702 intel_clock(dev
, refclk
, &clock
);
704 if (!intel_PLL_is_valid(crtc
, &clock
))
707 this_err
= abs(clock
.dot
- target
);
708 if (this_err
< err
) {
717 return (err
!= target
);
721 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
722 int target
, int refclk
, intel_clock_t
*best_clock
)
724 struct drm_device
*dev
= crtc
->dev
;
725 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
729 /* approximately equals target * 0.00488 */
730 int err_most
= (target
>> 8) + (target
>> 10);
733 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
734 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
736 clock
.p2
= limit
->p2
.p2_fast
;
738 clock
.p2
= limit
->p2
.p2_slow
;
740 if (target
< limit
->p2
.dot_limit
)
741 clock
.p2
= limit
->p2
.p2_slow
;
743 clock
.p2
= limit
->p2
.p2_fast
;
746 memset(best_clock
, 0, sizeof(*best_clock
));
747 max_n
= limit
->n
.max
;
748 /* based on hardware requriment prefer smaller n to precision */
749 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
750 /* based on hardware requirment prefere larger m1,m2, p1 */
751 for (clock
.m1
= limit
->m1
.max
;
752 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
753 for (clock
.m2
= limit
->m2
.max
;
754 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
755 for (clock
.p1
= limit
->p1
.max
;
756 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
759 intel_clock(dev
, refclk
, &clock
);
760 if (!intel_PLL_is_valid(crtc
, &clock
))
762 this_err
= abs(clock
.dot
- target
) ;
763 if (this_err
< err_most
) {
777 intel_find_pll_igdng_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
778 int target
, int refclk
, intel_clock_t
*best_clock
)
780 struct drm_device
*dev
= crtc
->dev
;
782 if (target
< 200000) {
795 intel_clock(dev
, refclk
, &clock
);
796 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
801 intel_igdng_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
802 int target
, int refclk
, intel_clock_t
*best_clock
)
804 struct drm_device
*dev
= crtc
->dev
;
805 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
812 /* eDP has only 2 clock choice, no n/m/p setting */
816 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
817 return intel_find_pll_igdng_dp(limit
, crtc
, target
,
820 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
821 if ((I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) ==
823 clock
.p2
= limit
->p2
.p2_fast
;
825 clock
.p2
= limit
->p2
.p2_slow
;
827 if (target
< limit
->p2
.dot_limit
)
828 clock
.p2
= limit
->p2
.p2_slow
;
830 clock
.p2
= limit
->p2
.p2_fast
;
833 memset(best_clock
, 0, sizeof(*best_clock
));
834 max_n
= limit
->n
.max
;
835 /* based on hardware requriment prefer smaller n to precision */
836 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
837 /* based on hardware requirment prefere larger m1,m2, p1 */
838 for (clock
.m1
= limit
->m1
.max
;
839 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
840 for (clock
.m2
= limit
->m2
.max
;
841 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
842 for (clock
.p1
= limit
->p1
.max
;
843 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
846 intel_clock(dev
, refclk
, &clock
);
847 if (!intel_PLL_is_valid(crtc
, &clock
))
849 this_err
= abs((10000 - (target
*10000/clock
.dot
)));
850 if (this_err
< err_most
) {
855 /* found on first matching */
866 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
868 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
869 int target
, int refclk
, intel_clock_t
*best_clock
)
872 if (target
< 200000) {
885 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
886 clock
.p
= (clock
.p1
* clock
.p2
);
887 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
888 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
893 intel_wait_for_vblank(struct drm_device
*dev
)
895 /* Wait for 20ms, i.e. one cycle at 50hz. */
900 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
901 struct drm_framebuffer
*old_fb
)
903 struct drm_device
*dev
= crtc
->dev
;
904 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
905 struct drm_i915_master_private
*master_priv
;
906 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
907 struct intel_framebuffer
*intel_fb
;
908 struct drm_i915_gem_object
*obj_priv
;
909 struct drm_gem_object
*obj
;
910 int pipe
= intel_crtc
->pipe
;
911 unsigned long Start
, Offset
;
912 int dspbase
= (pipe
== 0 ? DSPAADDR
: DSPBADDR
);
913 int dspsurf
= (pipe
== 0 ? DSPASURF
: DSPBSURF
);
914 int dspstride
= (pipe
== 0) ? DSPASTRIDE
: DSPBSTRIDE
;
915 int dsptileoff
= (pipe
== 0 ? DSPATILEOFF
: DSPBTILEOFF
);
916 int dspcntr_reg
= (pipe
== 0) ? DSPACNTR
: DSPBCNTR
;
917 u32 dspcntr
, alignment
;
922 DRM_DEBUG("No FB bound\n");
931 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe
);
935 intel_fb
= to_intel_framebuffer(crtc
->fb
);
937 obj_priv
= obj
->driver_private
;
939 switch (obj_priv
->tiling_mode
) {
940 case I915_TILING_NONE
:
941 alignment
= 64 * 1024;
944 /* pin() will align the object as required by fence */
948 /* FIXME: Is this true? */
949 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
955 mutex_lock(&dev
->struct_mutex
);
956 ret
= i915_gem_object_pin(obj
, alignment
);
958 mutex_unlock(&dev
->struct_mutex
);
962 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
964 i915_gem_object_unpin(obj
);
965 mutex_unlock(&dev
->struct_mutex
);
969 /* Pre-i965 needs to install a fence for tiled scan-out */
970 if (!IS_I965G(dev
) &&
971 obj_priv
->fence_reg
== I915_FENCE_REG_NONE
&&
972 obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
973 ret
= i915_gem_object_get_fence_reg(obj
);
975 i915_gem_object_unpin(obj
);
976 mutex_unlock(&dev
->struct_mutex
);
981 dspcntr
= I915_READ(dspcntr_reg
);
982 /* Mask out pixel format bits in case we change it */
983 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
984 switch (crtc
->fb
->bits_per_pixel
) {
986 dspcntr
|= DISPPLANE_8BPP
;
989 if (crtc
->fb
->depth
== 15)
990 dspcntr
|= DISPPLANE_15_16BPP
;
992 dspcntr
|= DISPPLANE_16BPP
;
996 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
999 DRM_ERROR("Unknown color depth\n");
1000 i915_gem_object_unpin(obj
);
1001 mutex_unlock(&dev
->struct_mutex
);
1004 if (IS_I965G(dev
)) {
1005 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1006 dspcntr
|= DISPPLANE_TILED
;
1008 dspcntr
&= ~DISPPLANE_TILED
;
1013 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
1015 I915_WRITE(dspcntr_reg
, dspcntr
);
1017 Start
= obj_priv
->gtt_offset
;
1018 Offset
= y
* crtc
->fb
->pitch
+ x
* (crtc
->fb
->bits_per_pixel
/ 8);
1020 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start
, Offset
, x
, y
);
1021 I915_WRITE(dspstride
, crtc
->fb
->pitch
);
1022 if (IS_I965G(dev
)) {
1023 I915_WRITE(dspbase
, Offset
);
1025 I915_WRITE(dspsurf
, Start
);
1027 I915_WRITE(dsptileoff
, (y
<< 16) | x
);
1029 I915_WRITE(dspbase
, Start
+ Offset
);
1033 intel_wait_for_vblank(dev
);
1036 intel_fb
= to_intel_framebuffer(old_fb
);
1037 i915_gem_object_unpin(intel_fb
->obj
);
1039 mutex_unlock(&dev
->struct_mutex
);
1041 if (!dev
->primary
->master
)
1044 master_priv
= dev
->primary
->master
->driver_priv
;
1045 if (!master_priv
->sarea_priv
)
1049 master_priv
->sarea_priv
->pipeB_x
= x
;
1050 master_priv
->sarea_priv
->pipeB_y
= y
;
1052 master_priv
->sarea_priv
->pipeA_x
= x
;
1053 master_priv
->sarea_priv
->pipeA_y
= y
;
1059 /* Disable the VGA plane that we never use */
1060 static void i915_disable_vga (struct drm_device
*dev
)
1062 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1067 vga_reg
= CPU_VGACNTRL
;
1071 if (I915_READ(vga_reg
) & VGA_DISP_DISABLE
)
1074 I915_WRITE8(VGA_SR_INDEX
, 1);
1075 sr1
= I915_READ8(VGA_SR_DATA
);
1076 I915_WRITE8(VGA_SR_DATA
, sr1
| (1 << 5));
1079 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
1082 static void igdng_disable_pll_edp (struct drm_crtc
*crtc
)
1084 struct drm_device
*dev
= crtc
->dev
;
1085 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1089 dpa_ctl
= I915_READ(DP_A
);
1090 dpa_ctl
&= ~DP_PLL_ENABLE
;
1091 I915_WRITE(DP_A
, dpa_ctl
);
1094 static void igdng_enable_pll_edp (struct drm_crtc
*crtc
)
1096 struct drm_device
*dev
= crtc
->dev
;
1097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1100 dpa_ctl
= I915_READ(DP_A
);
1101 dpa_ctl
|= DP_PLL_ENABLE
;
1102 I915_WRITE(DP_A
, dpa_ctl
);
1107 static void igdng_set_pll_edp (struct drm_crtc
*crtc
, int clock
)
1109 struct drm_device
*dev
= crtc
->dev
;
1110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1113 DRM_DEBUG("eDP PLL enable for clock %d\n", clock
);
1114 dpa_ctl
= I915_READ(DP_A
);
1115 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1117 if (clock
< 200000) {
1119 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1120 /* workaround for 160Mhz:
1121 1) program 0x4600c bits 15:0 = 0x8124
1122 2) program 0x46010 bit 0 = 1
1123 3) program 0x46034 bit 24 = 1
1124 4) program 0x64000 bit 14 = 1
1126 temp
= I915_READ(0x4600c);
1128 I915_WRITE(0x4600c, temp
| 0x8124);
1130 temp
= I915_READ(0x46010);
1131 I915_WRITE(0x46010, temp
| 1);
1133 temp
= I915_READ(0x46034);
1134 I915_WRITE(0x46034, temp
| (1 << 24));
1136 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1138 I915_WRITE(DP_A
, dpa_ctl
);
1143 static void igdng_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
1145 struct drm_device
*dev
= crtc
->dev
;
1146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1147 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1148 int pipe
= intel_crtc
->pipe
;
1149 int plane
= intel_crtc
->plane
;
1150 int pch_dpll_reg
= (pipe
== 0) ? PCH_DPLL_A
: PCH_DPLL_B
;
1151 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
1152 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
1153 int dspbase_reg
= (plane
== 0) ? DSPAADDR
: DSPBADDR
;
1154 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
1155 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
1156 int fdi_rx_iir_reg
= (pipe
== 0) ? FDI_RXA_IIR
: FDI_RXB_IIR
;
1157 int fdi_rx_imr_reg
= (pipe
== 0) ? FDI_RXA_IMR
: FDI_RXB_IMR
;
1158 int transconf_reg
= (pipe
== 0) ? TRANSACONF
: TRANSBCONF
;
1159 int pf_ctl_reg
= (pipe
== 0) ? PFA_CTL_1
: PFB_CTL_1
;
1160 int pf_win_size
= (pipe
== 0) ? PFA_WIN_SZ
: PFB_WIN_SZ
;
1161 int pf_win_pos
= (pipe
== 0) ? PFA_WIN_POS
: PFB_WIN_POS
;
1162 int cpu_htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
1163 int cpu_hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
1164 int cpu_hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
1165 int cpu_vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
1166 int cpu_vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
1167 int cpu_vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
1168 int trans_htot_reg
= (pipe
== 0) ? TRANS_HTOTAL_A
: TRANS_HTOTAL_B
;
1169 int trans_hblank_reg
= (pipe
== 0) ? TRANS_HBLANK_A
: TRANS_HBLANK_B
;
1170 int trans_hsync_reg
= (pipe
== 0) ? TRANS_HSYNC_A
: TRANS_HSYNC_B
;
1171 int trans_vtot_reg
= (pipe
== 0) ? TRANS_VTOTAL_A
: TRANS_VTOTAL_B
;
1172 int trans_vblank_reg
= (pipe
== 0) ? TRANS_VBLANK_A
: TRANS_VBLANK_B
;
1173 int trans_vsync_reg
= (pipe
== 0) ? TRANS_VSYNC_A
: TRANS_VSYNC_B
;
1175 int tries
= 5, j
, n
;
1177 /* XXX: When our outputs are all unaware of DPMS modes other than off
1178 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1181 case DRM_MODE_DPMS_ON
:
1182 case DRM_MODE_DPMS_STANDBY
:
1183 case DRM_MODE_DPMS_SUSPEND
:
1184 DRM_DEBUG("crtc %d dpms on\n", pipe
);
1186 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
1187 temp
= I915_READ(PCH_LVDS
);
1188 if ((temp
& LVDS_PORT_EN
) == 0) {
1189 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
1190 POSTING_READ(PCH_LVDS
);
1195 /* enable eDP PLL */
1196 igdng_enable_pll_edp(crtc
);
1198 /* enable PCH DPLL */
1199 temp
= I915_READ(pch_dpll_reg
);
1200 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
1201 I915_WRITE(pch_dpll_reg
, temp
| DPLL_VCO_ENABLE
);
1202 I915_READ(pch_dpll_reg
);
1205 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1206 temp
= I915_READ(fdi_rx_reg
);
1207 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_PLL_ENABLE
|
1209 FDI_DP_PORT_WIDTH_X4
); /* default 4 lanes */
1210 I915_READ(fdi_rx_reg
);
1213 /* Enable CPU FDI TX PLL, always on for IGDNG */
1214 temp
= I915_READ(fdi_tx_reg
);
1215 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
1216 I915_WRITE(fdi_tx_reg
, temp
| FDI_TX_PLL_ENABLE
);
1217 I915_READ(fdi_tx_reg
);
1222 /* Enable panel fitting for LVDS */
1223 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
1224 temp
= I915_READ(pf_ctl_reg
);
1225 I915_WRITE(pf_ctl_reg
, temp
| PF_ENABLE
| PF_FILTER_MED_3x3
);
1227 /* currently full aspect */
1228 I915_WRITE(pf_win_pos
, 0);
1230 I915_WRITE(pf_win_size
,
1231 (dev_priv
->panel_fixed_mode
->hdisplay
<< 16) |
1232 (dev_priv
->panel_fixed_mode
->vdisplay
));
1235 /* Enable CPU pipe */
1236 temp
= I915_READ(pipeconf_reg
);
1237 if ((temp
& PIPEACONF_ENABLE
) == 0) {
1238 I915_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
1239 I915_READ(pipeconf_reg
);
1243 /* configure and enable CPU plane */
1244 temp
= I915_READ(dspcntr_reg
);
1245 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
1246 I915_WRITE(dspcntr_reg
, temp
| DISPLAY_PLANE_ENABLE
);
1247 /* Flush the plane changes */
1248 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1252 /* enable CPU FDI TX and PCH FDI RX */
1253 temp
= I915_READ(fdi_tx_reg
);
1254 temp
|= FDI_TX_ENABLE
;
1255 temp
|= FDI_DP_PORT_WIDTH_X4
; /* default */
1256 temp
&= ~FDI_LINK_TRAIN_NONE
;
1257 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1258 I915_WRITE(fdi_tx_reg
, temp
);
1259 I915_READ(fdi_tx_reg
);
1261 temp
= I915_READ(fdi_rx_reg
);
1262 temp
&= ~FDI_LINK_TRAIN_NONE
;
1263 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1264 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_ENABLE
);
1265 I915_READ(fdi_rx_reg
);
1270 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1272 temp
= I915_READ(fdi_rx_imr_reg
);
1273 temp
&= ~FDI_RX_SYMBOL_LOCK
;
1274 temp
&= ~FDI_RX_BIT_LOCK
;
1275 I915_WRITE(fdi_rx_imr_reg
, temp
);
1276 I915_READ(fdi_rx_imr_reg
);
1279 temp
= I915_READ(fdi_rx_iir_reg
);
1280 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp
);
1282 if ((temp
& FDI_RX_BIT_LOCK
) == 0) {
1283 for (j
= 0; j
< tries
; j
++) {
1284 temp
= I915_READ(fdi_rx_iir_reg
);
1285 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp
);
1286 if (temp
& FDI_RX_BIT_LOCK
)
1291 I915_WRITE(fdi_rx_iir_reg
,
1292 temp
| FDI_RX_BIT_LOCK
);
1294 DRM_DEBUG("train 1 fail\n");
1296 I915_WRITE(fdi_rx_iir_reg
,
1297 temp
| FDI_RX_BIT_LOCK
);
1298 DRM_DEBUG("train 1 ok 2!\n");
1300 temp
= I915_READ(fdi_tx_reg
);
1301 temp
&= ~FDI_LINK_TRAIN_NONE
;
1302 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1303 I915_WRITE(fdi_tx_reg
, temp
);
1305 temp
= I915_READ(fdi_rx_reg
);
1306 temp
&= ~FDI_LINK_TRAIN_NONE
;
1307 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1308 I915_WRITE(fdi_rx_reg
, temp
);
1312 temp
= I915_READ(fdi_rx_iir_reg
);
1313 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp
);
1315 if ((temp
& FDI_RX_SYMBOL_LOCK
) == 0) {
1316 for (j
= 0; j
< tries
; j
++) {
1317 temp
= I915_READ(fdi_rx_iir_reg
);
1318 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp
);
1319 if (temp
& FDI_RX_SYMBOL_LOCK
)
1324 I915_WRITE(fdi_rx_iir_reg
,
1325 temp
| FDI_RX_SYMBOL_LOCK
);
1326 DRM_DEBUG("train 2 ok 1!\n");
1328 DRM_DEBUG("train 2 fail\n");
1330 I915_WRITE(fdi_rx_iir_reg
,
1331 temp
| FDI_RX_SYMBOL_LOCK
);
1332 DRM_DEBUG("train 2 ok 2!\n");
1334 DRM_DEBUG("train done\n");
1336 /* set transcoder timing */
1337 I915_WRITE(trans_htot_reg
, I915_READ(cpu_htot_reg
));
1338 I915_WRITE(trans_hblank_reg
, I915_READ(cpu_hblank_reg
));
1339 I915_WRITE(trans_hsync_reg
, I915_READ(cpu_hsync_reg
));
1341 I915_WRITE(trans_vtot_reg
, I915_READ(cpu_vtot_reg
));
1342 I915_WRITE(trans_vblank_reg
, I915_READ(cpu_vblank_reg
));
1343 I915_WRITE(trans_vsync_reg
, I915_READ(cpu_vsync_reg
));
1345 /* enable PCH transcoder */
1346 temp
= I915_READ(transconf_reg
);
1347 I915_WRITE(transconf_reg
, temp
| TRANS_ENABLE
);
1348 I915_READ(transconf_reg
);
1350 while ((I915_READ(transconf_reg
) & TRANS_STATE_ENABLE
) == 0)
1355 temp
= I915_READ(fdi_tx_reg
);
1356 temp
&= ~FDI_LINK_TRAIN_NONE
;
1357 I915_WRITE(fdi_tx_reg
, temp
| FDI_LINK_TRAIN_NONE
|
1358 FDI_TX_ENHANCE_FRAME_ENABLE
);
1359 I915_READ(fdi_tx_reg
);
1361 temp
= I915_READ(fdi_rx_reg
);
1362 temp
&= ~FDI_LINK_TRAIN_NONE
;
1363 I915_WRITE(fdi_rx_reg
, temp
| FDI_LINK_TRAIN_NONE
|
1364 FDI_RX_ENHANCE_FRAME_ENABLE
);
1365 I915_READ(fdi_rx_reg
);
1367 /* wait one idle pattern time */
1372 intel_crtc_load_lut(crtc
);
1375 case DRM_MODE_DPMS_OFF
:
1376 DRM_DEBUG("crtc %d dpms off\n", pipe
);
1378 /* Disable display plane */
1379 temp
= I915_READ(dspcntr_reg
);
1380 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
1381 I915_WRITE(dspcntr_reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
1382 /* Flush the plane changes */
1383 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1384 I915_READ(dspbase_reg
);
1387 i915_disable_vga(dev
);
1389 /* disable cpu pipe, disable after all planes disabled */
1390 temp
= I915_READ(pipeconf_reg
);
1391 if ((temp
& PIPEACONF_ENABLE
) != 0) {
1392 I915_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
1393 I915_READ(pipeconf_reg
);
1395 /* wait for cpu pipe off, pipe state */
1396 while ((I915_READ(pipeconf_reg
) & I965_PIPECONF_ACTIVE
) != 0) {
1402 DRM_DEBUG("pipe %d off delay\n", pipe
);
1407 DRM_DEBUG("crtc %d is disabled\n", pipe
);
1412 temp
= I915_READ(pf_ctl_reg
);
1413 if ((temp
& PF_ENABLE
) != 0) {
1414 I915_WRITE(pf_ctl_reg
, temp
& ~PF_ENABLE
);
1415 I915_READ(pf_ctl_reg
);
1417 I915_WRITE(pf_win_size
, 0);
1419 /* disable CPU FDI tx and PCH FDI rx */
1420 temp
= I915_READ(fdi_tx_reg
);
1421 I915_WRITE(fdi_tx_reg
, temp
& ~FDI_TX_ENABLE
);
1422 I915_READ(fdi_tx_reg
);
1424 temp
= I915_READ(fdi_rx_reg
);
1425 I915_WRITE(fdi_rx_reg
, temp
& ~FDI_RX_ENABLE
);
1426 I915_READ(fdi_rx_reg
);
1430 /* still set train pattern 1 */
1431 temp
= I915_READ(fdi_tx_reg
);
1432 temp
&= ~FDI_LINK_TRAIN_NONE
;
1433 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1434 I915_WRITE(fdi_tx_reg
, temp
);
1436 temp
= I915_READ(fdi_rx_reg
);
1437 temp
&= ~FDI_LINK_TRAIN_NONE
;
1438 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1439 I915_WRITE(fdi_rx_reg
, temp
);
1443 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
1444 temp
= I915_READ(PCH_LVDS
);
1445 I915_WRITE(PCH_LVDS
, temp
& ~LVDS_PORT_EN
);
1446 I915_READ(PCH_LVDS
);
1450 /* disable PCH transcoder */
1451 temp
= I915_READ(transconf_reg
);
1452 if ((temp
& TRANS_ENABLE
) != 0) {
1453 I915_WRITE(transconf_reg
, temp
& ~TRANS_ENABLE
);
1454 I915_READ(transconf_reg
);
1456 /* wait for PCH transcoder off, transcoder state */
1457 while ((I915_READ(transconf_reg
) & TRANS_STATE_ENABLE
) != 0) {
1463 DRM_DEBUG("transcoder %d off delay\n", pipe
);
1471 /* disable PCH DPLL */
1472 temp
= I915_READ(pch_dpll_reg
);
1473 if ((temp
& DPLL_VCO_ENABLE
) != 0) {
1474 I915_WRITE(pch_dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
1475 I915_READ(pch_dpll_reg
);
1479 igdng_disable_pll_edp(crtc
);
1482 temp
= I915_READ(fdi_rx_reg
);
1483 temp
&= ~FDI_SEL_PCDCLK
;
1484 I915_WRITE(fdi_rx_reg
, temp
);
1485 I915_READ(fdi_rx_reg
);
1487 temp
= I915_READ(fdi_rx_reg
);
1488 temp
&= ~FDI_RX_PLL_ENABLE
;
1489 I915_WRITE(fdi_rx_reg
, temp
);
1490 I915_READ(fdi_rx_reg
);
1492 /* Disable CPU FDI TX PLL */
1493 temp
= I915_READ(fdi_tx_reg
);
1494 if ((temp
& FDI_TX_PLL_ENABLE
) != 0) {
1495 I915_WRITE(fdi_tx_reg
, temp
& ~FDI_TX_PLL_ENABLE
);
1496 I915_READ(fdi_tx_reg
);
1500 /* Wait for the clocks to turn off. */
1506 static void i9xx_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
1508 struct drm_device
*dev
= crtc
->dev
;
1509 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1510 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1511 int pipe
= intel_crtc
->pipe
;
1512 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
1513 int dspcntr_reg
= (pipe
== 0) ? DSPACNTR
: DSPBCNTR
;
1514 int dspbase_reg
= (pipe
== 0) ? DSPAADDR
: DSPBADDR
;
1515 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
1518 /* XXX: When our outputs are all unaware of DPMS modes other than off
1519 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1522 case DRM_MODE_DPMS_ON
:
1523 case DRM_MODE_DPMS_STANDBY
:
1524 case DRM_MODE_DPMS_SUSPEND
:
1525 /* Enable the DPLL */
1526 temp
= I915_READ(dpll_reg
);
1527 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
1528 I915_WRITE(dpll_reg
, temp
);
1529 I915_READ(dpll_reg
);
1530 /* Wait for the clocks to stabilize. */
1532 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
1533 I915_READ(dpll_reg
);
1534 /* Wait for the clocks to stabilize. */
1536 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
1537 I915_READ(dpll_reg
);
1538 /* Wait for the clocks to stabilize. */
1542 /* Enable the pipe */
1543 temp
= I915_READ(pipeconf_reg
);
1544 if ((temp
& PIPEACONF_ENABLE
) == 0)
1545 I915_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
1547 /* Enable the plane */
1548 temp
= I915_READ(dspcntr_reg
);
1549 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
1550 I915_WRITE(dspcntr_reg
, temp
| DISPLAY_PLANE_ENABLE
);
1551 /* Flush the plane changes */
1552 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1555 intel_crtc_load_lut(crtc
);
1557 /* Give the overlay scaler a chance to enable if it's on this pipe */
1558 //intel_crtc_dpms_video(crtc, true); TODO
1559 intel_update_watermarks(dev
);
1561 case DRM_MODE_DPMS_OFF
:
1562 intel_update_watermarks(dev
);
1563 /* Give the overlay scaler a chance to disable if it's on this pipe */
1564 //intel_crtc_dpms_video(crtc, FALSE); TODO
1565 drm_vblank_off(dev
, pipe
);
1567 /* Disable the VGA plane that we never use */
1568 i915_disable_vga(dev
);
1570 /* Disable display plane */
1571 temp
= I915_READ(dspcntr_reg
);
1572 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
1573 I915_WRITE(dspcntr_reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
1574 /* Flush the plane changes */
1575 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1576 I915_READ(dspbase_reg
);
1579 if (!IS_I9XX(dev
)) {
1580 /* Wait for vblank for the disable to take effect */
1581 intel_wait_for_vblank(dev
);
1584 /* Next, disable display pipes */
1585 temp
= I915_READ(pipeconf_reg
);
1586 if ((temp
& PIPEACONF_ENABLE
) != 0) {
1587 I915_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
1588 I915_READ(pipeconf_reg
);
1591 /* Wait for vblank for the disable to take effect. */
1592 intel_wait_for_vblank(dev
);
1594 temp
= I915_READ(dpll_reg
);
1595 if ((temp
& DPLL_VCO_ENABLE
) != 0) {
1596 I915_WRITE(dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
1597 I915_READ(dpll_reg
);
1600 /* Wait for the clocks to turn off. */
1607 * Sets the power management mode of the pipe and plane.
1609 * This code should probably grow support for turning the cursor off and back
1610 * on appropriately at the same time as we're turning the pipe off/on.
1612 static void intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
1614 struct drm_device
*dev
= crtc
->dev
;
1615 struct drm_i915_master_private
*master_priv
;
1616 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1617 int pipe
= intel_crtc
->pipe
;
1621 igdng_crtc_dpms(crtc
, mode
);
1623 i9xx_crtc_dpms(crtc
, mode
);
1625 if (!dev
->primary
->master
)
1628 master_priv
= dev
->primary
->master
->driver_priv
;
1629 if (!master_priv
->sarea_priv
)
1632 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
1636 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
1637 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
1640 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
1641 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
1644 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe
);
1648 intel_crtc
->dpms_mode
= mode
;
1651 static void intel_crtc_prepare (struct drm_crtc
*crtc
)
1653 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
1654 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
1657 static void intel_crtc_commit (struct drm_crtc
*crtc
)
1659 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
1660 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
1663 void intel_encoder_prepare (struct drm_encoder
*encoder
)
1665 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
1666 /* lvds has its own version of prepare see intel_lvds_prepare */
1667 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
1670 void intel_encoder_commit (struct drm_encoder
*encoder
)
1672 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
1673 /* lvds has its own version of commit see intel_lvds_commit */
1674 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
1677 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
1678 struct drm_display_mode
*mode
,
1679 struct drm_display_mode
*adjusted_mode
)
1681 struct drm_device
*dev
= crtc
->dev
;
1682 if (IS_IGDNG(dev
)) {
1683 /* FDI link clock is fixed at 2.7G */
1684 if (mode
->clock
* 3 > 27000 * 4)
1685 return MODE_CLOCK_HIGH
;
1691 /** Returns the core display clock speed for i830 - i945 */
1692 static int intel_get_core_clock_speed(struct drm_device
*dev
)
1695 /* Core clock values taken from the published datasheets.
1696 * The 830 may go up to 166 Mhz, which we should check.
1700 else if (IS_I915G(dev
))
1702 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_IGDGM(dev
))
1704 else if (IS_I915GM(dev
)) {
1707 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
1709 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
1712 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
1713 case GC_DISPLAY_CLOCK_333_MHZ
:
1716 case GC_DISPLAY_CLOCK_190_200_MHZ
:
1720 } else if (IS_I865G(dev
))
1722 else if (IS_I855(dev
)) {
1724 /* Assume that the hardware is in the high speed state. This
1725 * should be the default.
1727 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
1728 case GC_CLOCK_133_200
:
1729 case GC_CLOCK_100_200
:
1731 case GC_CLOCK_166_250
:
1733 case GC_CLOCK_100_133
:
1736 } else /* 852, 830 */
1739 return 0; /* Silence gcc warning */
1743 * Return the pipe currently connected to the panel fitter,
1744 * or -1 if the panel fitter is not present or not in use
1746 static int intel_panel_fitter_pipe (struct drm_device
*dev
)
1748 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1751 /* i830 doesn't have a panel fitter */
1755 pfit_control
= I915_READ(PFIT_CONTROL
);
1757 /* See if the panel fitter is in use */
1758 if ((pfit_control
& PFIT_ENABLE
) == 0)
1761 /* 965 can place panel fitter on either pipe */
1763 return (pfit_control
>> 29) & 0x3;
1765 /* older chips can only use pipe 1 */
1778 fdi_reduce_ratio(u32
*num
, u32
*den
)
1780 while (*num
> 0xffffff || *den
> 0xffffff) {
1786 #define DATA_N 0x800000
1787 #define LINK_N 0x80000
1790 igdng_compute_m_n(int bits_per_pixel
, int nlanes
,
1791 int pixel_clock
, int link_clock
,
1792 struct fdi_m_n
*m_n
)
1796 m_n
->tu
= 64; /* default size */
1798 temp
= (u64
) DATA_N
* pixel_clock
;
1799 temp
= div_u64(temp
, link_clock
);
1800 m_n
->gmch_m
= div_u64(temp
* bits_per_pixel
, nlanes
);
1801 m_n
->gmch_m
>>= 3; /* convert to bytes_per_pixel */
1802 m_n
->gmch_n
= DATA_N
;
1803 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
1805 temp
= (u64
) LINK_N
* pixel_clock
;
1806 m_n
->link_m
= div_u64(temp
, link_clock
);
1807 m_n
->link_n
= LINK_N
;
1808 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
1812 struct intel_watermark_params
{
1813 unsigned long fifo_size
;
1814 unsigned long max_wm
;
1815 unsigned long default_wm
;
1816 unsigned long guard_size
;
1817 unsigned long cacheline_size
;
1820 /* IGD has different values for various configs */
1821 static struct intel_watermark_params igd_display_wm
= {
1828 static struct intel_watermark_params igd_display_hplloff_wm
= {
1835 static struct intel_watermark_params igd_cursor_wm
= {
1839 IGD_CURSOR_GUARD_WM
,
1842 static struct intel_watermark_params igd_cursor_hplloff_wm
= {
1846 IGD_CURSOR_GUARD_WM
,
1849 static struct intel_watermark_params i945_wm_info
= {
1856 static struct intel_watermark_params i915_wm_info
= {
1863 static struct intel_watermark_params i855_wm_info
= {
1870 static struct intel_watermark_params i830_wm_info
= {
1879 * intel_calculate_wm - calculate watermark level
1880 * @clock_in_khz: pixel clock
1881 * @wm: chip FIFO params
1882 * @pixel_size: display pixel size
1883 * @latency_ns: memory latency for the platform
1885 * Calculate the watermark level (the level at which the display plane will
1886 * start fetching from memory again). Each chip has a different display
1887 * FIFO size and allocation, so the caller needs to figure that out and pass
1888 * in the correct intel_watermark_params structure.
1890 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1891 * on the pixel size. When it reaches the watermark level, it'll start
1892 * fetching FIFO line sized based chunks from memory until the FIFO fills
1893 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1894 * will occur, and a display engine hang could result.
1896 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
1897 struct intel_watermark_params
*wm
,
1899 unsigned long latency_ns
)
1901 long entries_required
, wm_size
;
1904 * Note: we need to make sure we don't overflow for various clock &
1906 * clocks go from a few thousand to several hundred thousand.
1907 * latency is usually a few thousand
1909 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
1911 entries_required
/= wm
->cacheline_size
;
1913 DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required
);
1915 wm_size
= wm
->fifo_size
- (entries_required
+ wm
->guard_size
);
1917 DRM_DEBUG("FIFO watermark level: %d\n", wm_size
);
1919 /* Don't promote wm_size to unsigned... */
1920 if (wm_size
> (long)wm
->max_wm
)
1921 wm_size
= wm
->max_wm
;
1923 wm_size
= wm
->default_wm
;
1927 struct cxsr_latency
{
1929 unsigned long fsb_freq
;
1930 unsigned long mem_freq
;
1931 unsigned long display_sr
;
1932 unsigned long display_hpll_disable
;
1933 unsigned long cursor_sr
;
1934 unsigned long cursor_hpll_disable
;
1937 static struct cxsr_latency cxsr_latency_table
[] = {
1938 {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
1939 {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
1940 {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
1942 {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
1943 {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
1944 {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
1946 {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
1947 {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
1948 {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
1950 {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
1951 {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
1952 {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
1954 {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
1955 {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
1956 {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
1958 {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
1959 {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
1960 {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
1963 static struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
, int fsb
,
1967 struct cxsr_latency
*latency
;
1969 if (fsb
== 0 || mem
== 0)
1972 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
1973 latency
= &cxsr_latency_table
[i
];
1974 if (is_desktop
== latency
->is_desktop
&&
1975 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
1978 if (i
>= ARRAY_SIZE(cxsr_latency_table
)) {
1979 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
1985 static void igd_disable_cxsr(struct drm_device
*dev
)
1987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1990 /* deactivate cxsr */
1991 reg
= I915_READ(DSPFW3
);
1992 reg
&= ~(IGD_SELF_REFRESH_EN
);
1993 I915_WRITE(DSPFW3
, reg
);
1994 DRM_INFO("Big FIFO is disabled\n");
1997 static void igd_enable_cxsr(struct drm_device
*dev
, unsigned long clock
,
2000 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2003 struct cxsr_latency
*latency
;
2005 latency
= intel_get_cxsr_latency(IS_IGDG(dev
), dev_priv
->fsb_freq
,
2006 dev_priv
->mem_freq
);
2008 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2009 igd_disable_cxsr(dev
);
2014 wm
= intel_calculate_wm(clock
, &igd_display_wm
, pixel_size
,
2015 latency
->display_sr
);
2016 reg
= I915_READ(DSPFW1
);
2019 I915_WRITE(DSPFW1
, reg
);
2020 DRM_DEBUG("DSPFW1 register is %x\n", reg
);
2023 wm
= intel_calculate_wm(clock
, &igd_cursor_wm
, pixel_size
,
2024 latency
->cursor_sr
);
2025 reg
= I915_READ(DSPFW3
);
2026 reg
&= ~(0x3f << 24);
2027 reg
|= (wm
& 0x3f) << 24;
2028 I915_WRITE(DSPFW3
, reg
);
2030 /* Display HPLL off SR */
2031 wm
= intel_calculate_wm(clock
, &igd_display_hplloff_wm
,
2032 latency
->display_hpll_disable
, I915_FIFO_LINE_SIZE
);
2033 reg
= I915_READ(DSPFW3
);
2036 I915_WRITE(DSPFW3
, reg
);
2038 /* cursor HPLL off SR */
2039 wm
= intel_calculate_wm(clock
, &igd_cursor_hplloff_wm
, pixel_size
,
2040 latency
->cursor_hpll_disable
);
2041 reg
= I915_READ(DSPFW3
);
2042 reg
&= ~(0x3f << 16);
2043 reg
|= (wm
& 0x3f) << 16;
2044 I915_WRITE(DSPFW3
, reg
);
2045 DRM_DEBUG("DSPFW3 register is %x\n", reg
);
2048 reg
= I915_READ(DSPFW3
);
2049 reg
|= IGD_SELF_REFRESH_EN
;
2050 I915_WRITE(DSPFW3
, reg
);
2052 DRM_INFO("Big FIFO is enabled\n");
2058 * Latency for FIFO fetches is dependent on several factors:
2059 * - memory configuration (speed, channels)
2061 * - current MCH state
2062 * It can be fairly high in some situations, so here we assume a fairly
2063 * pessimal value. It's a tradeoff between extra memory fetches (if we
2064 * set this value too high, the FIFO will fetch frequently to stay full)
2065 * and power consumption (set it too low to save power and we might see
2066 * FIFO underruns and display "flicker").
2068 * A value of 5us seems to be a good balance; safe for very low end
2069 * platforms but not overly aggressive on lower latency configs.
2071 const static int latency_ns
= 5000;
2073 static int intel_get_fifo_size(struct drm_device
*dev
, int plane
)
2075 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2076 uint32_t dsparb
= I915_READ(DSPARB
);
2081 size
= dsparb
& 0x7f;
2083 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) -
2085 } else if (IS_I85X(dev
)) {
2087 size
= dsparb
& 0x1ff;
2089 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) -
2091 size
>>= 1; /* Convert to cachelines */
2092 } else if (IS_845G(dev
)) {
2093 size
= dsparb
& 0x7f;
2094 size
>>= 2; /* Convert to cachelines */
2096 size
= dsparb
& 0x7f;
2097 size
>>= 1; /* Convert to cachelines */
2100 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb
, plane
? "B" : "A",
2106 static void i965_update_wm(struct drm_device
*dev
)
2108 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2110 DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
2112 /* 965 has limitations... */
2113 I915_WRITE(DSPFW1
, (8 << 16) | (8 << 8) | (8 << 0));
2114 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
2117 static void i9xx_update_wm(struct drm_device
*dev
, int planea_clock
,
2118 int planeb_clock
, int sr_hdisplay
, int pixel_size
)
2120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2123 int total_size
, cacheline_size
, cwm
, srwm
= 1;
2124 int planea_wm
, planeb_wm
;
2125 struct intel_watermark_params planea_params
, planeb_params
;
2126 unsigned long line_time_us
;
2127 int sr_clock
, sr_entries
= 0;
2129 /* Create copies of the base settings for each pipe */
2130 if (IS_I965GM(dev
) || IS_I945GM(dev
))
2131 planea_params
= planeb_params
= i945_wm_info
;
2132 else if (IS_I9XX(dev
))
2133 planea_params
= planeb_params
= i915_wm_info
;
2135 planea_params
= planeb_params
= i855_wm_info
;
2137 /* Grab a couple of global values before we overwrite them */
2138 total_size
= planea_params
.fifo_size
;
2139 cacheline_size
= planea_params
.cacheline_size
;
2141 /* Update per-plane FIFO sizes */
2142 planea_params
.fifo_size
= intel_get_fifo_size(dev
, 0);
2143 planeb_params
.fifo_size
= intel_get_fifo_size(dev
, 1);
2145 planea_wm
= intel_calculate_wm(planea_clock
, &planea_params
,
2146 pixel_size
, latency_ns
);
2147 planeb_wm
= intel_calculate_wm(planeb_clock
, &planeb_params
,
2148 pixel_size
, latency_ns
);
2149 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
2152 * Overlay gets an aggressive default since video jitter is bad.
2156 /* Calc sr entries for one plane configs */
2157 if (sr_hdisplay
&& (!planea_clock
|| !planeb_clock
)) {
2158 /* self-refresh has much higher latency */
2159 const static int sr_latency_ns
= 6000;
2161 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
2162 line_time_us
= ((sr_hdisplay
* 1000) / sr_clock
);
2164 /* Use ns/us then divide to preserve precision */
2165 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1) *
2166 pixel_size
* sr_hdisplay
) / 1000;
2167 sr_entries
= roundup(sr_entries
/ cacheline_size
, 1);
2168 DRM_DEBUG("self-refresh entries: %d\n", sr_entries
);
2169 srwm
= total_size
- sr_entries
;
2173 I915_WRITE(FW_BLC_SELF
, (srwm
& 0x3f));
2176 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2177 planea_wm
, planeb_wm
, cwm
, srwm
);
2179 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
2180 fwater_hi
= (cwm
& 0x1f);
2182 /* Set request length to 8 cachelines per fetch */
2183 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
2184 fwater_hi
= fwater_hi
| (1 << 8);
2186 I915_WRITE(FW_BLC
, fwater_lo
);
2187 I915_WRITE(FW_BLC2
, fwater_hi
);
2190 static void i830_update_wm(struct drm_device
*dev
, int planea_clock
,
2193 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2194 uint32_t fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
2197 i830_wm_info
.fifo_size
= intel_get_fifo_size(dev
, 0);
2199 planea_wm
= intel_calculate_wm(planea_clock
, &i830_wm_info
,
2200 pixel_size
, latency_ns
);
2201 fwater_lo
|= (3<<8) | planea_wm
;
2203 DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm
);
2205 I915_WRITE(FW_BLC
, fwater_lo
);
2209 * intel_update_watermarks - update FIFO watermark values based on current modes
2211 * Calculate watermark values for the various WM regs based on current mode
2212 * and plane configuration.
2214 * There are several cases to deal with here:
2215 * - normal (i.e. non-self-refresh)
2216 * - self-refresh (SR) mode
2217 * - lines are large relative to FIFO size (buffer can hold up to 2)
2218 * - lines are small relative to FIFO size (buffer can hold more than 2
2219 * lines), so need to account for TLB latency
2221 * The normal calculation is:
2222 * watermark = dotclock * bytes per pixel * latency
2223 * where latency is platform & configuration dependent (we assume pessimal
2226 * The SR calculation is:
2227 * watermark = (trunc(latency/line time)+1) * surface width *
2230 * line time = htotal / dotclock
2231 * and latency is assumed to be high, as above.
2233 * The final value programmed to the register should always be rounded up,
2234 * and include an extra 2 entries to account for clock crossings.
2236 * We don't use the sprite, so we can ignore that. And on Crestline we have
2237 * to set the non-SR watermarks to 8.
2239 static void intel_update_watermarks(struct drm_device
*dev
)
2241 struct drm_crtc
*crtc
;
2242 struct intel_crtc
*intel_crtc
;
2243 int sr_hdisplay
= 0;
2244 unsigned long planea_clock
= 0, planeb_clock
= 0, sr_clock
= 0;
2245 int enabled
= 0, pixel_size
= 0;
2247 if (DSPARB_HWCONTROL(dev
))
2250 /* Get the clock config from both planes */
2251 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2252 intel_crtc
= to_intel_crtc(crtc
);
2253 if (crtc
->enabled
) {
2255 if (intel_crtc
->plane
== 0) {
2256 DRM_DEBUG("plane A (pipe %d) clock: %d\n",
2257 intel_crtc
->pipe
, crtc
->mode
.clock
);
2258 planea_clock
= crtc
->mode
.clock
;
2260 DRM_DEBUG("plane B (pipe %d) clock: %d\n",
2261 intel_crtc
->pipe
, crtc
->mode
.clock
);
2262 planeb_clock
= crtc
->mode
.clock
;
2264 sr_hdisplay
= crtc
->mode
.hdisplay
;
2265 sr_clock
= crtc
->mode
.clock
;
2267 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
2269 pixel_size
= 4; /* by default */
2276 /* Single plane configs can enable self refresh */
2277 if (enabled
== 1 && IS_IGD(dev
))
2278 igd_enable_cxsr(dev
, sr_clock
, pixel_size
);
2279 else if (IS_IGD(dev
))
2280 igd_disable_cxsr(dev
);
2283 i965_update_wm(dev
);
2284 else if (IS_I9XX(dev
) || IS_MOBILE(dev
))
2285 i9xx_update_wm(dev
, planea_clock
, planeb_clock
, sr_hdisplay
,
2288 i830_update_wm(dev
, planea_clock
, pixel_size
);
2291 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
2292 struct drm_display_mode
*mode
,
2293 struct drm_display_mode
*adjusted_mode
,
2295 struct drm_framebuffer
*old_fb
)
2297 struct drm_device
*dev
= crtc
->dev
;
2298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2299 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2300 int pipe
= intel_crtc
->pipe
;
2301 int fp_reg
= (pipe
== 0) ? FPA0
: FPB0
;
2302 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
2303 int dpll_md_reg
= (intel_crtc
->pipe
== 0) ? DPLL_A_MD
: DPLL_B_MD
;
2304 int dspcntr_reg
= (pipe
== 0) ? DSPACNTR
: DSPBCNTR
;
2305 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
2306 int htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
2307 int hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
2308 int hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
2309 int vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
2310 int vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
2311 int vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
2312 int dspsize_reg
= (pipe
== 0) ? DSPASIZE
: DSPBSIZE
;
2313 int dsppos_reg
= (pipe
== 0) ? DSPAPOS
: DSPBPOS
;
2314 int pipesrc_reg
= (pipe
== 0) ? PIPEASRC
: PIPEBSRC
;
2315 int refclk
, num_outputs
= 0;
2316 intel_clock_t clock
;
2317 u32 dpll
= 0, fp
= 0, dspcntr
, pipeconf
;
2318 bool ok
, is_sdvo
= false, is_dvo
= false;
2319 bool is_crt
= false, is_lvds
= false, is_tv
= false, is_dp
= false;
2320 bool is_edp
= false;
2321 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2322 struct drm_connector
*connector
;
2323 const intel_limit_t
*limit
;
2325 struct fdi_m_n m_n
= {0};
2326 int data_m1_reg
= (pipe
== 0) ? PIPEA_DATA_M1
: PIPEB_DATA_M1
;
2327 int data_n1_reg
= (pipe
== 0) ? PIPEA_DATA_N1
: PIPEB_DATA_N1
;
2328 int link_m1_reg
= (pipe
== 0) ? PIPEA_LINK_M1
: PIPEB_LINK_M1
;
2329 int link_n1_reg
= (pipe
== 0) ? PIPEA_LINK_N1
: PIPEB_LINK_N1
;
2330 int pch_fp_reg
= (pipe
== 0) ? PCH_FPA0
: PCH_FPB0
;
2331 int pch_dpll_reg
= (pipe
== 0) ? PCH_DPLL_A
: PCH_DPLL_B
;
2332 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
2333 int lvds_reg
= LVDS
;
2335 int sdvo_pixel_multiply
;
2338 drm_vblank_pre_modeset(dev
, pipe
);
2340 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
2341 struct intel_output
*intel_output
= to_intel_output(connector
);
2343 if (!connector
->encoder
|| connector
->encoder
->crtc
!= crtc
)
2346 switch (intel_output
->type
) {
2347 case INTEL_OUTPUT_LVDS
:
2350 case INTEL_OUTPUT_SDVO
:
2351 case INTEL_OUTPUT_HDMI
:
2353 if (intel_output
->needs_tv_clock
)
2356 case INTEL_OUTPUT_DVO
:
2359 case INTEL_OUTPUT_TVOUT
:
2362 case INTEL_OUTPUT_ANALOG
:
2365 case INTEL_OUTPUT_DISPLAYPORT
:
2368 case INTEL_OUTPUT_EDP
:
2376 if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_outputs
< 2) {
2377 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
2378 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk
/ 1000);
2379 } else if (IS_I9XX(dev
)) {
2382 refclk
= 120000; /* 120Mhz refclk */
2389 * Returns a set of divisors for the desired target clock with the given
2390 * refclk, or FALSE. The returned values represent the clock equation:
2391 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2393 limit
= intel_limit(crtc
);
2394 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, &clock
);
2396 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2397 drm_vblank_post_modeset(dev
, pipe
);
2401 /* SDVO TV has fixed PLL values depend on its clock range,
2402 this mirrors vbios setting. */
2403 if (is_sdvo
&& is_tv
) {
2404 if (adjusted_mode
->clock
>= 100000
2405 && adjusted_mode
->clock
< 140500) {
2411 } else if (adjusted_mode
->clock
>= 140500
2412 && adjusted_mode
->clock
<= 200000) {
2422 if (IS_IGDNG(dev
)) {
2423 int lane
, link_bw
, bpp
;
2424 /* eDP doesn't require FDI link, so just set DP M/N
2425 according to current link config */
2427 struct drm_connector
*edp
;
2428 target_clock
= mode
->clock
;
2429 edp
= intel_pipe_get_output(crtc
);
2430 intel_edp_link_config(to_intel_output(edp
),
2433 /* DP over FDI requires target mode clock
2434 instead of link clock */
2436 target_clock
= mode
->clock
;
2438 target_clock
= adjusted_mode
->clock
;
2443 /* determine panel color depth */
2444 temp
= I915_READ(pipeconf_reg
);
2446 switch (temp
& PIPE_BPC_MASK
) {
2460 DRM_ERROR("unknown pipe bpc value\n");
2464 igdng_compute_m_n(bpp
, lane
, target_clock
,
2468 /* Ironlake: try to setup display ref clock before DPLL
2469 * enabling. This is only under driver's control after
2470 * PCH B stepping, previous chipset stepping should be
2471 * ignoring this setting.
2473 if (IS_IGDNG(dev
)) {
2474 temp
= I915_READ(PCH_DREF_CONTROL
);
2475 /* Always enable nonspread source */
2476 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
2477 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
2478 I915_WRITE(PCH_DREF_CONTROL
, temp
);
2479 POSTING_READ(PCH_DREF_CONTROL
);
2481 temp
&= ~DREF_SSC_SOURCE_MASK
;
2482 temp
|= DREF_SSC_SOURCE_ENABLE
;
2483 I915_WRITE(PCH_DREF_CONTROL
, temp
);
2484 POSTING_READ(PCH_DREF_CONTROL
);
2489 if (dev_priv
->lvds_use_ssc
) {
2490 temp
|= DREF_SSC1_ENABLE
;
2491 I915_WRITE(PCH_DREF_CONTROL
, temp
);
2492 POSTING_READ(PCH_DREF_CONTROL
);
2496 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
2497 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
2498 I915_WRITE(PCH_DREF_CONTROL
, temp
);
2499 POSTING_READ(PCH_DREF_CONTROL
);
2501 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
2502 I915_WRITE(PCH_DREF_CONTROL
, temp
);
2503 POSTING_READ(PCH_DREF_CONTROL
);
2509 fp
= (1 << clock
.n
) << 16 | clock
.m1
<< 8 | clock
.m2
;
2511 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
2514 dpll
= DPLL_VGA_MODE_DIS
;
2518 dpll
|= DPLLB_MODE_LVDS
;
2520 dpll
|= DPLLB_MODE_DAC_SERIAL
;
2522 dpll
|= DPLL_DVO_HIGH_SPEED
;
2523 sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
2524 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
2525 dpll
|= (sdvo_pixel_multiply
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
2526 else if (IS_IGDNG(dev
))
2527 dpll
|= (sdvo_pixel_multiply
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
2530 dpll
|= DPLL_DVO_HIGH_SPEED
;
2532 /* compute bitmask from p1 value */
2534 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD
;
2536 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
2539 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
2543 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
2546 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
2549 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
2552 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
2555 if (IS_I965G(dev
) && !IS_IGDNG(dev
))
2556 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
2559 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
2562 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
2564 dpll
|= (clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
2566 dpll
|= PLL_P2_DIVIDE_BY_4
;
2570 if (is_sdvo
&& is_tv
)
2571 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
2573 /* XXX: just matching BIOS for now */
2574 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
2576 else if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_outputs
< 2)
2577 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
2579 dpll
|= PLL_REF_INPUT_DREFCLK
;
2581 /* setup pipeconf */
2582 pipeconf
= I915_READ(pipeconf_reg
);
2584 /* Set up the display plane register */
2585 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2587 /* IGDNG's plane is forced to pipe, bit 24 is to
2588 enable color space conversion */
2589 if (!IS_IGDNG(dev
)) {
2591 dspcntr
|= DISPPLANE_SEL_PIPE_A
;
2593 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2596 if (pipe
== 0 && !IS_I965G(dev
)) {
2597 /* Enable pixel doubling when the dot clock is > 90% of the (display)
2600 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
2603 if (mode
->clock
> intel_get_core_clock_speed(dev
) * 9 / 10)
2604 pipeconf
|= PIPEACONF_DOUBLE_WIDE
;
2606 pipeconf
&= ~PIPEACONF_DOUBLE_WIDE
;
2609 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2610 pipeconf
|= PIPEACONF_ENABLE
;
2611 dpll
|= DPLL_VCO_ENABLE
;
2614 /* Disable the panel fitter if it was on our pipe */
2615 if (!IS_IGDNG(dev
) && intel_panel_fitter_pipe(dev
) == pipe
)
2616 I915_WRITE(PFIT_CONTROL
, 0);
2618 DRM_DEBUG("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
2619 drm_mode_debug_printmodeline(mode
);
2621 /* assign to IGDNG registers */
2622 if (IS_IGDNG(dev
)) {
2623 fp_reg
= pch_fp_reg
;
2624 dpll_reg
= pch_dpll_reg
;
2628 igdng_disable_pll_edp(crtc
);
2629 } else if ((dpll
& DPLL_VCO_ENABLE
)) {
2630 I915_WRITE(fp_reg
, fp
);
2631 I915_WRITE(dpll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
2632 I915_READ(dpll_reg
);
2636 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
2637 * This is an exception to the general rule that mode_set doesn't turn
2644 lvds_reg
= PCH_LVDS
;
2646 lvds
= I915_READ(lvds_reg
);
2647 lvds
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
| LVDS_PIPEB_SELECT
;
2648 /* Set the B0-B3 data pairs corresponding to whether we're going to
2649 * set the DPLLs for dual-channel mode or not.
2652 lvds
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
2654 lvds
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
2656 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
2657 * appropriately here, but we need to look more thoroughly into how
2658 * panels behave in the two modes.
2661 I915_WRITE(lvds_reg
, lvds
);
2662 I915_READ(lvds_reg
);
2665 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
2668 I915_WRITE(fp_reg
, fp
);
2669 I915_WRITE(dpll_reg
, dpll
);
2670 I915_READ(dpll_reg
);
2671 /* Wait for the clocks to stabilize. */
2674 if (IS_I965G(dev
) && !IS_IGDNG(dev
)) {
2675 sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
2676 I915_WRITE(dpll_md_reg
, (0 << DPLL_MD_UDI_DIVIDER_SHIFT
) |
2677 ((sdvo_pixel_multiply
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
));
2679 /* write it again -- the BIOS does, after all */
2680 I915_WRITE(dpll_reg
, dpll
);
2682 I915_READ(dpll_reg
);
2683 /* Wait for the clocks to stabilize. */
2687 I915_WRITE(htot_reg
, (adjusted_mode
->crtc_hdisplay
- 1) |
2688 ((adjusted_mode
->crtc_htotal
- 1) << 16));
2689 I915_WRITE(hblank_reg
, (adjusted_mode
->crtc_hblank_start
- 1) |
2690 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
2691 I915_WRITE(hsync_reg
, (adjusted_mode
->crtc_hsync_start
- 1) |
2692 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
2693 I915_WRITE(vtot_reg
, (adjusted_mode
->crtc_vdisplay
- 1) |
2694 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
2695 I915_WRITE(vblank_reg
, (adjusted_mode
->crtc_vblank_start
- 1) |
2696 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
2697 I915_WRITE(vsync_reg
, (adjusted_mode
->crtc_vsync_start
- 1) |
2698 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
2699 /* pipesrc and dspsize control the size that is scaled from, which should
2700 * always be the user's requested size.
2702 if (!IS_IGDNG(dev
)) {
2703 I915_WRITE(dspsize_reg
, ((mode
->vdisplay
- 1) << 16) |
2704 (mode
->hdisplay
- 1));
2705 I915_WRITE(dsppos_reg
, 0);
2707 I915_WRITE(pipesrc_reg
, ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
2709 if (IS_IGDNG(dev
)) {
2710 I915_WRITE(data_m1_reg
, TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
2711 I915_WRITE(data_n1_reg
, TU_SIZE(m_n
.tu
) | m_n
.gmch_n
);
2712 I915_WRITE(link_m1_reg
, m_n
.link_m
);
2713 I915_WRITE(link_n1_reg
, m_n
.link_n
);
2716 igdng_set_pll_edp(crtc
, adjusted_mode
->clock
);
2718 /* enable FDI RX PLL too */
2719 temp
= I915_READ(fdi_rx_reg
);
2720 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_PLL_ENABLE
);
2725 I915_WRITE(pipeconf_reg
, pipeconf
);
2726 I915_READ(pipeconf_reg
);
2728 intel_wait_for_vblank(dev
);
2730 if (IS_IGDNG(dev
)) {
2731 /* enable address swizzle for tiling buffer */
2732 temp
= I915_READ(DISP_ARB_CTL
);
2733 I915_WRITE(DISP_ARB_CTL
, temp
| DISP_TILE_SURFACE_SWIZZLING
);
2736 I915_WRITE(dspcntr_reg
, dspcntr
);
2738 /* Flush the plane changes */
2739 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
2741 intel_update_watermarks(dev
);
2743 drm_vblank_post_modeset(dev
, pipe
);
2748 /** Loads the palette/gamma unit for the CRTC with the prepared values */
2749 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
2751 struct drm_device
*dev
= crtc
->dev
;
2752 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2753 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2754 int palreg
= (intel_crtc
->pipe
== 0) ? PALETTE_A
: PALETTE_B
;
2757 /* The clocks have to be on to load the palette. */
2761 /* use legacy palette for IGDNG */
2763 palreg
= (intel_crtc
->pipe
== 0) ? LGC_PALETTE_A
:
2766 for (i
= 0; i
< 256; i
++) {
2767 I915_WRITE(palreg
+ 4 * i
,
2768 (intel_crtc
->lut_r
[i
] << 16) |
2769 (intel_crtc
->lut_g
[i
] << 8) |
2770 intel_crtc
->lut_b
[i
]);
2774 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
2775 struct drm_file
*file_priv
,
2777 uint32_t width
, uint32_t height
)
2779 struct drm_device
*dev
= crtc
->dev
;
2780 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2781 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2782 struct drm_gem_object
*bo
;
2783 struct drm_i915_gem_object
*obj_priv
;
2784 int pipe
= intel_crtc
->pipe
;
2785 uint32_t control
= (pipe
== 0) ? CURACNTR
: CURBCNTR
;
2786 uint32_t base
= (pipe
== 0) ? CURABASE
: CURBBASE
;
2787 uint32_t temp
= I915_READ(control
);
2793 /* if we want to turn off the cursor ignore width and height */
2795 DRM_DEBUG("cursor off\n");
2796 if (IS_MOBILE(dev
) || IS_I9XX(dev
)) {
2797 temp
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
2798 temp
|= CURSOR_MODE_DISABLE
;
2800 temp
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
2804 mutex_lock(&dev
->struct_mutex
);
2808 /* Currently we only support 64x64 cursors */
2809 if (width
!= 64 || height
!= 64) {
2810 DRM_ERROR("we currently only support 64x64 cursors\n");
2814 bo
= drm_gem_object_lookup(dev
, file_priv
, handle
);
2818 obj_priv
= bo
->driver_private
;
2820 if (bo
->size
< width
* height
* 4) {
2821 DRM_ERROR("buffer is to small\n");
2826 /* we only need to pin inside GTT if cursor is non-phy */
2827 mutex_lock(&dev
->struct_mutex
);
2828 if (!dev_priv
->cursor_needs_physical
) {
2829 ret
= i915_gem_object_pin(bo
, PAGE_SIZE
);
2831 DRM_ERROR("failed to pin cursor bo\n");
2834 addr
= obj_priv
->gtt_offset
;
2836 ret
= i915_gem_attach_phys_object(dev
, bo
, (pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
);
2838 DRM_ERROR("failed to attach phys object\n");
2841 addr
= obj_priv
->phys_obj
->handle
->busaddr
;
2845 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
2847 /* Hooray for CUR*CNTR differences */
2848 if (IS_MOBILE(dev
) || IS_I9XX(dev
)) {
2849 temp
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
2850 temp
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
2851 temp
|= (pipe
<< 28); /* Connect to correct pipe */
2853 temp
&= ~(CURSOR_FORMAT_MASK
);
2854 temp
|= CURSOR_ENABLE
;
2855 temp
|= CURSOR_FORMAT_ARGB
| CURSOR_GAMMA_ENABLE
;
2859 I915_WRITE(control
, temp
);
2860 I915_WRITE(base
, addr
);
2862 if (intel_crtc
->cursor_bo
) {
2863 if (dev_priv
->cursor_needs_physical
) {
2864 if (intel_crtc
->cursor_bo
!= bo
)
2865 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
2867 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
2868 drm_gem_object_unreference(intel_crtc
->cursor_bo
);
2870 mutex_unlock(&dev
->struct_mutex
);
2872 intel_crtc
->cursor_addr
= addr
;
2873 intel_crtc
->cursor_bo
= bo
;
2877 mutex_lock(&dev
->struct_mutex
);
2879 drm_gem_object_unreference(bo
);
2880 mutex_unlock(&dev
->struct_mutex
);
2884 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
2886 struct drm_device
*dev
= crtc
->dev
;
2887 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2888 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2889 int pipe
= intel_crtc
->pipe
;
2894 temp
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
2898 temp
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
2902 temp
|= x
<< CURSOR_X_SHIFT
;
2903 temp
|= y
<< CURSOR_Y_SHIFT
;
2905 adder
= intel_crtc
->cursor_addr
;
2906 I915_WRITE((pipe
== 0) ? CURAPOS
: CURBPOS
, temp
);
2907 I915_WRITE((pipe
== 0) ? CURABASE
: CURBBASE
, adder
);
2912 /** Sets the color ramps on behalf of RandR */
2913 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
2914 u16 blue
, int regno
)
2916 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2918 intel_crtc
->lut_r
[regno
] = red
>> 8;
2919 intel_crtc
->lut_g
[regno
] = green
>> 8;
2920 intel_crtc
->lut_b
[regno
] = blue
>> 8;
2923 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
2924 u16
*blue
, uint32_t size
)
2926 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2932 for (i
= 0; i
< 256; i
++) {
2933 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
2934 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
2935 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
2938 intel_crtc_load_lut(crtc
);
2942 * Get a pipe with a simple mode set on it for doing load-based monitor
2945 * It will be up to the load-detect code to adjust the pipe as appropriate for
2946 * its requirements. The pipe will be connected to no other outputs.
2948 * Currently this code will only succeed if there is a pipe with no outputs
2949 * configured for it. In the future, it could choose to temporarily disable
2950 * some outputs to free up a pipe for its use.
2952 * \return crtc, or NULL if no pipes are available.
2955 /* VESA 640x480x72Hz mode to set on the pipe */
2956 static struct drm_display_mode load_detect_mode
= {
2957 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
2958 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
2961 struct drm_crtc
*intel_get_load_detect_pipe(struct intel_output
*intel_output
,
2962 struct drm_display_mode
*mode
,
2965 struct intel_crtc
*intel_crtc
;
2966 struct drm_crtc
*possible_crtc
;
2967 struct drm_crtc
*supported_crtc
=NULL
;
2968 struct drm_encoder
*encoder
= &intel_output
->enc
;
2969 struct drm_crtc
*crtc
= NULL
;
2970 struct drm_device
*dev
= encoder
->dev
;
2971 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
2972 struct drm_crtc_helper_funcs
*crtc_funcs
;
2976 * Algorithm gets a little messy:
2977 * - if the connector already has an assigned crtc, use it (but make
2978 * sure it's on first)
2979 * - try to find the first unused crtc that can drive this connector,
2980 * and use that if we find one
2981 * - if there are no unused crtcs available, try to use the first
2982 * one we found that supports the connector
2985 /* See if we already have a CRTC for this connector */
2986 if (encoder
->crtc
) {
2987 crtc
= encoder
->crtc
;
2988 /* Make sure the crtc and connector are running */
2989 intel_crtc
= to_intel_crtc(crtc
);
2990 *dpms_mode
= intel_crtc
->dpms_mode
;
2991 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
2992 crtc_funcs
= crtc
->helper_private
;
2993 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
2994 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
2999 /* Find an unused one (if possible) */
3000 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
3002 if (!(encoder
->possible_crtcs
& (1 << i
)))
3004 if (!possible_crtc
->enabled
) {
3005 crtc
= possible_crtc
;
3008 if (!supported_crtc
)
3009 supported_crtc
= possible_crtc
;
3013 * If we didn't find an unused CRTC, don't use any.
3019 encoder
->crtc
= crtc
;
3020 intel_output
->base
.encoder
= encoder
;
3021 intel_output
->load_detect_temp
= true;
3023 intel_crtc
= to_intel_crtc(crtc
);
3024 *dpms_mode
= intel_crtc
->dpms_mode
;
3026 if (!crtc
->enabled
) {
3028 mode
= &load_detect_mode
;
3029 drm_crtc_helper_set_mode(crtc
, mode
, 0, 0, crtc
->fb
);
3031 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
3032 crtc_funcs
= crtc
->helper_private
;
3033 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
3036 /* Add this connector to the crtc */
3037 encoder_funcs
->mode_set(encoder
, &crtc
->mode
, &crtc
->mode
);
3038 encoder_funcs
->commit(encoder
);
3040 /* let the connector get through one full cycle before testing */
3041 intel_wait_for_vblank(dev
);
3046 void intel_release_load_detect_pipe(struct intel_output
*intel_output
, int dpms_mode
)
3048 struct drm_encoder
*encoder
= &intel_output
->enc
;
3049 struct drm_device
*dev
= encoder
->dev
;
3050 struct drm_crtc
*crtc
= encoder
->crtc
;
3051 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
3052 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
3054 if (intel_output
->load_detect_temp
) {
3055 encoder
->crtc
= NULL
;
3056 intel_output
->base
.encoder
= NULL
;
3057 intel_output
->load_detect_temp
= false;
3058 crtc
->enabled
= drm_helper_crtc_in_use(crtc
);
3059 drm_helper_disable_unused_functions(dev
);
3062 /* Switch crtc and output back off if necessary */
3063 if (crtc
->enabled
&& dpms_mode
!= DRM_MODE_DPMS_ON
) {
3064 if (encoder
->crtc
== crtc
)
3065 encoder_funcs
->dpms(encoder
, dpms_mode
);
3066 crtc_funcs
->dpms(crtc
, dpms_mode
);
3070 /* Returns the clock of the currently programmed mode of the given pipe. */
3071 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
3073 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3074 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3075 int pipe
= intel_crtc
->pipe
;
3076 u32 dpll
= I915_READ((pipe
== 0) ? DPLL_A
: DPLL_B
);
3078 intel_clock_t clock
;
3080 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
3081 fp
= I915_READ((pipe
== 0) ? FPA0
: FPB0
);
3083 fp
= I915_READ((pipe
== 0) ? FPA1
: FPB1
);
3085 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
3087 clock
.n
= ffs((fp
& FP_N_IGD_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
3088 clock
.m2
= (fp
& FP_M2_IGD_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
3090 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
3091 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
3096 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_IGD
) >>
3097 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD
);
3099 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
3100 DPLL_FPA01_P1_POST_DIV_SHIFT
);
3102 switch (dpll
& DPLL_MODE_MASK
) {
3103 case DPLLB_MODE_DAC_SERIAL
:
3104 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
3107 case DPLLB_MODE_LVDS
:
3108 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
3112 DRM_DEBUG("Unknown DPLL mode %08x in programmed "
3113 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
3117 /* XXX: Handle the 100Mhz refclk */
3118 intel_clock(dev
, 96000, &clock
);
3120 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
3123 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
3124 DPLL_FPA01_P1_POST_DIV_SHIFT
);
3127 if ((dpll
& PLL_REF_INPUT_MASK
) ==
3128 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
3129 /* XXX: might not be 66MHz */
3130 intel_clock(dev
, 66000, &clock
);
3132 intel_clock(dev
, 48000, &clock
);
3134 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
3137 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
3138 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
3140 if (dpll
& PLL_P2_DIVIDE_BY_4
)
3145 intel_clock(dev
, 48000, &clock
);
3149 /* XXX: It would be nice to validate the clocks, but we can't reuse
3150 * i830PllIsValid() because it relies on the xf86_config connector
3151 * configuration being accurate, which it isn't necessarily.
3157 /** Returns the currently programmed mode of the given pipe. */
3158 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
3159 struct drm_crtc
*crtc
)
3161 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3162 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3163 int pipe
= intel_crtc
->pipe
;
3164 struct drm_display_mode
*mode
;
3165 int htot
= I915_READ((pipe
== 0) ? HTOTAL_A
: HTOTAL_B
);
3166 int hsync
= I915_READ((pipe
== 0) ? HSYNC_A
: HSYNC_B
);
3167 int vtot
= I915_READ((pipe
== 0) ? VTOTAL_A
: VTOTAL_B
);
3168 int vsync
= I915_READ((pipe
== 0) ? VSYNC_A
: VSYNC_B
);
3170 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
3174 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
3175 mode
->hdisplay
= (htot
& 0xffff) + 1;
3176 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
3177 mode
->hsync_start
= (hsync
& 0xffff) + 1;
3178 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
3179 mode
->vdisplay
= (vtot
& 0xffff) + 1;
3180 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
3181 mode
->vsync_start
= (vsync
& 0xffff) + 1;
3182 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
3184 drm_mode_set_name(mode
);
3185 drm_mode_set_crtcinfo(mode
, 0);
3190 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
3192 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3194 if (intel_crtc
->mode_set
.mode
)
3195 drm_mode_destroy(crtc
->dev
, intel_crtc
->mode_set
.mode
);
3196 drm_crtc_cleanup(crtc
);
3200 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
3201 .dpms
= intel_crtc_dpms
,
3202 .mode_fixup
= intel_crtc_mode_fixup
,
3203 .mode_set
= intel_crtc_mode_set
,
3204 .mode_set_base
= intel_pipe_set_base
,
3205 .prepare
= intel_crtc_prepare
,
3206 .commit
= intel_crtc_commit
,
3209 static const struct drm_crtc_funcs intel_crtc_funcs
= {
3210 .cursor_set
= intel_crtc_cursor_set
,
3211 .cursor_move
= intel_crtc_cursor_move
,
3212 .gamma_set
= intel_crtc_gamma_set
,
3213 .set_config
= drm_crtc_helper_set_config
,
3214 .destroy
= intel_crtc_destroy
,
3218 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
3220 struct intel_crtc
*intel_crtc
;
3223 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
3224 if (intel_crtc
== NULL
)
3227 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
3229 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
3230 intel_crtc
->pipe
= pipe
;
3231 intel_crtc
->plane
= pipe
;
3232 for (i
= 0; i
< 256; i
++) {
3233 intel_crtc
->lut_r
[i
] = i
;
3234 intel_crtc
->lut_g
[i
] = i
;
3235 intel_crtc
->lut_b
[i
] = i
;
3238 intel_crtc
->cursor_addr
= 0;
3239 intel_crtc
->dpms_mode
= DRM_MODE_DPMS_OFF
;
3240 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
3242 intel_crtc
->mode_set
.crtc
= &intel_crtc
->base
;
3243 intel_crtc
->mode_set
.connectors
= (struct drm_connector
**)(intel_crtc
+ 1);
3244 intel_crtc
->mode_set
.num_connectors
= 0;
3246 if (i915_fbpercrtc
) {
3253 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
3254 struct drm_file
*file_priv
)
3256 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3257 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
3258 struct drm_crtc
*crtc
= NULL
;
3262 DRM_ERROR("called with no initialization\n");
3266 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3267 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3268 if (crtc
->base
.id
== pipe_from_crtc_id
->crtc_id
) {
3269 pipe
= intel_crtc
->pipe
;
3275 DRM_ERROR("no such CRTC id\n");
3279 pipe_from_crtc_id
->pipe
= pipe
;
3284 struct drm_crtc
*intel_get_crtc_from_pipe(struct drm_device
*dev
, int pipe
)
3286 struct drm_crtc
*crtc
= NULL
;
3288 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3289 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3290 if (intel_crtc
->pipe
== pipe
)
3296 static int intel_connector_clones(struct drm_device
*dev
, int type_mask
)
3299 struct drm_connector
*connector
;
3302 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3303 struct intel_output
*intel_output
= to_intel_output(connector
);
3304 if (type_mask
& intel_output
->clone_mask
)
3305 index_mask
|= (1 << entry
);
3312 static void intel_setup_outputs(struct drm_device
*dev
)
3314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3315 struct drm_connector
*connector
;
3317 intel_crt_init(dev
);
3319 /* Set up integrated LVDS */
3320 if (IS_MOBILE(dev
) && !IS_I830(dev
))
3321 intel_lvds_init(dev
);
3323 if (IS_IGDNG(dev
)) {
3326 if (IS_MOBILE(dev
) && (I915_READ(DP_A
) & DP_DETECTED
))
3327 intel_dp_init(dev
, DP_A
);
3329 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
3331 /* found = intel_sdvo_init(dev, HDMIB); */
3334 intel_hdmi_init(dev
, HDMIB
);
3335 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
3336 intel_dp_init(dev
, PCH_DP_B
);
3339 if (I915_READ(HDMIC
) & PORT_DETECTED
)
3340 intel_hdmi_init(dev
, HDMIC
);
3342 if (I915_READ(HDMID
) & PORT_DETECTED
)
3343 intel_hdmi_init(dev
, HDMID
);
3345 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
3346 intel_dp_init(dev
, PCH_DP_C
);
3348 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
3349 intel_dp_init(dev
, PCH_DP_D
);
3351 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
3354 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
3355 found
= intel_sdvo_init(dev
, SDVOB
);
3356 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
))
3357 intel_hdmi_init(dev
, SDVOB
);
3359 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
3360 intel_dp_init(dev
, DP_B
);
3363 /* Before G4X SDVOC doesn't have its own detect register */
3365 if (I915_READ(SDVOB
) & SDVO_DETECTED
)
3366 found
= intel_sdvo_init(dev
, SDVOC
);
3368 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
3370 if (SUPPORTS_INTEGRATED_HDMI(dev
))
3371 intel_hdmi_init(dev
, SDVOC
);
3372 if (SUPPORTS_INTEGRATED_DP(dev
))
3373 intel_dp_init(dev
, DP_C
);
3376 if (SUPPORTS_INTEGRATED_DP(dev
) && (I915_READ(DP_D
) & DP_DETECTED
))
3377 intel_dp_init(dev
, DP_D
);
3378 } else if (IS_I8XX(dev
))
3379 intel_dvo_init(dev
);
3381 if (SUPPORTS_TV(dev
))
3384 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3385 struct intel_output
*intel_output
= to_intel_output(connector
);
3386 struct drm_encoder
*encoder
= &intel_output
->enc
;
3388 encoder
->possible_crtcs
= intel_output
->crtc_mask
;
3389 encoder
->possible_clones
= intel_connector_clones(dev
,
3390 intel_output
->clone_mask
);
3394 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
3396 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
3397 struct drm_device
*dev
= fb
->dev
;
3400 intelfb_remove(dev
, fb
);
3402 drm_framebuffer_cleanup(fb
);
3403 mutex_lock(&dev
->struct_mutex
);
3404 drm_gem_object_unreference(intel_fb
->obj
);
3405 mutex_unlock(&dev
->struct_mutex
);
3410 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
3411 struct drm_file
*file_priv
,
3412 unsigned int *handle
)
3414 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
3415 struct drm_gem_object
*object
= intel_fb
->obj
;
3417 return drm_gem_handle_create(file_priv
, object
, handle
);
3420 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
3421 .destroy
= intel_user_framebuffer_destroy
,
3422 .create_handle
= intel_user_framebuffer_create_handle
,
3425 int intel_framebuffer_create(struct drm_device
*dev
,
3426 struct drm_mode_fb_cmd
*mode_cmd
,
3427 struct drm_framebuffer
**fb
,
3428 struct drm_gem_object
*obj
)
3430 struct intel_framebuffer
*intel_fb
;
3433 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
3437 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
3439 DRM_ERROR("framebuffer init failed %d\n", ret
);
3443 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
3445 intel_fb
->obj
= obj
;
3447 *fb
= &intel_fb
->base
;
3453 static struct drm_framebuffer
*
3454 intel_user_framebuffer_create(struct drm_device
*dev
,
3455 struct drm_file
*filp
,
3456 struct drm_mode_fb_cmd
*mode_cmd
)
3458 struct drm_gem_object
*obj
;
3459 struct drm_framebuffer
*fb
;
3462 obj
= drm_gem_object_lookup(dev
, filp
, mode_cmd
->handle
);
3466 ret
= intel_framebuffer_create(dev
, mode_cmd
, &fb
, obj
);
3468 mutex_lock(&dev
->struct_mutex
);
3469 drm_gem_object_unreference(obj
);
3470 mutex_unlock(&dev
->struct_mutex
);
3477 static const struct drm_mode_config_funcs intel_mode_funcs
= {
3478 .fb_create
= intel_user_framebuffer_create
,
3479 .fb_changed
= intelfb_probe
,
3482 void intel_modeset_init(struct drm_device
*dev
)
3487 drm_mode_config_init(dev
);
3489 dev
->mode_config
.min_width
= 0;
3490 dev
->mode_config
.min_height
= 0;
3492 dev
->mode_config
.funcs
= (void *)&intel_mode_funcs
;
3494 if (IS_I965G(dev
)) {
3495 dev
->mode_config
.max_width
= 8192;
3496 dev
->mode_config
.max_height
= 8192;
3497 } else if (IS_I9XX(dev
)) {
3498 dev
->mode_config
.max_width
= 4096;
3499 dev
->mode_config
.max_height
= 4096;
3501 dev
->mode_config
.max_width
= 2048;
3502 dev
->mode_config
.max_height
= 2048;
3505 /* set memory base */
3507 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 2);
3509 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 0);
3511 if (IS_MOBILE(dev
) || IS_I9XX(dev
))
3515 DRM_DEBUG("%d display pipe%s available.\n",
3516 num_pipe
, num_pipe
> 1 ? "s" : "");
3518 for (i
= 0; i
< num_pipe
; i
++) {
3519 intel_crtc_init(dev
, i
);
3522 intel_setup_outputs(dev
);
3525 void intel_modeset_cleanup(struct drm_device
*dev
)
3527 drm_mode_config_cleanup(dev
);
3531 /* current intel driver doesn't take advantage of encoders
3532 always give back the encoder for the connector
3534 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
3536 struct intel_output
*intel_output
= to_intel_output(connector
);
3538 return &intel_output
->enc
;