2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/sysdev.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
40 #include <acpi/acpi_bus.h>
42 #include <linux/bootmem.h>
43 #include <linux/dmar.h>
44 #include <linux/hpet.h>
50 #include <asm/proto.h>
53 #include <asm/timer.h>
54 #include <asm/i8259.h>
56 #include <asm/msidef.h>
57 #include <asm/hypertransport.h>
58 #include <asm/setup.h>
59 #include <asm/irq_remapping.h>
61 #include <asm/uv/uv_hub.h>
62 #include <asm/uv/uv_irq.h>
65 #include <mach_apic.h>
66 #include <mach_apicdef.h>
68 #define __apicdebuginit(type) static type __init
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug
= -1;
76 static DEFINE_SPINLOCK(ioapic_lock
);
77 static DEFINE_SPINLOCK(vector_lock
);
80 * # of IRQ routing registers
82 int nr_ioapic_registers
[MAX_IO_APICS
];
84 /* I/O APIC entries */
85 struct mp_config_ioapic mp_ioapics
[MAX_IO_APICS
];
88 /* MP IRQ source entries */
89 struct mp_config_intsrc mp_irqs
[MAX_IRQ_SOURCES
];
91 /* # of MP IRQ source entries */
94 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
95 int mp_bus_id_to_type
[MAX_MP_BUSSES
];
98 DECLARE_BITMAP(mp_bus_not_pci
, MAX_MP_BUSSES
);
100 int skip_ioapic_setup
;
102 static int __init
parse_noapic(char *str
)
104 /* disable IO-APIC */
105 disable_ioapic_setup();
108 early_param("noapic", parse_noapic
);
113 * This is performance-critical, we want to do it O(1)
115 * the indexing order of this array favors 1:1 mappings
116 * between pins and IRQs.
119 struct irq_pin_list
{
121 struct irq_pin_list
*next
;
124 static struct irq_pin_list
*get_one_free_irq_2_pin(int cpu
)
126 struct irq_pin_list
*pin
;
129 node
= cpu_to_node(cpu
);
131 pin
= kzalloc_node(sizeof(*pin
), GFP_ATOMIC
, node
);
132 printk(KERN_DEBUG
" alloc irq_2_pin on cpu %d node %d\n", cpu
, node
);
138 struct irq_pin_list
*irq_2_pin
;
139 cpumask_var_t domain
;
140 cpumask_var_t old_domain
;
141 unsigned move_cleanup_count
;
143 u8 move_in_progress
: 1;
144 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
145 u8 move_desc_pending
: 1;
149 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
150 #ifdef CONFIG_SPARSE_IRQ
151 static struct irq_cfg irq_cfgx
[] = {
153 static struct irq_cfg irq_cfgx
[NR_IRQS
] = {
155 [0] = { .vector
= IRQ0_VECTOR
, },
156 [1] = { .vector
= IRQ1_VECTOR
, },
157 [2] = { .vector
= IRQ2_VECTOR
, },
158 [3] = { .vector
= IRQ3_VECTOR
, },
159 [4] = { .vector
= IRQ4_VECTOR
, },
160 [5] = { .vector
= IRQ5_VECTOR
, },
161 [6] = { .vector
= IRQ6_VECTOR
, },
162 [7] = { .vector
= IRQ7_VECTOR
, },
163 [8] = { .vector
= IRQ8_VECTOR
, },
164 [9] = { .vector
= IRQ9_VECTOR
, },
165 [10] = { .vector
= IRQ10_VECTOR
, },
166 [11] = { .vector
= IRQ11_VECTOR
, },
167 [12] = { .vector
= IRQ12_VECTOR
, },
168 [13] = { .vector
= IRQ13_VECTOR
, },
169 [14] = { .vector
= IRQ14_VECTOR
, },
170 [15] = { .vector
= IRQ15_VECTOR
, },
173 int __init
arch_early_irq_init(void)
176 struct irq_desc
*desc
;
181 count
= ARRAY_SIZE(irq_cfgx
);
183 for (i
= 0; i
< count
; i
++) {
184 desc
= irq_to_desc(i
);
185 desc
->chip_data
= &cfg
[i
];
186 alloc_bootmem_cpumask_var(&cfg
[i
].domain
);
187 alloc_bootmem_cpumask_var(&cfg
[i
].old_domain
);
188 if (i
< NR_IRQS_LEGACY
)
189 cpumask_setall(cfg
[i
].domain
);
195 #ifdef CONFIG_SPARSE_IRQ
196 static struct irq_cfg
*irq_cfg(unsigned int irq
)
198 struct irq_cfg
*cfg
= NULL
;
199 struct irq_desc
*desc
;
201 desc
= irq_to_desc(irq
);
203 cfg
= desc
->chip_data
;
208 static struct irq_cfg
*get_one_free_irq_cfg(int cpu
)
213 node
= cpu_to_node(cpu
);
215 cfg
= kzalloc_node(sizeof(*cfg
), GFP_ATOMIC
, node
);
217 if (!alloc_cpumask_var_node(&cfg
->domain
, GFP_ATOMIC
, node
)) {
220 } else if (!alloc_cpumask_var_node(&cfg
->old_domain
,
222 free_cpumask_var(cfg
->domain
);
226 cpumask_clear(cfg
->domain
);
227 cpumask_clear(cfg
->old_domain
);
230 printk(KERN_DEBUG
" alloc irq_cfg on cpu %d node %d\n", cpu
, node
);
235 int arch_init_chip_data(struct irq_desc
*desc
, int cpu
)
239 cfg
= desc
->chip_data
;
241 desc
->chip_data
= get_one_free_irq_cfg(cpu
);
242 if (!desc
->chip_data
) {
243 printk(KERN_ERR
"can not alloc irq_cfg\n");
251 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
254 init_copy_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
, int cpu
)
256 struct irq_pin_list
*old_entry
, *head
, *tail
, *entry
;
258 cfg
->irq_2_pin
= NULL
;
259 old_entry
= old_cfg
->irq_2_pin
;
263 entry
= get_one_free_irq_2_pin(cpu
);
267 entry
->apic
= old_entry
->apic
;
268 entry
->pin
= old_entry
->pin
;
271 old_entry
= old_entry
->next
;
273 entry
= get_one_free_irq_2_pin(cpu
);
281 /* still use the old one */
284 entry
->apic
= old_entry
->apic
;
285 entry
->pin
= old_entry
->pin
;
288 old_entry
= old_entry
->next
;
292 cfg
->irq_2_pin
= head
;
295 static void free_irq_2_pin(struct irq_cfg
*old_cfg
, struct irq_cfg
*cfg
)
297 struct irq_pin_list
*entry
, *next
;
299 if (old_cfg
->irq_2_pin
== cfg
->irq_2_pin
)
302 entry
= old_cfg
->irq_2_pin
;
309 old_cfg
->irq_2_pin
= NULL
;
312 void arch_init_copy_chip_data(struct irq_desc
*old_desc
,
313 struct irq_desc
*desc
, int cpu
)
316 struct irq_cfg
*old_cfg
;
318 cfg
= get_one_free_irq_cfg(cpu
);
323 desc
->chip_data
= cfg
;
325 old_cfg
= old_desc
->chip_data
;
327 memcpy(cfg
, old_cfg
, sizeof(struct irq_cfg
));
329 init_copy_irq_2_pin(old_cfg
, cfg
, cpu
);
332 static void free_irq_cfg(struct irq_cfg
*old_cfg
)
337 void arch_free_chip_data(struct irq_desc
*old_desc
, struct irq_desc
*desc
)
339 struct irq_cfg
*old_cfg
, *cfg
;
341 old_cfg
= old_desc
->chip_data
;
342 cfg
= desc
->chip_data
;
348 free_irq_2_pin(old_cfg
, cfg
);
349 free_irq_cfg(old_cfg
);
350 old_desc
->chip_data
= NULL
;
355 set_extra_move_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
357 struct irq_cfg
*cfg
= desc
->chip_data
;
359 if (!cfg
->move_in_progress
) {
360 /* it means that domain is not changed */
361 if (!cpumask_intersects(&desc
->affinity
, mask
))
362 cfg
->move_desc_pending
= 1;
368 static struct irq_cfg
*irq_cfg(unsigned int irq
)
370 return irq
< nr_irqs
? irq_cfgx
+ irq
: NULL
;
375 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
377 set_extra_move_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
384 unsigned int unused
[3];
388 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
390 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
391 + (mp_ioapics
[idx
].mp_apicaddr
& ~PAGE_MASK
);
394 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
396 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
397 writel(reg
, &io_apic
->index
);
398 return readl(&io_apic
->data
);
401 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
403 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
404 writel(reg
, &io_apic
->index
);
405 writel(value
, &io_apic
->data
);
409 * Re-write a value: to be used for read-modify-write
410 * cycles where the read already set up the index register.
412 * Older SiS APIC requires we rewrite the index register
414 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
416 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
419 writel(reg
, &io_apic
->index
);
420 writel(value
, &io_apic
->data
);
423 static bool io_apic_level_ack_pending(struct irq_cfg
*cfg
)
425 struct irq_pin_list
*entry
;
428 spin_lock_irqsave(&ioapic_lock
, flags
);
429 entry
= cfg
->irq_2_pin
;
437 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
438 /* Is the remote IRR bit set? */
439 if (reg
& IO_APIC_REDIR_REMOTE_IRR
) {
440 spin_unlock_irqrestore(&ioapic_lock
, flags
);
447 spin_unlock_irqrestore(&ioapic_lock
, flags
);
453 struct { u32 w1
, w2
; };
454 struct IO_APIC_route_entry entry
;
457 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
459 union entry_union eu
;
461 spin_lock_irqsave(&ioapic_lock
, flags
);
462 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
463 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
464 spin_unlock_irqrestore(&ioapic_lock
, flags
);
469 * When we write a new IO APIC routing entry, we need to write the high
470 * word first! If the mask bit in the low word is clear, we will enable
471 * the interrupt, and we need to make sure the entry is fully populated
472 * before that happens.
475 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
477 union entry_union eu
;
479 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
480 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
483 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
486 spin_lock_irqsave(&ioapic_lock
, flags
);
487 __ioapic_write_entry(apic
, pin
, e
);
488 spin_unlock_irqrestore(&ioapic_lock
, flags
);
492 * When we mask an IO APIC routing entry, we need to write the low
493 * word first, in order to set the mask bit before we change the
496 static void ioapic_mask_entry(int apic
, int pin
)
499 union entry_union eu
= { .entry
.mask
= 1 };
501 spin_lock_irqsave(&ioapic_lock
, flags
);
502 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
503 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
504 spin_unlock_irqrestore(&ioapic_lock
, flags
);
508 static void send_cleanup_vector(struct irq_cfg
*cfg
)
510 cpumask_var_t cleanup_mask
;
512 if (unlikely(!alloc_cpumask_var(&cleanup_mask
, GFP_ATOMIC
))) {
514 cfg
->move_cleanup_count
= 0;
515 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
516 cfg
->move_cleanup_count
++;
517 for_each_cpu_and(i
, cfg
->old_domain
, cpu_online_mask
)
518 send_IPI_mask(cpumask_of(i
), IRQ_MOVE_CLEANUP_VECTOR
);
520 cpumask_and(cleanup_mask
, cfg
->old_domain
, cpu_online_mask
);
521 cfg
->move_cleanup_count
= cpumask_weight(cleanup_mask
);
522 send_IPI_mask(cleanup_mask
, IRQ_MOVE_CLEANUP_VECTOR
);
523 free_cpumask_var(cleanup_mask
);
525 cfg
->move_in_progress
= 0;
528 static void __target_IO_APIC_irq(unsigned int irq
, unsigned int dest
, struct irq_cfg
*cfg
)
531 struct irq_pin_list
*entry
;
532 u8 vector
= cfg
->vector
;
534 entry
= cfg
->irq_2_pin
;
543 #ifdef CONFIG_INTR_REMAP
545 * With interrupt-remapping, destination information comes
546 * from interrupt-remapping table entry.
548 if (!irq_remapped(irq
))
549 io_apic_write(apic
, 0x11 + pin
*2, dest
);
551 io_apic_write(apic
, 0x11 + pin
*2, dest
);
553 reg
= io_apic_read(apic
, 0x10 + pin
*2);
554 reg
&= ~IO_APIC_REDIR_VECTOR_MASK
;
556 io_apic_modify(apic
, 0x10 + pin
*2, reg
);
564 assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
);
567 * Either sets desc->affinity to a valid value, and returns cpu_mask_to_apicid
568 * of that, or returns BAD_APICID and leaves desc->affinity untouched.
571 set_desc_affinity(struct irq_desc
*desc
, const struct cpumask
*mask
)
576 if (!cpumask_intersects(mask
, cpu_online_mask
))
580 cfg
= desc
->chip_data
;
581 if (assign_irq_vector(irq
, cfg
, mask
))
584 cpumask_and(&desc
->affinity
, cfg
->domain
, mask
);
585 set_extra_move_desc(desc
, mask
);
586 return cpu_mask_to_apicid_and(&desc
->affinity
, cpu_online_mask
);
590 set_ioapic_affinity_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
598 cfg
= desc
->chip_data
;
600 spin_lock_irqsave(&ioapic_lock
, flags
);
601 dest
= set_desc_affinity(desc
, mask
);
602 if (dest
!= BAD_APICID
) {
603 /* Only the high 8 bits are valid. */
604 dest
= SET_APIC_LOGICAL_ID(dest
);
605 __target_IO_APIC_irq(irq
, dest
, cfg
);
607 spin_unlock_irqrestore(&ioapic_lock
, flags
);
611 set_ioapic_affinity_irq(unsigned int irq
, const struct cpumask
*mask
)
613 struct irq_desc
*desc
;
615 desc
= irq_to_desc(irq
);
617 set_ioapic_affinity_irq_desc(desc
, mask
);
619 #endif /* CONFIG_SMP */
622 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
623 * shared ISA-space IRQs, so we have to support them. We are super
624 * fast in the common case, and fast for shared ISA-space IRQs.
626 static void add_pin_to_irq_cpu(struct irq_cfg
*cfg
, int cpu
, int apic
, int pin
)
628 struct irq_pin_list
*entry
;
630 entry
= cfg
->irq_2_pin
;
632 entry
= get_one_free_irq_2_pin(cpu
);
634 printk(KERN_ERR
"can not alloc irq_2_pin to add %d - %d\n",
638 cfg
->irq_2_pin
= entry
;
644 while (entry
->next
) {
645 /* not again, please */
646 if (entry
->apic
== apic
&& entry
->pin
== pin
)
652 entry
->next
= get_one_free_irq_2_pin(cpu
);
659 * Reroute an IRQ to a different pin.
661 static void __init
replace_pin_at_irq_cpu(struct irq_cfg
*cfg
, int cpu
,
662 int oldapic
, int oldpin
,
663 int newapic
, int newpin
)
665 struct irq_pin_list
*entry
= cfg
->irq_2_pin
;
669 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
670 entry
->apic
= newapic
;
673 /* every one is different, right? */
679 /* why? call replace before add? */
681 add_pin_to_irq_cpu(cfg
, cpu
, newapic
, newpin
);
684 static inline void io_apic_modify_irq(struct irq_cfg
*cfg
,
685 int mask_and
, int mask_or
,
686 void (*final
)(struct irq_pin_list
*entry
))
689 struct irq_pin_list
*entry
;
691 for (entry
= cfg
->irq_2_pin
; entry
!= NULL
; entry
= entry
->next
) {
694 reg
= io_apic_read(entry
->apic
, 0x10 + pin
* 2);
697 io_apic_modify(entry
->apic
, 0x10 + pin
* 2, reg
);
703 static void __unmask_IO_APIC_irq(struct irq_cfg
*cfg
)
705 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
, 0, NULL
);
709 static void io_apic_sync(struct irq_pin_list
*entry
)
712 * Synchronize the IO-APIC and the CPU by doing
713 * a dummy read from the IO-APIC
715 struct io_apic __iomem
*io_apic
;
716 io_apic
= io_apic_base(entry
->apic
);
717 readl(&io_apic
->data
);
720 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
722 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, &io_apic_sync
);
724 #else /* CONFIG_X86_32 */
725 static void __mask_IO_APIC_irq(struct irq_cfg
*cfg
)
727 io_apic_modify_irq(cfg
, ~0, IO_APIC_REDIR_MASKED
, NULL
);
730 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg
*cfg
)
732 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_LEVEL_TRIGGER
,
733 IO_APIC_REDIR_MASKED
, NULL
);
736 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg
*cfg
)
738 io_apic_modify_irq(cfg
, ~IO_APIC_REDIR_MASKED
,
739 IO_APIC_REDIR_LEVEL_TRIGGER
, NULL
);
741 #endif /* CONFIG_X86_32 */
743 static void mask_IO_APIC_irq_desc(struct irq_desc
*desc
)
745 struct irq_cfg
*cfg
= desc
->chip_data
;
750 spin_lock_irqsave(&ioapic_lock
, flags
);
751 __mask_IO_APIC_irq(cfg
);
752 spin_unlock_irqrestore(&ioapic_lock
, flags
);
755 static void unmask_IO_APIC_irq_desc(struct irq_desc
*desc
)
757 struct irq_cfg
*cfg
= desc
->chip_data
;
760 spin_lock_irqsave(&ioapic_lock
, flags
);
761 __unmask_IO_APIC_irq(cfg
);
762 spin_unlock_irqrestore(&ioapic_lock
, flags
);
765 static void mask_IO_APIC_irq(unsigned int irq
)
767 struct irq_desc
*desc
= irq_to_desc(irq
);
769 mask_IO_APIC_irq_desc(desc
);
771 static void unmask_IO_APIC_irq(unsigned int irq
)
773 struct irq_desc
*desc
= irq_to_desc(irq
);
775 unmask_IO_APIC_irq_desc(desc
);
778 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
780 struct IO_APIC_route_entry entry
;
782 /* Check delivery_mode to be sure we're not clearing an SMI pin */
783 entry
= ioapic_read_entry(apic
, pin
);
784 if (entry
.delivery_mode
== dest_SMI
)
787 * Disable it in the IO-APIC irq-routing table:
789 ioapic_mask_entry(apic
, pin
);
792 static void clear_IO_APIC (void)
796 for (apic
= 0; apic
< nr_ioapics
; apic
++)
797 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
798 clear_IO_APIC_pin(apic
, pin
);
801 #if !defined(CONFIG_SMP) && defined(CONFIG_X86_32)
802 void send_IPI_self(int vector
)
809 apic_wait_icr_idle();
810 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
812 * Send the IPI. The write to APIC_ICR fires this off.
814 apic_write(APIC_ICR
, cfg
);
816 #endif /* !CONFIG_SMP && CONFIG_X86_32*/
820 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
821 * specific CPU-side IRQs.
825 static int pirq_entries
[MAX_PIRQS
];
826 static int pirqs_enabled
;
828 static int __init
ioapic_pirq_setup(char *str
)
831 int ints
[MAX_PIRQS
+1];
833 get_options(str
, ARRAY_SIZE(ints
), ints
);
835 for (i
= 0; i
< MAX_PIRQS
; i
++)
836 pirq_entries
[i
] = -1;
839 apic_printk(APIC_VERBOSE
, KERN_INFO
840 "PIRQ redirection, working around broken MP-BIOS.\n");
842 if (ints
[0] < MAX_PIRQS
)
845 for (i
= 0; i
< max
; i
++) {
846 apic_printk(APIC_VERBOSE
, KERN_DEBUG
847 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
849 * PIRQs are mapped upside down, usually.
851 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
856 __setup("pirq=", ioapic_pirq_setup
);
857 #endif /* CONFIG_X86_32 */
859 #ifdef CONFIG_INTR_REMAP
860 /* I/O APIC RTE contents at the OS boot up */
861 static struct IO_APIC_route_entry
*early_ioapic_entries
[MAX_IO_APICS
];
864 * Saves and masks all the unmasked IO-APIC RTE's
866 int save_mask_IO_APIC_setup(void)
868 union IO_APIC_reg_01 reg_01
;
873 * The number of IO-APIC IRQ registers (== #pins):
875 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
876 spin_lock_irqsave(&ioapic_lock
, flags
);
877 reg_01
.raw
= io_apic_read(apic
, 1);
878 spin_unlock_irqrestore(&ioapic_lock
, flags
);
879 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
882 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
883 early_ioapic_entries
[apic
] =
884 kzalloc(sizeof(struct IO_APIC_route_entry
) *
885 nr_ioapic_registers
[apic
], GFP_KERNEL
);
886 if (!early_ioapic_entries
[apic
])
890 for (apic
= 0; apic
< nr_ioapics
; apic
++)
891 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
892 struct IO_APIC_route_entry entry
;
894 entry
= early_ioapic_entries
[apic
][pin
] =
895 ioapic_read_entry(apic
, pin
);
898 ioapic_write_entry(apic
, pin
, entry
);
906 kfree(early_ioapic_entries
[apic
--]);
907 memset(early_ioapic_entries
, 0,
908 ARRAY_SIZE(early_ioapic_entries
));
913 void restore_IO_APIC_setup(void)
917 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
918 if (!early_ioapic_entries
[apic
])
920 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
921 ioapic_write_entry(apic
, pin
,
922 early_ioapic_entries
[apic
][pin
]);
923 kfree(early_ioapic_entries
[apic
]);
924 early_ioapic_entries
[apic
] = NULL
;
928 void reinit_intr_remapped_IO_APIC(int intr_remapping
)
931 * for now plain restore of previous settings.
932 * TBD: In the case of OS enabling interrupt-remapping,
933 * IO-APIC RTE's need to be setup to point to interrupt-remapping
934 * table entries. for now, do a plain restore, and wait for
935 * the setup_IO_APIC_irqs() to do proper initialization.
937 restore_IO_APIC_setup();
942 * Find the IRQ entry number of a certain pin.
944 static int find_irq_entry(int apic
, int pin
, int type
)
948 for (i
= 0; i
< mp_irq_entries
; i
++)
949 if (mp_irqs
[i
].mp_irqtype
== type
&&
950 (mp_irqs
[i
].mp_dstapic
== mp_ioapics
[apic
].mp_apicid
||
951 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
) &&
952 mp_irqs
[i
].mp_dstirq
== pin
)
959 * Find the pin to which IRQ[irq] (ISA) is connected
961 static int __init
find_isa_irq_pin(int irq
, int type
)
965 for (i
= 0; i
< mp_irq_entries
; i
++) {
966 int lbus
= mp_irqs
[i
].mp_srcbus
;
968 if (test_bit(lbus
, mp_bus_not_pci
) &&
969 (mp_irqs
[i
].mp_irqtype
== type
) &&
970 (mp_irqs
[i
].mp_srcbusirq
== irq
))
972 return mp_irqs
[i
].mp_dstirq
;
977 static int __init
find_isa_irq_apic(int irq
, int type
)
981 for (i
= 0; i
< mp_irq_entries
; i
++) {
982 int lbus
= mp_irqs
[i
].mp_srcbus
;
984 if (test_bit(lbus
, mp_bus_not_pci
) &&
985 (mp_irqs
[i
].mp_irqtype
== type
) &&
986 (mp_irqs
[i
].mp_srcbusirq
== irq
))
989 if (i
< mp_irq_entries
) {
991 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
992 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
)
1001 * Find a specific PCI IRQ entry.
1002 * Not an __init, possibly needed by modules
1004 static int pin_2_irq(int idx
, int apic
, int pin
);
1006 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
1008 int apic
, i
, best_guess
= -1;
1010 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1012 if (test_bit(bus
, mp_bus_not_pci
)) {
1013 apic_printk(APIC_VERBOSE
, "PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
1016 for (i
= 0; i
< mp_irq_entries
; i
++) {
1017 int lbus
= mp_irqs
[i
].mp_srcbus
;
1019 for (apic
= 0; apic
< nr_ioapics
; apic
++)
1020 if (mp_ioapics
[apic
].mp_apicid
== mp_irqs
[i
].mp_dstapic
||
1021 mp_irqs
[i
].mp_dstapic
== MP_APIC_ALL
)
1024 if (!test_bit(lbus
, mp_bus_not_pci
) &&
1025 !mp_irqs
[i
].mp_irqtype
&&
1027 (slot
== ((mp_irqs
[i
].mp_srcbusirq
>> 2) & 0x1f))) {
1028 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mp_dstirq
);
1030 if (!(apic
|| IO_APIC_IRQ(irq
)))
1033 if (pin
== (mp_irqs
[i
].mp_srcbusirq
& 3))
1036 * Use the first all-but-pin matching entry as a
1037 * best-guess fuzzy result for broken mptables.
1046 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
1048 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1050 * EISA Edge/Level control register, ELCR
1052 static int EISA_ELCR(unsigned int irq
)
1054 if (irq
< NR_IRQS_LEGACY
) {
1055 unsigned int port
= 0x4d0 + (irq
>> 3);
1056 return (inb(port
) >> (irq
& 7)) & 1;
1058 apic_printk(APIC_VERBOSE
, KERN_INFO
1059 "Broken MPtable reports ISA irq %d\n", irq
);
1065 /* ISA interrupts are always polarity zero edge triggered,
1066 * when listed as conforming in the MP table. */
1068 #define default_ISA_trigger(idx) (0)
1069 #define default_ISA_polarity(idx) (0)
1071 /* EISA interrupts are always polarity zero and can be edge or level
1072 * trigger depending on the ELCR value. If an interrupt is listed as
1073 * EISA conforming in the MP table, that means its trigger type must
1074 * be read in from the ELCR */
1076 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mp_srcbusirq))
1077 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
1079 /* PCI interrupts are always polarity one level triggered,
1080 * when listed as conforming in the MP table. */
1082 #define default_PCI_trigger(idx) (1)
1083 #define default_PCI_polarity(idx) (1)
1085 /* MCA interrupts are always polarity zero level triggered,
1086 * when listed as conforming in the MP table. */
1088 #define default_MCA_trigger(idx) (1)
1089 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
1091 static int MPBIOS_polarity(int idx
)
1093 int bus
= mp_irqs
[idx
].mp_srcbus
;
1097 * Determine IRQ line polarity (high active or low active):
1099 switch (mp_irqs
[idx
].mp_irqflag
& 3)
1101 case 0: /* conforms, ie. bus-type dependent polarity */
1102 if (test_bit(bus
, mp_bus_not_pci
))
1103 polarity
= default_ISA_polarity(idx
);
1105 polarity
= default_PCI_polarity(idx
);
1107 case 1: /* high active */
1112 case 2: /* reserved */
1114 printk(KERN_WARNING
"broken BIOS!!\n");
1118 case 3: /* low active */
1123 default: /* invalid */
1125 printk(KERN_WARNING
"broken BIOS!!\n");
1133 static int MPBIOS_trigger(int idx
)
1135 int bus
= mp_irqs
[idx
].mp_srcbus
;
1139 * Determine IRQ trigger mode (edge or level sensitive):
1141 switch ((mp_irqs
[idx
].mp_irqflag
>>2) & 3)
1143 case 0: /* conforms, ie. bus-type dependent */
1144 if (test_bit(bus
, mp_bus_not_pci
))
1145 trigger
= default_ISA_trigger(idx
);
1147 trigger
= default_PCI_trigger(idx
);
1148 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1149 switch (mp_bus_id_to_type
[bus
]) {
1150 case MP_BUS_ISA
: /* ISA pin */
1152 /* set before the switch */
1155 case MP_BUS_EISA
: /* EISA pin */
1157 trigger
= default_EISA_trigger(idx
);
1160 case MP_BUS_PCI
: /* PCI pin */
1162 /* set before the switch */
1165 case MP_BUS_MCA
: /* MCA pin */
1167 trigger
= default_MCA_trigger(idx
);
1172 printk(KERN_WARNING
"broken BIOS!!\n");
1184 case 2: /* reserved */
1186 printk(KERN_WARNING
"broken BIOS!!\n");
1195 default: /* invalid */
1197 printk(KERN_WARNING
"broken BIOS!!\n");
1205 static inline int irq_polarity(int idx
)
1207 return MPBIOS_polarity(idx
);
1210 static inline int irq_trigger(int idx
)
1212 return MPBIOS_trigger(idx
);
1215 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
1216 static int pin_2_irq(int idx
, int apic
, int pin
)
1219 int bus
= mp_irqs
[idx
].mp_srcbus
;
1222 * Debugging check, we are in big trouble if this message pops up!
1224 if (mp_irqs
[idx
].mp_dstirq
!= pin
)
1225 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1227 if (test_bit(bus
, mp_bus_not_pci
)) {
1228 irq
= mp_irqs
[idx
].mp_srcbusirq
;
1231 * PCI IRQs are mapped in order
1235 irq
+= nr_ioapic_registers
[i
++];
1238 * For MPS mode, so far only needed by ES7000 platform
1240 if (ioapic_renumber_irq
)
1241 irq
= ioapic_renumber_irq(apic
, irq
);
1244 #ifdef CONFIG_X86_32
1246 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1248 if ((pin
>= 16) && (pin
<= 23)) {
1249 if (pirq_entries
[pin
-16] != -1) {
1250 if (!pirq_entries
[pin
-16]) {
1251 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1252 "disabling PIRQ%d\n", pin
-16);
1254 irq
= pirq_entries
[pin
-16];
1255 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1256 "using PIRQ%d -> IRQ %d\n",
1266 void lock_vector_lock(void)
1268 /* Used to the online set of cpus does not change
1269 * during assign_irq_vector.
1271 spin_lock(&vector_lock
);
1274 void unlock_vector_lock(void)
1276 spin_unlock(&vector_lock
);
1280 __assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1283 * NOTE! The local APIC isn't very good at handling
1284 * multiple interrupts at the same interrupt level.
1285 * As the interrupt level is determined by taking the
1286 * vector number and shifting that right by 4, we
1287 * want to spread these out a bit so that they don't
1288 * all fall in the same interrupt level.
1290 * Also, we've got to be careful not to trash gate
1291 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1293 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1294 unsigned int old_vector
;
1296 cpumask_var_t tmp_mask
;
1298 if ((cfg
->move_in_progress
) || cfg
->move_cleanup_count
)
1301 if (!alloc_cpumask_var(&tmp_mask
, GFP_ATOMIC
))
1304 old_vector
= cfg
->vector
;
1306 cpumask_and(tmp_mask
, mask
, cpu_online_mask
);
1307 cpumask_and(tmp_mask
, cfg
->domain
, tmp_mask
);
1308 if (!cpumask_empty(tmp_mask
)) {
1309 free_cpumask_var(tmp_mask
);
1314 /* Only try and allocate irqs on cpus that are present */
1316 for_each_cpu_and(cpu
, mask
, cpu_online_mask
) {
1320 vector_allocation_domain(cpu
, tmp_mask
);
1322 vector
= current_vector
;
1323 offset
= current_offset
;
1326 if (vector
>= first_system_vector
) {
1327 /* If out of vectors on large boxen, must share them. */
1328 offset
= (offset
+ 1) % 8;
1329 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1331 if (unlikely(current_vector
== vector
))
1334 if (test_bit(vector
, used_vectors
))
1337 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1338 if (per_cpu(vector_irq
, new_cpu
)[vector
] != -1)
1341 current_vector
= vector
;
1342 current_offset
= offset
;
1344 cfg
->move_in_progress
= 1;
1345 cpumask_copy(cfg
->old_domain
, cfg
->domain
);
1347 for_each_cpu_and(new_cpu
, tmp_mask
, cpu_online_mask
)
1348 per_cpu(vector_irq
, new_cpu
)[vector
] = irq
;
1349 cfg
->vector
= vector
;
1350 cpumask_copy(cfg
->domain
, tmp_mask
);
1354 free_cpumask_var(tmp_mask
);
1359 assign_irq_vector(int irq
, struct irq_cfg
*cfg
, const struct cpumask
*mask
)
1362 unsigned long flags
;
1364 spin_lock_irqsave(&vector_lock
, flags
);
1365 err
= __assign_irq_vector(irq
, cfg
, mask
);
1366 spin_unlock_irqrestore(&vector_lock
, flags
);
1370 static void __clear_irq_vector(int irq
, struct irq_cfg
*cfg
)
1374 BUG_ON(!cfg
->vector
);
1376 vector
= cfg
->vector
;
1377 for_each_cpu_and(cpu
, cfg
->domain
, cpu_online_mask
)
1378 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1381 cpumask_clear(cfg
->domain
);
1383 if (likely(!cfg
->move_in_progress
))
1385 for_each_cpu_and(cpu
, cfg
->old_domain
, cpu_online_mask
) {
1386 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
;
1388 if (per_cpu(vector_irq
, cpu
)[vector
] != irq
)
1390 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1394 cfg
->move_in_progress
= 0;
1397 void __setup_vector_irq(int cpu
)
1399 /* Initialize vector_irq on a new cpu */
1400 /* This function must be called with vector_lock held */
1402 struct irq_cfg
*cfg
;
1403 struct irq_desc
*desc
;
1405 /* Mark the inuse vectors */
1406 for_each_irq_desc(irq
, desc
) {
1407 cfg
= desc
->chip_data
;
1408 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1410 vector
= cfg
->vector
;
1411 per_cpu(vector_irq
, cpu
)[vector
] = irq
;
1413 /* Mark the free vectors */
1414 for (vector
= 0; vector
< NR_VECTORS
; ++vector
) {
1415 irq
= per_cpu(vector_irq
, cpu
)[vector
];
1420 if (!cpumask_test_cpu(cpu
, cfg
->domain
))
1421 per_cpu(vector_irq
, cpu
)[vector
] = -1;
1425 static struct irq_chip ioapic_chip
;
1426 #ifdef CONFIG_INTR_REMAP
1427 static struct irq_chip ir_ioapic_chip
;
1430 #define IOAPIC_AUTO -1
1431 #define IOAPIC_EDGE 0
1432 #define IOAPIC_LEVEL 1
1434 #ifdef CONFIG_X86_32
1435 static inline int IO_APIC_irq_trigger(int irq
)
1439 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1440 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1441 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1442 if ((idx
!= -1) && (irq
== pin_2_irq(idx
, apic
, pin
)))
1443 return irq_trigger(idx
);
1447 * nonexistent IRQs are edge default
1452 static inline int IO_APIC_irq_trigger(int irq
)
1458 static void ioapic_register_intr(int irq
, struct irq_desc
*desc
, unsigned long trigger
)
1461 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1462 trigger
== IOAPIC_LEVEL
)
1463 desc
->status
|= IRQ_LEVEL
;
1465 desc
->status
&= ~IRQ_LEVEL
;
1467 #ifdef CONFIG_INTR_REMAP
1468 if (irq_remapped(irq
)) {
1469 desc
->status
|= IRQ_MOVE_PCNTXT
;
1471 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1475 set_irq_chip_and_handler_name(irq
, &ir_ioapic_chip
,
1476 handle_edge_irq
, "edge");
1480 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1481 trigger
== IOAPIC_LEVEL
)
1482 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1486 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1487 handle_edge_irq
, "edge");
1490 static int setup_ioapic_entry(int apic
, int irq
,
1491 struct IO_APIC_route_entry
*entry
,
1492 unsigned int destination
, int trigger
,
1493 int polarity
, int vector
)
1496 * add it to the IO-APIC irq-routing table:
1498 memset(entry
,0,sizeof(*entry
));
1500 #ifdef CONFIG_INTR_REMAP
1501 if (intr_remapping_enabled
) {
1502 struct intel_iommu
*iommu
= map_ioapic_to_ir(apic
);
1504 struct IR_IO_APIC_route_entry
*ir_entry
=
1505 (struct IR_IO_APIC_route_entry
*) entry
;
1509 panic("No mapping iommu for ioapic %d\n", apic
);
1511 index
= alloc_irte(iommu
, irq
, 1);
1513 panic("Failed to allocate IRTE for ioapic %d\n", apic
);
1515 memset(&irte
, 0, sizeof(irte
));
1518 irte
.dst_mode
= INT_DEST_MODE
;
1519 irte
.trigger_mode
= trigger
;
1520 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
1521 irte
.vector
= vector
;
1522 irte
.dest_id
= IRTE_DEST(destination
);
1524 modify_irte(irq
, &irte
);
1526 ir_entry
->index2
= (index
>> 15) & 0x1;
1528 ir_entry
->format
= 1;
1529 ir_entry
->index
= (index
& 0x7fff);
1533 entry
->delivery_mode
= INT_DELIVERY_MODE
;
1534 entry
->dest_mode
= INT_DEST_MODE
;
1535 entry
->dest
= destination
;
1538 entry
->mask
= 0; /* enable IRQ */
1539 entry
->trigger
= trigger
;
1540 entry
->polarity
= polarity
;
1541 entry
->vector
= vector
;
1543 /* Mask level triggered irqs.
1544 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1551 static void setup_IO_APIC_irq(int apic
, int pin
, unsigned int irq
, struct irq_desc
*desc
,
1552 int trigger
, int polarity
)
1554 struct irq_cfg
*cfg
;
1555 struct IO_APIC_route_entry entry
;
1558 if (!IO_APIC_IRQ(irq
))
1561 cfg
= desc
->chip_data
;
1563 if (assign_irq_vector(irq
, cfg
, TARGET_CPUS
))
1566 dest
= cpu_mask_to_apicid_and(cfg
->domain
, TARGET_CPUS
);
1568 apic_printk(APIC_VERBOSE
,KERN_DEBUG
1569 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1570 "IRQ %d Mode:%i Active:%i)\n",
1571 apic
, mp_ioapics
[apic
].mp_apicid
, pin
, cfg
->vector
,
1572 irq
, trigger
, polarity
);
1575 if (setup_ioapic_entry(mp_ioapics
[apic
].mp_apicid
, irq
, &entry
,
1576 dest
, trigger
, polarity
, cfg
->vector
)) {
1577 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1578 mp_ioapics
[apic
].mp_apicid
, pin
);
1579 __clear_irq_vector(irq
, cfg
);
1583 ioapic_register_intr(irq
, desc
, trigger
);
1584 if (irq
< NR_IRQS_LEGACY
)
1585 disable_8259A_irq(irq
);
1587 ioapic_write_entry(apic
, pin
, entry
);
1590 static void __init
setup_IO_APIC_irqs(void)
1592 int apic
, pin
, idx
, irq
;
1594 struct irq_desc
*desc
;
1595 struct irq_cfg
*cfg
;
1596 int cpu
= boot_cpu_id
;
1598 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1600 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1601 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1603 idx
= find_irq_entry(apic
, pin
, mp_INT
);
1607 apic_printk(APIC_VERBOSE
,
1608 KERN_DEBUG
" %d-%d",
1609 mp_ioapics
[apic
].mp_apicid
,
1612 apic_printk(APIC_VERBOSE
, " %d-%d",
1613 mp_ioapics
[apic
].mp_apicid
,
1618 apic_printk(APIC_VERBOSE
,
1619 " (apicid-pin) not connected\n");
1623 irq
= pin_2_irq(idx
, apic
, pin
);
1624 #ifdef CONFIG_X86_32
1625 if (multi_timer_check(apic
, irq
))
1628 desc
= irq_to_desc_alloc_cpu(irq
, cpu
);
1630 printk(KERN_INFO
"can not get irq_desc for %d\n", irq
);
1633 cfg
= desc
->chip_data
;
1634 add_pin_to_irq_cpu(cfg
, cpu
, apic
, pin
);
1636 setup_IO_APIC_irq(apic
, pin
, irq
, desc
,
1637 irq_trigger(idx
), irq_polarity(idx
));
1642 apic_printk(APIC_VERBOSE
,
1643 " (apicid-pin) not connected\n");
1647 * Set up the timer pin, possibly with the 8259A-master behind.
1649 static void __init
setup_timer_IRQ0_pin(unsigned int apic
, unsigned int pin
,
1652 struct IO_APIC_route_entry entry
;
1654 #ifdef CONFIG_INTR_REMAP
1655 if (intr_remapping_enabled
)
1659 memset(&entry
, 0, sizeof(entry
));
1662 * We use logical delivery to get the timer IRQ
1665 entry
.dest_mode
= INT_DEST_MODE
;
1666 entry
.mask
= 1; /* mask IRQ now */
1667 entry
.dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1668 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1671 entry
.vector
= vector
;
1674 * The timer IRQ doesn't have to know that behind the
1675 * scene we may have a 8259A-master in AEOI mode ...
1677 set_irq_chip_and_handler_name(0, &ioapic_chip
, handle_edge_irq
, "edge");
1680 * Add it to the IO-APIC irq-routing table:
1682 ioapic_write_entry(apic
, pin
, entry
);
1686 __apicdebuginit(void) print_IO_APIC(void)
1689 union IO_APIC_reg_00 reg_00
;
1690 union IO_APIC_reg_01 reg_01
;
1691 union IO_APIC_reg_02 reg_02
;
1692 union IO_APIC_reg_03 reg_03
;
1693 unsigned long flags
;
1694 struct irq_cfg
*cfg
;
1695 struct irq_desc
*desc
;
1698 if (apic_verbosity
== APIC_QUIET
)
1701 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1702 for (i
= 0; i
< nr_ioapics
; i
++)
1703 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1704 mp_ioapics
[i
].mp_apicid
, nr_ioapic_registers
[i
]);
1707 * We are a bit conservative about what we expect. We have to
1708 * know about every hardware change ASAP.
1710 printk(KERN_INFO
"testing the IO APIC.......................\n");
1712 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1714 spin_lock_irqsave(&ioapic_lock
, flags
);
1715 reg_00
.raw
= io_apic_read(apic
, 0);
1716 reg_01
.raw
= io_apic_read(apic
, 1);
1717 if (reg_01
.bits
.version
>= 0x10)
1718 reg_02
.raw
= io_apic_read(apic
, 2);
1719 if (reg_01
.bits
.version
>= 0x20)
1720 reg_03
.raw
= io_apic_read(apic
, 3);
1721 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1724 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mp_apicid
);
1725 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1726 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1727 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1728 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1730 printk(KERN_DEBUG
".... register #01: %08X\n", *(int *)®_01
);
1731 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1733 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1734 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1737 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1738 * but the value of reg_02 is read as the previous read register
1739 * value, so ignore it if reg_02 == reg_01.
1741 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1742 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1743 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1747 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1748 * or reg_03, but the value of reg_0[23] is read as the previous read
1749 * register value, so ignore it if reg_03 == reg_0[12].
1751 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1752 reg_03
.raw
!= reg_01
.raw
) {
1753 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1754 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1757 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1759 printk(KERN_DEBUG
" NR Dst Mask Trig IRR Pol"
1760 " Stat Dmod Deli Vect: \n");
1762 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1763 struct IO_APIC_route_entry entry
;
1765 entry
= ioapic_read_entry(apic
, i
);
1767 printk(KERN_DEBUG
" %02x %03X ",
1772 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1777 entry
.delivery_status
,
1779 entry
.delivery_mode
,
1784 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1785 for_each_irq_desc(irq
, desc
) {
1786 struct irq_pin_list
*entry
;
1788 cfg
= desc
->chip_data
;
1789 entry
= cfg
->irq_2_pin
;
1792 printk(KERN_DEBUG
"IRQ%d ", irq
);
1794 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1797 entry
= entry
->next
;
1802 printk(KERN_INFO
".................................... done.\n");
1807 __apicdebuginit(void) print_APIC_bitfield(int base
)
1812 if (apic_verbosity
== APIC_QUIET
)
1815 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1816 for (i
= 0; i
< 8; i
++) {
1817 v
= apic_read(base
+ i
*0x10);
1818 for (j
= 0; j
< 32; j
++) {
1828 __apicdebuginit(void) print_local_APIC(void *dummy
)
1830 unsigned int v
, ver
, maxlvt
;
1833 if (apic_verbosity
== APIC_QUIET
)
1836 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1837 smp_processor_id(), hard_smp_processor_id());
1838 v
= apic_read(APIC_ID
);
1839 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, read_apic_id());
1840 v
= apic_read(APIC_LVR
);
1841 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1842 ver
= GET_APIC_VERSION(v
);
1843 maxlvt
= lapic_get_maxlvt();
1845 v
= apic_read(APIC_TASKPRI
);
1846 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1848 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1849 if (!APIC_XAPIC(ver
)) {
1850 v
= apic_read(APIC_ARBPRI
);
1851 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1852 v
& APIC_ARBPRI_MASK
);
1854 v
= apic_read(APIC_PROCPRI
);
1855 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1859 * Remote read supported only in the 82489DX and local APIC for
1860 * Pentium processors.
1862 if (!APIC_INTEGRATED(ver
) || maxlvt
== 3) {
1863 v
= apic_read(APIC_RRR
);
1864 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1867 v
= apic_read(APIC_LDR
);
1868 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1869 if (!x2apic_enabled()) {
1870 v
= apic_read(APIC_DFR
);
1871 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1873 v
= apic_read(APIC_SPIV
);
1874 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1876 printk(KERN_DEBUG
"... APIC ISR field:\n");
1877 print_APIC_bitfield(APIC_ISR
);
1878 printk(KERN_DEBUG
"... APIC TMR field:\n");
1879 print_APIC_bitfield(APIC_TMR
);
1880 printk(KERN_DEBUG
"... APIC IRR field:\n");
1881 print_APIC_bitfield(APIC_IRR
);
1883 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1884 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1885 apic_write(APIC_ESR
, 0);
1887 v
= apic_read(APIC_ESR
);
1888 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1891 icr
= apic_icr_read();
1892 printk(KERN_DEBUG
"... APIC ICR: %08x\n", (u32
)icr
);
1893 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", (u32
)(icr
>> 32));
1895 v
= apic_read(APIC_LVTT
);
1896 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1898 if (maxlvt
> 3) { /* PC is LVT#4. */
1899 v
= apic_read(APIC_LVTPC
);
1900 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1902 v
= apic_read(APIC_LVT0
);
1903 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1904 v
= apic_read(APIC_LVT1
);
1905 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1907 if (maxlvt
> 2) { /* ERR is LVT#3. */
1908 v
= apic_read(APIC_LVTERR
);
1909 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1912 v
= apic_read(APIC_TMICT
);
1913 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1914 v
= apic_read(APIC_TMCCT
);
1915 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1916 v
= apic_read(APIC_TDCR
);
1917 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1921 __apicdebuginit(void) print_all_local_APICs(void)
1926 for_each_online_cpu(cpu
)
1927 smp_call_function_single(cpu
, print_local_APIC
, NULL
, 1);
1931 __apicdebuginit(void) print_PIC(void)
1934 unsigned long flags
;
1936 if (apic_verbosity
== APIC_QUIET
)
1939 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1941 spin_lock_irqsave(&i8259A_lock
, flags
);
1943 v
= inb(0xa1) << 8 | inb(0x21);
1944 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1946 v
= inb(0xa0) << 8 | inb(0x20);
1947 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1951 v
= inb(0xa0) << 8 | inb(0x20);
1955 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1957 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1959 v
= inb(0x4d1) << 8 | inb(0x4d0);
1960 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1963 __apicdebuginit(int) print_all_ICs(void)
1966 print_all_local_APICs();
1972 fs_initcall(print_all_ICs
);
1975 /* Where if anywhere is the i8259 connect in external int mode */
1976 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
1978 void __init
enable_IO_APIC(void)
1980 union IO_APIC_reg_01 reg_01
;
1981 int i8259_apic
, i8259_pin
;
1983 unsigned long flags
;
1985 #ifdef CONFIG_X86_32
1988 for (i
= 0; i
< MAX_PIRQS
; i
++)
1989 pirq_entries
[i
] = -1;
1993 * The number of IO-APIC IRQ registers (== #pins):
1995 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1996 spin_lock_irqsave(&ioapic_lock
, flags
);
1997 reg_01
.raw
= io_apic_read(apic
, 1);
1998 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1999 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
2001 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
2003 /* See if any of the pins is in ExtINT mode */
2004 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
2005 struct IO_APIC_route_entry entry
;
2006 entry
= ioapic_read_entry(apic
, pin
);
2008 /* If the interrupt line is enabled and in ExtInt mode
2009 * I have found the pin where the i8259 is connected.
2011 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
2012 ioapic_i8259
.apic
= apic
;
2013 ioapic_i8259
.pin
= pin
;
2019 /* Look to see what if the MP table has reported the ExtINT */
2020 /* If we could not find the appropriate pin by looking at the ioapic
2021 * the i8259 probably is not connected the ioapic but give the
2022 * mptable a chance anyway.
2024 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
2025 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
2026 /* Trust the MP table if nothing is setup in the hardware */
2027 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
2028 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
2029 ioapic_i8259
.pin
= i8259_pin
;
2030 ioapic_i8259
.apic
= i8259_apic
;
2032 /* Complain if the MP table and the hardware disagree */
2033 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
2034 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
2036 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
2040 * Do not trust the IO-APIC being empty at bootup
2046 * Not an __init, needed by the reboot code
2048 void disable_IO_APIC(void)
2051 * Clear the IO-APIC before rebooting:
2056 * If the i8259 is routed through an IOAPIC
2057 * Put that IOAPIC in virtual wire mode
2058 * so legacy interrupts can be delivered.
2060 if (ioapic_i8259
.pin
!= -1) {
2061 struct IO_APIC_route_entry entry
;
2063 memset(&entry
, 0, sizeof(entry
));
2064 entry
.mask
= 0; /* Enabled */
2065 entry
.trigger
= 0; /* Edge */
2067 entry
.polarity
= 0; /* High */
2068 entry
.delivery_status
= 0;
2069 entry
.dest_mode
= 0; /* Physical */
2070 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
2072 entry
.dest
= read_apic_id();
2075 * Add it to the IO-APIC irq-routing table:
2077 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
2080 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
2083 #ifdef CONFIG_X86_32
2085 * function to set the IO-APIC physical IDs based on the
2086 * values stored in the MPC table.
2088 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2091 static void __init
setup_ioapic_ids_from_mpc(void)
2093 union IO_APIC_reg_00 reg_00
;
2094 physid_mask_t phys_id_present_map
;
2097 unsigned char old_id
;
2098 unsigned long flags
;
2100 if (x86_quirks
->setup_ioapic_ids
&& x86_quirks
->setup_ioapic_ids())
2104 * Don't check I/O APIC IDs for xAPIC systems. They have
2105 * no meaning without the serial APIC bus.
2107 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
2108 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
2111 * This is broken; anything with a real cpu count has to
2112 * circumvent this idiocy regardless.
2114 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2117 * Set the IOAPIC ID to the value stored in the MPC table.
2119 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
2121 /* Read the register 0 value */
2122 spin_lock_irqsave(&ioapic_lock
, flags
);
2123 reg_00
.raw
= io_apic_read(apic
, 0);
2124 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2126 old_id
= mp_ioapics
[apic
].mp_apicid
;
2128 if (mp_ioapics
[apic
].mp_apicid
>= get_physical_broadcast()) {
2129 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2130 apic
, mp_ioapics
[apic
].mp_apicid
);
2131 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2133 mp_ioapics
[apic
].mp_apicid
= reg_00
.bits
.ID
;
2137 * Sanity check, is the ID really free? Every APIC in a
2138 * system must have a unique ID or we get lots of nice
2139 * 'stuck on smp_invalidate_needed IPI wait' messages.
2141 if (check_apicid_used(phys_id_present_map
,
2142 mp_ioapics
[apic
].mp_apicid
)) {
2143 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2144 apic
, mp_ioapics
[apic
].mp_apicid
);
2145 for (i
= 0; i
< get_physical_broadcast(); i
++)
2146 if (!physid_isset(i
, phys_id_present_map
))
2148 if (i
>= get_physical_broadcast())
2149 panic("Max APIC ID exceeded!\n");
2150 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
2152 physid_set(i
, phys_id_present_map
);
2153 mp_ioapics
[apic
].mp_apicid
= i
;
2156 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mp_apicid
);
2157 apic_printk(APIC_VERBOSE
, "Setting %d in the "
2158 "phys_id_present_map\n",
2159 mp_ioapics
[apic
].mp_apicid
);
2160 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
2165 * We need to adjust the IRQ routing table
2166 * if the ID changed.
2168 if (old_id
!= mp_ioapics
[apic
].mp_apicid
)
2169 for (i
= 0; i
< mp_irq_entries
; i
++)
2170 if (mp_irqs
[i
].mp_dstapic
== old_id
)
2171 mp_irqs
[i
].mp_dstapic
2172 = mp_ioapics
[apic
].mp_apicid
;
2175 * Read the right value from the MPC table and
2176 * write it into the ID register.
2178 apic_printk(APIC_VERBOSE
, KERN_INFO
2179 "...changing IO-APIC physical APIC ID to %d ...",
2180 mp_ioapics
[apic
].mp_apicid
);
2182 reg_00
.bits
.ID
= mp_ioapics
[apic
].mp_apicid
;
2183 spin_lock_irqsave(&ioapic_lock
, flags
);
2184 io_apic_write(apic
, 0, reg_00
.raw
);
2185 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2190 spin_lock_irqsave(&ioapic_lock
, flags
);
2191 reg_00
.raw
= io_apic_read(apic
, 0);
2192 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2193 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mp_apicid
)
2194 printk("could not set ID!\n");
2196 apic_printk(APIC_VERBOSE
, " ok.\n");
2201 int no_timer_check __initdata
;
2203 static int __init
notimercheck(char *s
)
2208 __setup("no_timer_check", notimercheck
);
2211 * There is a nasty bug in some older SMP boards, their mptable lies
2212 * about the timer IRQ. We do the following to work around the situation:
2214 * - timer IRQ defaults to IO-APIC IRQ
2215 * - if this function detects that timer IRQs are defunct, then we fall
2216 * back to ISA timer IRQs
2218 static int __init
timer_irq_works(void)
2220 unsigned long t1
= jiffies
;
2221 unsigned long flags
;
2226 local_save_flags(flags
);
2228 /* Let ten ticks pass... */
2229 mdelay((10 * 1000) / HZ
);
2230 local_irq_restore(flags
);
2233 * Expect a few ticks at least, to be sure some possible
2234 * glue logic does not lock up after one or two first
2235 * ticks in a non-ExtINT mode. Also the local APIC
2236 * might have cached one ExtINT interrupt. Finally, at
2237 * least one tick may be lost due to delays.
2241 if (time_after(jiffies
, t1
+ 4))
2247 * In the SMP+IOAPIC case it might happen that there are an unspecified
2248 * number of pending IRQ events unhandled. These cases are very rare,
2249 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2250 * better to do it this way as thus we do not have to be aware of
2251 * 'pending' interrupts in the IRQ path, except at this point.
2254 * Edge triggered needs to resend any interrupt
2255 * that was delayed but this is now handled in the device
2260 * Starting up a edge-triggered IO-APIC interrupt is
2261 * nasty - we need to make sure that we get the edge.
2262 * If it is already asserted for some reason, we need
2263 * return 1 to indicate that is was pending.
2265 * This is not complete - we should be able to fake
2266 * an edge even if it isn't on the 8259A...
2269 static unsigned int startup_ioapic_irq(unsigned int irq
)
2271 int was_pending
= 0;
2272 unsigned long flags
;
2273 struct irq_cfg
*cfg
;
2275 spin_lock_irqsave(&ioapic_lock
, flags
);
2276 if (irq
< NR_IRQS_LEGACY
) {
2277 disable_8259A_irq(irq
);
2278 if (i8259A_irq_pending(irq
))
2282 __unmask_IO_APIC_irq(cfg
);
2283 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2288 #ifdef CONFIG_X86_64
2289 static int ioapic_retrigger_irq(unsigned int irq
)
2292 struct irq_cfg
*cfg
= irq_cfg(irq
);
2293 unsigned long flags
;
2295 spin_lock_irqsave(&vector_lock
, flags
);
2296 send_IPI_mask(cpumask_of(cpumask_first(cfg
->domain
)), cfg
->vector
);
2297 spin_unlock_irqrestore(&vector_lock
, flags
);
2302 static int ioapic_retrigger_irq(unsigned int irq
)
2304 send_IPI_self(irq_cfg(irq
)->vector
);
2311 * Level and edge triggered IO-APIC interrupts need different handling,
2312 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2313 * handled with the level-triggered descriptor, but that one has slightly
2314 * more overhead. Level-triggered interrupts cannot be handled with the
2315 * edge-triggered handler, without risking IRQ storms and other ugly
2321 #ifdef CONFIG_INTR_REMAP
2322 static void ir_irq_migration(struct work_struct
*work
);
2324 static DECLARE_DELAYED_WORK(ir_migration_work
, ir_irq_migration
);
2327 * Migrate the IO-APIC irq in the presence of intr-remapping.
2329 * For edge triggered, irq migration is a simple atomic update(of vector
2330 * and cpu destination) of IRTE and flush the hardware cache.
2332 * For level triggered, we need to modify the io-apic RTE aswell with the update
2333 * vector information, along with modifying IRTE with vector and destination.
2334 * So irq migration for level triggered is little bit more complex compared to
2335 * edge triggered migration. But the good news is, we use the same algorithm
2336 * for level triggered migration as we have today, only difference being,
2337 * we now initiate the irq migration from process context instead of the
2338 * interrupt context.
2340 * In future, when we do a directed EOI (combined with cpu EOI broadcast
2341 * suppression) to the IO-APIC, level triggered irq migration will also be
2342 * as simple as edge triggered migration and we can do the irq migration
2343 * with a simple atomic update to IO-APIC RTE.
2346 migrate_ioapic_irq_desc(struct irq_desc
*desc
, const struct cpumask
*mask
)
2348 struct irq_cfg
*cfg
;
2350 int modify_ioapic_rte
;
2352 unsigned long flags
;
2355 if (!cpumask_intersects(mask
, cpu_online_mask
))
2359 if (get_irte(irq
, &irte
))
2362 cfg
= desc
->chip_data
;
2363 if (assign_irq_vector(irq
, cfg
, mask
))
2366 set_extra_move_desc(desc
, mask
);
2368 dest
= cpu_mask_to_apicid_and(cfg
->domain
, mask
);
2370 modify_ioapic_rte
= desc
->status
& IRQ_LEVEL
;
2371 if (modify_ioapic_rte
) {
2372 spin_lock_irqsave(&ioapic_lock
, flags
);
2373 __target_IO_APIC_irq(irq
, dest
, cfg
);
2374 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2377 irte
.vector
= cfg
->vector
;
2378 irte
.dest_id
= IRTE_DEST(dest
);
2381 * Modified the IRTE and flushes the Interrupt entry cache.
2383 modify_irte(irq
, &irte
);
2385 if (cfg
->move_in_progress
)
2386 send_cleanup_vector(cfg
);
2388 cpumask_copy(&desc
->affinity
, mask
);
2391 static int migrate_irq_remapped_level_desc(struct irq_desc
*desc
)
2394 struct irq_cfg
*cfg
= desc
->chip_data
;
2396 mask_IO_APIC_irq_desc(desc
);
2398 if (io_apic_level_ack_pending(cfg
)) {
2400 * Interrupt in progress. Migrating irq now will change the
2401 * vector information in the IO-APIC RTE and that will confuse
2402 * the EOI broadcast performed by cpu.
2403 * So, delay the irq migration to the next instance.
2405 schedule_delayed_work(&ir_migration_work
, 1);
2409 /* everthing is clear. we have right of way */
2410 migrate_ioapic_irq_desc(desc
, &desc
->pending_mask
);
2413 desc
->status
&= ~IRQ_MOVE_PENDING
;
2414 cpumask_clear(&desc
->pending_mask
);
2417 unmask_IO_APIC_irq_desc(desc
);
2422 static void ir_irq_migration(struct work_struct
*work
)
2425 struct irq_desc
*desc
;
2427 for_each_irq_desc(irq
, desc
) {
2428 if (desc
->status
& IRQ_MOVE_PENDING
) {
2429 unsigned long flags
;
2431 spin_lock_irqsave(&desc
->lock
, flags
);
2432 if (!desc
->chip
->set_affinity
||
2433 !(desc
->status
& IRQ_MOVE_PENDING
)) {
2434 desc
->status
&= ~IRQ_MOVE_PENDING
;
2435 spin_unlock_irqrestore(&desc
->lock
, flags
);
2439 desc
->chip
->set_affinity(irq
, &desc
->pending_mask
);
2440 spin_unlock_irqrestore(&desc
->lock
, flags
);
2446 * Migrates the IRQ destination in the process context.
2448 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc
*desc
,
2449 const struct cpumask
*mask
)
2451 if (desc
->status
& IRQ_LEVEL
) {
2452 desc
->status
|= IRQ_MOVE_PENDING
;
2453 cpumask_copy(&desc
->pending_mask
, mask
);
2454 migrate_irq_remapped_level_desc(desc
);
2458 migrate_ioapic_irq_desc(desc
, mask
);
2460 static void set_ir_ioapic_affinity_irq(unsigned int irq
,
2461 const struct cpumask
*mask
)
2463 struct irq_desc
*desc
= irq_to_desc(irq
);
2465 set_ir_ioapic_affinity_irq_desc(desc
, mask
);
2469 asmlinkage
void smp_irq_move_cleanup_interrupt(void)
2471 unsigned vector
, me
;
2477 me
= smp_processor_id();
2478 for (vector
= FIRST_EXTERNAL_VECTOR
; vector
< NR_VECTORS
; vector
++) {
2480 struct irq_desc
*desc
;
2481 struct irq_cfg
*cfg
;
2482 irq
= __get_cpu_var(vector_irq
)[vector
];
2487 desc
= irq_to_desc(irq
);
2492 spin_lock(&desc
->lock
);
2493 if (!cfg
->move_cleanup_count
)
2496 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2499 __get_cpu_var(vector_irq
)[vector
] = -1;
2500 cfg
->move_cleanup_count
--;
2502 spin_unlock(&desc
->lock
);
2508 static void irq_complete_move(struct irq_desc
**descp
)
2510 struct irq_desc
*desc
= *descp
;
2511 struct irq_cfg
*cfg
= desc
->chip_data
;
2512 unsigned vector
, me
;
2514 if (likely(!cfg
->move_in_progress
)) {
2515 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2516 if (likely(!cfg
->move_desc_pending
))
2519 /* domain has not changed, but affinity did */
2520 me
= smp_processor_id();
2521 if (cpu_isset(me
, desc
->affinity
)) {
2522 *descp
= desc
= move_irq_desc(desc
, me
);
2523 /* get the new one */
2524 cfg
= desc
->chip_data
;
2525 cfg
->move_desc_pending
= 0;
2531 vector
= ~get_irq_regs()->orig_ax
;
2532 me
= smp_processor_id();
2533 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2534 *descp
= desc
= move_irq_desc(desc
, me
);
2535 /* get the new one */
2536 cfg
= desc
->chip_data
;
2539 if (vector
== cfg
->vector
&& cpumask_test_cpu(me
, cfg
->domain
))
2540 send_cleanup_vector(cfg
);
2543 static inline void irq_complete_move(struct irq_desc
**descp
) {}
2546 #ifdef CONFIG_INTR_REMAP
2547 static void ack_x2apic_level(unsigned int irq
)
2552 static void ack_x2apic_edge(unsigned int irq
)
2559 static void ack_apic_edge(unsigned int irq
)
2561 struct irq_desc
*desc
= irq_to_desc(irq
);
2563 irq_complete_move(&desc
);
2564 move_native_irq(irq
);
2568 atomic_t irq_mis_count
;
2570 static void ack_apic_level(unsigned int irq
)
2572 struct irq_desc
*desc
= irq_to_desc(irq
);
2574 #ifdef CONFIG_X86_32
2578 struct irq_cfg
*cfg
;
2579 int do_unmask_irq
= 0;
2581 irq_complete_move(&desc
);
2582 #ifdef CONFIG_GENERIC_PENDING_IRQ
2583 /* If we are moving the irq we need to mask it */
2584 if (unlikely(desc
->status
& IRQ_MOVE_PENDING
)) {
2586 mask_IO_APIC_irq_desc(desc
);
2590 #ifdef CONFIG_X86_32
2592 * It appears there is an erratum which affects at least version 0x11
2593 * of I/O APIC (that's the 82093AA and cores integrated into various
2594 * chipsets). Under certain conditions a level-triggered interrupt is
2595 * erroneously delivered as edge-triggered one but the respective IRR
2596 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2597 * message but it will never arrive and further interrupts are blocked
2598 * from the source. The exact reason is so far unknown, but the
2599 * phenomenon was observed when two consecutive interrupt requests
2600 * from a given source get delivered to the same CPU and the source is
2601 * temporarily disabled in between.
2603 * A workaround is to simulate an EOI message manually. We achieve it
2604 * by setting the trigger mode to edge and then to level when the edge
2605 * trigger mode gets detected in the TMR of a local APIC for a
2606 * level-triggered interrupt. We mask the source for the time of the
2607 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2608 * The idea is from Manfred Spraul. --macro
2610 cfg
= desc
->chip_data
;
2613 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
2617 * We must acknowledge the irq before we move it or the acknowledge will
2618 * not propagate properly.
2622 /* Now we can move and renable the irq */
2623 if (unlikely(do_unmask_irq
)) {
2624 /* Only migrate the irq if the ack has been received.
2626 * On rare occasions the broadcast level triggered ack gets
2627 * delayed going to ioapics, and if we reprogram the
2628 * vector while Remote IRR is still set the irq will never
2631 * To prevent this scenario we read the Remote IRR bit
2632 * of the ioapic. This has two effects.
2633 * - On any sane system the read of the ioapic will
2634 * flush writes (and acks) going to the ioapic from
2636 * - We get to see if the ACK has actually been delivered.
2638 * Based on failed experiments of reprogramming the
2639 * ioapic entry from outside of irq context starting
2640 * with masking the ioapic entry and then polling until
2641 * Remote IRR was clear before reprogramming the
2642 * ioapic I don't trust the Remote IRR bit to be
2643 * completey accurate.
2645 * However there appears to be no other way to plug
2646 * this race, so if the Remote IRR bit is not
2647 * accurate and is causing problems then it is a hardware bug
2648 * and you can go talk to the chipset vendor about it.
2650 cfg
= desc
->chip_data
;
2651 if (!io_apic_level_ack_pending(cfg
))
2652 move_masked_irq(irq
);
2653 unmask_IO_APIC_irq_desc(desc
);
2656 #ifdef CONFIG_X86_32
2657 if (!(v
& (1 << (i
& 0x1f)))) {
2658 atomic_inc(&irq_mis_count
);
2659 spin_lock(&ioapic_lock
);
2660 __mask_and_edge_IO_APIC_irq(cfg
);
2661 __unmask_and_level_IO_APIC_irq(cfg
);
2662 spin_unlock(&ioapic_lock
);
2667 static struct irq_chip ioapic_chip __read_mostly
= {
2669 .startup
= startup_ioapic_irq
,
2670 .mask
= mask_IO_APIC_irq
,
2671 .unmask
= unmask_IO_APIC_irq
,
2672 .ack
= ack_apic_edge
,
2673 .eoi
= ack_apic_level
,
2675 .set_affinity
= set_ioapic_affinity_irq
,
2677 .retrigger
= ioapic_retrigger_irq
,
2680 #ifdef CONFIG_INTR_REMAP
2681 static struct irq_chip ir_ioapic_chip __read_mostly
= {
2682 .name
= "IR-IO-APIC",
2683 .startup
= startup_ioapic_irq
,
2684 .mask
= mask_IO_APIC_irq
,
2685 .unmask
= unmask_IO_APIC_irq
,
2686 .ack
= ack_x2apic_edge
,
2687 .eoi
= ack_x2apic_level
,
2689 .set_affinity
= set_ir_ioapic_affinity_irq
,
2691 .retrigger
= ioapic_retrigger_irq
,
2695 static inline void init_IO_APIC_traps(void)
2698 struct irq_desc
*desc
;
2699 struct irq_cfg
*cfg
;
2702 * NOTE! The local APIC isn't very good at handling
2703 * multiple interrupts at the same interrupt level.
2704 * As the interrupt level is determined by taking the
2705 * vector number and shifting that right by 4, we
2706 * want to spread these out a bit so that they don't
2707 * all fall in the same interrupt level.
2709 * Also, we've got to be careful not to trash gate
2710 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2712 for_each_irq_desc(irq
, desc
) {
2713 cfg
= desc
->chip_data
;
2714 if (IO_APIC_IRQ(irq
) && cfg
&& !cfg
->vector
) {
2716 * Hmm.. We don't have an entry for this,
2717 * so default to an old-fashioned 8259
2718 * interrupt if we can..
2720 if (irq
< NR_IRQS_LEGACY
)
2721 make_8259A_irq(irq
);
2723 /* Strange. Oh, well.. */
2724 desc
->chip
= &no_irq_chip
;
2730 * The local APIC irq-chip implementation:
2733 static void mask_lapic_irq(unsigned int irq
)
2737 v
= apic_read(APIC_LVT0
);
2738 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2741 static void unmask_lapic_irq(unsigned int irq
)
2745 v
= apic_read(APIC_LVT0
);
2746 apic_write(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2749 static void ack_lapic_irq(unsigned int irq
)
2754 static struct irq_chip lapic_chip __read_mostly
= {
2755 .name
= "local-APIC",
2756 .mask
= mask_lapic_irq
,
2757 .unmask
= unmask_lapic_irq
,
2758 .ack
= ack_lapic_irq
,
2761 static void lapic_register_intr(int irq
, struct irq_desc
*desc
)
2763 desc
->status
&= ~IRQ_LEVEL
;
2764 set_irq_chip_and_handler_name(irq
, &lapic_chip
, handle_edge_irq
,
2768 static void __init
setup_nmi(void)
2771 * Dirty trick to enable the NMI watchdog ...
2772 * We put the 8259A master into AEOI mode and
2773 * unmask on all local APICs LVT0 as NMI.
2775 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2776 * is from Maciej W. Rozycki - so we do not have to EOI from
2777 * the NMI handler or the timer interrupt.
2779 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2781 enable_NMI_through_LVT0();
2783 apic_printk(APIC_VERBOSE
, " done.\n");
2787 * This looks a bit hackish but it's about the only one way of sending
2788 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2789 * not support the ExtINT mode, unfortunately. We need to send these
2790 * cycles as some i82489DX-based boards have glue logic that keeps the
2791 * 8259A interrupt line asserted until INTA. --macro
2793 static inline void __init
unlock_ExtINT_logic(void)
2796 struct IO_APIC_route_entry entry0
, entry1
;
2797 unsigned char save_control
, save_freq_select
;
2799 pin
= find_isa_irq_pin(8, mp_INT
);
2804 apic
= find_isa_irq_apic(8, mp_INT
);
2810 entry0
= ioapic_read_entry(apic
, pin
);
2811 clear_IO_APIC_pin(apic
, pin
);
2813 memset(&entry1
, 0, sizeof(entry1
));
2815 entry1
.dest_mode
= 0; /* physical delivery */
2816 entry1
.mask
= 0; /* unmask IRQ now */
2817 entry1
.dest
= hard_smp_processor_id();
2818 entry1
.delivery_mode
= dest_ExtINT
;
2819 entry1
.polarity
= entry0
.polarity
;
2823 ioapic_write_entry(apic
, pin
, entry1
);
2825 save_control
= CMOS_READ(RTC_CONTROL
);
2826 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2827 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2829 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2834 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2838 CMOS_WRITE(save_control
, RTC_CONTROL
);
2839 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2840 clear_IO_APIC_pin(apic
, pin
);
2842 ioapic_write_entry(apic
, pin
, entry0
);
2845 static int disable_timer_pin_1 __initdata
;
2846 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2847 static int __init
disable_timer_pin_setup(char *arg
)
2849 disable_timer_pin_1
= 1;
2852 early_param("disable_timer_pin_1", disable_timer_pin_setup
);
2854 int timer_through_8259 __initdata
;
2857 * This code may look a bit paranoid, but it's supposed to cooperate with
2858 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2859 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2860 * fanatically on his truly buggy board.
2862 * FIXME: really need to revamp this for all platforms.
2864 static inline void __init
check_timer(void)
2866 struct irq_desc
*desc
= irq_to_desc(0);
2867 struct irq_cfg
*cfg
= desc
->chip_data
;
2868 int cpu
= boot_cpu_id
;
2869 int apic1
, pin1
, apic2
, pin2
;
2870 unsigned long flags
;
2874 local_irq_save(flags
);
2876 ver
= apic_read(APIC_LVR
);
2877 ver
= GET_APIC_VERSION(ver
);
2880 * get/set the timer IRQ vector:
2882 disable_8259A_irq(0);
2883 assign_irq_vector(0, cfg
, TARGET_CPUS
);
2886 * As IRQ0 is to be enabled in the 8259A, the virtual
2887 * wire has to be disabled in the local APIC. Also
2888 * timer interrupts need to be acknowledged manually in
2889 * the 8259A for the i82489DX when using the NMI
2890 * watchdog as that APIC treats NMIs as level-triggered.
2891 * The AEOI mode will finish them in the 8259A
2894 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2896 #ifdef CONFIG_X86_32
2897 timer_ack
= (nmi_watchdog
== NMI_IO_APIC
&& !APIC_INTEGRATED(ver
));
2900 pin1
= find_isa_irq_pin(0, mp_INT
);
2901 apic1
= find_isa_irq_apic(0, mp_INT
);
2902 pin2
= ioapic_i8259
.pin
;
2903 apic2
= ioapic_i8259
.apic
;
2905 apic_printk(APIC_QUIET
, KERN_INFO
"..TIMER: vector=0x%02X "
2906 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2907 cfg
->vector
, apic1
, pin1
, apic2
, pin2
);
2910 * Some BIOS writers are clueless and report the ExtINTA
2911 * I/O APIC input from the cascaded 8259A as the timer
2912 * interrupt input. So just in case, if only one pin
2913 * was found above, try it both directly and through the
2917 #ifdef CONFIG_INTR_REMAP
2918 if (intr_remapping_enabled
)
2919 panic("BIOS bug: timer not connected to IO-APIC");
2924 } else if (pin2
== -1) {
2931 * Ok, does IRQ0 through the IOAPIC work?
2934 add_pin_to_irq_cpu(cfg
, cpu
, apic1
, pin1
);
2935 setup_timer_IRQ0_pin(apic1
, pin1
, cfg
->vector
);
2937 unmask_IO_APIC_irq_desc(desc
);
2938 if (timer_irq_works()) {
2939 if (nmi_watchdog
== NMI_IO_APIC
) {
2941 enable_8259A_irq(0);
2943 if (disable_timer_pin_1
> 0)
2944 clear_IO_APIC_pin(0, pin1
);
2947 #ifdef CONFIG_INTR_REMAP
2948 if (intr_remapping_enabled
)
2949 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2951 clear_IO_APIC_pin(apic1
, pin1
);
2953 apic_printk(APIC_QUIET
, KERN_ERR
"..MP-BIOS bug: "
2954 "8254 timer not connected to IO-APIC\n");
2956 apic_printk(APIC_QUIET
, KERN_INFO
"...trying to set up timer "
2957 "(IRQ0) through the 8259A ...\n");
2958 apic_printk(APIC_QUIET
, KERN_INFO
2959 "..... (found apic %d pin %d) ...\n", apic2
, pin2
);
2961 * legacy devices should be connected to IO APIC #0
2963 replace_pin_at_irq_cpu(cfg
, cpu
, apic1
, pin1
, apic2
, pin2
);
2964 setup_timer_IRQ0_pin(apic2
, pin2
, cfg
->vector
);
2965 unmask_IO_APIC_irq_desc(desc
);
2966 enable_8259A_irq(0);
2967 if (timer_irq_works()) {
2968 apic_printk(APIC_QUIET
, KERN_INFO
"....... works.\n");
2969 timer_through_8259
= 1;
2970 if (nmi_watchdog
== NMI_IO_APIC
) {
2971 disable_8259A_irq(0);
2973 enable_8259A_irq(0);
2978 * Cleanup, just in case ...
2980 disable_8259A_irq(0);
2981 clear_IO_APIC_pin(apic2
, pin2
);
2982 apic_printk(APIC_QUIET
, KERN_INFO
"....... failed.\n");
2985 if (nmi_watchdog
== NMI_IO_APIC
) {
2986 apic_printk(APIC_QUIET
, KERN_WARNING
"timer doesn't work "
2987 "through the IO-APIC - disabling NMI Watchdog!\n");
2988 nmi_watchdog
= NMI_NONE
;
2990 #ifdef CONFIG_X86_32
2994 apic_printk(APIC_QUIET
, KERN_INFO
2995 "...trying to set up timer as Virtual Wire IRQ...\n");
2997 lapic_register_intr(0, desc
);
2998 apic_write(APIC_LVT0
, APIC_DM_FIXED
| cfg
->vector
); /* Fixed mode */
2999 enable_8259A_irq(0);
3001 if (timer_irq_works()) {
3002 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3005 disable_8259A_irq(0);
3006 apic_write(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| cfg
->vector
);
3007 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed.\n");
3009 apic_printk(APIC_QUIET
, KERN_INFO
3010 "...trying to set up timer as ExtINT IRQ...\n");
3014 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
3016 unlock_ExtINT_logic();
3018 if (timer_irq_works()) {
3019 apic_printk(APIC_QUIET
, KERN_INFO
"..... works.\n");
3022 apic_printk(APIC_QUIET
, KERN_INFO
"..... failed :(.\n");
3023 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
3024 "report. Then try booting with the 'noapic' option.\n");
3026 local_irq_restore(flags
);
3030 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3031 * to devices. However there may be an I/O APIC pin available for
3032 * this interrupt regardless. The pin may be left unconnected, but
3033 * typically it will be reused as an ExtINT cascade interrupt for
3034 * the master 8259A. In the MPS case such a pin will normally be
3035 * reported as an ExtINT interrupt in the MP table. With ACPI
3036 * there is no provision for ExtINT interrupts, and in the absence
3037 * of an override it would be treated as an ordinary ISA I/O APIC
3038 * interrupt, that is edge-triggered and unmasked by default. We
3039 * used to do this, but it caused problems on some systems because
3040 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3041 * the same ExtINT cascade interrupt to drive the local APIC of the
3042 * bootstrap processor. Therefore we refrain from routing IRQ2 to
3043 * the I/O APIC in all cases now. No actual device should request
3044 * it anyway. --macro
3046 #define PIC_IRQS (1 << PIC_CASCADE_IR)
3048 void __init
setup_IO_APIC(void)
3051 #ifdef CONFIG_X86_32
3055 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3059 io_apic_irqs
= ~PIC_IRQS
;
3061 apic_printk(APIC_VERBOSE
, "ENABLING IO-APIC IRQs\n");
3063 * Set up IO-APIC IRQ routing.
3065 #ifdef CONFIG_X86_32
3067 setup_ioapic_ids_from_mpc();
3070 setup_IO_APIC_irqs();
3071 init_IO_APIC_traps();
3076 * Called after all the initialization is done. If we didnt find any
3077 * APIC bugs then we can allow the modify fast path
3080 static int __init
io_apic_bug_finalize(void)
3082 if (sis_apic_bug
== -1)
3087 late_initcall(io_apic_bug_finalize
);
3089 struct sysfs_ioapic_data
{
3090 struct sys_device dev
;
3091 struct IO_APIC_route_entry entry
[0];
3093 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
3095 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
3097 struct IO_APIC_route_entry
*entry
;
3098 struct sysfs_ioapic_data
*data
;
3101 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3102 entry
= data
->entry
;
3103 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++, entry
++ )
3104 *entry
= ioapic_read_entry(dev
->id
, i
);
3109 static int ioapic_resume(struct sys_device
*dev
)
3111 struct IO_APIC_route_entry
*entry
;
3112 struct sysfs_ioapic_data
*data
;
3113 unsigned long flags
;
3114 union IO_APIC_reg_00 reg_00
;
3117 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
3118 entry
= data
->entry
;
3120 spin_lock_irqsave(&ioapic_lock
, flags
);
3121 reg_00
.raw
= io_apic_read(dev
->id
, 0);
3122 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mp_apicid
) {
3123 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mp_apicid
;
3124 io_apic_write(dev
->id
, 0, reg_00
.raw
);
3126 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3127 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
3128 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
3133 static struct sysdev_class ioapic_sysdev_class
= {
3135 .suspend
= ioapic_suspend
,
3136 .resume
= ioapic_resume
,
3139 static int __init
ioapic_init_sysfs(void)
3141 struct sys_device
* dev
;
3144 error
= sysdev_class_register(&ioapic_sysdev_class
);
3148 for (i
= 0; i
< nr_ioapics
; i
++ ) {
3149 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
3150 * sizeof(struct IO_APIC_route_entry
);
3151 mp_ioapic_data
[i
] = kzalloc(size
, GFP_KERNEL
);
3152 if (!mp_ioapic_data
[i
]) {
3153 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3156 dev
= &mp_ioapic_data
[i
]->dev
;
3158 dev
->cls
= &ioapic_sysdev_class
;
3159 error
= sysdev_register(dev
);
3161 kfree(mp_ioapic_data
[i
]);
3162 mp_ioapic_data
[i
] = NULL
;
3163 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
3171 device_initcall(ioapic_init_sysfs
);
3174 * Dynamic irq allocate and deallocation
3176 unsigned int create_irq_nr(unsigned int irq_want
)
3178 /* Allocate an unused irq */
3181 unsigned long flags
;
3182 struct irq_cfg
*cfg_new
= NULL
;
3183 int cpu
= boot_cpu_id
;
3184 struct irq_desc
*desc_new
= NULL
;
3187 spin_lock_irqsave(&vector_lock
, flags
);
3188 for (new = irq_want
; new < NR_IRQS
; new++) {
3189 if (platform_legacy_irq(new))
3192 desc_new
= irq_to_desc_alloc_cpu(new, cpu
);
3194 printk(KERN_INFO
"can not get irq_desc for %d\n", new);
3197 cfg_new
= desc_new
->chip_data
;
3199 if (cfg_new
->vector
!= 0)
3201 if (__assign_irq_vector(new, cfg_new
, TARGET_CPUS
) == 0)
3205 spin_unlock_irqrestore(&vector_lock
, flags
);
3208 dynamic_irq_init(irq
);
3209 /* restore it, in case dynamic_irq_init clear it */
3211 desc_new
->chip_data
= cfg_new
;
3216 static int nr_irqs_gsi
= NR_IRQS_LEGACY
;
3217 int create_irq(void)
3219 unsigned int irq_want
;
3222 irq_want
= nr_irqs_gsi
;
3223 irq
= create_irq_nr(irq_want
);
3231 void destroy_irq(unsigned int irq
)
3233 unsigned long flags
;
3234 struct irq_cfg
*cfg
;
3235 struct irq_desc
*desc
;
3237 /* store it, in case dynamic_irq_cleanup clear it */
3238 desc
= irq_to_desc(irq
);
3239 cfg
= desc
->chip_data
;
3240 dynamic_irq_cleanup(irq
);
3241 /* connect back irq_cfg */
3243 desc
->chip_data
= cfg
;
3245 #ifdef CONFIG_INTR_REMAP
3248 spin_lock_irqsave(&vector_lock
, flags
);
3249 __clear_irq_vector(irq
, cfg
);
3250 spin_unlock_irqrestore(&vector_lock
, flags
);
3254 * MSI message composition
3256 #ifdef CONFIG_PCI_MSI
3257 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
3259 struct irq_cfg
*cfg
;
3264 err
= assign_irq_vector(irq
, cfg
, TARGET_CPUS
);
3268 dest
= cpu_mask_to_apicid_and(cfg
->domain
, TARGET_CPUS
);
3270 #ifdef CONFIG_INTR_REMAP
3271 if (irq_remapped(irq
)) {
3276 ir_index
= map_irq_to_irte_handle(irq
, &sub_handle
);
3277 BUG_ON(ir_index
== -1);
3279 memset (&irte
, 0, sizeof(irte
));
3282 irte
.dst_mode
= INT_DEST_MODE
;
3283 irte
.trigger_mode
= 0; /* edge */
3284 irte
.dlvry_mode
= INT_DELIVERY_MODE
;
3285 irte
.vector
= cfg
->vector
;
3286 irte
.dest_id
= IRTE_DEST(dest
);
3288 modify_irte(irq
, &irte
);
3290 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3291 msg
->data
= sub_handle
;
3292 msg
->address_lo
= MSI_ADDR_BASE_LO
| MSI_ADDR_IR_EXT_INT
|
3294 MSI_ADDR_IR_INDEX1(ir_index
) |
3295 MSI_ADDR_IR_INDEX2(ir_index
);
3299 msg
->address_hi
= MSI_ADDR_BASE_HI
;
3302 ((INT_DEST_MODE
== 0) ?
3303 MSI_ADDR_DEST_MODE_PHYSICAL
:
3304 MSI_ADDR_DEST_MODE_LOGICAL
) |
3305 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3306 MSI_ADDR_REDIRECTION_CPU
:
3307 MSI_ADDR_REDIRECTION_LOWPRI
) |
3308 MSI_ADDR_DEST_ID(dest
);
3311 MSI_DATA_TRIGGER_EDGE
|
3312 MSI_DATA_LEVEL_ASSERT
|
3313 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3314 MSI_DATA_DELIVERY_FIXED
:
3315 MSI_DATA_DELIVERY_LOWPRI
) |
3316 MSI_DATA_VECTOR(cfg
->vector
);
3322 static void set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3324 struct irq_desc
*desc
= irq_to_desc(irq
);
3325 struct irq_cfg
*cfg
;
3329 dest
= set_desc_affinity(desc
, mask
);
3330 if (dest
== BAD_APICID
)
3333 cfg
= desc
->chip_data
;
3335 read_msi_msg_desc(desc
, &msg
);
3337 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3338 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3339 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3340 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3342 write_msi_msg_desc(desc
, &msg
);
3344 #ifdef CONFIG_INTR_REMAP
3346 * Migrate the MSI irq to another cpumask. This migration is
3347 * done in the process context using interrupt-remapping hardware.
3350 ir_set_msi_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3352 struct irq_desc
*desc
= irq_to_desc(irq
);
3353 struct irq_cfg
*cfg
= desc
->chip_data
;
3357 if (get_irte(irq
, &irte
))
3360 dest
= set_desc_affinity(desc
, mask
);
3361 if (dest
== BAD_APICID
)
3364 irte
.vector
= cfg
->vector
;
3365 irte
.dest_id
= IRTE_DEST(dest
);
3368 * atomically update the IRTE with the new destination and vector.
3370 modify_irte(irq
, &irte
);
3373 * After this point, all the interrupts will start arriving
3374 * at the new destination. So, time to cleanup the previous
3375 * vector allocation.
3377 if (cfg
->move_in_progress
)
3378 send_cleanup_vector(cfg
);
3382 #endif /* CONFIG_SMP */
3385 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3386 * which implement the MSI or MSI-X Capability Structure.
3388 static struct irq_chip msi_chip
= {
3390 .unmask
= unmask_msi_irq
,
3391 .mask
= mask_msi_irq
,
3392 .ack
= ack_apic_edge
,
3394 .set_affinity
= set_msi_irq_affinity
,
3396 .retrigger
= ioapic_retrigger_irq
,
3399 #ifdef CONFIG_INTR_REMAP
3400 static struct irq_chip msi_ir_chip
= {
3401 .name
= "IR-PCI-MSI",
3402 .unmask
= unmask_msi_irq
,
3403 .mask
= mask_msi_irq
,
3404 .ack
= ack_x2apic_edge
,
3406 .set_affinity
= ir_set_msi_irq_affinity
,
3408 .retrigger
= ioapic_retrigger_irq
,
3412 * Map the PCI dev to the corresponding remapping hardware unit
3413 * and allocate 'nvec' consecutive interrupt-remapping table entries
3416 static int msi_alloc_irte(struct pci_dev
*dev
, int irq
, int nvec
)
3418 struct intel_iommu
*iommu
;
3421 iommu
= map_dev_to_ir(dev
);
3424 "Unable to map PCI %s to iommu\n", pci_name(dev
));
3428 index
= alloc_irte(iommu
, irq
, nvec
);
3431 "Unable to allocate %d IRTE for PCI %s\n", nvec
,
3439 static int setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
, int irq
)
3444 ret
= msi_compose_msg(dev
, irq
, &msg
);
3448 set_irq_msi(irq
, msidesc
);
3449 write_msi_msg(irq
, &msg
);
3451 #ifdef CONFIG_INTR_REMAP
3452 if (irq_remapped(irq
)) {
3453 struct irq_desc
*desc
= irq_to_desc(irq
);
3455 * irq migration in process context
3457 desc
->status
|= IRQ_MOVE_PCNTXT
;
3458 set_irq_chip_and_handler_name(irq
, &msi_ir_chip
, handle_edge_irq
, "edge");
3461 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
, "edge");
3463 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for MSI/MSI-X\n", irq
);
3468 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*msidesc
)
3472 unsigned int irq_want
;
3474 irq_want
= nr_irqs_gsi
;
3475 irq
= create_irq_nr(irq_want
);
3479 #ifdef CONFIG_INTR_REMAP
3480 if (!intr_remapping_enabled
)
3483 ret
= msi_alloc_irte(dev
, irq
, 1);
3488 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3495 #ifdef CONFIG_INTR_REMAP
3502 int arch_setup_msi_irqs(struct pci_dev
*dev
, int nvec
, int type
)
3505 int ret
, sub_handle
;
3506 struct msi_desc
*msidesc
;
3507 unsigned int irq_want
;
3509 #ifdef CONFIG_INTR_REMAP
3510 struct intel_iommu
*iommu
= 0;
3514 irq_want
= nr_irqs_gsi
;
3516 list_for_each_entry(msidesc
, &dev
->msi_list
, list
) {
3517 irq
= create_irq_nr(irq_want
);
3521 #ifdef CONFIG_INTR_REMAP
3522 if (!intr_remapping_enabled
)
3527 * allocate the consecutive block of IRTE's
3530 index
= msi_alloc_irte(dev
, irq
, nvec
);
3536 iommu
= map_dev_to_ir(dev
);
3542 * setup the mapping between the irq and the IRTE
3543 * base index, the sub_handle pointing to the
3544 * appropriate interrupt remap table entry.
3546 set_irte_irq(irq
, iommu
, index
, sub_handle
);
3550 ret
= setup_msi_irq(dev
, msidesc
, irq
);
3562 void arch_teardown_msi_irq(unsigned int irq
)
3569 static void dmar_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3571 struct irq_desc
*desc
= irq_to_desc(irq
);
3572 struct irq_cfg
*cfg
;
3576 dest
= set_desc_affinity(desc
, mask
);
3577 if (dest
== BAD_APICID
)
3580 cfg
= desc
->chip_data
;
3582 dmar_msi_read(irq
, &msg
);
3584 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3585 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3586 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3587 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3589 dmar_msi_write(irq
, &msg
);
3592 #endif /* CONFIG_SMP */
3594 struct irq_chip dmar_msi_type
= {
3596 .unmask
= dmar_msi_unmask
,
3597 .mask
= dmar_msi_mask
,
3598 .ack
= ack_apic_edge
,
3600 .set_affinity
= dmar_msi_set_affinity
,
3602 .retrigger
= ioapic_retrigger_irq
,
3605 int arch_setup_dmar_msi(unsigned int irq
)
3610 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3613 dmar_msi_write(irq
, &msg
);
3614 set_irq_chip_and_handler_name(irq
, &dmar_msi_type
, handle_edge_irq
,
3620 #ifdef CONFIG_HPET_TIMER
3623 static void hpet_msi_set_affinity(unsigned int irq
, const struct cpumask
*mask
)
3625 struct irq_desc
*desc
= irq_to_desc(irq
);
3626 struct irq_cfg
*cfg
;
3630 dest
= set_desc_affinity(desc
, mask
);
3631 if (dest
== BAD_APICID
)
3634 cfg
= desc
->chip_data
;
3636 hpet_msi_read(irq
, &msg
);
3638 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
3639 msg
.data
|= MSI_DATA_VECTOR(cfg
->vector
);
3640 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
3641 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
3643 hpet_msi_write(irq
, &msg
);
3646 #endif /* CONFIG_SMP */
3648 struct irq_chip hpet_msi_type
= {
3650 .unmask
= hpet_msi_unmask
,
3651 .mask
= hpet_msi_mask
,
3652 .ack
= ack_apic_edge
,
3654 .set_affinity
= hpet_msi_set_affinity
,
3656 .retrigger
= ioapic_retrigger_irq
,
3659 int arch_setup_hpet_msi(unsigned int irq
)
3664 ret
= msi_compose_msg(NULL
, irq
, &msg
);
3668 hpet_msi_write(irq
, &msg
);
3669 set_irq_chip_and_handler_name(irq
, &hpet_msi_type
, handle_edge_irq
,
3676 #endif /* CONFIG_PCI_MSI */
3678 * Hypertransport interrupt support
3680 #ifdef CONFIG_HT_IRQ
3684 static void target_ht_irq(unsigned int irq
, unsigned int dest
, u8 vector
)
3686 struct ht_irq_msg msg
;
3687 fetch_ht_irq_msg(irq
, &msg
);
3689 msg
.address_lo
&= ~(HT_IRQ_LOW_VECTOR_MASK
| HT_IRQ_LOW_DEST_ID_MASK
);
3690 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
3692 msg
.address_lo
|= HT_IRQ_LOW_VECTOR(vector
) | HT_IRQ_LOW_DEST_ID(dest
);
3693 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
3695 write_ht_irq_msg(irq
, &msg
);
3698 static void set_ht_irq_affinity(unsigned int irq
, const struct cpumask
*mask
)
3700 struct irq_desc
*desc
= irq_to_desc(irq
);
3701 struct irq_cfg
*cfg
;
3704 dest
= set_desc_affinity(desc
, mask
);
3705 if (dest
== BAD_APICID
)
3708 cfg
= desc
->chip_data
;
3710 target_ht_irq(irq
, dest
, cfg
->vector
);
3715 static struct irq_chip ht_irq_chip
= {
3717 .mask
= mask_ht_irq
,
3718 .unmask
= unmask_ht_irq
,
3719 .ack
= ack_apic_edge
,
3721 .set_affinity
= set_ht_irq_affinity
,
3723 .retrigger
= ioapic_retrigger_irq
,
3726 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
3728 struct irq_cfg
*cfg
;
3732 err
= assign_irq_vector(irq
, cfg
, TARGET_CPUS
);
3734 struct ht_irq_msg msg
;
3737 dest
= cpu_mask_to_apicid_and(cfg
->domain
, TARGET_CPUS
);
3739 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
3743 HT_IRQ_LOW_DEST_ID(dest
) |
3744 HT_IRQ_LOW_VECTOR(cfg
->vector
) |
3745 ((INT_DEST_MODE
== 0) ?
3746 HT_IRQ_LOW_DM_PHYSICAL
:
3747 HT_IRQ_LOW_DM_LOGICAL
) |
3748 HT_IRQ_LOW_RQEOI_EDGE
|
3749 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
3750 HT_IRQ_LOW_MT_FIXED
:
3751 HT_IRQ_LOW_MT_ARBITRATED
) |
3752 HT_IRQ_LOW_IRQ_MASKED
;
3754 write_ht_irq_msg(irq
, &msg
);
3756 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
3757 handle_edge_irq
, "edge");
3759 dev_printk(KERN_DEBUG
, &dev
->dev
, "irq %d for HT\n", irq
);
3763 #endif /* CONFIG_HT_IRQ */
3765 #ifdef CONFIG_X86_64
3767 * Re-target the irq to the specified CPU and enable the specified MMR located
3768 * on the specified blade to allow the sending of MSIs to the specified CPU.
3770 int arch_enable_uv_irq(char *irq_name
, unsigned int irq
, int cpu
, int mmr_blade
,
3771 unsigned long mmr_offset
)
3773 const struct cpumask
*eligible_cpu
= cpumask_of(cpu
);
3774 struct irq_cfg
*cfg
;
3776 unsigned long mmr_value
;
3777 struct uv_IO_APIC_route_entry
*entry
;
3778 unsigned long flags
;
3783 err
= assign_irq_vector(irq
, cfg
, eligible_cpu
);
3787 spin_lock_irqsave(&vector_lock
, flags
);
3788 set_irq_chip_and_handler_name(irq
, &uv_irq_chip
, handle_percpu_irq
,
3790 spin_unlock_irqrestore(&vector_lock
, flags
);
3793 entry
= (struct uv_IO_APIC_route_entry
*)&mmr_value
;
3794 BUG_ON(sizeof(struct uv_IO_APIC_route_entry
) != sizeof(unsigned long));
3796 entry
->vector
= cfg
->vector
;
3797 entry
->delivery_mode
= INT_DELIVERY_MODE
;
3798 entry
->dest_mode
= INT_DEST_MODE
;
3799 entry
->polarity
= 0;
3802 entry
->dest
= cpu_mask_to_apicid(eligible_cpu
);
3804 mmr_pnode
= uv_blade_to_pnode(mmr_blade
);
3805 uv_write_global_mmr64(mmr_pnode
, mmr_offset
, mmr_value
);
3811 * Disable the specified MMR located on the specified blade so that MSIs are
3812 * longer allowed to be sent.
3814 void arch_disable_uv_irq(int mmr_blade
, unsigned long mmr_offset
)
3816 unsigned long mmr_value
;
3817 struct uv_IO_APIC_route_entry
*entry
;
3821 entry
= (struct uv_IO_APIC_route_entry
*)&mmr_value
;
3822 BUG_ON(sizeof(struct uv_IO_APIC_route_entry
) != sizeof(unsigned long));
3826 mmr_pnode
= uv_blade_to_pnode(mmr_blade
);
3827 uv_write_global_mmr64(mmr_pnode
, mmr_offset
, mmr_value
);
3829 #endif /* CONFIG_X86_64 */
3831 int __init
io_apic_get_redir_entries (int ioapic
)
3833 union IO_APIC_reg_01 reg_01
;
3834 unsigned long flags
;
3836 spin_lock_irqsave(&ioapic_lock
, flags
);
3837 reg_01
.raw
= io_apic_read(ioapic
, 1);
3838 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3840 return reg_01
.bits
.entries
;
3843 void __init
probe_nr_irqs_gsi(void)
3848 for (idx
= 0; idx
< nr_ioapics
; idx
++)
3849 nr
+= io_apic_get_redir_entries(idx
) + 1;
3851 if (nr
> nr_irqs_gsi
)
3855 /* --------------------------------------------------------------------------
3856 ACPI-based IOAPIC Configuration
3857 -------------------------------------------------------------------------- */
3861 #ifdef CONFIG_X86_32
3862 int __init
io_apic_get_unique_id(int ioapic
, int apic_id
)
3864 union IO_APIC_reg_00 reg_00
;
3865 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
3867 unsigned long flags
;
3871 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3872 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3873 * supports up to 16 on one shared APIC bus.
3875 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3876 * advantage of new APIC bus architecture.
3879 if (physids_empty(apic_id_map
))
3880 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
3882 spin_lock_irqsave(&ioapic_lock
, flags
);
3883 reg_00
.raw
= io_apic_read(ioapic
, 0);
3884 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3886 if (apic_id
>= get_physical_broadcast()) {
3887 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
3888 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
3889 apic_id
= reg_00
.bits
.ID
;
3893 * Every APIC in a system must have a unique ID or we get lots of nice
3894 * 'stuck on smp_invalidate_needed IPI wait' messages.
3896 if (check_apicid_used(apic_id_map
, apic_id
)) {
3898 for (i
= 0; i
< get_physical_broadcast(); i
++) {
3899 if (!check_apicid_used(apic_id_map
, i
))
3903 if (i
== get_physical_broadcast())
3904 panic("Max apic_id exceeded!\n");
3906 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
3907 "trying %d\n", ioapic
, apic_id
, i
);
3912 tmp
= apicid_to_cpu_present(apic_id
);
3913 physids_or(apic_id_map
, apic_id_map
, tmp
);
3915 if (reg_00
.bits
.ID
!= apic_id
) {
3916 reg_00
.bits
.ID
= apic_id
;
3918 spin_lock_irqsave(&ioapic_lock
, flags
);
3919 io_apic_write(ioapic
, 0, reg_00
.raw
);
3920 reg_00
.raw
= io_apic_read(ioapic
, 0);
3921 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3924 if (reg_00
.bits
.ID
!= apic_id
) {
3925 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
3930 apic_printk(APIC_VERBOSE
, KERN_INFO
3931 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
3936 int __init
io_apic_get_version(int ioapic
)
3938 union IO_APIC_reg_01 reg_01
;
3939 unsigned long flags
;
3941 spin_lock_irqsave(&ioapic_lock
, flags
);
3942 reg_01
.raw
= io_apic_read(ioapic
, 1);
3943 spin_unlock_irqrestore(&ioapic_lock
, flags
);
3945 return reg_01
.bits
.version
;
3949 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int triggering
, int polarity
)
3951 struct irq_desc
*desc
;
3952 struct irq_cfg
*cfg
;
3953 int cpu
= boot_cpu_id
;
3955 if (!IO_APIC_IRQ(irq
)) {
3956 apic_printk(APIC_QUIET
,KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
3961 desc
= irq_to_desc_alloc_cpu(irq
, cpu
);
3963 printk(KERN_INFO
"can not get irq_desc %d\n", irq
);
3968 * IRQs < 16 are already in the irq_2_pin[] map
3970 if (irq
>= NR_IRQS_LEGACY
) {
3971 cfg
= desc
->chip_data
;
3972 add_pin_to_irq_cpu(cfg
, cpu
, ioapic
, pin
);
3975 setup_IO_APIC_irq(ioapic
, pin
, irq
, desc
, triggering
, polarity
);
3981 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
3985 if (skip_ioapic_setup
)
3988 for (i
= 0; i
< mp_irq_entries
; i
++)
3989 if (mp_irqs
[i
].mp_irqtype
== mp_INT
&&
3990 mp_irqs
[i
].mp_srcbusirq
== bus_irq
)
3992 if (i
>= mp_irq_entries
)
3995 *trigger
= irq_trigger(i
);
3996 *polarity
= irq_polarity(i
);
4000 #endif /* CONFIG_ACPI */
4003 * This function currently is only a helper for the i386 smp boot process where
4004 * we need to reprogram the ioredtbls to cater for the cpus which have come online
4005 * so mask in all cases should simply be TARGET_CPUS
4008 void __init
setup_ioapic_dest(void)
4010 int pin
, ioapic
, irq
, irq_entry
;
4011 struct irq_desc
*desc
;
4012 struct irq_cfg
*cfg
;
4013 const struct cpumask
*mask
;
4015 if (skip_ioapic_setup
== 1)
4018 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
4019 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
4020 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
4021 if (irq_entry
== -1)
4023 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
4025 /* setup_IO_APIC_irqs could fail to get vector for some device
4026 * when you have too many devices, because at that time only boot
4029 desc
= irq_to_desc(irq
);
4030 cfg
= desc
->chip_data
;
4032 setup_IO_APIC_irq(ioapic
, pin
, irq
, desc
,
4033 irq_trigger(irq_entry
),
4034 irq_polarity(irq_entry
));
4040 * Honour affinities which have been set in early boot
4043 (IRQ_NO_BALANCING
| IRQ_AFFINITY_SET
))
4044 mask
= &desc
->affinity
;
4048 #ifdef CONFIG_INTR_REMAP
4049 if (intr_remapping_enabled
)
4050 set_ir_ioapic_affinity_irq_desc(desc
, mask
);
4053 set_ioapic_affinity_irq_desc(desc
, mask
);
4060 #define IOAPIC_RESOURCE_NAME_SIZE 11
4062 static struct resource
*ioapic_resources
;
4064 static struct resource
* __init
ioapic_setup_resources(void)
4067 struct resource
*res
;
4071 if (nr_ioapics
<= 0)
4074 n
= IOAPIC_RESOURCE_NAME_SIZE
+ sizeof(struct resource
);
4077 mem
= alloc_bootmem(n
);
4081 mem
+= sizeof(struct resource
) * nr_ioapics
;
4083 for (i
= 0; i
< nr_ioapics
; i
++) {
4085 res
[i
].flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
;
4086 sprintf(mem
, "IOAPIC %u", i
);
4087 mem
+= IOAPIC_RESOURCE_NAME_SIZE
;
4091 ioapic_resources
= res
;
4096 void __init
ioapic_init_mappings(void)
4098 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
4099 struct resource
*ioapic_res
;
4102 ioapic_res
= ioapic_setup_resources();
4103 for (i
= 0; i
< nr_ioapics
; i
++) {
4104 if (smp_found_config
) {
4105 ioapic_phys
= mp_ioapics
[i
].mp_apicaddr
;
4106 #ifdef CONFIG_X86_32
4109 "WARNING: bogus zero IO-APIC "
4110 "address found in MPTABLE, "
4111 "disabling IO/APIC support!\n");
4112 smp_found_config
= 0;
4113 skip_ioapic_setup
= 1;
4114 goto fake_ioapic_page
;
4118 #ifdef CONFIG_X86_32
4121 ioapic_phys
= (unsigned long)
4122 alloc_bootmem_pages(PAGE_SIZE
);
4123 ioapic_phys
= __pa(ioapic_phys
);
4125 set_fixmap_nocache(idx
, ioapic_phys
);
4126 apic_printk(APIC_VERBOSE
,
4127 "mapped IOAPIC to %08lx (%08lx)\n",
4128 __fix_to_virt(idx
), ioapic_phys
);
4131 if (ioapic_res
!= NULL
) {
4132 ioapic_res
->start
= ioapic_phys
;
4133 ioapic_res
->end
= ioapic_phys
+ (4 * 1024) - 1;
4139 static int __init
ioapic_insert_resources(void)
4142 struct resource
*r
= ioapic_resources
;
4146 "IO APIC resources could be not be allocated.\n");
4150 for (i
= 0; i
< nr_ioapics
; i
++) {
4151 insert_resource(&iomem_resource
, r
);
4158 /* Insert the IO APIC resources after PCI initialization has occured to handle
4159 * IO APICS that are mapped in on a BAR in PCI space. */
4160 late_initcall(ioapic_insert_resources
);