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sparc: Create common header file for prom_{32,64}.c
[linux-2.6/mini2440.git] / arch / sparc / kernel / prom_64.c
blob651448d3cc5abdf4a77a17eab6a9599824dbfc03
1 /*
2 * Procedures for creating, accessing and interpreting the device tree.
3 *
4 * Paul Mackerras August 1996.
5 * Copyright (C) 1996-2005 Paul Mackerras.
6 *
7 * Adapted for 64bit PowerPC by Dave Engebretsen and Peter Bergner.
8 * {engebret|bergner}@us.ibm.com
9 *
10 * Adapted for sparc64 by David S. Miller davem@davemloft.net
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version
15 * 2 of the License, or (at your option) any later version.
16 */
17
18 #include <linux/kernel.h>
19 #include <linux/types.h>
20 #include <linux/string.h>
21 #include <linux/mm.h>
22 #include <linux/module.h>
23 #include <linux/lmb.h>
24 #include <linux/of_device.h>
25
26 #include <asm/prom.h>
27 #include <asm/oplib.h>
28 #include <asm/irq.h>
29 #include <asm/asi.h>
30 #include <asm/upa.h>
31 #include <asm/smp.h>
32
33 #include "prom.h"
34
35 struct device_node *of_find_node_by_phandle(phandle handle)
36 {
37 struct device_node *np;
38
39 for (np = allnodes; np; np = np->allnext)
40 if (np->node == handle)
41 break;
42
43 return np;
44 }
45 EXPORT_SYMBOL(of_find_node_by_phandle);
46
47 int of_getintprop_default(struct device_node *np, const char *name, int def)
48 {
49 struct property *prop;
50 int len;
51
52 prop = of_find_property(np, name, &len);
53 if (!prop || len != 4)
54 return def;
55
56 return *(int *) prop->value;
57 }
58 EXPORT_SYMBOL(of_getintprop_default);
59
60 DEFINE_MUTEX(of_set_property_mutex);
61 EXPORT_SYMBOL(of_set_property_mutex);
62
63 int of_set_property(struct device_node *dp, const char *name, void *val, int len)
64 {
65 struct property **prevp;
66 void *new_val;
67 int err;
68
69 new_val = kmalloc(len, GFP_KERNEL);
70 if (!new_val)
71 return -ENOMEM;
72
73 memcpy(new_val, val, len);
74
75 err = -ENODEV;
76
77 write_lock(&devtree_lock);
78 prevp = &dp->properties;
79 while (*prevp) {
80 struct property *prop = *prevp;
81
82 if (!strcasecmp(prop->name, name)) {
83 void *old_val = prop->value;
84 int ret;
85
86 mutex_lock(&of_set_property_mutex);
87 ret = prom_setprop(dp->node, name, val, len);
88 mutex_unlock(&of_set_property_mutex);
89
90 err = -EINVAL;
91 if (ret >= 0) {
92 prop->value = new_val;
93 prop->length = len;
94
95 if (OF_IS_DYNAMIC(prop))
96 kfree(old_val);
97
98 OF_MARK_DYNAMIC(prop);
99
100 err = 0;
101 }
102 break;
103 }
104 prevp = &(*prevp)->next;
105 }
106 write_unlock(&devtree_lock);
107
108 /* XXX Upate procfs if necessary... */
109
110 return err;
111 }
112 EXPORT_SYMBOL(of_set_property);
113
114 int of_find_in_proplist(const char *list, const char *match, int len)
115 {
116 while (len > 0) {
117 int l;
118
119 if (!strcmp(list, match))
120 return 1;
121 l = strlen(list) + 1;
122 list += l;
123 len -= l;
124 }
125 return 0;
126 }
127 EXPORT_SYMBOL(of_find_in_proplist);
128
129 static unsigned int prom_early_allocated __initdata;
130
131 static void * __init prom_early_alloc(unsigned long size)
132 {
133 unsigned long paddr = lmb_alloc(size, SMP_CACHE_BYTES);
134 void *ret;
135
136 if (!paddr) {
137 prom_printf("prom_early_alloc(%lu) failed\n");
138 prom_halt();
139 }
140
141 ret = __va(paddr);
142 memset(ret, 0, size);
143 prom_early_allocated += size;
144
145 return ret;
146 }
147
148 #ifdef CONFIG_PCI
149 /* PSYCHO interrupt mapping support. */
150 #define PSYCHO_IMAP_A_SLOT0 0x0c00UL
151 #define PSYCHO_IMAP_B_SLOT0 0x0c20UL
152 static unsigned long psycho_pcislot_imap_offset(unsigned long ino)
153 {
154 unsigned int bus = (ino & 0x10) >> 4;
155 unsigned int slot = (ino & 0x0c) >> 2;
156
157 if (bus == 0)
158 return PSYCHO_IMAP_A_SLOT0 + (slot * 8);
159 else
160 return PSYCHO_IMAP_B_SLOT0 + (slot * 8);
161 }
162
163 #define PSYCHO_OBIO_IMAP_BASE 0x1000UL
164
165 #define PSYCHO_ONBOARD_IRQ_BASE 0x20
166 #define psycho_onboard_imap_offset(__ino) \
167 (PSYCHO_OBIO_IMAP_BASE + (((__ino) & 0x1f) << 3))
168
169 #define PSYCHO_ICLR_A_SLOT0 0x1400UL
170 #define PSYCHO_ICLR_SCSI 0x1800UL
171
172 #define psycho_iclr_offset(ino) \
173 ((ino & 0x20) ? (PSYCHO_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
174 (PSYCHO_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
175
176 static unsigned int psycho_irq_build(struct device_node *dp,
177 unsigned int ino,
178 void *_data)
179 {
180 unsigned long controller_regs = (unsigned long) _data;
181 unsigned long imap, iclr;
182 unsigned long imap_off, iclr_off;
183 int inofixup = 0;
184
185 ino &= 0x3f;
186 if (ino < PSYCHO_ONBOARD_IRQ_BASE) {
187 /* PCI slot */
188 imap_off = psycho_pcislot_imap_offset(ino);
189 } else {
190 /* Onboard device */
191 imap_off = psycho_onboard_imap_offset(ino);
192 }
193
194 /* Now build the IRQ bucket. */
195 imap = controller_regs + imap_off;
196
197 iclr_off = psycho_iclr_offset(ino);
198 iclr = controller_regs + iclr_off;
199
200 if ((ino & 0x20) == 0)
201 inofixup = ino & 0x03;
202
203 return build_irq(inofixup, iclr, imap);
204 }
205
206 static void __init psycho_irq_trans_init(struct device_node *dp)
207 {
208 const struct linux_prom64_registers *regs;
209
210 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
211 dp->irq_trans->irq_build = psycho_irq_build;
212
213 regs = of_get_property(dp, "reg", NULL);
214 dp->irq_trans->data = (void *) regs[2].phys_addr;
215 }
216
217 #define sabre_read(__reg) \
218 ({ u64 __ret; \
219 __asm__ __volatile__("ldxa [%1] %2, %0" \
220 : "=r" (__ret) \
221 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
222 : "memory"); \
223 __ret; \
224 })
225
226 struct sabre_irq_data {
227 unsigned long controller_regs;
228 unsigned int pci_first_busno;
229 };
230 #define SABRE_CONFIGSPACE 0x001000000UL
231 #define SABRE_WRSYNC 0x1c20UL
232
233 #define SABRE_CONFIG_BASE(CONFIG_SPACE) \
234 (CONFIG_SPACE | (1UL << 24))
235 #define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG) \
236 (((unsigned long)(BUS) << 16) | \
237 ((unsigned long)(DEVFN) << 8) | \
238 ((unsigned long)(REG)))
239
240 /* When a device lives behind a bridge deeper in the PCI bus topology
241 * than APB, a special sequence must run to make sure all pending DMA
242 * transfers at the time of IRQ delivery are visible in the coherency
243 * domain by the cpu. This sequence is to perform a read on the far
244 * side of the non-APB bridge, then perform a read of Sabre's DMA
245 * write-sync register.
246 */
247 static void sabre_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
248 {
249 unsigned int phys_hi = (unsigned int) (unsigned long) _arg1;
250 struct sabre_irq_data *irq_data = _arg2;
251 unsigned long controller_regs = irq_data->controller_regs;
252 unsigned long sync_reg = controller_regs + SABRE_WRSYNC;
253 unsigned long config_space = controller_regs + SABRE_CONFIGSPACE;
254 unsigned int bus, devfn;
255 u16 _unused;
256
257 config_space = SABRE_CONFIG_BASE(config_space);
258
259 bus = (phys_hi >> 16) & 0xff;
260 devfn = (phys_hi >> 8) & 0xff;
261
262 config_space |= SABRE_CONFIG_ENCODE(bus, devfn, 0x00);
263
264 __asm__ __volatile__("membar #Sync\n\t"
265 "lduha [%1] %2, %0\n\t"
266 "membar #Sync"
267 : "=r" (_unused)
268 : "r" ((u16 *) config_space),
269 "i" (ASI_PHYS_BYPASS_EC_E_L)
270 : "memory");
271
272 sabre_read(sync_reg);
273 }
274
275 #define SABRE_IMAP_A_SLOT0 0x0c00UL
276 #define SABRE_IMAP_B_SLOT0 0x0c20UL
277 #define SABRE_ICLR_A_SLOT0 0x1400UL
278 #define SABRE_ICLR_B_SLOT0 0x1480UL
279 #define SABRE_ICLR_SCSI 0x1800UL
280 #define SABRE_ICLR_ETH 0x1808UL
281 #define SABRE_ICLR_BPP 0x1810UL
282 #define SABRE_ICLR_AU_REC 0x1818UL
283 #define SABRE_ICLR_AU_PLAY 0x1820UL
284 #define SABRE_ICLR_PFAIL 0x1828UL
285 #define SABRE_ICLR_KMS 0x1830UL
286 #define SABRE_ICLR_FLPY 0x1838UL
287 #define SABRE_ICLR_SHW 0x1840UL
288 #define SABRE_ICLR_KBD 0x1848UL
289 #define SABRE_ICLR_MS 0x1850UL
290 #define SABRE_ICLR_SER 0x1858UL
291 #define SABRE_ICLR_UE 0x1870UL
292 #define SABRE_ICLR_CE 0x1878UL
293 #define SABRE_ICLR_PCIERR 0x1880UL
294
295 static unsigned long sabre_pcislot_imap_offset(unsigned long ino)
296 {
297 unsigned int bus = (ino & 0x10) >> 4;
298 unsigned int slot = (ino & 0x0c) >> 2;
299
300 if (bus == 0)
301 return SABRE_IMAP_A_SLOT0 + (slot * 8);
302 else
303 return SABRE_IMAP_B_SLOT0 + (slot * 8);
304 }
305
306 #define SABRE_OBIO_IMAP_BASE 0x1000UL
307 #define SABRE_ONBOARD_IRQ_BASE 0x20
308 #define sabre_onboard_imap_offset(__ino) \
309 (SABRE_OBIO_IMAP_BASE + (((__ino) & 0x1f) << 3))
310
311 #define sabre_iclr_offset(ino) \
312 ((ino & 0x20) ? (SABRE_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
313 (SABRE_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
314
315 static int sabre_device_needs_wsync(struct device_node *dp)
316 {
317 struct device_node *parent = dp->parent;
318 const char *parent_model, *parent_compat;
319
320 /* This traversal up towards the root is meant to
321 * handle two cases:
322 *
323 * 1) non-PCI bus sitting under PCI, such as 'ebus'
324 * 2) the PCI controller interrupts themselves, which
325 * will use the sabre_irq_build but do not need
326 * the DMA synchronization handling
327 */
328 while (parent) {
329 if (!strcmp(parent->type, "pci"))
330 break;
331 parent = parent->parent;
332 }
333
334 if (!parent)
335 return 0;
336
337 parent_model = of_get_property(parent,
338 "model", NULL);
339 if (parent_model &&
340 (!strcmp(parent_model, "SUNW,sabre") ||
341 !strcmp(parent_model, "SUNW,simba")))
342 return 0;
343
344 parent_compat = of_get_property(parent,
345 "compatible", NULL);
346 if (parent_compat &&
347 (!strcmp(parent_compat, "pci108e,a000") ||
348 !strcmp(parent_compat, "pci108e,a001")))
349 return 0;
350
351 return 1;
352 }
353
354 static unsigned int sabre_irq_build(struct device_node *dp,
355 unsigned int ino,
356 void *_data)
357 {
358 struct sabre_irq_data *irq_data = _data;
359 unsigned long controller_regs = irq_data->controller_regs;
360 const struct linux_prom_pci_registers *regs;
361 unsigned long imap, iclr;
362 unsigned long imap_off, iclr_off;
363 int inofixup = 0;
364 int virt_irq;
365
366 ino &= 0x3f;
367 if (ino < SABRE_ONBOARD_IRQ_BASE) {
368 /* PCI slot */
369 imap_off = sabre_pcislot_imap_offset(ino);
370 } else {
371 /* onboard device */
372 imap_off = sabre_onboard_imap_offset(ino);
373 }
374
375 /* Now build the IRQ bucket. */
376 imap = controller_regs + imap_off;
377
378 iclr_off = sabre_iclr_offset(ino);
379 iclr = controller_regs + iclr_off;
380
381 if ((ino & 0x20) == 0)
382 inofixup = ino & 0x03;
383
384 virt_irq = build_irq(inofixup, iclr, imap);
385
386 /* If the parent device is a PCI<->PCI bridge other than
387 * APB, we have to install a pre-handler to ensure that
388 * all pending DMA is drained before the interrupt handler
389 * is run.
390 */
391 regs = of_get_property(dp, "reg", NULL);
392 if (regs && sabre_device_needs_wsync(dp)) {
393 irq_install_pre_handler(virt_irq,
394 sabre_wsync_handler,
395 (void *) (long) regs->phys_hi,
396 (void *) irq_data);
397 }
398
399 return virt_irq;
400 }
401
402 static void __init sabre_irq_trans_init(struct device_node *dp)
403 {
404 const struct linux_prom64_registers *regs;
405 struct sabre_irq_data *irq_data;
406 const u32 *busrange;
407
408 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
409 dp->irq_trans->irq_build = sabre_irq_build;
410
411 irq_data = prom_early_alloc(sizeof(struct sabre_irq_data));
412
413 regs = of_get_property(dp, "reg", NULL);
414 irq_data->controller_regs = regs[0].phys_addr;
415
416 busrange = of_get_property(dp, "bus-range", NULL);
417 irq_data->pci_first_busno = busrange[0];
418
419 dp->irq_trans->data = irq_data;
420 }
421
422 /* SCHIZO interrupt mapping support. Unlike Psycho, for this controller the
423 * imap/iclr registers are per-PBM.
424 */
425 #define SCHIZO_IMAP_BASE 0x1000UL
426 #define SCHIZO_ICLR_BASE 0x1400UL
427
428 static unsigned long schizo_imap_offset(unsigned long ino)
429 {
430 return SCHIZO_IMAP_BASE + (ino * 8UL);
431 }
432
433 static unsigned long schizo_iclr_offset(unsigned long ino)
434 {
435 return SCHIZO_ICLR_BASE + (ino * 8UL);
436 }
437
438 static unsigned long schizo_ino_to_iclr(unsigned long pbm_regs,
439 unsigned int ino)
440 {
441
442 return pbm_regs + schizo_iclr_offset(ino);
443 }
444
445 static unsigned long schizo_ino_to_imap(unsigned long pbm_regs,
446 unsigned int ino)
447 {
448 return pbm_regs + schizo_imap_offset(ino);
449 }
450
451 #define schizo_read(__reg) \
452 ({ u64 __ret; \
453 __asm__ __volatile__("ldxa [%1] %2, %0" \
454 : "=r" (__ret) \
455 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
456 : "memory"); \
457 __ret; \
458 })
459 #define schizo_write(__reg, __val) \
460 __asm__ __volatile__("stxa %0, [%1] %2" \
461 : /* no outputs */ \
462 : "r" (__val), "r" (__reg), \
463 "i" (ASI_PHYS_BYPASS_EC_E) \
464 : "memory")
465
466 static void tomatillo_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
467 {
468 unsigned long sync_reg = (unsigned long) _arg2;
469 u64 mask = 1UL << (ino & IMAP_INO);
470 u64 val;
471 int limit;
472
473 schizo_write(sync_reg, mask);
474
475 limit = 100000;
476 val = 0;
477 while (--limit) {
478 val = schizo_read(sync_reg);
479 if (!(val & mask))
480 break;
481 }
482 if (limit <= 0) {
483 printk("tomatillo_wsync_handler: DMA won't sync [%lx:%lx]\n",
484 val, mask);
485 }
486
487 if (_arg1) {
488 static unsigned char cacheline[64]
489 __attribute__ ((aligned (64)));
490
491 __asm__ __volatile__("rd %%fprs, %0\n\t"
492 "or %0, %4, %1\n\t"
493 "wr %1, 0x0, %%fprs\n\t"
494 "stda %%f0, [%5] %6\n\t"
495 "wr %0, 0x0, %%fprs\n\t"
496 "membar #Sync"
497 : "=&r" (mask), "=&r" (val)
498 : "0" (mask), "1" (val),
499 "i" (FPRS_FEF), "r" (&cacheline[0]),
500 "i" (ASI_BLK_COMMIT_P));
501 }
502 }
503
504 struct schizo_irq_data {
505 unsigned long pbm_regs;
506 unsigned long sync_reg;
507 u32 portid;
508 int chip_version;
509 };
510
511 static unsigned int schizo_irq_build(struct device_node *dp,
512 unsigned int ino,
513 void *_data)
514 {
515 struct schizo_irq_data *irq_data = _data;
516 unsigned long pbm_regs = irq_data->pbm_regs;
517 unsigned long imap, iclr;
518 int ign_fixup;
519 int virt_irq;
520 int is_tomatillo;
521
522 ino &= 0x3f;
523
524 /* Now build the IRQ bucket. */
525 imap = schizo_ino_to_imap(pbm_regs, ino);
526 iclr = schizo_ino_to_iclr(pbm_regs, ino);
527
528 /* On Schizo, no inofixup occurs. This is because each
529 * INO has it's own IMAP register. On Psycho and Sabre
530 * there is only one IMAP register for each PCI slot even
531 * though four different INOs can be generated by each
532 * PCI slot.
533 *
534 * But, for JBUS variants (essentially, Tomatillo), we have
535 * to fixup the lowest bit of the interrupt group number.
536 */
537 ign_fixup = 0;
538
539 is_tomatillo = (irq_data->sync_reg != 0UL);
540
541 if (is_tomatillo) {
542 if (irq_data->portid & 1)
543 ign_fixup = (1 << 6);
544 }
545
546 virt_irq = build_irq(ign_fixup, iclr, imap);
547
548 if (is_tomatillo) {
549 irq_install_pre_handler(virt_irq,
550 tomatillo_wsync_handler,
551 ((irq_data->chip_version <= 4) ?
552 (void *) 1 : (void *) 0),
553 (void *) irq_data->sync_reg);
554 }
555
556 return virt_irq;
557 }
558
559 static void __init __schizo_irq_trans_init(struct device_node *dp,
560 int is_tomatillo)
561 {
562 const struct linux_prom64_registers *regs;
563 struct schizo_irq_data *irq_data;
564
565 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
566 dp->irq_trans->irq_build = schizo_irq_build;
567
568 irq_data = prom_early_alloc(sizeof(struct schizo_irq_data));
569
570 regs = of_get_property(dp, "reg", NULL);
571 dp->irq_trans->data = irq_data;
572
573 irq_data->pbm_regs = regs[0].phys_addr;
574 if (is_tomatillo)
575 irq_data->sync_reg = regs[3].phys_addr + 0x1a18UL;
576 else
577 irq_data->sync_reg = 0UL;
578 irq_data->portid = of_getintprop_default(dp, "portid", 0);
579 irq_data->chip_version = of_getintprop_default(dp, "version#", 0);
580 }
581
582 static void __init schizo_irq_trans_init(struct device_node *dp)
583 {
584 __schizo_irq_trans_init(dp, 0);
585 }
586
587 static void __init tomatillo_irq_trans_init(struct device_node *dp)
588 {
589 __schizo_irq_trans_init(dp, 1);
590 }
591
592 static unsigned int pci_sun4v_irq_build(struct device_node *dp,
593 unsigned int devino,
594 void *_data)
595 {
596 u32 devhandle = (u32) (unsigned long) _data;
597
598 return sun4v_build_irq(devhandle, devino);
599 }
600
601 static void __init pci_sun4v_irq_trans_init(struct device_node *dp)
602 {
603 const struct linux_prom64_registers *regs;
604
605 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
606 dp->irq_trans->irq_build = pci_sun4v_irq_build;
607
608 regs = of_get_property(dp, "reg", NULL);
609 dp->irq_trans->data = (void *) (unsigned long)
610 ((regs->phys_addr >> 32UL) & 0x0fffffff);
611 }
612
613 struct fire_irq_data {
614 unsigned long pbm_regs;
615 u32 portid;
616 };
617
618 #define FIRE_IMAP_BASE 0x001000
619 #define FIRE_ICLR_BASE 0x001400
620
621 static unsigned long fire_imap_offset(unsigned long ino)
622 {
623 return FIRE_IMAP_BASE + (ino * 8UL);
624 }
625
626 static unsigned long fire_iclr_offset(unsigned long ino)
627 {
628 return FIRE_ICLR_BASE + (ino * 8UL);
629 }
630
631 static unsigned long fire_ino_to_iclr(unsigned long pbm_regs,
632 unsigned int ino)
633 {
634 return pbm_regs + fire_iclr_offset(ino);
635 }
636
637 static unsigned long fire_ino_to_imap(unsigned long pbm_regs,
638 unsigned int ino)
639 {
640 return pbm_regs + fire_imap_offset(ino);
641 }
642
643 static unsigned int fire_irq_build(struct device_node *dp,
644 unsigned int ino,
645 void *_data)
646 {
647 struct fire_irq_data *irq_data = _data;
648 unsigned long pbm_regs = irq_data->pbm_regs;
649 unsigned long imap, iclr;
650 unsigned long int_ctrlr;
651
652 ino &= 0x3f;
653
654 /* Now build the IRQ bucket. */
655 imap = fire_ino_to_imap(pbm_regs, ino);
656 iclr = fire_ino_to_iclr(pbm_regs, ino);
657
658 /* Set the interrupt controller number. */
659 int_ctrlr = 1 << 6;
660 upa_writeq(int_ctrlr, imap);
661
662 /* The interrupt map registers do not have an INO field
663 * like other chips do. They return zero in the INO
664 * field, and the interrupt controller number is controlled
665 * in bits 6 to 9. So in order for build_irq() to get
666 * the INO right we pass it in as part of the fixup
667 * which will get added to the map register zero value
668 * read by build_irq().
669 */
670 ino |= (irq_data->portid << 6);
671 ino -= int_ctrlr;
672 return build_irq(ino, iclr, imap);
673 }
674
675 static void __init fire_irq_trans_init(struct device_node *dp)
676 {
677 const struct linux_prom64_registers *regs;
678 struct fire_irq_data *irq_data;
679
680 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
681 dp->irq_trans->irq_build = fire_irq_build;
682
683 irq_data = prom_early_alloc(sizeof(struct fire_irq_data));
684
685 regs = of_get_property(dp, "reg", NULL);
686 dp->irq_trans->data = irq_data;
687
688 irq_data->pbm_regs = regs[0].phys_addr;
689 irq_data->portid = of_getintprop_default(dp, "portid", 0);
690 }
691 #endif /* CONFIG_PCI */
692
693 #ifdef CONFIG_SBUS
694 /* INO number to IMAP register offset for SYSIO external IRQ's.
695 * This should conform to both Sunfire/Wildfire server and Fusion
696 * desktop designs.
697 */
698 #define SYSIO_IMAP_SLOT0 0x2c00UL
699 #define SYSIO_IMAP_SLOT1 0x2c08UL
700 #define SYSIO_IMAP_SLOT2 0x2c10UL
701 #define SYSIO_IMAP_SLOT3 0x2c18UL
702 #define SYSIO_IMAP_SCSI 0x3000UL
703 #define SYSIO_IMAP_ETH 0x3008UL
704 #define SYSIO_IMAP_BPP 0x3010UL
705 #define SYSIO_IMAP_AUDIO 0x3018UL
706 #define SYSIO_IMAP_PFAIL 0x3020UL
707 #define SYSIO_IMAP_KMS 0x3028UL
708 #define SYSIO_IMAP_FLPY 0x3030UL
709 #define SYSIO_IMAP_SHW 0x3038UL
710 #define SYSIO_IMAP_KBD 0x3040UL
711 #define SYSIO_IMAP_MS 0x3048UL
712 #define SYSIO_IMAP_SER 0x3050UL
713 #define SYSIO_IMAP_TIM0 0x3060UL
714 #define SYSIO_IMAP_TIM1 0x3068UL
715 #define SYSIO_IMAP_UE 0x3070UL
716 #define SYSIO_IMAP_CE 0x3078UL
717 #define SYSIO_IMAP_SBERR 0x3080UL
718 #define SYSIO_IMAP_PMGMT 0x3088UL
719 #define SYSIO_IMAP_GFX 0x3090UL
720 #define SYSIO_IMAP_EUPA 0x3098UL
721
722 #define bogon ((unsigned long) -1)
723 static unsigned long sysio_irq_offsets[] = {
724 /* SBUS Slot 0 --> 3, level 1 --> 7 */
725 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
726 SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0, SYSIO_IMAP_SLOT0,
727 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
728 SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1, SYSIO_IMAP_SLOT1,
729 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
730 SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2, SYSIO_IMAP_SLOT2,
731 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
732 SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3, SYSIO_IMAP_SLOT3,
733
734 /* Onboard devices (not relevant/used on SunFire). */
735 SYSIO_IMAP_SCSI,
736 SYSIO_IMAP_ETH,
737 SYSIO_IMAP_BPP,
738 bogon,
739 SYSIO_IMAP_AUDIO,
740 SYSIO_IMAP_PFAIL,
741 bogon,
742 bogon,
743 SYSIO_IMAP_KMS,
744 SYSIO_IMAP_FLPY,
745 SYSIO_IMAP_SHW,
746 SYSIO_IMAP_KBD,
747 SYSIO_IMAP_MS,
748 SYSIO_IMAP_SER,
749 bogon,
750 bogon,
751 SYSIO_IMAP_TIM0,
752 SYSIO_IMAP_TIM1,
753 bogon,
754 bogon,
755 SYSIO_IMAP_UE,
756 SYSIO_IMAP_CE,
757 SYSIO_IMAP_SBERR,
758 SYSIO_IMAP_PMGMT,
759 SYSIO_IMAP_GFX,
760 SYSIO_IMAP_EUPA,
761 };
762
763 #undef bogon
764
765 #define NUM_SYSIO_OFFSETS ARRAY_SIZE(sysio_irq_offsets)
766
767 /* Convert Interrupt Mapping register pointer to associated
768 * Interrupt Clear register pointer, SYSIO specific version.
769 */
770 #define SYSIO_ICLR_UNUSED0 0x3400UL
771 #define SYSIO_ICLR_SLOT0 0x3408UL
772 #define SYSIO_ICLR_SLOT1 0x3448UL
773 #define SYSIO_ICLR_SLOT2 0x3488UL
774 #define SYSIO_ICLR_SLOT3 0x34c8UL
775 static unsigned long sysio_imap_to_iclr(unsigned long imap)
776 {
777 unsigned long diff = SYSIO_ICLR_UNUSED0 - SYSIO_IMAP_SLOT0;
778 return imap + diff;
779 }
780
781 static unsigned int sbus_of_build_irq(struct device_node *dp,
782 unsigned int ino,
783 void *_data)
784 {
785 unsigned long reg_base = (unsigned long) _data;
786 const struct linux_prom_registers *regs;
787 unsigned long imap, iclr;
788 int sbus_slot = 0;
789 int sbus_level = 0;
790
791 ino &= 0x3f;
792
793 regs = of_get_property(dp, "reg", NULL);
794 if (regs)
795 sbus_slot = regs->which_io;
796
797 if (ino < 0x20)
798 ino += (sbus_slot * 8);
799
800 imap = sysio_irq_offsets[ino];
801 if (imap == ((unsigned long)-1)) {
802 prom_printf("get_irq_translations: Bad SYSIO INO[%x]\n",
803 ino);
804 prom_halt();
805 }
806 imap += reg_base;
807
808 /* SYSIO inconsistency. For external SLOTS, we have to select
809 * the right ICLR register based upon the lower SBUS irq level
810 * bits.
811 */
812 if (ino >= 0x20) {
813 iclr = sysio_imap_to_iclr(imap);
814 } else {
815 sbus_level = ino & 0x7;
816
817 switch(sbus_slot) {
818 case 0:
819 iclr = reg_base + SYSIO_ICLR_SLOT0;
820 break;
821 case 1:
822 iclr = reg_base + SYSIO_ICLR_SLOT1;
823 break;
824 case 2:
825 iclr = reg_base + SYSIO_ICLR_SLOT2;
826 break;
827 default:
828 case 3:
829 iclr = reg_base + SYSIO_ICLR_SLOT3;
830 break;
831 };
832
833 iclr += ((unsigned long)sbus_level - 1UL) * 8UL;
834 }
835 return build_irq(sbus_level, iclr, imap);
836 }
837
838 static void __init sbus_irq_trans_init(struct device_node *dp)
839 {
840 const struct linux_prom64_registers *regs;
841
842 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
843 dp->irq_trans->irq_build = sbus_of_build_irq;
844
845 regs = of_get_property(dp, "reg", NULL);
846 dp->irq_trans->data = (void *) (unsigned long) regs->phys_addr;
847 }
848 #endif /* CONFIG_SBUS */
849
850
851 static unsigned int central_build_irq(struct device_node *dp,
852 unsigned int ino,
853 void *_data)
854 {
855 struct device_node *central_dp = _data;
856 struct of_device *central_op = of_find_device_by_node(central_dp);
857 struct resource *res;
858 unsigned long imap, iclr;
859 u32 tmp;
860
861 if (!strcmp(dp->name, "eeprom")) {
862 res = &central_op->resource[5];
863 } else if (!strcmp(dp->name, "zs")) {
864 res = &central_op->resource[4];
865 } else if (!strcmp(dp->name, "clock-board")) {
866 res = &central_op->resource[3];
867 } else {
868 return ino;
869 }
870
871 imap = res->start + 0x00UL;
872 iclr = res->start + 0x10UL;
873
874 /* Set the INO state to idle, and disable. */
875 upa_writel(0, iclr);
876 upa_readl(iclr);
877
878 tmp = upa_readl(imap);
879 tmp &= ~0x80000000;
880 upa_writel(tmp, imap);
881
882 return build_irq(0, iclr, imap);
883 }
884
885 static void __init central_irq_trans_init(struct device_node *dp)
886 {
887 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
888 dp->irq_trans->irq_build = central_build_irq;
889
890 dp->irq_trans->data = dp;
891 }
892
893 struct irq_trans {
894 const char *name;
895 void (*init)(struct device_node *);
896 };
897
898 #ifdef CONFIG_PCI
899 static struct irq_trans __initdata pci_irq_trans_table[] = {
900 { "SUNW,sabre", sabre_irq_trans_init },
901 { "pci108e,a000", sabre_irq_trans_init },
902 { "pci108e,a001", sabre_irq_trans_init },
903 { "SUNW,psycho", psycho_irq_trans_init },
904 { "pci108e,8000", psycho_irq_trans_init },
905 { "SUNW,schizo", schizo_irq_trans_init },
906 { "pci108e,8001", schizo_irq_trans_init },
907 { "SUNW,schizo+", schizo_irq_trans_init },
908 { "pci108e,8002", schizo_irq_trans_init },
909 { "SUNW,tomatillo", tomatillo_irq_trans_init },
910 { "pci108e,a801", tomatillo_irq_trans_init },
911 { "SUNW,sun4v-pci", pci_sun4v_irq_trans_init },
912 { "pciex108e,80f0", fire_irq_trans_init },
913 };
914 #endif
915
916 static unsigned int sun4v_vdev_irq_build(struct device_node *dp,
917 unsigned int devino,
918 void *_data)
919 {
920 u32 devhandle = (u32) (unsigned long) _data;
921
922 return sun4v_build_irq(devhandle, devino);
923 }
924
925 static void __init sun4v_vdev_irq_trans_init(struct device_node *dp)
926 {
927 const struct linux_prom64_registers *regs;
928
929 dp->irq_trans = prom_early_alloc(sizeof(struct of_irq_controller));
930 dp->irq_trans->irq_build = sun4v_vdev_irq_build;
931
932 regs = of_get_property(dp, "reg", NULL);
933 dp->irq_trans->data = (void *) (unsigned long)
934 ((regs->phys_addr >> 32UL) & 0x0fffffff);
935 }
936
937 static void __init irq_trans_init(struct device_node *dp)
938 {
939 #ifdef CONFIG_PCI
940 const char *model;
941 int i;
942 #endif
943
944 #ifdef CONFIG_PCI
945 model = of_get_property(dp, "model", NULL);
946 if (!model)
947 model = of_get_property(dp, "compatible", NULL);
948 if (model) {
949 for (i = 0; i < ARRAY_SIZE(pci_irq_trans_table); i++) {
950 struct irq_trans *t = &pci_irq_trans_table[i];
951
952 if (!strcmp(model, t->name)) {
953 t->init(dp);
954 return;
955 }
956 }
957 }
958 #endif
959 #ifdef CONFIG_SBUS
960 if (!strcmp(dp->name, "sbus") ||
961 !strcmp(dp->name, "sbi")) {
962 sbus_irq_trans_init(dp);
963 return;
964 }
965 #endif
966 if (!strcmp(dp->name, "fhc") &&
967 !strcmp(dp->parent->name, "central")) {
968 central_irq_trans_init(dp);
969 return;
970 }
971 if (!strcmp(dp->name, "virtual-devices") ||
972 !strcmp(dp->name, "niu")) {
973 sun4v_vdev_irq_trans_init(dp);
974 return;
975 }
976 }
977
978 static int is_root_node(const struct device_node *dp)
979 {
980 if (!dp)
981 return 0;
982
983 return (dp->parent == NULL);
984 }
985
986 /* The following routines deal with the black magic of fully naming a
987 * node.
988 *
989 * Certain well known named nodes are just the simple name string.
990 *
991 * Actual devices have an address specifier appended to the base name
992 * string, like this "foo@addr". The "addr" can be in any number of
993 * formats, and the platform plus the type of the node determine the
994 * format and how it is constructed.
995 *
996 * For children of the ROOT node, the naming convention is fixed and
997 * determined by whether this is a sun4u or sun4v system.
998 *
999 * For children of other nodes, it is bus type specific. So
1000 * we walk up the tree until we discover a "device_type" property
1001 * we recognize and we go from there.
1002 *
1003 * As an example, the boot device on my workstation has a full path:
1004 *
1005 * /pci@1e,600000/ide@d/disk@0,0:c
1006 */
1007 static void __init sun4v_path_component(struct device_node *dp, char *tmp_buf)
1008 {
1009 struct linux_prom64_registers *regs;
1010 struct property *rprop;
1011 u32 high_bits, low_bits, type;
1012
1013 rprop = of_find_property(dp, "reg", NULL);
1014 if (!rprop)
1015 return;
1016
1017 regs = rprop->value;
1018 if (!is_root_node(dp->parent)) {
1019 sprintf(tmp_buf, "%s@%x,%x",
1020 dp->name,
1021 (unsigned int) (regs->phys_addr >> 32UL),
1022 (unsigned int) (regs->phys_addr & 0xffffffffUL));
1023 return;
1024 }
1025
1026 type = regs->phys_addr >> 60UL;
1027 high_bits = (regs->phys_addr >> 32UL) & 0x0fffffffUL;
1028 low_bits = (regs->phys_addr & 0xffffffffUL);
1029
1030 if (type == 0 || type == 8) {
1031 const char *prefix = (type == 0) ? "m" : "i";
1032
1033 if (low_bits)
1034 sprintf(tmp_buf, "%s@%s%x,%x",
1035 dp->name, prefix,
1036 high_bits, low_bits);
1037 else
1038 sprintf(tmp_buf, "%s@%s%x",
1039 dp->name,
1040 prefix,
1041 high_bits);
1042 } else if (type == 12) {
1043 sprintf(tmp_buf, "%s@%x",
1044 dp->name, high_bits);
1045 }
1046 }
1047
1048 static void __init sun4u_path_component(struct device_node *dp, char *tmp_buf)
1049 {
1050 struct linux_prom64_registers *regs;
1051 struct property *prop;
1052
1053 prop = of_find_property(dp, "reg", NULL);
1054 if (!prop)
1055 return;
1056
1057 regs = prop->value;
1058 if (!is_root_node(dp->parent)) {
1059 sprintf(tmp_buf, "%s@%x,%x",
1060 dp->name,
1061 (unsigned int) (regs->phys_addr >> 32UL),
1062 (unsigned int) (regs->phys_addr & 0xffffffffUL));
1063 return;
1064 }
1065
1066 prop = of_find_property(dp, "upa-portid", NULL);
1067 if (!prop)
1068 prop = of_find_property(dp, "portid", NULL);
1069 if (prop) {
1070 unsigned long mask = 0xffffffffUL;
1071
1072 if (tlb_type >= cheetah)
1073 mask = 0x7fffff;
1074
1075 sprintf(tmp_buf, "%s@%x,%x",
1076 dp->name,
1077 *(u32 *)prop->value,
1078 (unsigned int) (regs->phys_addr & mask));
1079 }
1080 }
1081
1082 /* "name@slot,offset" */
1083 static void __init sbus_path_component(struct device_node *dp, char *tmp_buf)
1084 {
1085 struct linux_prom_registers *regs;
1086 struct property *prop;
1087
1088 prop = of_find_property(dp, "reg", NULL);
1089 if (!prop)
1090 return;
1091
1092 regs = prop->value;
1093 sprintf(tmp_buf, "%s@%x,%x",
1094 dp->name,
1095 regs->which_io,
1096 regs->phys_addr);
1097 }
1098
1099 /* "name@devnum[,func]" */
1100 static void __init pci_path_component(struct device_node *dp, char *tmp_buf)
1101 {
1102 struct linux_prom_pci_registers *regs;
1103 struct property *prop;
1104 unsigned int devfn;
1105
1106 prop = of_find_property(dp, "reg", NULL);
1107 if (!prop)
1108 return;
1109
1110 regs = prop->value;
1111 devfn = (regs->phys_hi >> 8) & 0xff;
1112 if (devfn & 0x07) {
1113 sprintf(tmp_buf, "%s@%x,%x",
1114 dp->name,
1115 devfn >> 3,
1116 devfn & 0x07);
1117 } else {
1118 sprintf(tmp_buf, "%s@%x",
1119 dp->name,
1120 devfn >> 3);
1121 }
1122 }
1123
1124 /* "name@UPA_PORTID,offset" */
1125 static void __init upa_path_component(struct device_node *dp, char *tmp_buf)
1126 {
1127 struct linux_prom64_registers *regs;
1128 struct property *prop;
1129
1130 prop = of_find_property(dp, "reg", NULL);
1131 if (!prop)
1132 return;
1133
1134 regs = prop->value;
1135
1136 prop = of_find_property(dp, "upa-portid", NULL);
1137 if (!prop)
1138 return;
1139
1140 sprintf(tmp_buf, "%s@%x,%x",
1141 dp->name,
1142 *(u32 *) prop->value,
1143 (unsigned int) (regs->phys_addr & 0xffffffffUL));
1144 }
1145
1146 /* "name@reg" */
1147 static void __init vdev_path_component(struct device_node *dp, char *tmp_buf)
1148 {
1149 struct property *prop;
1150 u32 *regs;
1151
1152 prop = of_find_property(dp, "reg", NULL);
1153 if (!prop)
1154 return;
1155
1156 regs = prop->value;
1157
1158 sprintf(tmp_buf, "%s@%x", dp->name, *regs);
1159 }
1160
1161 /* "name@addrhi,addrlo" */
1162 static void __init ebus_path_component(struct device_node *dp, char *tmp_buf)
1163 {
1164 struct linux_prom64_registers *regs;
1165 struct property *prop;
1166
1167 prop = of_find_property(dp, "reg", NULL);
1168 if (!prop)
1169 return;
1170
1171 regs = prop->value;
1172
1173 sprintf(tmp_buf, "%s@%x,%x",
1174 dp->name,
1175 (unsigned int) (regs->phys_addr >> 32UL),
1176 (unsigned int) (regs->phys_addr & 0xffffffffUL));
1177 }
1178
1179 /* "name@bus,addr" */
1180 static void __init i2c_path_component(struct device_node *dp, char *tmp_buf)
1181 {
1182 struct property *prop;
1183 u32 *regs;
1184
1185 prop = of_find_property(dp, "reg", NULL);
1186 if (!prop)
1187 return;
1188
1189 regs = prop->value;
1190
1191 /* This actually isn't right... should look at the #address-cells
1192 * property of the i2c bus node etc. etc.
1193 */
1194 sprintf(tmp_buf, "%s@%x,%x",
1195 dp->name, regs[0], regs[1]);
1196 }
1197
1198 /* "name@reg0[,reg1]" */
1199 static void __init usb_path_component(struct device_node *dp, char *tmp_buf)
1200 {
1201 struct property *prop;
1202 u32 *regs;
1203
1204 prop = of_find_property(dp, "reg", NULL);
1205 if (!prop)
1206 return;
1207
1208 regs = prop->value;
1209
1210 if (prop->length == sizeof(u32) || regs[1] == 1) {
1211 sprintf(tmp_buf, "%s@%x",
1212 dp->name, regs[0]);
1213 } else {
1214 sprintf(tmp_buf, "%s@%x,%x",
1215 dp->name, regs[0], regs[1]);
1216 }
1217 }
1218
1219 /* "name@reg0reg1[,reg2reg3]" */
1220 static void __init ieee1394_path_component(struct device_node *dp, char *tmp_buf)
1221 {
1222 struct property *prop;
1223 u32 *regs;
1224
1225 prop = of_find_property(dp, "reg", NULL);
1226 if (!prop)
1227 return;
1228
1229 regs = prop->value;
1230
1231 if (regs[2] || regs[3]) {
1232 sprintf(tmp_buf, "%s@%08x%08x,%04x%08x",
1233 dp->name, regs[0], regs[1], regs[2], regs[3]);
1234 } else {
1235 sprintf(tmp_buf, "%s@%08x%08x",
1236 dp->name, regs[0], regs[1]);
1237 }
1238 }
1239
1240 static void __init __build_path_component(struct device_node *dp, char *tmp_buf)
1241 {
1242 struct device_node *parent = dp->parent;
1243
1244 if (parent != NULL) {
1245 if (!strcmp(parent->type, "pci") ||
1246 !strcmp(parent->type, "pciex")) {
1247 pci_path_component(dp, tmp_buf);
1248 return;
1249 }
1250 if (!strcmp(parent->type, "sbus")) {
1251 sbus_path_component(dp, tmp_buf);
1252 return;
1253 }
1254 if (!strcmp(parent->type, "upa")) {
1255 upa_path_component(dp, tmp_buf);
1256 return;
1257 }
1258 if (!strcmp(parent->type, "ebus")) {
1259 ebus_path_component(dp, tmp_buf);
1260 return;
1261 }
1262 if (!strcmp(parent->name, "usb") ||
1263 !strcmp(parent->name, "hub")) {
1264 usb_path_component(dp, tmp_buf);
1265 return;
1266 }
1267 if (!strcmp(parent->type, "i2c")) {
1268 i2c_path_component(dp, tmp_buf);
1269 return;
1270 }
1271 if (!strcmp(parent->type, "firewire")) {
1272 ieee1394_path_component(dp, tmp_buf);
1273 return;
1274 }
1275 if (!strcmp(parent->type, "virtual-devices")) {
1276 vdev_path_component(dp, tmp_buf);
1277 return;
1278 }
1279 /* "isa" is handled with platform naming */
1280 }
1281
1282 /* Use platform naming convention. */
1283 if (tlb_type == hypervisor) {
1284 sun4v_path_component(dp, tmp_buf);
1285 return;
1286 } else {
1287 sun4u_path_component(dp, tmp_buf);
1288 }
1289 }
1290
1291 static char * __init build_path_component(struct device_node *dp)
1292 {
1293 char tmp_buf[64], *n;
1294
1295 tmp_buf[0] = '\0';
1296 __build_path_component(dp, tmp_buf);
1297 if (tmp_buf[0] == '\0')
1298 strcpy(tmp_buf, dp->name);
1299
1300 n = prom_early_alloc(strlen(tmp_buf) + 1);
1301 strcpy(n, tmp_buf);
1302
1303 return n;
1304 }
1305
1306 static char * __init build_full_name(struct device_node *dp)
1307 {
1308 int len, ourlen, plen;
1309 char *n;
1310
1311 plen = strlen(dp->parent->full_name);
1312 ourlen = strlen(dp->path_component_name);
1313 len = ourlen + plen + 2;
1314
1315 n = prom_early_alloc(len);
1316 strcpy(n, dp->parent->full_name);
1317 if (!is_root_node(dp->parent)) {
1318 strcpy(n + plen, "/");
1319 plen++;
1320 }
1321 strcpy(n + plen, dp->path_component_name);
1322
1323 return n;
1324 }
1325
1326 static unsigned int unique_id;
1327
1328 static struct property * __init build_one_prop(phandle node, char *prev, char *special_name, void *special_val, int special_len)
1329 {
1330 static struct property *tmp = NULL;
1331 struct property *p;
1332
1333 if (tmp) {
1334 p = tmp;
1335 memset(p, 0, sizeof(*p) + 32);
1336 tmp = NULL;
1337 } else {
1338 p = prom_early_alloc(sizeof(struct property) + 32);
1339 p->unique_id = unique_id++;
1340 }
1341
1342 p->name = (char *) (p + 1);
1343 if (special_name) {
1344 strcpy(p->name, special_name);
1345 p->length = special_len;
1346 p->value = prom_early_alloc(special_len);
1347 memcpy(p->value, special_val, special_len);
1348 } else {
1349 if (prev == NULL) {
1350 prom_firstprop(node, p->name);
1351 } else {
1352 prom_nextprop(node, prev, p->name);
1353 }
1354 if (strlen(p->name) == 0) {
1355 tmp = p;
1356 return NULL;
1357 }
1358 p->length = prom_getproplen(node, p->name);
1359 if (p->length <= 0) {
1360 p->length = 0;
1361 } else {
1362 p->value = prom_early_alloc(p->length + 1);
1363 prom_getproperty(node, p->name, p->value, p->length);
1364 ((unsigned char *)p->value)[p->length] = '\0';
1365 }
1366 }
1367 return p;
1368 }
1369
1370 static struct property * __init build_prop_list(phandle node)
1371 {
1372 struct property *head, *tail;
1373
1374 head = tail = build_one_prop(node, NULL,
1375 ".node", &node, sizeof(node));
1376
1377 tail->next = build_one_prop(node, NULL, NULL, NULL, 0);
1378 tail = tail->next;
1379 while(tail) {
1380 tail->next = build_one_prop(node, tail->name,
1381 NULL, NULL, 0);
1382 tail = tail->next;
1383 }
1384
1385 return head;
1386 }
1387
1388 static char * __init get_one_property(phandle node, const char *name)
1389 {
1390 char *buf = "<NULL>";
1391 int len;
1392
1393 len = prom_getproplen(node, name);
1394 if (len > 0) {
1395 buf = prom_early_alloc(len);
1396 prom_getproperty(node, name, buf, len);
1397 }
1398
1399 return buf;
1400 }
1401
1402 static struct device_node * __init create_node(phandle node, struct device_node *parent)
1403 {
1404 struct device_node *dp;
1405
1406 if (!node)
1407 return NULL;
1408
1409 dp = prom_early_alloc(sizeof(*dp));
1410 dp->unique_id = unique_id++;
1411 dp->parent = parent;
1412
1413 kref_init(&dp->kref);
1414
1415 dp->name = get_one_property(node, "name");
1416 dp->type = get_one_property(node, "device_type");
1417 dp->node = node;
1418
1419 dp->properties = build_prop_list(node);
1420
1421 irq_trans_init(dp);
1422
1423 return dp;
1424 }
1425
1426 static struct device_node * __init build_tree(struct device_node *parent, phandle node, struct device_node ***nextp)
1427 {
1428 struct device_node *ret = NULL, *prev_sibling = NULL;
1429 struct device_node *dp;
1430
1431 while (1) {
1432 dp = create_node(node, parent);
1433 if (!dp)
1434 break;
1435
1436 if (prev_sibling)
1437 prev_sibling->sibling = dp;
1438
1439 if (!ret)
1440 ret = dp;
1441 prev_sibling = dp;
1442
1443 *(*nextp) = dp;
1444 *nextp = &dp->allnext;
1445
1446 dp->path_component_name = build_path_component(dp);
1447 dp->full_name = build_full_name(dp);
1448
1449 dp->child = build_tree(dp, prom_getchild(node), nextp);
1450
1451 node = prom_getsibling(node);
1452 }
1453
1454 return ret;
1455 }
1456
1457 static const char *get_mid_prop(void)
1458 {
1459 return (tlb_type == spitfire ? "upa-portid" : "portid");
1460 }
1461
1462 struct device_node *of_find_node_by_cpuid(int cpuid)
1463 {
1464 struct device_node *dp;
1465 const char *mid_prop = get_mid_prop();
1466
1467 for_each_node_by_type(dp, "cpu") {
1468 int id = of_getintprop_default(dp, mid_prop, -1);
1469 const char *this_mid_prop = mid_prop;
1470
1471 if (id < 0) {
1472 this_mid_prop = "cpuid";
1473 id = of_getintprop_default(dp, this_mid_prop, -1);
1474 }
1475
1476 if (id < 0) {
1477 prom_printf("OF: Serious problem, cpu lacks "
1478 "%s property", this_mid_prop);
1479 prom_halt();
1480 }
1481 if (cpuid == id)
1482 return dp;
1483 }
1484 return NULL;
1485 }
1486
1487 static void __init of_fill_in_cpu_data(void)
1488 {
1489 struct device_node *dp;
1490 const char *mid_prop = get_mid_prop();
1491
1492 ncpus_probed = 0;
1493 for_each_node_by_type(dp, "cpu") {
1494 int cpuid = of_getintprop_default(dp, mid_prop, -1);
1495 const char *this_mid_prop = mid_prop;
1496 struct device_node *portid_parent;
1497 int portid = -1;
1498
1499 portid_parent = NULL;
1500 if (cpuid < 0) {
1501 this_mid_prop = "cpuid";
1502 cpuid = of_getintprop_default(dp, this_mid_prop, -1);
1503 if (cpuid >= 0) {
1504 int limit = 2;
1505
1506 portid_parent = dp;
1507 while (limit--) {
1508 portid_parent = portid_parent->parent;
1509 if (!portid_parent)
1510 break;
1511 portid = of_getintprop_default(portid_parent,
1512 "portid", -1);
1513 if (portid >= 0)
1514 break;
1515 }
1516 }
1517 }
1518
1519 if (cpuid < 0) {
1520 prom_printf("OF: Serious problem, cpu lacks "
1521 "%s property", this_mid_prop);
1522 prom_halt();
1523 }
1524
1525 ncpus_probed++;
1526
1527 #ifdef CONFIG_SMP
1528 if (cpuid >= NR_CPUS) {
1529 printk(KERN_WARNING "Ignoring CPU %d which is "
1530 ">= NR_CPUS (%d)\n",
1531 cpuid, NR_CPUS);
1532 continue;
1533 }
1534 #else
1535 /* On uniprocessor we only want the values for the
1536 * real physical cpu the kernel booted onto, however
1537 * cpu_data() only has one entry at index 0.
1538 */
1539 if (cpuid != real_hard_smp_processor_id())
1540 continue;
1541 cpuid = 0;
1542 #endif
1543
1544 cpu_data(cpuid).clock_tick =
1545 of_getintprop_default(dp, "clock-frequency", 0);
1546
1547 if (portid_parent) {
1548 cpu_data(cpuid).dcache_size =
1549 of_getintprop_default(dp, "l1-dcache-size",
1550 16 * 1024);
1551 cpu_data(cpuid).dcache_line_size =
1552 of_getintprop_default(dp, "l1-dcache-line-size",
1553 32);
1554 cpu_data(cpuid).icache_size =
1555 of_getintprop_default(dp, "l1-icache-size",
1556 8 * 1024);
1557 cpu_data(cpuid).icache_line_size =
1558 of_getintprop_default(dp, "l1-icache-line-size",
1559 32);
1560 cpu_data(cpuid).ecache_size =
1561 of_getintprop_default(dp, "l2-cache-size", 0);
1562 cpu_data(cpuid).ecache_line_size =
1563 of_getintprop_default(dp, "l2-cache-line-size", 0);
1564 if (!cpu_data(cpuid).ecache_size ||
1565 !cpu_data(cpuid).ecache_line_size) {
1566 cpu_data(cpuid).ecache_size =
1567 of_getintprop_default(portid_parent,
1568 "l2-cache-size",
1569 (4 * 1024 * 1024));
1570 cpu_data(cpuid).ecache_line_size =
1571 of_getintprop_default(portid_parent,
1572 "l2-cache-line-size", 64);
1573 }
1574
1575 cpu_data(cpuid).core_id = portid + 1;
1576 cpu_data(cpuid).proc_id = portid;
1577 #ifdef CONFIG_SMP
1578 sparc64_multi_core = 1;
1579 #endif
1580 } else {
1581 cpu_data(cpuid).dcache_size =
1582 of_getintprop_default(dp, "dcache-size", 16 * 1024);
1583 cpu_data(cpuid).dcache_line_size =
1584 of_getintprop_default(dp, "dcache-line-size", 32);
1585
1586 cpu_data(cpuid).icache_size =
1587 of_getintprop_default(dp, "icache-size", 16 * 1024);
1588 cpu_data(cpuid).icache_line_size =
1589 of_getintprop_default(dp, "icache-line-size", 32);
1590
1591 cpu_data(cpuid).ecache_size =
1592 of_getintprop_default(dp, "ecache-size",
1593 (4 * 1024 * 1024));
1594 cpu_data(cpuid).ecache_line_size =
1595 of_getintprop_default(dp, "ecache-line-size", 64);
1596
1597 cpu_data(cpuid).core_id = 0;
1598 cpu_data(cpuid).proc_id = -1;
1599 }
1600
1601 #ifdef CONFIG_SMP
1602 cpu_set(cpuid, cpu_present_map);
1603 cpu_set(cpuid, cpu_possible_map);
1604 #endif
1605 }
1606
1607 smp_fill_in_sib_core_maps();
1608 }
1609
1610 struct device_node *of_console_device;
1611 EXPORT_SYMBOL(of_console_device);
1612
1613 char *of_console_path;
1614 EXPORT_SYMBOL(of_console_path);
1615
1616 char *of_console_options;
1617 EXPORT_SYMBOL(of_console_options);
1618
1619 static void __init of_console_init(void)
1620 {
1621 char *msg = "OF stdout device is: %s\n";
1622 struct device_node *dp;
1623 const char *type;
1624 phandle node;
1625
1626 of_console_path = prom_early_alloc(256);
1627 if (prom_ihandle2path(prom_stdout, of_console_path, 256) < 0) {
1628 prom_printf("Cannot obtain path of stdout.\n");
1629 prom_halt();
1630 }
1631 of_console_options = strrchr(of_console_path, ':');
1632 if (of_console_options) {
1633 of_console_options++;
1634 if (*of_console_options == '\0')
1635 of_console_options = NULL;
1636 }
1637
1638 node = prom_inst2pkg(prom_stdout);
1639 if (!node) {
1640 prom_printf("Cannot resolve stdout node from "
1641 "instance %08x.\n", prom_stdout);
1642 prom_halt();
1643 }
1644
1645 dp = of_find_node_by_phandle(node);
1646 type = of_get_property(dp, "device_type", NULL);
1647 if (!type) {
1648 prom_printf("Console stdout lacks device_type property.\n");
1649 prom_halt();
1650 }
1651
1652 if (strcmp(type, "display") && strcmp(type, "serial")) {
1653 prom_printf("Console device_type is neither display "
1654 "nor serial.\n");
1655 prom_halt();
1656 }
1657
1658 of_console_device = dp;
1659
1660 printk(msg, of_console_path);
1661 }
1662
1663 void __init prom_build_devicetree(void)
1664 {
1665 struct device_node **nextp;
1666
1667 allnodes = create_node(prom_root_node, NULL);
1668 allnodes->path_component_name = "";
1669 allnodes->full_name = "/";
1670
1671 nextp = &allnodes->allnext;
1672 allnodes->child = build_tree(allnodes,
1673 prom_getchild(allnodes->node),
1674 &nextp);
1675 of_console_init();
1676
1677 printk("PROM: Built device tree with %u bytes of memory.\n",
1678 prom_early_allocated);
1679
1680 if (tlb_type != hypervisor)
1681 of_fill_in_cpu_data();
1682 }
Support for the Chinese Samsung S3C2440 based development boards