arch/arm/plat-s3c24xx/pm.c

   1 /* linux/arch/arm/plat-s3c24xx/pm.c
   2  *
   3  * Copyright (c) 2004,2006 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C24XX Power Manager (Suspend-To-RAM) support
   7  *
   8  * See Documentation/arm/Samsung-S3C24XX/Suspend.txt for more information
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  23  *
  24  * Parts based on arch/arm/mach-pxa/pm.c
  25  *
  26  * Thanks to Dimitry Andric for debugging
  27 */
  28
  29 #include <linux/init.h>
  30 #include <linux/suspend.h>
  31 #include <linux/errno.h>
  32 #include <linux/time.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/crc32.h>
  35 #include <linux/ioport.h>
  36 #include <linux/serial_core.h>
  37 #include <linux/io.h>
  38
  39 #include <asm/cacheflush.h>
  40 #include <mach/hardware.h>
  41
  42 #include <plat/regs-serial.h>
  43 #include <mach/regs-clock.h>
  44 #include <mach/regs-gpio.h>
  45 #include <mach/regs-mem.h>
  46 #include <mach/regs-irq.h>
  47
  48 #include <asm/mach/time.h>
  49
  50 #include <plat/pm.h>
  51
  52 /* for external use */
  53
  54 unsigned long s3c_pm_flags;
  55
  56 #define PFX "s3c24xx-pm: "
  57
  58 static struct sleep_save core_save[] = {
  59         SAVE_ITEM(S3C2410_LOCKTIME),
  60         SAVE_ITEM(S3C2410_CLKCON),
  61
  62         /* we restore the timings here, with the proviso that the board
  63          * brings the system up in an slower, or equal frequency setting
  64          * to the original system.
  65          *
  66          * if we cannot guarantee this, then things are going to go very
  67          * wrong here, as we modify the refresh and both pll settings.
  68          */
  69
  70         SAVE_ITEM(S3C2410_BWSCON),
  71         SAVE_ITEM(S3C2410_BANKCON0),
  72         SAVE_ITEM(S3C2410_BANKCON1),
  73         SAVE_ITEM(S3C2410_BANKCON2),
  74         SAVE_ITEM(S3C2410_BANKCON3),
  75         SAVE_ITEM(S3C2410_BANKCON4),
  76         SAVE_ITEM(S3C2410_BANKCON5),
  77
  78 #ifndef CONFIG_CPU_FREQ
  79         SAVE_ITEM(S3C2410_CLKDIVN),
  80         SAVE_ITEM(S3C2410_MPLLCON),
  81         SAVE_ITEM(S3C2410_REFRESH),
  82 #endif
  83         SAVE_ITEM(S3C2410_UPLLCON),
  84         SAVE_ITEM(S3C2410_CLKSLOW),
  85 };
  86
  87 static struct gpio_sleep {
  88         void __iomem    *base;
  89         unsigned int     gpcon;
  90         unsigned int     gpdat;
  91         unsigned int     gpup;
  92 } gpio_save[] = {
  93         [0] = {
  94                 .base   = S3C2410_GPACON,
  95         },
  96         [1] = {
  97                 .base   = S3C2410_GPBCON,
  98         },
  99         [2] = {
 100                 .base   = S3C2410_GPCCON,
 101         },
 102         [3] = {
 103                 .base   = S3C2410_GPDCON,
 104         },
 105         [4] = {
 106                 .base   = S3C2410_GPECON,
 107         },
 108         [5] = {
 109                 .base   = S3C2410_GPFCON,
 110         },
 111         [6] = {
 112                 .base   = S3C2410_GPGCON,
 113         },
 114         [7] = {
 115                 .base   = S3C2410_GPHCON,
 116         },
 117 };
 118
 119 static struct sleep_save misc_save[] = {
 120         SAVE_ITEM(S3C2410_DCLKCON),
 121 };
 122
 123 #ifdef CONFIG_S3C2410_PM_DEBUG
 124
 125 #define SAVE_UART(va) \
 126         SAVE_ITEM((va) + S3C2410_ULCON), \
 127         SAVE_ITEM((va) + S3C2410_UCON), \
 128         SAVE_ITEM((va) + S3C2410_UFCON), \
 129         SAVE_ITEM((va) + S3C2410_UMCON), \
 130         SAVE_ITEM((va) + S3C2410_UBRDIV)
 131
 132 static struct sleep_save uart_save[] = {
 133         SAVE_UART(S3C24XX_VA_UART0),
 134         SAVE_UART(S3C24XX_VA_UART1),
 135 #ifndef CONFIG_CPU_S3C2400
 136         SAVE_UART(S3C24XX_VA_UART2),
 137 #endif
 138 };
 139
 140 /* debug
 141  *
 142  * we send the debug to printascii() to allow it to be seen if the
 143  * system never wakes up from the sleep
 144 */
 145
 146 extern void printascii(const char *);
 147
 148 void pm_dbg(const char *fmt, ...)
 149 {
 150         va_list va;
 151         char buff[256];
 152
 153         va_start(va, fmt);
 154         vsprintf(buff, fmt, va);
 155         va_end(va);
 156
 157         printascii(buff);
 158 }
 159
 160 static void s3c2410_pm_debug_init(void)
 161 {
 162         unsigned long tmp = __raw_readl(S3C2410_CLKCON);
 163
 164         /* re-start uart clocks */
 165         tmp |= S3C2410_CLKCON_UART0;
 166         tmp |= S3C2410_CLKCON_UART1;
 167         tmp |= S3C2410_CLKCON_UART2;
 168
 169         __raw_writel(tmp, S3C2410_CLKCON);
 170         udelay(10);
 171 }
 172
 173 #define DBG(fmt...) pm_dbg(fmt)
 174 #else
 175 #define DBG(fmt...) printk(KERN_DEBUG fmt)
 176
 177 #define s3c2410_pm_debug_init() do { } while(0)
 178
 179 static struct sleep_save uart_save[] = {};
 180 #endif
 181
 182 #if defined(CONFIG_S3C2410_PM_CHECK) && CONFIG_S3C2410_PM_CHECK_CHUNKSIZE != 0
 183
 184 /* suspend checking code...
 185  *
 186  * this next area does a set of crc checks over all the installed
 187  * memory, so the system can verify if the resume was ok.
 188  *
 189  * CONFIG_S3C2410_PM_CHECK_CHUNKSIZE defines the block-size for the CRC,
 190  * increasing it will mean that the area corrupted will be less easy to spot,
 191  * and reducing the size will cause the CRC save area to grow
 192 */
 193
 194 #define CHECK_CHUNKSIZE (CONFIG_S3C2410_PM_CHECK_CHUNKSIZE * 1024)
 195
 196 static u32 crc_size;    /* size needed for the crc block */
 197 static u32 *crcs;       /* allocated over suspend/resume */
 198
 199 typedef u32 *(run_fn_t)(struct resource *ptr, u32 *arg);
 200
 201 /* s3c2410_pm_run_res
 202  *
 203  * go thorugh the given resource list, and look for system ram
 204 */
 205
 206 static void s3c2410_pm_run_res(struct resource *ptr, run_fn_t fn, u32 *arg)
 207 {
 208         while (ptr != NULL) {
 209                 if (ptr->child != NULL)
 210                         s3c2410_pm_run_res(ptr->child, fn, arg);
 211
 212                 if ((ptr->flags & IORESOURCE_MEM) &&
 213                     strcmp(ptr->name, "System RAM") == 0) {
 214                         DBG("Found system RAM at %08lx..%08lx\n",
 215                             ptr->start, ptr->end);
 216                         arg = (fn)(ptr, arg);
 217                 }
 218
 219                 ptr = ptr->sibling;
 220         }
 221 }
 222
 223 static void s3c2410_pm_run_sysram(run_fn_t fn, u32 *arg)
 224 {
 225         s3c2410_pm_run_res(&iomem_resource, fn, arg);
 226 }
 227
 228 static u32 *s3c2410_pm_countram(struct resource *res, u32 *val)
 229 {
 230         u32 size = (u32)(res->end - res->start)+1;
 231
 232         size += CHECK_CHUNKSIZE-1;
 233         size /= CHECK_CHUNKSIZE;
 234
 235         DBG("Area %08lx..%08lx, %d blocks\n", res->start, res->end, size);
 236
 237         *val += size * sizeof(u32);
 238         return val;
 239 }
 240
 241 /* s3c2410_pm_prepare_check
 242  *
 243  * prepare the necessary information for creating the CRCs. This
 244  * must be done before the final save, as it will require memory
 245  * allocating, and thus touching bits of the kernel we do not
 246  * know about.
 247 */
 248
 249 static void s3c2410_pm_check_prepare(void)
 250 {
 251         crc_size = 0;
 252
 253         s3c2410_pm_run_sysram(s3c2410_pm_countram, &crc_size);
 254
 255         DBG("s3c2410_pm_prepare_check: %u checks needed\n", crc_size);
 256
 257         crcs = kmalloc(crc_size+4, GFP_KERNEL);
 258         if (crcs == NULL)
 259                 printk(KERN_ERR "Cannot allocated CRC save area\n");
 260 }
 261
 262 static u32 *s3c2410_pm_makecheck(struct resource *res, u32 *val)
 263 {
 264         unsigned long addr, left;
 265
 266         for (addr = res->start; addr < res->end;
 267              addr += CHECK_CHUNKSIZE) {
 268                 left = res->end - addr;
 269
 270                 if (left > CHECK_CHUNKSIZE)
 271                         left = CHECK_CHUNKSIZE;
 272
 273                 *val = crc32_le(~0, phys_to_virt(addr), left);
 274                 val++;
 275         }
 276
 277         return val;
 278 }
 279
 280 /* s3c2410_pm_check_store
 281  *
 282  * compute the CRC values for the memory blocks before the final
 283  * sleep.
 284 */
 285
 286 static void s3c2410_pm_check_store(void)
 287 {
 288         if (crcs != NULL)
 289                 s3c2410_pm_run_sysram(s3c2410_pm_makecheck, crcs);
 290 }
 291
 292 /* in_region
 293  *
 294  * return TRUE if the area defined by ptr..ptr+size contatins the
 295  * what..what+whatsz
 296 */
 297
 298 static inline int in_region(void *ptr, int size, void *what, size_t whatsz)
 299 {
 300         if ((what+whatsz) < ptr)
 301                 return 0;
 302
 303         if (what > (ptr+size))
 304                 return 0;
 305
 306         return 1;
 307 }
 308
 309 static u32 *s3c2410_pm_runcheck(struct resource *res, u32 *val)
 310 {
 311         void *save_at = phys_to_virt(s3c2410_sleep_save_phys);
 312         unsigned long addr;
 313         unsigned long left;
 314         void *ptr;
 315         u32 calc;
 316
 317         for (addr = res->start; addr < res->end;
 318              addr += CHECK_CHUNKSIZE) {
 319                 left = res->end - addr;
 320
 321                 if (left > CHECK_CHUNKSIZE)
 322                         left = CHECK_CHUNKSIZE;
 323
 324                 ptr = phys_to_virt(addr);
 325
 326                 if (in_region(ptr, left, crcs, crc_size)) {
 327                         DBG("skipping %08lx, has crc block in\n", addr);
 328                         goto skip_check;
 329                 }
 330
 331                 if (in_region(ptr, left, save_at, 32*4 )) {
 332                         DBG("skipping %08lx, has save block in\n", addr);
 333                         goto skip_check;
 334                 }
 335
 336                 /* calculate and check the checksum */
 337
 338                 calc = crc32_le(~0, ptr, left);
 339                 if (calc != *val) {
 340                         printk(KERN_ERR PFX "Restore CRC error at "
 341                                "%08lx (%08x vs %08x)\n", addr, calc, *val);
 342
 343                         DBG("Restore CRC error at %08lx (%08x vs %08x)\n",
 344                             addr, calc, *val);
 345                 }
 346
 347         skip_check:
 348                 val++;
 349         }
 350
 351         return val;
 352 }
 353
 354 /* s3c2410_pm_check_restore
 355  *
 356  * check the CRCs after the restore event and free the memory used
 357  * to hold them
 358 */
 359
 360 static void s3c2410_pm_check_restore(void)
 361 {
 362         if (crcs != NULL) {
 363                 s3c2410_pm_run_sysram(s3c2410_pm_runcheck, crcs);
 364                 kfree(crcs);
 365                 crcs = NULL;
 366         }
 367 }
 368
 369 #else
 370
 371 #define s3c2410_pm_check_prepare() do { } while(0)
 372 #define s3c2410_pm_check_restore() do { } while(0)
 373 #define s3c2410_pm_check_store()   do { } while(0)
 374 #endif
 375
 376 /* helper functions to save and restore register state */
 377
 378 void s3c2410_pm_do_save(struct sleep_save *ptr, int count)
 379 {
 380         for (; count > 0; count--, ptr++) {
 381                 ptr->val = __raw_readl(ptr->reg);
 382                 DBG("saved %p value %08lx\n", ptr->reg, ptr->val);
 383         }
 384 }
 385
 386 /* s3c2410_pm_do_restore
 387  *
 388  * restore the system from the given list of saved registers
 389  *
 390  * Note, we do not use DBG() in here, as the system may not have
 391  * restore the UARTs state yet
 392 */
 393
 394 void s3c2410_pm_do_restore(struct sleep_save *ptr, int count)
 395 {
 396         for (; count > 0; count--, ptr++) {
 397                 printk(KERN_DEBUG "restore %p (restore %08lx, was %08x)\n",
 398                        ptr->reg, ptr->val, __raw_readl(ptr->reg));
 399
 400                 __raw_writel(ptr->val, ptr->reg);
 401         }
 402 }
 403
 404 /* s3c2410_pm_do_restore_core
 405  *
 406  * similar to s3c2410_pm_do_restore_core
 407  *
 408  * WARNING: Do not put any debug in here that may effect memory or use
 409  * peripherals, as things may be changing!
 410 */
 411
 412 static void s3c2410_pm_do_restore_core(struct sleep_save *ptr, int count)
 413 {
 414         for (; count > 0; count--, ptr++) {
 415                 __raw_writel(ptr->val, ptr->reg);
 416         }
 417 }
 418
 419 /* s3c2410_pm_show_resume_irqs
 420  *
 421  * print any IRQs asserted at resume time (ie, we woke from)
 422 */
 423
 424 static void s3c2410_pm_show_resume_irqs(int start, unsigned long which,
 425                                         unsigned long mask)
 426 {
 427         int i;
 428
 429         which &= ~mask;
 430
 431         for (i = 0; i <= 31; i++) {
 432                 if ((which) & (1L<<i)) {
 433                         DBG("IRQ %d asserted at resume\n", start+i);
 434                 }
 435         }
 436 }
 437
 438 /* s3c2410_pm_check_resume_pin
 439  *
 440  * check to see if the pin is configured correctly for sleep mode, and
 441  * make any necessary adjustments if it is not
 442 */
 443
 444 static void s3c2410_pm_check_resume_pin(unsigned int pin, unsigned int irqoffs)
 445 {
 446         unsigned long irqstate;
 447         unsigned long pinstate;
 448         int irq = s3c2410_gpio_getirq(pin);
 449
 450         if (irqoffs < 4)
 451                 irqstate = s3c_irqwake_intmask & (1L<<irqoffs);
 452         else
 453                 irqstate = s3c_irqwake_eintmask & (1L<<irqoffs);
 454
 455         pinstate = s3c2410_gpio_getcfg(pin);
 456
 457         if (!irqstate) {
 458                 if (pinstate == S3C2410_GPIO_IRQ)
 459                         DBG("Leaving IRQ %d (pin %d) enabled\n", irq, pin);
 460         } else {
 461                 if (pinstate == S3C2410_GPIO_IRQ) {
 462                         DBG("Disabling IRQ %d (pin %d)\n", irq, pin);
 463                         s3c2410_gpio_cfgpin(pin, S3C2410_GPIO_INPUT);
 464                 }
 465         }
 466 }
 467
 468 /* s3c2410_pm_configure_extint
 469  *
 470  * configure all external interrupt pins
 471 */
 472
 473 static void s3c2410_pm_configure_extint(void)
 474 {
 475         int pin;
 476
 477         /* for each of the external interrupts (EINT0..EINT15) we
 478          * need to check wether it is an external interrupt source,
 479          * and then configure it as an input if it is not
 480         */
 481
 482         for (pin = S3C2410_GPF0; pin <= S3C2410_GPF7; pin++) {
 483                 s3c2410_pm_check_resume_pin(pin, pin - S3C2410_GPF0);
 484         }
 485
 486         for (pin = S3C2410_GPG0; pin <= S3C2410_GPG7; pin++) {
 487                 s3c2410_pm_check_resume_pin(pin, (pin - S3C2410_GPG0)+8);
 488         }
 489 }
 490
 491 /* offsets for CON/DAT/UP registers */
 492
 493 #define OFFS_CON        (S3C2410_GPACON - S3C2410_GPACON)
 494 #define OFFS_DAT        (S3C2410_GPADAT - S3C2410_GPACON)
 495 #define OFFS_UP         (S3C2410_GPBUP  - S3C2410_GPBCON)
 496
 497 /* s3c2410_pm_save_gpios()
 498  *
 499  * Save the state of the GPIOs
 500  */
 501
 502 static void s3c2410_pm_save_gpios(void)
 503 {
 504         struct gpio_sleep *gps = gpio_save;
 505         unsigned int gpio;
 506
 507         for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
 508                 void __iomem *base = gps->base;
 509
 510                 gps->gpcon = __raw_readl(base + OFFS_CON);
 511                 gps->gpdat = __raw_readl(base + OFFS_DAT);
 512
 513                 if (gpio > 0)
 514                         gps->gpup = __raw_readl(base + OFFS_UP);
 515
 516         }
 517 }
 518
 519 /* Test whether the given masked+shifted bits of an GPIO configuration
 520  * are one of the SFN (special function) modes. */
 521
 522 static inline int is_sfn(unsigned long con)
 523 {
 524         return (con == 2 || con == 3);
 525 }
 526
 527 /* Test if the given masked+shifted GPIO configuration is an input */
 528
 529 static inline int is_in(unsigned long con)
 530 {
 531         return con == 0;
 532 }
 533
 534 /* Test if the given masked+shifted GPIO configuration is an output */
 535
 536 static inline int is_out(unsigned long con)
 537 {
 538         return con == 1;
 539 }
 540
 541 /* s3c2410_pm_restore_gpio()
 542  *
 543  * Restore one of the GPIO banks that was saved during suspend. This is
 544  * not as simple as once thought, due to the possibility of glitches
 545  * from the order that the CON and DAT registers are set in.
 546  *
 547  * The three states the pin can be are {IN,OUT,SFN} which gives us 9
 548  * combinations of changes to check. Three of these, if the pin stays
 549  * in the same configuration can be discounted. This leaves us with
 550  * the following:
 551  *
 552  * { IN => OUT }  Change DAT first
 553  * { IN => SFN }  Change CON first
 554  * { OUT => SFN } Change CON first, so new data will not glitch
 555  * { OUT => IN }  Change CON first, so new data will not glitch
 556  * { SFN => IN }  Change CON first
 557  * { SFN => OUT } Change DAT first, so new data will not glitch [1]
 558  *
 559  * We do not currently deal with the UP registers as these control
 560  * weak resistors, so a small delay in change should not need to bring
 561  * these into the calculations.
 562  *
 563  * [1] this assumes that writing to a pin DAT whilst in SFN will set the
 564  *     state for when it is next output.
 565  */
 566
 567 static void s3c2410_pm_restore_gpio(int index, struct gpio_sleep *gps)
 568 {
 569         void __iomem *base = gps->base;
 570         unsigned long gps_gpcon = gps->gpcon;
 571         unsigned long gps_gpdat = gps->gpdat;
 572         unsigned long old_gpcon;
 573         unsigned long old_gpdat;
 574         unsigned long old_gpup = 0x0;
 575         unsigned long gpcon;
 576         int nr;
 577
 578         old_gpcon = __raw_readl(base + OFFS_CON);
 579         old_gpdat = __raw_readl(base + OFFS_DAT);
 580
 581         if (base == S3C2410_GPACON) {
 582                 /* GPACON only has one bit per control / data and no PULLUPs.
 583                  * GPACON[x] = 0 => Output, 1 => SFN */
 584
 585                 /* first set all SFN bits to SFN */
 586
 587                 gpcon = old_gpcon | gps->gpcon;
 588                 __raw_writel(gpcon, base + OFFS_CON);
 589
 590                 /* now set all the other bits */
 591
 592                 __raw_writel(gps_gpdat, base + OFFS_DAT);
 593                 __raw_writel(gps_gpcon, base + OFFS_CON);
 594         } else {
 595                 unsigned long old, new, mask;
 596                 unsigned long change_mask = 0x0;
 597
 598                 old_gpup = __raw_readl(base + OFFS_UP);
 599
 600                 /* Create a change_mask of all the items that need to have
 601                  * their CON value changed before their DAT value, so that
 602                  * we minimise the work between the two settings.
 603                  */
 604
 605                 for (nr = 0, mask = 0x03; nr < 32; nr += 2, mask <<= 2) {
 606                         old = (old_gpcon & mask) >> nr;
 607                         new = (gps_gpcon & mask) >> nr;
 608
 609                         /* If there is no change, then skip */
 610
 611                         if (old == new)
 612                                 continue;
 613
 614                         /* If both are special function, then skip */
 615
 616                         if (is_sfn(old) && is_sfn(new))
 617                                 continue;
 618
 619                         /* Change is IN => OUT, do not change now */
 620
 621                         if (is_in(old) && is_out(new))
 622                                 continue;
 623
 624                         /* Change is SFN => OUT, do not change now */
 625
 626                         if (is_sfn(old) && is_out(new))
 627                                 continue;
 628
 629                         /* We should now be at the case of IN=>SFN,
 630                          * OUT=>SFN, OUT=>IN, SFN=>IN. */
 631
 632                         change_mask |= mask;
 633                 }
 634
 635                 /* Write the new CON settings */
 636
 637                 gpcon = old_gpcon & ~change_mask;
 638                 gpcon |= gps_gpcon & change_mask;
 639
 640                 __raw_writel(gpcon, base + OFFS_CON);
 641
 642                 /* Now change any items that require DAT,CON */
 643
 644                 __raw_writel(gps_gpdat, base + OFFS_DAT);
 645                 __raw_writel(gps_gpcon, base + OFFS_CON);
 646                 __raw_writel(gps->gpup, base + OFFS_UP);
 647         }
 648
 649         DBG("GPIO[%d] CON %08lx => %08lx, DAT %08lx => %08lx\n",
 650             index, old_gpcon, gps_gpcon, old_gpdat, gps_gpdat);
 651 }
 652
 653
 654 /** s3c2410_pm_restore_gpios()
 655  *
 656  * Restore the state of the GPIOs
 657  */
 658
 659 static void s3c2410_pm_restore_gpios(void)
 660 {
 661         struct gpio_sleep *gps = gpio_save;
 662         int gpio;
 663
 664         for (gpio = 0; gpio < ARRAY_SIZE(gpio_save); gpio++, gps++) {
 665                 s3c2410_pm_restore_gpio(gpio, gps);
 666         }
 667 }
 668
 669 void (*pm_cpu_prep)(void);
 670 void (*pm_cpu_sleep)(void);
 671
 672 #define any_allowed(mask, allow) (((mask) & (allow)) != (allow))
 673
 674 /* s3c2410_pm_enter
 675  *
 676  * central control for sleep/resume process
 677 */
 678
 679 static int s3c2410_pm_enter(suspend_state_t state)
 680 {
 681         unsigned long regs_save[16];
 682
 683         /* ensure the debug is initialised (if enabled) */
 684
 685         s3c2410_pm_debug_init();
 686
 687         DBG("s3c2410_pm_enter(%d)\n", state);
 688
 689         if (pm_cpu_prep == NULL || pm_cpu_sleep == NULL) {
 690                 printk(KERN_ERR PFX "error: no cpu sleep functions set\n");
 691                 return -EINVAL;
 692         }
 693
 694         /* check if we have anything to wake-up with... bad things seem
 695          * to happen if you suspend with no wakeup (system will often
 696          * require a full power-cycle)
 697         */
 698
 699         if (!any_allowed(s3c_irqwake_intmask, s3c_irqwake_intallow) &&
 700             !any_allowed(s3c_irqwake_eintmask, s3c_irqwake_eintallow)) {
 701                 printk(KERN_ERR PFX "No sources enabled for wake-up!\n");
 702                 printk(KERN_ERR PFX "Aborting sleep\n");
 703                 return -EINVAL;
 704         }
 705
 706         /* prepare check area if configured */
 707
 708         s3c2410_pm_check_prepare();
 709
 710         /* store the physical address of the register recovery block */
 711
 712         s3c2410_sleep_save_phys = virt_to_phys(regs_save);
 713
 714         DBG("s3c2410_sleep_save_phys=0x%08lx\n", s3c2410_sleep_save_phys);
 715
 716         /* save all necessary core registers not covered by the drivers */
 717
 718         s3c2410_pm_save_gpios();
 719         s3c2410_pm_do_save(misc_save, ARRAY_SIZE(misc_save));
 720         s3c2410_pm_do_save(core_save, ARRAY_SIZE(core_save));
 721         s3c2410_pm_do_save(uart_save, ARRAY_SIZE(uart_save));
 722
 723         /* set the irq configuration for wake */
 724
 725         s3c2410_pm_configure_extint();
 726
 727         DBG("sleep: irq wakeup masks: %08lx,%08lx\n",
 728             s3c_irqwake_intmask, s3c_irqwake_eintmask);
 729
 730         __raw_writel(s3c_irqwake_intmask, S3C2410_INTMSK);
 731         __raw_writel(s3c_irqwake_eintmask, S3C2410_EINTMASK);
 732
 733         /* ack any outstanding external interrupts before we go to sleep */
 734
 735         __raw_writel(__raw_readl(S3C2410_EINTPEND), S3C2410_EINTPEND);
 736         __raw_writel(__raw_readl(S3C2410_INTPND), S3C2410_INTPND);
 737         __raw_writel(__raw_readl(S3C2410_SRCPND), S3C2410_SRCPND);
 738
 739         /* call cpu specific preparation */
 740
 741         pm_cpu_prep();
 742
 743         /* flush cache back to ram */
 744
 745         flush_cache_all();
 746
 747         s3c2410_pm_check_store();
 748
 749         /* send the cpu to sleep... */
 750
 751         __raw_writel(0x00, S3C2410_CLKCON);  /* turn off clocks over sleep */
 752
 753         /* s3c2410_cpu_save will also act as our return point from when
 754          * we resume as it saves its own register state, so use the return
 755          * code to differentiate return from save and return from sleep */
 756
 757         if (s3c2410_cpu_save(regs_save) == 0) {
 758                 flush_cache_all();
 759                 pm_cpu_sleep();
 760         }
 761
 762         /* restore the cpu state */
 763
 764         cpu_init();
 765
 766         /* restore the system state */
 767
 768         s3c2410_pm_do_restore_core(core_save, ARRAY_SIZE(core_save));
 769         s3c2410_pm_do_restore(misc_save, ARRAY_SIZE(misc_save));
 770         s3c2410_pm_do_restore(uart_save, ARRAY_SIZE(uart_save));
 771         s3c2410_pm_restore_gpios();
 772
 773         s3c2410_pm_debug_init();
 774
 775         /* check what irq (if any) restored the system */
 776
 777         DBG("post sleep: IRQs 0x%08x, 0x%08x\n",
 778             __raw_readl(S3C2410_SRCPND),
 779             __raw_readl(S3C2410_EINTPEND));
 780
 781         s3c2410_pm_show_resume_irqs(IRQ_EINT0, __raw_readl(S3C2410_SRCPND),
 782                                     s3c_irqwake_intmask);
 783
 784         s3c2410_pm_show_resume_irqs(IRQ_EINT4-4, __raw_readl(S3C2410_EINTPEND),
 785                                     s3c_irqwake_eintmask);
 786
 787         DBG("post sleep, preparing to return\n");
 788
 789         s3c2410_pm_check_restore();
 790
 791         /* ok, let's return from sleep */
 792
 793         DBG("S3C2410 PM Resume (post-restore)\n");
 794         return 0;
 795 }
 796
 797 static struct platform_suspend_ops s3c2410_pm_ops = {
 798         .enter          = s3c2410_pm_enter,
 799         .valid          = suspend_valid_only_mem,
 800 };
 801
 802 /* s3c2410_pm_init
 803  *
 804  * Attach the power management functions. This should be called
 805  * from the board specific initialisation if the board supports
 806  * it.
 807 */
 808
 809 int __init s3c2410_pm_init(void)
 810 {
 811         printk("S3C2410 Power Management, (c) 2004 Simtec Electronics\n");
 812
 813         suspend_set_ops(&s3c2410_pm_ops);
 814         return 0;
 815 }