2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/kernel_stat.h>
18 #include <linux/mc146818rtc.h>
19 #include <linux/acpi_pmtmr.h>
20 #include <linux/clockchips.h>
21 #include <linux/interrupt.h>
22 #include <linux/bootmem.h>
23 #include <linux/ftrace.h>
24 #include <linux/ioport.h>
25 #include <linux/module.h>
26 #include <linux/sysdev.h>
27 #include <linux/delay.h>
28 #include <linux/timex.h>
29 #include <linux/dmar.h>
30 #include <linux/init.h>
31 #include <linux/cpu.h>
32 #include <linux/dmi.h>
33 #include <linux/nmi.h>
34 #include <linux/smp.h>
37 #include <asm/arch_hooks.h>
38 #include <asm/pgalloc.h>
39 #include <asm/genapic.h>
40 #include <asm/atomic.h>
41 #include <asm/mpspec.h>
42 #include <asm/i8253.h>
43 #include <asm/i8259.h>
44 #include <asm/proto.h>
52 unsigned int num_processors
;
53 unsigned disabled_cpus __cpuinitdata
;
54 /* Processor that is doing the boot up */
55 unsigned int boot_cpu_physical_apicid
= -1U;
56 EXPORT_SYMBOL(boot_cpu_physical_apicid
);
57 unsigned int max_physical_apicid
;
59 /* Bitmask of physically existing CPUs */
60 physid_mask_t phys_cpu_present_map
;
63 * Map cpu index to physical APIC ID
65 DEFINE_EARLY_PER_CPU(u16
, x86_cpu_to_apicid
, BAD_APICID
);
66 DEFINE_EARLY_PER_CPU(u16
, x86_bios_cpu_apicid
, BAD_APICID
);
67 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid
);
68 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid
);
72 * Knob to control our willingness to enable the local APIC.
76 static int force_enable_local_apic
;
78 * APIC command line parameters
80 static int __init
parse_lapic(char *arg
)
82 force_enable_local_apic
= 1;
85 early_param("lapic", parse_lapic
);
86 /* Local APIC was disabled by the BIOS and enabled by the kernel */
87 static int enabled_via_apicbase
;
92 static int apic_calibrate_pmtmr __initdata
;
93 static __init
int setup_apicpmtimer(char *s
)
95 apic_calibrate_pmtmr
= 1;
99 __setup("apicpmtimer", setup_apicpmtimer
);
108 /* x2apic enabled before OS handover */
109 static int x2apic_preenabled
;
110 static int disable_x2apic
;
111 static __init
int setup_nox2apic(char *str
)
114 setup_clear_cpu_cap(X86_FEATURE_X2APIC
);
117 early_param("nox2apic", setup_nox2apic
);
120 unsigned long mp_lapic_addr
;
122 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
123 static int disable_apic_timer __cpuinitdata
;
124 /* Local APIC timer works in C2 */
125 int local_apic_timer_c2_ok
;
126 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
128 int first_system_vector
= 0xfe;
131 * Debug level, exported for io_apic.c
133 unsigned int apic_verbosity
;
137 /* Have we found an MP table */
138 int smp_found_config
;
140 static struct resource lapic_resource
= {
141 .name
= "Local APIC",
142 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
145 static unsigned int calibration_result
;
147 static int lapic_next_event(unsigned long delta
,
148 struct clock_event_device
*evt
);
149 static void lapic_timer_setup(enum clock_event_mode mode
,
150 struct clock_event_device
*evt
);
151 static void lapic_timer_broadcast(const struct cpumask
*mask
);
152 static void apic_pm_activate(void);
155 * The local apic timer can be used for any function which is CPU local.
157 static struct clock_event_device lapic_clockevent
= {
159 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
160 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
162 .set_mode
= lapic_timer_setup
,
163 .set_next_event
= lapic_next_event
,
164 .broadcast
= lapic_timer_broadcast
,
168 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
170 static unsigned long apic_phys
;
173 * Get the LAPIC version
175 static inline int lapic_get_version(void)
177 return GET_APIC_VERSION(apic_read(APIC_LVR
));
181 * Check, if the APIC is integrated or a separate chip
183 static inline int lapic_is_integrated(void)
188 return APIC_INTEGRATED(lapic_get_version());
193 * Check, whether this is a modern or a first generation APIC
195 static int modern_apic(void)
197 /* AMD systems use old APIC versions, so check the CPU */
198 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
199 boot_cpu_data
.x86
>= 0xf)
201 return lapic_get_version() >= 0x14;
205 * Paravirt kernels also might be using these below ops. So we still
206 * use generic apic_read()/apic_write(), which might be pointing to different
207 * ops in PARAVIRT case.
209 void xapic_wait_icr_idle(void)
211 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
215 u32
safe_xapic_wait_icr_idle(void)
222 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
226 } while (timeout
++ < 1000);
231 void xapic_icr_write(u32 low
, u32 id
)
233 apic_write(APIC_ICR2
, SET_APIC_DEST_FIELD(id
));
234 apic_write(APIC_ICR
, low
);
237 static u64
xapic_icr_read(void)
241 icr2
= apic_read(APIC_ICR2
);
242 icr1
= apic_read(APIC_ICR
);
244 return icr1
| ((u64
)icr2
<< 32);
247 static struct apic_ops xapic_ops
= {
248 .read
= native_apic_mem_read
,
249 .write
= native_apic_mem_write
,
250 .icr_read
= xapic_icr_read
,
251 .icr_write
= xapic_icr_write
,
252 .wait_icr_idle
= xapic_wait_icr_idle
,
253 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
256 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
257 EXPORT_SYMBOL_GPL(apic_ops
);
260 static void x2apic_wait_icr_idle(void)
262 /* no need to wait for icr idle in x2apic */
266 static u32
safe_x2apic_wait_icr_idle(void)
268 /* no need to wait for icr idle in x2apic */
272 void x2apic_icr_write(u32 low
, u32 id
)
274 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
277 static u64
x2apic_icr_read(void)
281 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
285 static struct apic_ops x2apic_ops
= {
286 .read
= native_apic_msr_read
,
287 .write
= native_apic_msr_write
,
288 .icr_read
= x2apic_icr_read
,
289 .icr_write
= x2apic_icr_write
,
290 .wait_icr_idle
= x2apic_wait_icr_idle
,
291 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
296 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
298 void __cpuinit
enable_NMI_through_LVT0(void)
302 /* unmask and set to NMI */
305 /* Level triggered for 82489DX (32bit mode) */
306 if (!lapic_is_integrated())
307 v
|= APIC_LVT_LEVEL_TRIGGER
;
309 apic_write(APIC_LVT0
, v
);
314 * get_physical_broadcast - Get number of physical broadcast IDs
316 int get_physical_broadcast(void)
318 return modern_apic() ? 0xff : 0xf;
323 * lapic_get_maxlvt - get the maximum number of local vector table entries
325 int lapic_get_maxlvt(void)
329 v
= apic_read(APIC_LVR
);
331 * - we always have APIC integrated on 64bit mode
332 * - 82489DXs do not report # of LVT entries
334 return APIC_INTEGRATED(GET_APIC_VERSION(v
)) ? GET_APIC_MAXLVT(v
) : 2;
342 #define APIC_DIVISOR 16
345 * This function sets up the local APIC timer, with a timeout of
346 * 'clocks' APIC bus clock. During calibration we actually call
347 * this function twice on the boot CPU, once with a bogus timeout
348 * value, second time for real. The other (noncalibrating) CPUs
349 * call this function only once, with the real, calibrated value.
351 * We do reads before writes even if unnecessary, to get around the
352 * P5 APIC double write bug.
354 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
356 unsigned int lvtt_value
, tmp_value
;
358 lvtt_value
= LOCAL_TIMER_VECTOR
;
360 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
361 if (!lapic_is_integrated())
362 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
365 lvtt_value
|= APIC_LVT_MASKED
;
367 apic_write(APIC_LVTT
, lvtt_value
);
372 tmp_value
= apic_read(APIC_TDCR
);
373 apic_write(APIC_TDCR
,
374 (tmp_value
& ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
)) |
378 apic_write(APIC_TMICT
, clocks
/ APIC_DIVISOR
);
382 * Setup extended LVT, AMD specific (K8, family 10h)
384 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
385 * MCE interrupts are supported. Thus MCE offset must be set to 0.
387 * If mask=1, the LVT entry does not generate interrupts while mask=0
388 * enables the vector. See also the BKDGs.
391 #define APIC_EILVT_LVTOFF_MCE 0
392 #define APIC_EILVT_LVTOFF_IBS 1
394 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
396 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
397 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
402 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
404 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
405 return APIC_EILVT_LVTOFF_MCE
;
408 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
410 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
411 return APIC_EILVT_LVTOFF_IBS
;
413 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs
);
416 * Program the next event, relative to now
418 static int lapic_next_event(unsigned long delta
,
419 struct clock_event_device
*evt
)
421 apic_write(APIC_TMICT
, delta
);
426 * Setup the lapic timer in periodic or oneshot mode
428 static void lapic_timer_setup(enum clock_event_mode mode
,
429 struct clock_event_device
*evt
)
434 /* Lapic used as dummy for broadcast ? */
435 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
438 local_irq_save(flags
);
441 case CLOCK_EVT_MODE_PERIODIC
:
442 case CLOCK_EVT_MODE_ONESHOT
:
443 __setup_APIC_LVTT(calibration_result
,
444 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
446 case CLOCK_EVT_MODE_UNUSED
:
447 case CLOCK_EVT_MODE_SHUTDOWN
:
448 v
= apic_read(APIC_LVTT
);
449 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
450 apic_write(APIC_LVTT
, v
);
451 apic_write(APIC_TMICT
, 0xffffffff);
453 case CLOCK_EVT_MODE_RESUME
:
454 /* Nothing to do here */
458 local_irq_restore(flags
);
462 * Local APIC timer broadcast function
464 static void lapic_timer_broadcast(const struct cpumask
*mask
)
467 apic
->send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
472 * Setup the local APIC timer for this CPU. Copy the initilized values
473 * of the boot CPU and register the clock event in the framework.
475 static void __cpuinit
setup_APIC_timer(void)
477 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
479 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
480 levt
->cpumask
= cpumask_of(smp_processor_id());
482 clockevents_register_device(levt
);
486 * In this functions we calibrate APIC bus clocks to the external timer.
488 * We want to do the calibration only once since we want to have local timer
489 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
492 * This was previously done by reading the PIT/HPET and waiting for a wrap
493 * around to find out, that a tick has elapsed. I have a box, where the PIT
494 * readout is broken, so it never gets out of the wait loop again. This was
495 * also reported by others.
497 * Monitoring the jiffies value is inaccurate and the clockevents
498 * infrastructure allows us to do a simple substitution of the interrupt
501 * The calibration routine also uses the pm_timer when possible, as the PIT
502 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
503 * back to normal later in the boot process).
506 #define LAPIC_CAL_LOOPS (HZ/10)
508 static __initdata
int lapic_cal_loops
= -1;
509 static __initdata
long lapic_cal_t1
, lapic_cal_t2
;
510 static __initdata
unsigned long long lapic_cal_tsc1
, lapic_cal_tsc2
;
511 static __initdata
unsigned long lapic_cal_pm1
, lapic_cal_pm2
;
512 static __initdata
unsigned long lapic_cal_j1
, lapic_cal_j2
;
515 * Temporary interrupt handler.
517 static void __init
lapic_cal_handler(struct clock_event_device
*dev
)
519 unsigned long long tsc
= 0;
520 long tapic
= apic_read(APIC_TMCCT
);
521 unsigned long pm
= acpi_pm_read_early();
526 switch (lapic_cal_loops
++) {
528 lapic_cal_t1
= tapic
;
529 lapic_cal_tsc1
= tsc
;
531 lapic_cal_j1
= jiffies
;
534 case LAPIC_CAL_LOOPS
:
535 lapic_cal_t2
= tapic
;
536 lapic_cal_tsc2
= tsc
;
537 if (pm
< lapic_cal_pm1
)
538 pm
+= ACPI_PM_OVRRUN
;
540 lapic_cal_j2
= jiffies
;
545 static int __init
calibrate_by_pmtimer(long deltapm
, long *delta
)
547 const long pm_100ms
= PMTMR_TICKS_PER_SEC
/ 10;
548 const long pm_thresh
= pm_100ms
/ 100;
552 #ifndef CONFIG_X86_PM_TIMER
556 apic_printk(APIC_VERBOSE
, "... PM timer delta = %ld\n", deltapm
);
558 /* Check, if the PM timer is available */
562 mult
= clocksource_hz2mult(PMTMR_TICKS_PER_SEC
, 22);
564 if (deltapm
> (pm_100ms
- pm_thresh
) &&
565 deltapm
< (pm_100ms
+ pm_thresh
)) {
566 apic_printk(APIC_VERBOSE
, "... PM timer result ok\n");
568 res
= (((u64
)deltapm
) * mult
) >> 22;
569 do_div(res
, 1000000);
570 pr_warning("APIC calibration not consistent "
571 "with PM Timer: %ldms instead of 100ms\n",
573 /* Correct the lapic counter value */
574 res
= (((u64
)(*delta
)) * pm_100ms
);
575 do_div(res
, deltapm
);
576 pr_info("APIC delta adjusted to PM-Timer: "
577 "%lu (%ld)\n", (unsigned long)res
, *delta
);
584 static int __init
calibrate_APIC_clock(void)
586 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
587 void (*real_handler
)(struct clock_event_device
*dev
);
588 unsigned long deltaj
;
590 int pm_referenced
= 0;
594 /* Replace the global interrupt handler */
595 real_handler
= global_clock_event
->event_handler
;
596 global_clock_event
->event_handler
= lapic_cal_handler
;
599 * Setup the APIC counter to maximum. There is no way the lapic
600 * can underflow in the 100ms detection time frame
602 __setup_APIC_LVTT(0xffffffff, 0, 0);
604 /* Let the interrupts run */
607 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
612 /* Restore the real event handler */
613 global_clock_event
->event_handler
= real_handler
;
615 /* Build delta t1-t2 as apic timer counts down */
616 delta
= lapic_cal_t1
- lapic_cal_t2
;
617 apic_printk(APIC_VERBOSE
, "... lapic delta = %ld\n", delta
);
619 /* we trust the PM based calibration if possible */
620 pm_referenced
= !calibrate_by_pmtimer(lapic_cal_pm2
- lapic_cal_pm1
,
623 /* Calculate the scaled math multiplication factor */
624 lapic_clockevent
.mult
= div_sc(delta
, TICK_NSEC
* LAPIC_CAL_LOOPS
,
625 lapic_clockevent
.shift
);
626 lapic_clockevent
.max_delta_ns
=
627 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
628 lapic_clockevent
.min_delta_ns
=
629 clockevent_delta2ns(0xF, &lapic_clockevent
);
631 calibration_result
= (delta
* APIC_DIVISOR
) / LAPIC_CAL_LOOPS
;
633 apic_printk(APIC_VERBOSE
, "..... delta %ld\n", delta
);
634 apic_printk(APIC_VERBOSE
, "..... mult: %ld\n", lapic_clockevent
.mult
);
635 apic_printk(APIC_VERBOSE
, "..... calibration result: %u\n",
639 delta
= (long)(lapic_cal_tsc2
- lapic_cal_tsc1
);
640 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
642 (delta
/ LAPIC_CAL_LOOPS
) / (1000000 / HZ
),
643 (delta
/ LAPIC_CAL_LOOPS
) % (1000000 / HZ
));
646 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
648 calibration_result
/ (1000000 / HZ
),
649 calibration_result
% (1000000 / HZ
));
652 * Do a sanity check on the APIC calibration result
654 if (calibration_result
< (1000000 / HZ
)) {
656 pr_warning("APIC frequency too slow, disabling apic timer\n");
660 levt
->features
&= ~CLOCK_EVT_FEAT_DUMMY
;
663 * PM timer calibration failed or not turned on
664 * so lets try APIC timer based calibration
666 if (!pm_referenced
) {
667 apic_printk(APIC_VERBOSE
, "... verify APIC timer\n");
670 * Setup the apic timer manually
672 levt
->event_handler
= lapic_cal_handler
;
673 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC
, levt
);
674 lapic_cal_loops
= -1;
676 /* Let the interrupts run */
679 while (lapic_cal_loops
<= LAPIC_CAL_LOOPS
)
682 /* Stop the lapic timer */
683 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, levt
);
686 deltaj
= lapic_cal_j2
- lapic_cal_j1
;
687 apic_printk(APIC_VERBOSE
, "... jiffies delta = %lu\n", deltaj
);
689 /* Check, if the jiffies result is consistent */
690 if (deltaj
>= LAPIC_CAL_LOOPS
-2 && deltaj
<= LAPIC_CAL_LOOPS
+2)
691 apic_printk(APIC_VERBOSE
, "... jiffies result ok\n");
693 levt
->features
|= CLOCK_EVT_FEAT_DUMMY
;
697 if (levt
->features
& CLOCK_EVT_FEAT_DUMMY
) {
698 pr_warning("APIC timer disabled due to verification failure\n");
706 * Setup the boot APIC
708 * Calibrate and verify the result.
710 void __init
setup_boot_APIC_clock(void)
713 * The local apic timer can be disabled via the kernel
714 * commandline or from the CPU detection code. Register the lapic
715 * timer as a dummy clock event source on SMP systems, so the
716 * broadcast mechanism is used. On UP systems simply ignore it.
718 if (disable_apic_timer
) {
719 pr_info("Disabling APIC timer\n");
720 /* No broadcast on UP ! */
721 if (num_possible_cpus() > 1) {
722 lapic_clockevent
.mult
= 1;
728 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n"
729 "calibrating APIC timer ...\n");
731 if (calibrate_APIC_clock()) {
732 /* No broadcast on UP ! */
733 if (num_possible_cpus() > 1)
739 * If nmi_watchdog is set to IO_APIC, we need the
740 * PIT/HPET going. Otherwise register lapic as a dummy
743 if (nmi_watchdog
!= NMI_IO_APIC
)
744 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
746 pr_warning("APIC timer registered as dummy,"
747 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
749 /* Setup the lapic or request the broadcast */
753 void __cpuinit
setup_secondary_APIC_clock(void)
759 * The guts of the apic timer interrupt
761 static void local_apic_timer_interrupt(void)
763 int cpu
= smp_processor_id();
764 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
767 * Normally we should not be here till LAPIC has been initialized but
768 * in some cases like kdump, its possible that there is a pending LAPIC
769 * timer interrupt from previous kernel's context and is delivered in
770 * new kernel the moment interrupts are enabled.
772 * Interrupts are enabled early and LAPIC is setup much later, hence
773 * its possible that when we get here evt->event_handler is NULL.
774 * Check for event_handler being NULL and discard the interrupt as
777 if (!evt
->event_handler
) {
778 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
780 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
785 * the NMI deadlock-detector uses this.
787 inc_irq_stat(apic_timer_irqs
);
789 evt
->event_handler(evt
);
793 * Local APIC timer interrupt. This is the most natural way for doing
794 * local interrupts, but local timer interrupts can be emulated by
795 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
797 * [ if a single-CPU system runs an SMP kernel then we call the local
798 * interrupt as well. Thus we cannot inline the local irq ... ]
800 void __irq_entry
smp_apic_timer_interrupt(struct pt_regs
*regs
)
802 struct pt_regs
*old_regs
= set_irq_regs(regs
);
805 * NOTE! We'd better ACK the irq immediately,
806 * because timer handling can be slow.
810 * update_process_times() expects us to have done irq_enter().
811 * Besides, if we don't timer interrupts ignore the global
812 * interrupt lock, which is the WrongThing (tm) to do.
816 local_apic_timer_interrupt();
819 set_irq_regs(old_regs
);
822 int setup_profiling_timer(unsigned int multiplier
)
828 * Local APIC start and shutdown
832 * clear_local_APIC - shutdown the local APIC
834 * This is called, when a CPU is disabled and before rebooting, so the state of
835 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
836 * leftovers during boot.
838 void clear_local_APIC(void)
843 /* APIC hasn't been mapped yet */
847 maxlvt
= lapic_get_maxlvt();
849 * Masking an LVT entry can trigger a local APIC error
850 * if the vector is zero. Mask LVTERR first to prevent this.
853 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
854 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
857 * Careful: we have to set masks only first to deassert
858 * any level-triggered sources.
860 v
= apic_read(APIC_LVTT
);
861 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
862 v
= apic_read(APIC_LVT0
);
863 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
864 v
= apic_read(APIC_LVT1
);
865 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
867 v
= apic_read(APIC_LVTPC
);
868 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
871 /* lets not touch this if we didn't frob it */
872 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
874 v
= apic_read(APIC_LVTTHMR
);
875 apic_write(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
879 * Clean APIC state for other OSs:
881 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
882 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
883 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
885 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
887 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
889 /* Integrated APIC (!82489DX) ? */
890 if (lapic_is_integrated()) {
892 /* Clear ESR due to Pentium errata 3AP and 11AP */
893 apic_write(APIC_ESR
, 0);
899 * disable_local_APIC - clear and disable the local APIC
901 void disable_local_APIC(void)
905 /* APIC hasn't been mapped yet */
912 * Disable APIC (implies clearing of registers
915 value
= apic_read(APIC_SPIV
);
916 value
&= ~APIC_SPIV_APIC_ENABLED
;
917 apic_write(APIC_SPIV
, value
);
921 * When LAPIC was disabled by the BIOS and enabled by the kernel,
922 * restore the disabled state.
924 if (enabled_via_apicbase
) {
927 rdmsr(MSR_IA32_APICBASE
, l
, h
);
928 l
&= ~MSR_IA32_APICBASE_ENABLE
;
929 wrmsr(MSR_IA32_APICBASE
, l
, h
);
935 * If Linux enabled the LAPIC against the BIOS default disable it down before
936 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
937 * not power-off. Additionally clear all LVT entries before disable_local_APIC
938 * for the case where Linux didn't enable the LAPIC.
940 void lapic_shutdown(void)
947 local_irq_save(flags
);
950 if (!enabled_via_apicbase
)
954 disable_local_APIC();
957 local_irq_restore(flags
);
961 * This is to verify that we're looking at a real local APIC.
962 * Check these against your board if the CPUs aren't getting
963 * started for no apparent reason.
965 int __init
verify_local_APIC(void)
967 unsigned int reg0
, reg1
;
970 * The version register is read-only in a real APIC.
972 reg0
= apic_read(APIC_LVR
);
973 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
974 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
975 reg1
= apic_read(APIC_LVR
);
976 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
979 * The two version reads above should print the same
980 * numbers. If the second one is different, then we
981 * poke at a non-APIC.
987 * Check if the version looks reasonably.
989 reg1
= GET_APIC_VERSION(reg0
);
990 if (reg1
== 0x00 || reg1
== 0xff)
992 reg1
= lapic_get_maxlvt();
993 if (reg1
< 0x02 || reg1
== 0xff)
997 * The ID register is read/write in a real APIC.
999 reg0
= apic_read(APIC_ID
);
1000 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
1001 apic_write(APIC_ID
, reg0
^ apic
->apic_id_mask
);
1002 reg1
= apic_read(APIC_ID
);
1003 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
1004 apic_write(APIC_ID
, reg0
);
1005 if (reg1
!= (reg0
^ apic
->apic_id_mask
))
1009 * The next two are just to see if we have sane values.
1010 * They're only really relevant if we're in Virtual Wire
1011 * compatibility mode, but most boxes are anymore.
1013 reg0
= apic_read(APIC_LVT0
);
1014 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
1015 reg1
= apic_read(APIC_LVT1
);
1016 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
1022 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1024 void __init
sync_Arb_IDs(void)
1027 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1030 if (modern_apic() || boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
)
1036 apic_wait_icr_idle();
1038 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
1039 apic_write(APIC_ICR
, APIC_DEST_ALLINC
|
1040 APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
1044 * An initial setup of the virtual wire mode.
1046 void __init
init_bsp_APIC(void)
1051 * Don't do the setup now if we have a SMP BIOS as the
1052 * through-I/O-APIC virtual wire mode might be active.
1054 if (smp_found_config
|| !cpu_has_apic
)
1058 * Do not trust the local APIC being empty at bootup.
1065 value
= apic_read(APIC_SPIV
);
1066 value
&= ~APIC_VECTOR_MASK
;
1067 value
|= APIC_SPIV_APIC_ENABLED
;
1069 #ifdef CONFIG_X86_32
1070 /* This bit is reserved on P4/Xeon and should be cleared */
1071 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) &&
1072 (boot_cpu_data
.x86
== 15))
1073 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1076 value
|= APIC_SPIV_FOCUS_DISABLED
;
1077 value
|= SPURIOUS_APIC_VECTOR
;
1078 apic_write(APIC_SPIV
, value
);
1081 * Set up the virtual wire mode.
1083 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
1084 value
= APIC_DM_NMI
;
1085 if (!lapic_is_integrated()) /* 82489DX */
1086 value
|= APIC_LVT_LEVEL_TRIGGER
;
1087 apic_write(APIC_LVT1
, value
);
1090 static void __cpuinit
lapic_setup_esr(void)
1092 unsigned int oldvalue
, value
, maxlvt
;
1094 if (!lapic_is_integrated()) {
1095 pr_info("No ESR for 82489DX.\n");
1099 if (apic
->disable_esr
) {
1101 * Something untraceable is creating bad interrupts on
1102 * secondary quads ... for the moment, just leave the
1103 * ESR disabled - we can't do anything useful with the
1104 * errors anyway - mbligh
1106 pr_info("Leaving ESR disabled.\n");
1110 maxlvt
= lapic_get_maxlvt();
1111 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1112 apic_write(APIC_ESR
, 0);
1113 oldvalue
= apic_read(APIC_ESR
);
1115 /* enables sending errors */
1116 value
= ERROR_APIC_VECTOR
;
1117 apic_write(APIC_LVTERR
, value
);
1120 * spec says clear errors after enabling vector.
1123 apic_write(APIC_ESR
, 0);
1124 value
= apic_read(APIC_ESR
);
1125 if (value
!= oldvalue
)
1126 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
1127 "vector: 0x%08x after: 0x%08x\n",
1133 * setup_local_APIC - setup the local APIC
1135 void __cpuinit
setup_local_APIC(void)
1141 #ifdef CONFIG_X86_IO_APIC
1142 disable_ioapic_setup();
1147 #ifdef CONFIG_X86_32
1148 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1149 if (lapic_is_integrated() && apic
->disable_esr
) {
1150 apic_write(APIC_ESR
, 0);
1151 apic_write(APIC_ESR
, 0);
1152 apic_write(APIC_ESR
, 0);
1153 apic_write(APIC_ESR
, 0);
1160 * Double-check whether this APIC is really registered.
1161 * This is meaningless in clustered apic mode, so we skip it.
1163 if (!apic
->apic_id_registered())
1167 * Intel recommends to set DFR, LDR and TPR before enabling
1168 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1169 * document number 292116). So here it goes...
1171 apic
->init_apic_ldr();
1174 * Set Task Priority to 'accept all'. We never change this
1177 value
= apic_read(APIC_TASKPRI
);
1178 value
&= ~APIC_TPRI_MASK
;
1179 apic_write(APIC_TASKPRI
, value
);
1182 * After a crash, we no longer service the interrupts and a pending
1183 * interrupt from previous kernel might still have ISR bit set.
1185 * Most probably by now CPU has serviced that pending interrupt and
1186 * it might not have done the ack_APIC_irq() because it thought,
1187 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1188 * does not clear the ISR bit and cpu thinks it has already serivced
1189 * the interrupt. Hence a vector might get locked. It was noticed
1190 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1192 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
1193 value
= apic_read(APIC_ISR
+ i
*0x10);
1194 for (j
= 31; j
>= 0; j
--) {
1201 * Now that we are all set up, enable the APIC
1203 value
= apic_read(APIC_SPIV
);
1204 value
&= ~APIC_VECTOR_MASK
;
1208 value
|= APIC_SPIV_APIC_ENABLED
;
1210 #ifdef CONFIG_X86_32
1212 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1213 * certain networking cards. If high frequency interrupts are
1214 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1215 * entry is masked/unmasked at a high rate as well then sooner or
1216 * later IOAPIC line gets 'stuck', no more interrupts are received
1217 * from the device. If focus CPU is disabled then the hang goes
1220 * [ This bug can be reproduced easily with a level-triggered
1221 * PCI Ne2000 networking cards and PII/PIII processors, dual
1225 * Actually disabling the focus CPU check just makes the hang less
1226 * frequent as it makes the interrupt distributon model be more
1227 * like LRU than MRU (the short-term load is more even across CPUs).
1228 * See also the comment in end_level_ioapic_irq(). --macro
1232 * - enable focus processor (bit==0)
1233 * - 64bit mode always use processor focus
1234 * so no need to set it
1236 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
1240 * Set spurious IRQ vector
1242 value
|= SPURIOUS_APIC_VECTOR
;
1243 apic_write(APIC_SPIV
, value
);
1246 * Set up LVT0, LVT1:
1248 * set up through-local-APIC on the BP's LINT0. This is not
1249 * strictly necessary in pure symmetric-IO mode, but sometimes
1250 * we delegate interrupts to the 8259A.
1253 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1255 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
1256 if (!smp_processor_id() && (pic_mode
|| !value
)) {
1257 value
= APIC_DM_EXTINT
;
1258 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
1259 smp_processor_id());
1261 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
1262 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
1263 smp_processor_id());
1265 apic_write(APIC_LVT0
, value
);
1268 * only the BP should see the LINT1 NMI signal, obviously.
1270 if (!smp_processor_id())
1271 value
= APIC_DM_NMI
;
1273 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
1274 if (!lapic_is_integrated()) /* 82489DX */
1275 value
|= APIC_LVT_LEVEL_TRIGGER
;
1276 apic_write(APIC_LVT1
, value
);
1281 void __cpuinit
end_local_APIC_setup(void)
1285 #ifdef CONFIG_X86_32
1288 /* Disable the local apic timer */
1289 value
= apic_read(APIC_LVTT
);
1290 value
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1291 apic_write(APIC_LVTT
, value
);
1295 setup_apic_nmi_watchdog(NULL
);
1300 void check_x2apic(void)
1304 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1306 if (msr
& X2APIC_ENABLE
) {
1307 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n");
1308 x2apic_preenabled
= x2apic
= 1;
1309 apic_ops
= &x2apic_ops
;
1313 void enable_x2apic(void)
1317 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
1318 if (!(msr
& X2APIC_ENABLE
)) {
1319 pr_info("Enabling x2apic\n");
1320 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
1324 void __init
enable_IR_x2apic(void)
1326 #ifdef CONFIG_INTR_REMAP
1328 unsigned long flags
;
1330 if (!cpu_has_x2apic
)
1333 if (!x2apic_preenabled
&& disable_x2apic
) {
1334 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1335 "because of nox2apic\n");
1339 if (x2apic_preenabled
&& disable_x2apic
)
1340 panic("Bios already enabled x2apic, can't enforce nox2apic");
1342 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
1343 pr_info("Skipped enabling x2apic and Interrupt-remapping "
1344 "because of skipping io-apic setup\n");
1348 ret
= dmar_table_init();
1350 pr_info("dmar_table_init() failed with %d:\n", ret
);
1352 if (x2apic_preenabled
)
1353 panic("x2apic enabled by bios. But IR enabling failed");
1355 pr_info("Not enabling x2apic,Intr-remapping\n");
1359 local_irq_save(flags
);
1362 ret
= save_mask_IO_APIC_setup();
1364 pr_info("Saving IO-APIC state failed: %d\n", ret
);
1368 ret
= enable_intr_remapping(1);
1370 if (ret
&& x2apic_preenabled
) {
1371 local_irq_restore(flags
);
1372 panic("x2apic enabled by bios. But IR enabling failed");
1380 apic_ops
= &x2apic_ops
;
1387 * IR enabling failed
1389 restore_IO_APIC_setup();
1391 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
1395 local_irq_restore(flags
);
1398 if (!x2apic_preenabled
)
1399 pr_info("Enabled x2apic and interrupt-remapping\n");
1401 pr_info("Enabled Interrupt-remapping\n");
1403 pr_err("Failed to enable Interrupt-remapping and x2apic\n");
1405 if (!cpu_has_x2apic
)
1408 if (x2apic_preenabled
)
1409 panic("x2apic enabled prior OS handover,"
1410 " enable CONFIG_INTR_REMAP");
1412 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1418 #endif /* HAVE_X2APIC */
1420 #ifdef CONFIG_X86_64
1422 * Detect and enable local APICs on non-SMP boards.
1423 * Original code written by Keir Fraser.
1424 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1425 * not correctly set up (usually the APIC timer won't work etc.)
1427 static int __init
detect_init_APIC(void)
1429 if (!cpu_has_apic
) {
1430 pr_info("No local APIC present\n");
1434 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1435 boot_cpu_physical_apicid
= 0;
1440 * Detect and initialize APIC
1442 static int __init
detect_init_APIC(void)
1446 /* Disabled by kernel option? */
1450 switch (boot_cpu_data
.x86_vendor
) {
1451 case X86_VENDOR_AMD
:
1452 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
1453 (boot_cpu_data
.x86
== 15))
1456 case X86_VENDOR_INTEL
:
1457 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
1458 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
1465 if (!cpu_has_apic
) {
1467 * Over-ride BIOS and try to enable the local APIC only if
1468 * "lapic" specified.
1470 if (!force_enable_local_apic
) {
1471 pr_info("Local APIC disabled by BIOS -- "
1472 "you can enable it with \"lapic\"\n");
1476 * Some BIOSes disable the local APIC in the APIC_BASE
1477 * MSR. This can only be done in software for Intel P6 or later
1478 * and AMD K7 (Model > 1) or later.
1480 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1481 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
1482 pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1483 l
&= ~MSR_IA32_APICBASE_BASE
;
1484 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
1485 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1486 enabled_via_apicbase
= 1;
1490 * The APIC feature bit should now be enabled
1493 features
= cpuid_edx(1);
1494 if (!(features
& (1 << X86_FEATURE_APIC
))) {
1495 pr_warning("Could not enable APIC!\n");
1498 set_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1499 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1501 /* The BIOS may have set up the APIC at some other address */
1502 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1503 if (l
& MSR_IA32_APICBASE_ENABLE
)
1504 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
1506 pr_info("Found and enabled local APIC!\n");
1513 pr_info("No local APIC present or hardware disabled\n");
1518 #ifdef CONFIG_X86_64
1519 void __init
early_init_lapic_mapping(void)
1521 unsigned long phys_addr
;
1524 * If no local APIC can be found then go out
1525 * : it means there is no mpatable and MADT
1527 if (!smp_found_config
)
1530 phys_addr
= mp_lapic_addr
;
1532 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1533 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1534 APIC_BASE
, phys_addr
);
1537 * Fetch the APIC ID of the BSP in case we have a
1538 * default configuration (or the MP table is broken).
1540 boot_cpu_physical_apicid
= read_apic_id();
1545 * init_apic_mappings - initialize APIC mappings
1547 void __init
init_apic_mappings(void)
1551 boot_cpu_physical_apicid
= read_apic_id();
1557 * If no local APIC can be found then set up a fake all
1558 * zeroes page to simulate the local APIC and another
1559 * one for the IO-APIC.
1561 if (!smp_found_config
&& detect_init_APIC()) {
1562 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1563 apic_phys
= __pa(apic_phys
);
1565 apic_phys
= mp_lapic_addr
;
1567 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1568 apic_printk(APIC_VERBOSE
, "mapped APIC to %08lx (%08lx)\n",
1569 APIC_BASE
, apic_phys
);
1572 * Fetch the APIC ID of the BSP in case we have a
1573 * default configuration (or the MP table is broken).
1575 if (boot_cpu_physical_apicid
== -1U)
1576 boot_cpu_physical_apicid
= read_apic_id();
1580 * This initializes the IO-APIC and APIC hardware if this is
1583 int apic_version
[MAX_APICS
];
1585 int __init
APIC_init_uniprocessor(void)
1588 pr_info("Apic disabled\n");
1591 #ifdef CONFIG_X86_64
1592 if (!cpu_has_apic
) {
1594 pr_info("Apic disabled by BIOS\n");
1598 if (!smp_found_config
&& !cpu_has_apic
)
1602 * Complain if the BIOS pretends there is one.
1604 if (!cpu_has_apic
&&
1605 APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1606 pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
1607 boot_cpu_physical_apicid
);
1608 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_APIC
);
1616 #ifdef CONFIG_X86_64
1617 default_setup_apic_routing();
1620 verify_local_APIC();
1623 #ifdef CONFIG_X86_64
1624 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1627 * Hack: In case of kdump, after a crash, kernel might be booting
1628 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1629 * might be zero if read from MP tables. Get it from LAPIC.
1631 # ifdef CONFIG_CRASH_DUMP
1632 boot_cpu_physical_apicid
= read_apic_id();
1635 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1638 #ifdef CONFIG_X86_64
1640 * Now enable IO-APICs, actually call clear_IO_APIC
1641 * We need clear_IO_APIC before enabling vector on BP
1643 if (!skip_ioapic_setup
&& nr_ioapics
)
1647 #ifdef CONFIG_X86_IO_APIC
1648 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1650 localise_nmi_watchdog();
1651 end_local_APIC_setup();
1653 #ifdef CONFIG_X86_IO_APIC
1654 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1656 # ifdef CONFIG_X86_64
1662 #ifdef CONFIG_X86_64
1663 setup_boot_APIC_clock();
1664 check_nmi_watchdog();
1673 * Local APIC interrupts
1677 * This interrupt should _never_ happen with our APIC/SMP architecture
1679 void smp_spurious_interrupt(struct pt_regs
*regs
)
1686 * Check if this really is a spurious interrupt and ACK it
1687 * if it is a vectored one. Just in case...
1688 * Spurious interrupts should not be ACKed.
1690 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1691 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1694 inc_irq_stat(irq_spurious_count
);
1696 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1697 pr_info("spurious APIC interrupt on CPU#%d, "
1698 "should never happen.\n", smp_processor_id());
1703 * This interrupt should never happen with our APIC/SMP architecture
1705 void smp_error_interrupt(struct pt_regs
*regs
)
1711 /* First tickle the hardware, only then report what went on. -- REW */
1712 v
= apic_read(APIC_ESR
);
1713 apic_write(APIC_ESR
, 0);
1714 v1
= apic_read(APIC_ESR
);
1716 atomic_inc(&irq_err_count
);
1719 * Here is what the APIC error bits mean:
1721 * 1: Receive CS error
1722 * 2: Send accept error
1723 * 3: Receive accept error
1725 * 5: Send illegal vector
1726 * 6: Received illegal vector
1727 * 7: Illegal register address
1729 pr_debug("APIC error on CPU%d: %02x(%02x)\n",
1730 smp_processor_id(), v
, v1
);
1735 * connect_bsp_APIC - attach the APIC to the interrupt system
1737 void __init
connect_bsp_APIC(void)
1739 #ifdef CONFIG_X86_32
1742 * Do not trust the local APIC being empty at bootup.
1746 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1747 * local APIC to INT and NMI lines.
1749 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
1750 "enabling APIC mode.\n");
1755 if (apic
->enable_apic_mode
)
1756 apic
->enable_apic_mode();
1760 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1761 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1763 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1766 void disconnect_bsp_APIC(int virt_wire_setup
)
1770 #ifdef CONFIG_X86_32
1773 * Put the board back into PIC mode (has an effect only on
1774 * certain older boards). Note that APIC interrupts, including
1775 * IPIs, won't work beyond this point! The only exception are
1778 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
1779 "entering PIC mode.\n");
1786 /* Go back to Virtual Wire compatibility mode */
1788 /* For the spurious interrupt use vector F, and enable it */
1789 value
= apic_read(APIC_SPIV
);
1790 value
&= ~APIC_VECTOR_MASK
;
1791 value
|= APIC_SPIV_APIC_ENABLED
;
1793 apic_write(APIC_SPIV
, value
);
1795 if (!virt_wire_setup
) {
1797 * For LVT0 make it edge triggered, active high,
1798 * external and enabled
1800 value
= apic_read(APIC_LVT0
);
1801 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1802 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1803 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1804 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1805 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1806 apic_write(APIC_LVT0
, value
);
1809 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1813 * For LVT1 make it edge triggered, active high,
1816 value
= apic_read(APIC_LVT1
);
1817 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1818 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1819 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1820 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1821 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1822 apic_write(APIC_LVT1
, value
);
1825 void __cpuinit
generic_processor_info(int apicid
, int version
)
1832 if (version
== 0x0) {
1833 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! "
1834 "fixing up to 0x10. (tell your hw vendor)\n",
1838 apic_version
[apicid
] = version
;
1840 if (num_processors
>= nr_cpu_ids
) {
1841 int max
= nr_cpu_ids
;
1842 int thiscpu
= max
+ disabled_cpus
;
1845 "ACPI: NR_CPUS/possible_cpus limit of %i reached."
1846 " Processor %d/0x%x ignored.\n", max
, thiscpu
, apicid
);
1853 cpu
= cpumask_next_zero(-1, cpu_present_mask
);
1855 if (version
!= apic_version
[boot_cpu_physical_apicid
])
1857 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n",
1858 apic_version
[boot_cpu_physical_apicid
], cpu
, version
);
1860 physid_set(apicid
, phys_cpu_present_map
);
1861 if (apicid
== boot_cpu_physical_apicid
) {
1863 * x86_bios_cpu_apicid is required to have processors listed
1864 * in same order as logical cpu numbers. Hence the first
1865 * entry is BSP, and so on.
1869 if (apicid
> max_physical_apicid
)
1870 max_physical_apicid
= apicid
;
1872 #ifdef CONFIG_X86_32
1874 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1875 * but we need to work other dependencies like SMP_SUSPEND etc
1876 * before this can be done without some confusion.
1877 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1878 * - Ashok Raj <ashok.raj@intel.com>
1880 if (max_physical_apicid
>= 8) {
1881 switch (boot_cpu_data
.x86_vendor
) {
1882 case X86_VENDOR_INTEL
:
1883 if (!APIC_XAPIC(version
)) {
1887 /* If P4 and above fall through */
1888 case X86_VENDOR_AMD
:
1894 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
1895 early_per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1896 early_per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1899 set_cpu_possible(cpu
, true);
1900 set_cpu_present(cpu
, true);
1903 int hard_smp_processor_id(void)
1905 return read_apic_id();
1908 void default_init_apic_ldr(void)
1912 apic_write(APIC_DFR
, APIC_DFR_VALUE
);
1913 val
= apic_read(APIC_LDR
) & ~APIC_LDR_MASK
;
1914 val
|= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
1915 apic_write(APIC_LDR
, val
);
1918 #ifdef CONFIG_X86_32
1919 int default_apicid_to_node(int logical_apicid
)
1922 return apicid_2_node
[hard_smp_processor_id()];
1936 * 'active' is true if the local APIC was enabled by us and
1937 * not the BIOS; this signifies that we are also responsible
1938 * for disabling it before entering apm/acpi suspend
1941 /* r/w apic fields */
1942 unsigned int apic_id
;
1943 unsigned int apic_taskpri
;
1944 unsigned int apic_ldr
;
1945 unsigned int apic_dfr
;
1946 unsigned int apic_spiv
;
1947 unsigned int apic_lvtt
;
1948 unsigned int apic_lvtpc
;
1949 unsigned int apic_lvt0
;
1950 unsigned int apic_lvt1
;
1951 unsigned int apic_lvterr
;
1952 unsigned int apic_tmict
;
1953 unsigned int apic_tdcr
;
1954 unsigned int apic_thmr
;
1957 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1959 unsigned long flags
;
1962 if (!apic_pm_state
.active
)
1965 maxlvt
= lapic_get_maxlvt();
1967 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1968 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1969 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1970 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1971 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1972 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1974 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1975 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1976 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1977 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1978 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1979 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1980 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
1982 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1985 local_irq_save(flags
);
1986 disable_local_APIC();
1987 local_irq_restore(flags
);
1991 static int lapic_resume(struct sys_device
*dev
)
1994 unsigned long flags
;
1997 if (!apic_pm_state
.active
)
2000 maxlvt
= lapic_get_maxlvt();
2002 local_irq_save(flags
);
2011 * Make sure the APICBASE points to the right address
2013 * FIXME! This will be wrong if we ever support suspend on
2014 * SMP! We'll need to do this as part of the CPU restore!
2016 rdmsr(MSR_IA32_APICBASE
, l
, h
);
2017 l
&= ~MSR_IA32_APICBASE_BASE
;
2018 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
2019 wrmsr(MSR_IA32_APICBASE
, l
, h
);
2022 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
2023 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
2024 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
2025 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
2026 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
2027 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
2028 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
2029 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
2030 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2032 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
2035 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
2036 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
2037 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
2038 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
2039 apic_write(APIC_ESR
, 0);
2040 apic_read(APIC_ESR
);
2041 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
2042 apic_write(APIC_ESR
, 0);
2043 apic_read(APIC_ESR
);
2045 local_irq_restore(flags
);
2051 * This device has no shutdown method - fully functioning local APICs
2052 * are needed on every CPU up until machine_halt/restart/poweroff.
2055 static struct sysdev_class lapic_sysclass
= {
2057 .resume
= lapic_resume
,
2058 .suspend
= lapic_suspend
,
2061 static struct sys_device device_lapic
= {
2063 .cls
= &lapic_sysclass
,
2066 static void __cpuinit
apic_pm_activate(void)
2068 apic_pm_state
.active
= 1;
2071 static int __init
init_lapic_sysfs(void)
2077 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2079 error
= sysdev_class_register(&lapic_sysclass
);
2081 error
= sysdev_register(&device_lapic
);
2084 device_initcall(init_lapic_sysfs
);
2086 #else /* CONFIG_PM */
2088 static void apic_pm_activate(void) { }
2090 #endif /* CONFIG_PM */
2092 #ifdef CONFIG_X86_64
2094 * apic_is_clustered_box() -- Check if we can expect good TSC
2096 * Thus far, the major user of this is IBM's Summit2 series:
2098 * Clustered boxes may have unsynced TSC problems if they are
2099 * multi-chassis. Use available data to take a good guess.
2100 * If in doubt, go HPET.
2102 __cpuinit
int apic_is_clustered_box(void)
2104 int i
, clusters
, zeros
;
2106 u16
*bios_cpu_apicid
;
2107 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
2110 * there is not this kind of box with AMD CPU yet.
2111 * Some AMD box with quadcore cpu and 8 sockets apicid
2112 * will be [4, 0x23] or [8, 0x27] could be thought to
2113 * vsmp box still need checking...
2115 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
2118 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
2119 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
2121 for (i
= 0; i
< nr_cpu_ids
; i
++) {
2122 /* are we being called early in kernel startup? */
2123 if (bios_cpu_apicid
) {
2124 id
= bios_cpu_apicid
[i
];
2125 } else if (i
< nr_cpu_ids
) {
2127 id
= per_cpu(x86_bios_cpu_apicid
, i
);
2133 if (id
!= BAD_APICID
)
2134 __set_bit(APIC_CLUSTERID(id
), clustermap
);
2137 /* Problem: Partially populated chassis may not have CPUs in some of
2138 * the APIC clusters they have been allocated. Only present CPUs have
2139 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2140 * Since clusters are allocated sequentially, count zeros only if
2141 * they are bounded by ones.
2145 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
2146 if (test_bit(i
, clustermap
)) {
2147 clusters
+= 1 + zeros
;
2153 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2154 * not guaranteed to be synced between boards
2156 if (is_vsmp_box() && clusters
> 1)
2160 * If clusters > 2, then should be multi-chassis.
2161 * May have to revisit this when multi-core + hyperthreaded CPUs come
2162 * out, but AFAIK this will work even for them.
2164 return (clusters
> 2);
2169 * APIC command line parameters
2171 static int __init
setup_disableapic(char *arg
)
2174 setup_clear_cpu_cap(X86_FEATURE_APIC
);
2177 early_param("disableapic", setup_disableapic
);
2179 /* same as disableapic, for compatibility */
2180 static int __init
setup_nolapic(char *arg
)
2182 return setup_disableapic(arg
);
2184 early_param("nolapic", setup_nolapic
);
2186 static int __init
parse_lapic_timer_c2_ok(char *arg
)
2188 local_apic_timer_c2_ok
= 1;
2191 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
2193 static int __init
parse_disable_apic_timer(char *arg
)
2195 disable_apic_timer
= 1;
2198 early_param("noapictimer", parse_disable_apic_timer
);
2200 static int __init
parse_nolapic_timer(char *arg
)
2202 disable_apic_timer
= 1;
2205 early_param("nolapic_timer", parse_nolapic_timer
);
2207 static int __init
apic_set_verbosity(char *arg
)
2210 #ifdef CONFIG_X86_64
2211 skip_ioapic_setup
= 0;
2217 if (strcmp("debug", arg
) == 0)
2218 apic_verbosity
= APIC_DEBUG
;
2219 else if (strcmp("verbose", arg
) == 0)
2220 apic_verbosity
= APIC_VERBOSE
;
2222 pr_warning("APIC Verbosity level %s not recognised"
2223 " use apic=verbose or apic=debug\n", arg
);
2229 early_param("apic", apic_set_verbosity
);
2231 static int __init
lapic_insert_resource(void)
2236 /* Put local APIC into the resource map. */
2237 lapic_resource
.start
= apic_phys
;
2238 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
2239 insert_resource(&iomem_resource
, &lapic_resource
);
2245 * need call insert after e820_reserve_resources()
2246 * that is using request_resource
2248 late_initcall(lapic_insert_resource
);