2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/mc146818rtc.h>
29 #include <linux/compiler.h>
30 #include <linux/acpi.h>
31 #include <linux/module.h>
32 #include <linux/sysdev.h>
33 #include <linux/pci.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
43 #include <asm/timer.h>
44 #include <asm/i8259.h>
46 #include <asm/msidef.h>
47 #include <asm/hypertransport.h>
49 #include <mach_apic.h>
50 #include <mach_apicdef.h>
52 int (*ioapic_renumber_irq
)(int ioapic
, int irq
);
53 atomic_t irq_mis_count
;
55 /* Where if anywhere is the i8259 connect in external int mode */
56 static struct { int pin
, apic
; } ioapic_i8259
= { -1, -1 };
58 static DEFINE_SPINLOCK(ioapic_lock
);
59 static DEFINE_SPINLOCK(vector_lock
);
61 int timer_over_8254 __initdata
= 1;
64 * Is the SiS APIC rmw bug present ?
65 * -1 = don't know, 0 = no, 1 = yes
67 int sis_apic_bug
= -1;
70 * # of IRQ routing registers
72 int nr_ioapic_registers
[MAX_IO_APICS
];
74 static int disable_timer_pin_1 __initdata
;
77 * Rough estimation of how many shared IRQs there are, can
80 #define MAX_PLUS_SHARED_IRQS NR_IRQS
81 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
84 * This is performance-critical, we want to do it O(1)
86 * the indexing order of this array favors 1:1 mappings
87 * between pins and IRQs.
90 static struct irq_pin_list
{
92 } irq_2_pin
[PIN_MAP_SIZE
];
96 unsigned int unused
[3];
100 static __attribute_const__
struct io_apic __iomem
*io_apic_base(int idx
)
102 return (void __iomem
*) __fix_to_virt(FIX_IO_APIC_BASE_0
+ idx
)
103 + (mp_ioapics
[idx
].mpc_apicaddr
& ~PAGE_MASK
);
106 static inline unsigned int io_apic_read(unsigned int apic
, unsigned int reg
)
108 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
109 writel(reg
, &io_apic
->index
);
110 return readl(&io_apic
->data
);
113 static inline void io_apic_write(unsigned int apic
, unsigned int reg
, unsigned int value
)
115 struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
116 writel(reg
, &io_apic
->index
);
117 writel(value
, &io_apic
->data
);
121 * Re-write a value: to be used for read-modify-write
122 * cycles where the read already set up the index register.
124 * Older SiS APIC requires we rewrite the index register
126 static inline void io_apic_modify(unsigned int apic
, unsigned int reg
, unsigned int value
)
128 volatile struct io_apic __iomem
*io_apic
= io_apic_base(apic
);
130 writel(reg
, &io_apic
->index
);
131 writel(value
, &io_apic
->data
);
135 struct { u32 w1
, w2
; };
136 struct IO_APIC_route_entry entry
;
139 static struct IO_APIC_route_entry
ioapic_read_entry(int apic
, int pin
)
141 union entry_union eu
;
143 spin_lock_irqsave(&ioapic_lock
, flags
);
144 eu
.w1
= io_apic_read(apic
, 0x10 + 2 * pin
);
145 eu
.w2
= io_apic_read(apic
, 0x11 + 2 * pin
);
146 spin_unlock_irqrestore(&ioapic_lock
, flags
);
151 * When we write a new IO APIC routing entry, we need to write the high
152 * word first! If the mask bit in the low word is clear, we will enable
153 * the interrupt, and we need to make sure the entry is fully populated
154 * before that happens.
157 __ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
159 union entry_union eu
;
161 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
162 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
165 static void ioapic_write_entry(int apic
, int pin
, struct IO_APIC_route_entry e
)
168 spin_lock_irqsave(&ioapic_lock
, flags
);
169 __ioapic_write_entry(apic
, pin
, e
);
170 spin_unlock_irqrestore(&ioapic_lock
, flags
);
174 * When we mask an IO APIC routing entry, we need to write the low
175 * word first, in order to set the mask bit before we change the
178 static void ioapic_mask_entry(int apic
, int pin
)
181 union entry_union eu
= { .entry
.mask
= 1 };
183 spin_lock_irqsave(&ioapic_lock
, flags
);
184 io_apic_write(apic
, 0x10 + 2*pin
, eu
.w1
);
185 io_apic_write(apic
, 0x11 + 2*pin
, eu
.w2
);
186 spin_unlock_irqrestore(&ioapic_lock
, flags
);
190 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
191 * shared ISA-space IRQs, so we have to support them. We are super
192 * fast in the common case, and fast for shared ISA-space IRQs.
194 static void add_pin_to_irq(unsigned int irq
, int apic
, int pin
)
196 static int first_free_entry
= NR_IRQS
;
197 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
200 entry
= irq_2_pin
+ entry
->next
;
202 if (entry
->pin
!= -1) {
203 entry
->next
= first_free_entry
;
204 entry
= irq_2_pin
+ entry
->next
;
205 if (++first_free_entry
>= PIN_MAP_SIZE
)
206 panic("io_apic.c: whoops");
213 * Reroute an IRQ to a different pin.
215 static void __init
replace_pin_at_irq(unsigned int irq
,
216 int oldapic
, int oldpin
,
217 int newapic
, int newpin
)
219 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
222 if (entry
->apic
== oldapic
&& entry
->pin
== oldpin
) {
223 entry
->apic
= newapic
;
228 entry
= irq_2_pin
+ entry
->next
;
232 static void __modify_IO_APIC_irq (unsigned int irq
, unsigned long enable
, unsigned long disable
)
234 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
235 unsigned int pin
, reg
;
241 reg
= io_apic_read(entry
->apic
, 0x10 + pin
*2);
244 io_apic_modify(entry
->apic
, 0x10 + pin
*2, reg
);
247 entry
= irq_2_pin
+ entry
->next
;
252 static void __mask_IO_APIC_irq (unsigned int irq
)
254 __modify_IO_APIC_irq(irq
, 0x00010000, 0);
258 static void __unmask_IO_APIC_irq (unsigned int irq
)
260 __modify_IO_APIC_irq(irq
, 0, 0x00010000);
263 /* mask = 1, trigger = 0 */
264 static void __mask_and_edge_IO_APIC_irq (unsigned int irq
)
266 __modify_IO_APIC_irq(irq
, 0x00010000, 0x00008000);
269 /* mask = 0, trigger = 1 */
270 static void __unmask_and_level_IO_APIC_irq (unsigned int irq
)
272 __modify_IO_APIC_irq(irq
, 0x00008000, 0x00010000);
275 static void mask_IO_APIC_irq (unsigned int irq
)
279 spin_lock_irqsave(&ioapic_lock
, flags
);
280 __mask_IO_APIC_irq(irq
);
281 spin_unlock_irqrestore(&ioapic_lock
, flags
);
284 static void unmask_IO_APIC_irq (unsigned int irq
)
288 spin_lock_irqsave(&ioapic_lock
, flags
);
289 __unmask_IO_APIC_irq(irq
);
290 spin_unlock_irqrestore(&ioapic_lock
, flags
);
293 static void clear_IO_APIC_pin(unsigned int apic
, unsigned int pin
)
295 struct IO_APIC_route_entry entry
;
297 /* Check delivery_mode to be sure we're not clearing an SMI pin */
298 entry
= ioapic_read_entry(apic
, pin
);
299 if (entry
.delivery_mode
== dest_SMI
)
303 * Disable it in the IO-APIC irq-routing table:
305 ioapic_mask_entry(apic
, pin
);
308 static void clear_IO_APIC (void)
312 for (apic
= 0; apic
< nr_ioapics
; apic
++)
313 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++)
314 clear_IO_APIC_pin(apic
, pin
);
318 static void set_ioapic_affinity_irq(unsigned int irq
, cpumask_t cpumask
)
322 struct irq_pin_list
*entry
= irq_2_pin
+ irq
;
323 unsigned int apicid_value
;
326 cpus_and(tmp
, cpumask
, cpu_online_map
);
330 cpus_and(cpumask
, tmp
, CPU_MASK_ALL
);
332 apicid_value
= cpu_mask_to_apicid(cpumask
);
333 /* Prepare to do the io_apic_write */
334 apicid_value
= apicid_value
<< 24;
335 spin_lock_irqsave(&ioapic_lock
, flags
);
340 io_apic_write(entry
->apic
, 0x10 + 1 + pin
*2, apicid_value
);
343 entry
= irq_2_pin
+ entry
->next
;
345 irq_desc
[irq
].affinity
= cpumask
;
346 spin_unlock_irqrestore(&ioapic_lock
, flags
);
349 #if defined(CONFIG_IRQBALANCE)
350 # include <asm/processor.h> /* kernel_thread() */
351 # include <linux/kernel_stat.h> /* kstat */
352 # include <linux/slab.h> /* kmalloc() */
353 # include <linux/timer.h>
355 #define IRQBALANCE_CHECK_ARCH -999
356 #define MAX_BALANCED_IRQ_INTERVAL (5*HZ)
357 #define MIN_BALANCED_IRQ_INTERVAL (HZ/2)
358 #define BALANCED_IRQ_MORE_DELTA (HZ/10)
359 #define BALANCED_IRQ_LESS_DELTA (HZ)
361 static int irqbalance_disabled __read_mostly
= IRQBALANCE_CHECK_ARCH
;
362 static int physical_balance __read_mostly
;
363 static long balanced_irq_interval __read_mostly
= MAX_BALANCED_IRQ_INTERVAL
;
365 static struct irq_cpu_info
{
366 unsigned long * last_irq
;
367 unsigned long * irq_delta
;
369 } irq_cpu_data
[NR_CPUS
];
371 #define CPU_IRQ(cpu) (irq_cpu_data[cpu].irq)
372 #define LAST_CPU_IRQ(cpu,irq) (irq_cpu_data[cpu].last_irq[irq])
373 #define IRQ_DELTA(cpu,irq) (irq_cpu_data[cpu].irq_delta[irq])
375 #define IDLE_ENOUGH(cpu,now) \
376 (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
378 #define IRQ_ALLOWED(cpu, allowed_mask) cpu_isset(cpu, allowed_mask)
380 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(per_cpu(cpu_sibling_map, i)))
382 static cpumask_t balance_irq_affinity
[NR_IRQS
] = {
383 [0 ... NR_IRQS
-1] = CPU_MASK_ALL
386 void set_balance_irq_affinity(unsigned int irq
, cpumask_t mask
)
388 balance_irq_affinity
[irq
] = mask
;
391 static unsigned long move(int curr_cpu
, cpumask_t allowed_mask
,
392 unsigned long now
, int direction
)
400 if (unlikely(cpu
== curr_cpu
))
403 if (direction
== 1) {
412 } while (!cpu_online(cpu
) || !IRQ_ALLOWED(cpu
,allowed_mask
) ||
413 (search_idle
&& !IDLE_ENOUGH(cpu
,now
)));
418 static inline void balance_irq(int cpu
, int irq
)
420 unsigned long now
= jiffies
;
421 cpumask_t allowed_mask
;
422 unsigned int new_cpu
;
424 if (irqbalance_disabled
)
427 cpus_and(allowed_mask
, cpu_online_map
, balance_irq_affinity
[irq
]);
428 new_cpu
= move(cpu
, allowed_mask
, now
, 1);
429 if (cpu
!= new_cpu
) {
430 set_pending_irq(irq
, cpumask_of_cpu(new_cpu
));
434 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold
)
438 for_each_online_cpu(i
) {
439 for (j
= 0; j
< NR_IRQS
; j
++) {
440 if (!irq_desc
[j
].action
)
442 /* Is it a significant load ? */
443 if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i
),j
) <
444 useful_load_threshold
)
449 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
450 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
454 static void do_irq_balance(void)
457 unsigned long max_cpu_irq
= 0, min_cpu_irq
= (~0);
458 unsigned long move_this_load
= 0;
459 int max_loaded
= 0, min_loaded
= 0;
461 unsigned long useful_load_threshold
= balanced_irq_interval
+ 10;
463 int tmp_loaded
, first_attempt
= 1;
464 unsigned long tmp_cpu_irq
;
465 unsigned long imbalance
= 0;
466 cpumask_t allowed_mask
, target_cpu_mask
, tmp
;
468 for_each_possible_cpu(i
) {
473 package_index
= CPU_TO_PACKAGEINDEX(i
);
474 for (j
= 0; j
< NR_IRQS
; j
++) {
475 unsigned long value_now
, delta
;
476 /* Is this an active IRQ or balancing disabled ? */
477 if (!irq_desc
[j
].action
|| irq_balancing_disabled(j
))
479 if ( package_index
== i
)
480 IRQ_DELTA(package_index
,j
) = 0;
481 /* Determine the total count per processor per IRQ */
482 value_now
= (unsigned long) kstat_cpu(i
).irqs
[j
];
484 /* Determine the activity per processor per IRQ */
485 delta
= value_now
- LAST_CPU_IRQ(i
,j
);
487 /* Update last_cpu_irq[][] for the next time */
488 LAST_CPU_IRQ(i
,j
) = value_now
;
490 /* Ignore IRQs whose rate is less than the clock */
491 if (delta
< useful_load_threshold
)
493 /* update the load for the processor or package total */
494 IRQ_DELTA(package_index
,j
) += delta
;
496 /* Keep track of the higher numbered sibling as well */
497 if (i
!= package_index
)
500 * We have sibling A and sibling B in the package
502 * cpu_irq[A] = load for cpu A + load for cpu B
503 * cpu_irq[B] = load for cpu B
505 CPU_IRQ(package_index
) += delta
;
508 /* Find the least loaded processor package */
509 for_each_online_cpu(i
) {
510 if (i
!= CPU_TO_PACKAGEINDEX(i
))
512 if (min_cpu_irq
> CPU_IRQ(i
)) {
513 min_cpu_irq
= CPU_IRQ(i
);
517 max_cpu_irq
= ULONG_MAX
;
520 /* Look for heaviest loaded processor.
521 * We may come back to get the next heaviest loaded processor.
522 * Skip processors with trivial loads.
526 for_each_online_cpu(i
) {
527 if (i
!= CPU_TO_PACKAGEINDEX(i
))
529 if (max_cpu_irq
<= CPU_IRQ(i
))
531 if (tmp_cpu_irq
< CPU_IRQ(i
)) {
532 tmp_cpu_irq
= CPU_IRQ(i
);
537 if (tmp_loaded
== -1) {
538 /* In the case of small number of heavy interrupt sources,
539 * loading some of the cpus too much. We use Ingo's original
540 * approach to rotate them around.
542 if (!first_attempt
&& imbalance
>= useful_load_threshold
) {
543 rotate_irqs_among_cpus(useful_load_threshold
);
546 goto not_worth_the_effort
;
549 first_attempt
= 0; /* heaviest search */
550 max_cpu_irq
= tmp_cpu_irq
; /* load */
551 max_loaded
= tmp_loaded
; /* processor */
552 imbalance
= (max_cpu_irq
- min_cpu_irq
) / 2;
554 /* if imbalance is less than approx 10% of max load, then
555 * observe diminishing returns action. - quit
557 if (imbalance
< (max_cpu_irq
>> 3))
558 goto not_worth_the_effort
;
561 /* if we select an IRQ to move that can't go where we want, then
562 * see if there is another one to try.
566 for (j
= 0; j
< NR_IRQS
; j
++) {
567 /* Is this an active IRQ? */
568 if (!irq_desc
[j
].action
)
570 if (imbalance
<= IRQ_DELTA(max_loaded
,j
))
572 /* Try to find the IRQ that is closest to the imbalance
573 * without going over.
575 if (move_this_load
< IRQ_DELTA(max_loaded
,j
)) {
576 move_this_load
= IRQ_DELTA(max_loaded
,j
);
580 if (selected_irq
== -1) {
584 imbalance
= move_this_load
;
586 /* For physical_balance case, we accumulated both load
587 * values in the one of the siblings cpu_irq[],
588 * to use the same code for physical and logical processors
589 * as much as possible.
591 * NOTE: the cpu_irq[] array holds the sum of the load for
592 * sibling A and sibling B in the slot for the lowest numbered
593 * sibling (A), _AND_ the load for sibling B in the slot for
594 * the higher numbered sibling.
596 * We seek the least loaded sibling by making the comparison
599 load
= CPU_IRQ(min_loaded
) >> 1;
600 for_each_cpu_mask(j
, per_cpu(cpu_sibling_map
, min_loaded
)) {
601 if (load
> CPU_IRQ(j
)) {
602 /* This won't change cpu_sibling_map[min_loaded] */
608 cpus_and(allowed_mask
,
610 balance_irq_affinity
[selected_irq
]);
611 target_cpu_mask
= cpumask_of_cpu(min_loaded
);
612 cpus_and(tmp
, target_cpu_mask
, allowed_mask
);
614 if (!cpus_empty(tmp
)) {
615 /* mark for change destination */
616 set_pending_irq(selected_irq
, cpumask_of_cpu(min_loaded
));
618 /* Since we made a change, come back sooner to
619 * check for more variation.
621 balanced_irq_interval
= max((long)MIN_BALANCED_IRQ_INTERVAL
,
622 balanced_irq_interval
- BALANCED_IRQ_LESS_DELTA
);
627 not_worth_the_effort
:
629 * if we did not find an IRQ to move, then adjust the time interval
632 balanced_irq_interval
= min((long)MAX_BALANCED_IRQ_INTERVAL
,
633 balanced_irq_interval
+ BALANCED_IRQ_MORE_DELTA
);
637 static int balanced_irq(void *unused
)
640 unsigned long prev_balance_time
= jiffies
;
641 long time_remaining
= balanced_irq_interval
;
643 /* push everything to CPU 0 to give us a starting point. */
644 for (i
= 0 ; i
< NR_IRQS
; i
++) {
645 irq_desc
[i
].pending_mask
= cpumask_of_cpu(0);
646 set_pending_irq(i
, cpumask_of_cpu(0));
651 time_remaining
= schedule_timeout_interruptible(time_remaining
);
653 if (time_after(jiffies
,
654 prev_balance_time
+balanced_irq_interval
)) {
657 prev_balance_time
= jiffies
;
658 time_remaining
= balanced_irq_interval
;
665 static int __init
balanced_irq_init(void)
668 struct cpuinfo_x86
*c
;
671 cpus_shift_right(tmp
, cpu_online_map
, 2);
673 /* When not overwritten by the command line ask subarchitecture. */
674 if (irqbalance_disabled
== IRQBALANCE_CHECK_ARCH
)
675 irqbalance_disabled
= NO_BALANCE_IRQ
;
676 if (irqbalance_disabled
)
679 /* disable irqbalance completely if there is only one processor online */
680 if (num_online_cpus() < 2) {
681 irqbalance_disabled
= 1;
685 * Enable physical balance only if more than 1 physical processor
688 if (smp_num_siblings
> 1 && !cpus_empty(tmp
))
689 physical_balance
= 1;
691 for_each_online_cpu(i
) {
692 irq_cpu_data
[i
].irq_delta
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
693 irq_cpu_data
[i
].last_irq
= kmalloc(sizeof(unsigned long) * NR_IRQS
, GFP_KERNEL
);
694 if (irq_cpu_data
[i
].irq_delta
== NULL
|| irq_cpu_data
[i
].last_irq
== NULL
) {
695 printk(KERN_ERR
"balanced_irq_init: out of memory");
698 memset(irq_cpu_data
[i
].irq_delta
,0,sizeof(unsigned long) * NR_IRQS
);
699 memset(irq_cpu_data
[i
].last_irq
,0,sizeof(unsigned long) * NR_IRQS
);
702 printk(KERN_INFO
"Starting balanced_irq\n");
703 if (!IS_ERR(kthread_run(balanced_irq
, NULL
, "kirqd")))
705 printk(KERN_ERR
"balanced_irq_init: failed to spawn balanced_irq");
707 for_each_possible_cpu(i
) {
708 kfree(irq_cpu_data
[i
].irq_delta
);
709 irq_cpu_data
[i
].irq_delta
= NULL
;
710 kfree(irq_cpu_data
[i
].last_irq
);
711 irq_cpu_data
[i
].last_irq
= NULL
;
716 int __devinit
irqbalance_disable(char *str
)
718 irqbalance_disabled
= 1;
722 __setup("noirqbalance", irqbalance_disable
);
724 late_initcall(balanced_irq_init
);
725 #endif /* CONFIG_IRQBALANCE */
726 #endif /* CONFIG_SMP */
729 void send_IPI_self(int vector
)
736 apic_wait_icr_idle();
737 cfg
= APIC_DM_FIXED
| APIC_DEST_SELF
| vector
| APIC_DEST_LOGICAL
;
739 * Send the IPI. The write to APIC_ICR fires this off.
741 apic_write_around(APIC_ICR
, cfg
);
743 #endif /* !CONFIG_SMP */
747 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
748 * specific CPU-side IRQs.
752 static int pirq_entries
[MAX_PIRQS
];
753 static int pirqs_enabled
;
754 int skip_ioapic_setup
;
756 static int __init
ioapic_pirq_setup(char *str
)
759 int ints
[MAX_PIRQS
+1];
761 get_options(str
, ARRAY_SIZE(ints
), ints
);
763 for (i
= 0; i
< MAX_PIRQS
; i
++)
764 pirq_entries
[i
] = -1;
767 apic_printk(APIC_VERBOSE
, KERN_INFO
768 "PIRQ redirection, working around broken MP-BIOS.\n");
770 if (ints
[0] < MAX_PIRQS
)
773 for (i
= 0; i
< max
; i
++) {
774 apic_printk(APIC_VERBOSE
, KERN_DEBUG
775 "... PIRQ%d -> IRQ %d\n", i
, ints
[i
+1]);
777 * PIRQs are mapped upside down, usually.
779 pirq_entries
[MAX_PIRQS
-i
-1] = ints
[i
+1];
784 __setup("pirq=", ioapic_pirq_setup
);
787 * Find the IRQ entry number of a certain pin.
789 static int find_irq_entry(int apic
, int pin
, int type
)
793 for (i
= 0; i
< mp_irq_entries
; i
++)
794 if (mp_irqs
[i
].mpc_irqtype
== type
&&
795 (mp_irqs
[i
].mpc_dstapic
== mp_ioapics
[apic
].mpc_apicid
||
796 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
) &&
797 mp_irqs
[i
].mpc_dstirq
== pin
)
804 * Find the pin to which IRQ[irq] (ISA) is connected
806 static int __init
find_isa_irq_pin(int irq
, int type
)
810 for (i
= 0; i
< mp_irq_entries
; i
++) {
811 int lbus
= mp_irqs
[i
].mpc_srcbus
;
813 if (test_bit(lbus
, mp_bus_not_pci
) &&
814 (mp_irqs
[i
].mpc_irqtype
== type
) &&
815 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
817 return mp_irqs
[i
].mpc_dstirq
;
822 static int __init
find_isa_irq_apic(int irq
, int type
)
826 for (i
= 0; i
< mp_irq_entries
; i
++) {
827 int lbus
= mp_irqs
[i
].mpc_srcbus
;
829 if (test_bit(lbus
, mp_bus_not_pci
) &&
830 (mp_irqs
[i
].mpc_irqtype
== type
) &&
831 (mp_irqs
[i
].mpc_srcbusirq
== irq
))
834 if (i
< mp_irq_entries
) {
836 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
837 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
)
846 * Find a specific PCI IRQ entry.
847 * Not an __init, possibly needed by modules
849 static int pin_2_irq(int idx
, int apic
, int pin
);
851 int IO_APIC_get_PCI_irq_vector(int bus
, int slot
, int pin
)
853 int apic
, i
, best_guess
= -1;
855 apic_printk(APIC_DEBUG
, "querying PCI -> IRQ mapping bus:%d, "
856 "slot:%d, pin:%d.\n", bus
, slot
, pin
);
857 if (mp_bus_id_to_pci_bus
[bus
] == -1) {
858 printk(KERN_WARNING
"PCI BIOS passed nonexistent PCI bus %d!\n", bus
);
861 for (i
= 0; i
< mp_irq_entries
; i
++) {
862 int lbus
= mp_irqs
[i
].mpc_srcbus
;
864 for (apic
= 0; apic
< nr_ioapics
; apic
++)
865 if (mp_ioapics
[apic
].mpc_apicid
== mp_irqs
[i
].mpc_dstapic
||
866 mp_irqs
[i
].mpc_dstapic
== MP_APIC_ALL
)
869 if (!test_bit(lbus
, mp_bus_not_pci
) &&
870 !mp_irqs
[i
].mpc_irqtype
&&
872 (slot
== ((mp_irqs
[i
].mpc_srcbusirq
>> 2) & 0x1f))) {
873 int irq
= pin_2_irq(i
,apic
,mp_irqs
[i
].mpc_dstirq
);
875 if (!(apic
|| IO_APIC_IRQ(irq
)))
878 if (pin
== (mp_irqs
[i
].mpc_srcbusirq
& 3))
881 * Use the first all-but-pin matching entry as a
882 * best-guess fuzzy result for broken mptables.
890 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector
);
893 * This function currently is only a helper for the i386 smp boot process where
894 * we need to reprogram the ioredtbls to cater for the cpus which have come online
895 * so mask in all cases should simply be TARGET_CPUS
898 void __init
setup_ioapic_dest(void)
900 int pin
, ioapic
, irq
, irq_entry
;
902 if (skip_ioapic_setup
== 1)
905 for (ioapic
= 0; ioapic
< nr_ioapics
; ioapic
++) {
906 for (pin
= 0; pin
< nr_ioapic_registers
[ioapic
]; pin
++) {
907 irq_entry
= find_irq_entry(ioapic
, pin
, mp_INT
);
910 irq
= pin_2_irq(irq_entry
, ioapic
, pin
);
911 set_ioapic_affinity_irq(irq
, TARGET_CPUS
);
919 * EISA Edge/Level control register, ELCR
921 static int EISA_ELCR(unsigned int irq
)
924 unsigned int port
= 0x4d0 + (irq
>> 3);
925 return (inb(port
) >> (irq
& 7)) & 1;
927 apic_printk(APIC_VERBOSE
, KERN_INFO
928 "Broken MPtable reports ISA irq %d\n", irq
);
932 /* ISA interrupts are always polarity zero edge triggered,
933 * when listed as conforming in the MP table. */
935 #define default_ISA_trigger(idx) (0)
936 #define default_ISA_polarity(idx) (0)
938 /* EISA interrupts are always polarity zero and can be edge or level
939 * trigger depending on the ELCR value. If an interrupt is listed as
940 * EISA conforming in the MP table, that means its trigger type must
941 * be read in from the ELCR */
943 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
944 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
946 /* PCI interrupts are always polarity one level triggered,
947 * when listed as conforming in the MP table. */
949 #define default_PCI_trigger(idx) (1)
950 #define default_PCI_polarity(idx) (1)
952 /* MCA interrupts are always polarity zero level triggered,
953 * when listed as conforming in the MP table. */
955 #define default_MCA_trigger(idx) (1)
956 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
958 static int MPBIOS_polarity(int idx
)
960 int bus
= mp_irqs
[idx
].mpc_srcbus
;
964 * Determine IRQ line polarity (high active or low active):
966 switch (mp_irqs
[idx
].mpc_irqflag
& 3)
968 case 0: /* conforms, ie. bus-type dependent polarity */
970 polarity
= test_bit(bus
, mp_bus_not_pci
)?
971 default_ISA_polarity(idx
):
972 default_PCI_polarity(idx
);
975 case 1: /* high active */
980 case 2: /* reserved */
982 printk(KERN_WARNING
"broken BIOS!!\n");
986 case 3: /* low active */
991 default: /* invalid */
993 printk(KERN_WARNING
"broken BIOS!!\n");
1001 static int MPBIOS_trigger(int idx
)
1003 int bus
= mp_irqs
[idx
].mpc_srcbus
;
1007 * Determine IRQ trigger mode (edge or level sensitive):
1009 switch ((mp_irqs
[idx
].mpc_irqflag
>>2) & 3)
1011 case 0: /* conforms, ie. bus-type dependent */
1013 trigger
= test_bit(bus
, mp_bus_not_pci
)?
1014 default_ISA_trigger(idx
):
1015 default_PCI_trigger(idx
);
1016 switch (mp_bus_id_to_type
[bus
])
1018 case MP_BUS_ISA
: /* ISA pin */
1020 /* set before the switch */
1023 case MP_BUS_EISA
: /* EISA pin */
1025 trigger
= default_EISA_trigger(idx
);
1028 case MP_BUS_PCI
: /* PCI pin */
1030 /* set before the switch */
1033 case MP_BUS_MCA
: /* MCA pin */
1035 trigger
= default_MCA_trigger(idx
);
1040 printk(KERN_WARNING
"broken BIOS!!\n");
1052 case 2: /* reserved */
1054 printk(KERN_WARNING
"broken BIOS!!\n");
1063 default: /* invalid */
1065 printk(KERN_WARNING
"broken BIOS!!\n");
1073 static inline int irq_polarity(int idx
)
1075 return MPBIOS_polarity(idx
);
1078 static inline int irq_trigger(int idx
)
1080 return MPBIOS_trigger(idx
);
1083 static int pin_2_irq(int idx
, int apic
, int pin
)
1086 int bus
= mp_irqs
[idx
].mpc_srcbus
;
1089 * Debugging check, we are in big trouble if this message pops up!
1091 if (mp_irqs
[idx
].mpc_dstirq
!= pin
)
1092 printk(KERN_ERR
"broken BIOS or MPTABLE parser, ayiee!!\n");
1094 if (test_bit(bus
, mp_bus_not_pci
))
1095 irq
= mp_irqs
[idx
].mpc_srcbusirq
;
1098 * PCI IRQs are mapped in order
1102 irq
+= nr_ioapic_registers
[i
++];
1106 * For MPS mode, so far only needed by ES7000 platform
1108 if (ioapic_renumber_irq
)
1109 irq
= ioapic_renumber_irq(apic
, irq
);
1113 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1115 if ((pin
>= 16) && (pin
<= 23)) {
1116 if (pirq_entries
[pin
-16] != -1) {
1117 if (!pirq_entries
[pin
-16]) {
1118 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1119 "disabling PIRQ%d\n", pin
-16);
1121 irq
= pirq_entries
[pin
-16];
1122 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1123 "using PIRQ%d -> IRQ %d\n",
1131 static inline int IO_APIC_irq_trigger(int irq
)
1135 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1136 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1137 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1138 if ((idx
!= -1) && (irq
== pin_2_irq(idx
,apic
,pin
)))
1139 return irq_trigger(idx
);
1143 * nonexistent IRQs are edge default
1148 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1149 static u8 irq_vector
[NR_IRQ_VECTORS
] __read_mostly
= { FIRST_DEVICE_VECTOR
, 0 };
1151 static int __assign_irq_vector(int irq
)
1153 static int current_vector
= FIRST_DEVICE_VECTOR
, current_offset
= 0;
1156 BUG_ON((unsigned)irq
>= NR_IRQ_VECTORS
);
1158 if (irq_vector
[irq
] > 0)
1159 return irq_vector
[irq
];
1161 vector
= current_vector
;
1162 offset
= current_offset
;
1165 if (vector
>= FIRST_SYSTEM_VECTOR
) {
1166 offset
= (offset
+ 1) % 8;
1167 vector
= FIRST_DEVICE_VECTOR
+ offset
;
1169 if (vector
== current_vector
)
1171 if (test_and_set_bit(vector
, used_vectors
))
1174 current_vector
= vector
;
1175 current_offset
= offset
;
1176 irq_vector
[irq
] = vector
;
1181 static int assign_irq_vector(int irq
)
1183 unsigned long flags
;
1186 spin_lock_irqsave(&vector_lock
, flags
);
1187 vector
= __assign_irq_vector(irq
);
1188 spin_unlock_irqrestore(&vector_lock
, flags
);
1192 static struct irq_chip ioapic_chip
;
1194 #define IOAPIC_AUTO -1
1195 #define IOAPIC_EDGE 0
1196 #define IOAPIC_LEVEL 1
1198 static void ioapic_register_intr(int irq
, int vector
, unsigned long trigger
)
1200 if ((trigger
== IOAPIC_AUTO
&& IO_APIC_irq_trigger(irq
)) ||
1201 trigger
== IOAPIC_LEVEL
) {
1202 irq_desc
[irq
].status
|= IRQ_LEVEL
;
1203 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1204 handle_fasteoi_irq
, "fasteoi");
1206 irq_desc
[irq
].status
&= ~IRQ_LEVEL
;
1207 set_irq_chip_and_handler_name(irq
, &ioapic_chip
,
1208 handle_edge_irq
, "edge");
1210 set_intr_gate(vector
, interrupt
[irq
]);
1213 static void __init
setup_IO_APIC_irqs(void)
1215 struct IO_APIC_route_entry entry
;
1216 int apic
, pin
, idx
, irq
, first_notcon
= 1, vector
;
1217 unsigned long flags
;
1219 apic_printk(APIC_VERBOSE
, KERN_DEBUG
"init IO_APIC IRQs\n");
1221 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1222 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1225 * add it to the IO-APIC irq-routing table:
1227 memset(&entry
,0,sizeof(entry
));
1229 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1230 entry
.dest_mode
= INT_DEST_MODE
;
1231 entry
.mask
= 0; /* enable IRQ */
1232 entry
.dest
.logical
.logical_dest
=
1233 cpu_mask_to_apicid(TARGET_CPUS
);
1235 idx
= find_irq_entry(apic
,pin
,mp_INT
);
1238 apic_printk(APIC_VERBOSE
, KERN_DEBUG
1239 " IO-APIC (apicid-pin) %d-%d",
1240 mp_ioapics
[apic
].mpc_apicid
,
1244 apic_printk(APIC_VERBOSE
, ", %d-%d",
1245 mp_ioapics
[apic
].mpc_apicid
, pin
);
1249 if (!first_notcon
) {
1250 apic_printk(APIC_VERBOSE
, " not connected.\n");
1254 entry
.trigger
= irq_trigger(idx
);
1255 entry
.polarity
= irq_polarity(idx
);
1257 if (irq_trigger(idx
)) {
1262 irq
= pin_2_irq(idx
, apic
, pin
);
1264 * skip adding the timer int on secondary nodes, which causes
1265 * a small but painful rift in the time-space continuum
1267 if (multi_timer_check(apic
, irq
))
1270 add_pin_to_irq(irq
, apic
, pin
);
1272 if (!apic
&& !IO_APIC_IRQ(irq
))
1275 if (IO_APIC_IRQ(irq
)) {
1276 vector
= assign_irq_vector(irq
);
1277 entry
.vector
= vector
;
1278 ioapic_register_intr(irq
, vector
, IOAPIC_AUTO
);
1280 if (!apic
&& (irq
< 16))
1281 disable_8259A_irq(irq
);
1283 spin_lock_irqsave(&ioapic_lock
, flags
);
1284 __ioapic_write_entry(apic
, pin
, entry
);
1285 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1290 apic_printk(APIC_VERBOSE
, " not connected.\n");
1294 * Set up the 8259A-master output pin:
1296 static void __init
setup_ExtINT_IRQ0_pin(unsigned int apic
, unsigned int pin
, int vector
)
1298 struct IO_APIC_route_entry entry
;
1300 memset(&entry
,0,sizeof(entry
));
1302 disable_8259A_irq(0);
1305 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
1308 * We use logical delivery to get the timer IRQ
1311 entry
.dest_mode
= INT_DEST_MODE
;
1312 entry
.mask
= 0; /* unmask IRQ now */
1313 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
1314 entry
.delivery_mode
= INT_DELIVERY_MODE
;
1317 entry
.vector
= vector
;
1320 * The timer IRQ doesn't have to know that behind the
1321 * scene we have a 8259A-master in AEOI mode ...
1323 irq_desc
[0].chip
= &ioapic_chip
;
1324 set_irq_handler(0, handle_edge_irq
);
1327 * Add it to the IO-APIC irq-routing table:
1329 ioapic_write_entry(apic
, pin
, entry
);
1331 enable_8259A_irq(0);
1334 void __init
print_IO_APIC(void)
1337 union IO_APIC_reg_00 reg_00
;
1338 union IO_APIC_reg_01 reg_01
;
1339 union IO_APIC_reg_02 reg_02
;
1340 union IO_APIC_reg_03 reg_03
;
1341 unsigned long flags
;
1343 if (apic_verbosity
== APIC_QUIET
)
1346 printk(KERN_DEBUG
"number of MP IRQ sources: %d.\n", mp_irq_entries
);
1347 for (i
= 0; i
< nr_ioapics
; i
++)
1348 printk(KERN_DEBUG
"number of IO-APIC #%d registers: %d.\n",
1349 mp_ioapics
[i
].mpc_apicid
, nr_ioapic_registers
[i
]);
1352 * We are a bit conservative about what we expect. We have to
1353 * know about every hardware change ASAP.
1355 printk(KERN_INFO
"testing the IO APIC.......................\n");
1357 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1359 spin_lock_irqsave(&ioapic_lock
, flags
);
1360 reg_00
.raw
= io_apic_read(apic
, 0);
1361 reg_01
.raw
= io_apic_read(apic
, 1);
1362 if (reg_01
.bits
.version
>= 0x10)
1363 reg_02
.raw
= io_apic_read(apic
, 2);
1364 if (reg_01
.bits
.version
>= 0x20)
1365 reg_03
.raw
= io_apic_read(apic
, 3);
1366 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1368 printk(KERN_DEBUG
"IO APIC #%d......\n", mp_ioapics
[apic
].mpc_apicid
);
1369 printk(KERN_DEBUG
".... register #00: %08X\n", reg_00
.raw
);
1370 printk(KERN_DEBUG
"....... : physical APIC id: %02X\n", reg_00
.bits
.ID
);
1371 printk(KERN_DEBUG
"....... : Delivery Type: %X\n", reg_00
.bits
.delivery_type
);
1372 printk(KERN_DEBUG
"....... : LTS : %X\n", reg_00
.bits
.LTS
);
1374 printk(KERN_DEBUG
".... register #01: %08X\n", reg_01
.raw
);
1375 printk(KERN_DEBUG
"....... : max redirection entries: %04X\n", reg_01
.bits
.entries
);
1377 printk(KERN_DEBUG
"....... : PRQ implemented: %X\n", reg_01
.bits
.PRQ
);
1378 printk(KERN_DEBUG
"....... : IO APIC version: %04X\n", reg_01
.bits
.version
);
1381 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1382 * but the value of reg_02 is read as the previous read register
1383 * value, so ignore it if reg_02 == reg_01.
1385 if (reg_01
.bits
.version
>= 0x10 && reg_02
.raw
!= reg_01
.raw
) {
1386 printk(KERN_DEBUG
".... register #02: %08X\n", reg_02
.raw
);
1387 printk(KERN_DEBUG
"....... : arbitration: %02X\n", reg_02
.bits
.arbitration
);
1391 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1392 * or reg_03, but the value of reg_0[23] is read as the previous read
1393 * register value, so ignore it if reg_03 == reg_0[12].
1395 if (reg_01
.bits
.version
>= 0x20 && reg_03
.raw
!= reg_02
.raw
&&
1396 reg_03
.raw
!= reg_01
.raw
) {
1397 printk(KERN_DEBUG
".... register #03: %08X\n", reg_03
.raw
);
1398 printk(KERN_DEBUG
"....... : Boot DT : %X\n", reg_03
.bits
.boot_DT
);
1401 printk(KERN_DEBUG
".... IRQ redirection table:\n");
1403 printk(KERN_DEBUG
" NR Log Phy Mask Trig IRR Pol"
1404 " Stat Dest Deli Vect: \n");
1406 for (i
= 0; i
<= reg_01
.bits
.entries
; i
++) {
1407 struct IO_APIC_route_entry entry
;
1409 entry
= ioapic_read_entry(apic
, i
);
1411 printk(KERN_DEBUG
" %02x %03X %02X ",
1413 entry
.dest
.logical
.logical_dest
,
1414 entry
.dest
.physical
.physical_dest
1417 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1422 entry
.delivery_status
,
1424 entry
.delivery_mode
,
1429 printk(KERN_DEBUG
"IRQ to pin mappings:\n");
1430 for (i
= 0; i
< NR_IRQS
; i
++) {
1431 struct irq_pin_list
*entry
= irq_2_pin
+ i
;
1434 printk(KERN_DEBUG
"IRQ%d ", i
);
1436 printk("-> %d:%d", entry
->apic
, entry
->pin
);
1439 entry
= irq_2_pin
+ entry
->next
;
1444 printk(KERN_INFO
".................................... done.\n");
1451 static void print_APIC_bitfield (int base
)
1456 if (apic_verbosity
== APIC_QUIET
)
1459 printk(KERN_DEBUG
"0123456789abcdef0123456789abcdef\n" KERN_DEBUG
);
1460 for (i
= 0; i
< 8; i
++) {
1461 v
= apic_read(base
+ i
*0x10);
1462 for (j
= 0; j
< 32; j
++) {
1472 void /*__init*/ print_local_APIC(void * dummy
)
1474 unsigned int v
, ver
, maxlvt
;
1476 if (apic_verbosity
== APIC_QUIET
)
1479 printk("\n" KERN_DEBUG
"printing local APIC contents on CPU#%d/%d:\n",
1480 smp_processor_id(), hard_smp_processor_id());
1481 v
= apic_read(APIC_ID
);
1482 printk(KERN_INFO
"... APIC ID: %08x (%01x)\n", v
, GET_APIC_ID(v
));
1483 v
= apic_read(APIC_LVR
);
1484 printk(KERN_INFO
"... APIC VERSION: %08x\n", v
);
1485 ver
= GET_APIC_VERSION(v
);
1486 maxlvt
= lapic_get_maxlvt();
1488 v
= apic_read(APIC_TASKPRI
);
1489 printk(KERN_DEBUG
"... APIC TASKPRI: %08x (%02x)\n", v
, v
& APIC_TPRI_MASK
);
1491 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1492 v
= apic_read(APIC_ARBPRI
);
1493 printk(KERN_DEBUG
"... APIC ARBPRI: %08x (%02x)\n", v
,
1494 v
& APIC_ARBPRI_MASK
);
1495 v
= apic_read(APIC_PROCPRI
);
1496 printk(KERN_DEBUG
"... APIC PROCPRI: %08x\n", v
);
1499 v
= apic_read(APIC_EOI
);
1500 printk(KERN_DEBUG
"... APIC EOI: %08x\n", v
);
1501 v
= apic_read(APIC_RRR
);
1502 printk(KERN_DEBUG
"... APIC RRR: %08x\n", v
);
1503 v
= apic_read(APIC_LDR
);
1504 printk(KERN_DEBUG
"... APIC LDR: %08x\n", v
);
1505 v
= apic_read(APIC_DFR
);
1506 printk(KERN_DEBUG
"... APIC DFR: %08x\n", v
);
1507 v
= apic_read(APIC_SPIV
);
1508 printk(KERN_DEBUG
"... APIC SPIV: %08x\n", v
);
1510 printk(KERN_DEBUG
"... APIC ISR field:\n");
1511 print_APIC_bitfield(APIC_ISR
);
1512 printk(KERN_DEBUG
"... APIC TMR field:\n");
1513 print_APIC_bitfield(APIC_TMR
);
1514 printk(KERN_DEBUG
"... APIC IRR field:\n");
1515 print_APIC_bitfield(APIC_IRR
);
1517 if (APIC_INTEGRATED(ver
)) { /* !82489DX */
1518 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
1519 apic_write(APIC_ESR
, 0);
1520 v
= apic_read(APIC_ESR
);
1521 printk(KERN_DEBUG
"... APIC ESR: %08x\n", v
);
1524 v
= apic_read(APIC_ICR
);
1525 printk(KERN_DEBUG
"... APIC ICR: %08x\n", v
);
1526 v
= apic_read(APIC_ICR2
);
1527 printk(KERN_DEBUG
"... APIC ICR2: %08x\n", v
);
1529 v
= apic_read(APIC_LVTT
);
1530 printk(KERN_DEBUG
"... APIC LVTT: %08x\n", v
);
1532 if (maxlvt
> 3) { /* PC is LVT#4. */
1533 v
= apic_read(APIC_LVTPC
);
1534 printk(KERN_DEBUG
"... APIC LVTPC: %08x\n", v
);
1536 v
= apic_read(APIC_LVT0
);
1537 printk(KERN_DEBUG
"... APIC LVT0: %08x\n", v
);
1538 v
= apic_read(APIC_LVT1
);
1539 printk(KERN_DEBUG
"... APIC LVT1: %08x\n", v
);
1541 if (maxlvt
> 2) { /* ERR is LVT#3. */
1542 v
= apic_read(APIC_LVTERR
);
1543 printk(KERN_DEBUG
"... APIC LVTERR: %08x\n", v
);
1546 v
= apic_read(APIC_TMICT
);
1547 printk(KERN_DEBUG
"... APIC TMICT: %08x\n", v
);
1548 v
= apic_read(APIC_TMCCT
);
1549 printk(KERN_DEBUG
"... APIC TMCCT: %08x\n", v
);
1550 v
= apic_read(APIC_TDCR
);
1551 printk(KERN_DEBUG
"... APIC TDCR: %08x\n", v
);
1555 void print_all_local_APICs (void)
1557 on_each_cpu(print_local_APIC
, NULL
, 1, 1);
1560 void /*__init*/ print_PIC(void)
1563 unsigned long flags
;
1565 if (apic_verbosity
== APIC_QUIET
)
1568 printk(KERN_DEBUG
"\nprinting PIC contents\n");
1570 spin_lock_irqsave(&i8259A_lock
, flags
);
1572 v
= inb(0xa1) << 8 | inb(0x21);
1573 printk(KERN_DEBUG
"... PIC IMR: %04x\n", v
);
1575 v
= inb(0xa0) << 8 | inb(0x20);
1576 printk(KERN_DEBUG
"... PIC IRR: %04x\n", v
);
1580 v
= inb(0xa0) << 8 | inb(0x20);
1584 spin_unlock_irqrestore(&i8259A_lock
, flags
);
1586 printk(KERN_DEBUG
"... PIC ISR: %04x\n", v
);
1588 v
= inb(0x4d1) << 8 | inb(0x4d0);
1589 printk(KERN_DEBUG
"... PIC ELCR: %04x\n", v
);
1594 static void __init
enable_IO_APIC(void)
1596 union IO_APIC_reg_01 reg_01
;
1597 int i8259_apic
, i8259_pin
;
1599 unsigned long flags
;
1601 for (i
= 0; i
< PIN_MAP_SIZE
; i
++) {
1602 irq_2_pin
[i
].pin
= -1;
1603 irq_2_pin
[i
].next
= 0;
1606 for (i
= 0; i
< MAX_PIRQS
; i
++)
1607 pirq_entries
[i
] = -1;
1610 * The number of IO-APIC IRQ registers (== #pins):
1612 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1613 spin_lock_irqsave(&ioapic_lock
, flags
);
1614 reg_01
.raw
= io_apic_read(apic
, 1);
1615 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1616 nr_ioapic_registers
[apic
] = reg_01
.bits
.entries
+1;
1618 for(apic
= 0; apic
< nr_ioapics
; apic
++) {
1620 /* See if any of the pins is in ExtINT mode */
1621 for (pin
= 0; pin
< nr_ioapic_registers
[apic
]; pin
++) {
1622 struct IO_APIC_route_entry entry
;
1623 entry
= ioapic_read_entry(apic
, pin
);
1626 /* If the interrupt line is enabled and in ExtInt mode
1627 * I have found the pin where the i8259 is connected.
1629 if ((entry
.mask
== 0) && (entry
.delivery_mode
== dest_ExtINT
)) {
1630 ioapic_i8259
.apic
= apic
;
1631 ioapic_i8259
.pin
= pin
;
1637 /* Look to see what if the MP table has reported the ExtINT */
1638 /* If we could not find the appropriate pin by looking at the ioapic
1639 * the i8259 probably is not connected the ioapic but give the
1640 * mptable a chance anyway.
1642 i8259_pin
= find_isa_irq_pin(0, mp_ExtINT
);
1643 i8259_apic
= find_isa_irq_apic(0, mp_ExtINT
);
1644 /* Trust the MP table if nothing is setup in the hardware */
1645 if ((ioapic_i8259
.pin
== -1) && (i8259_pin
>= 0)) {
1646 printk(KERN_WARNING
"ExtINT not setup in hardware but reported by MP table\n");
1647 ioapic_i8259
.pin
= i8259_pin
;
1648 ioapic_i8259
.apic
= i8259_apic
;
1650 /* Complain if the MP table and the hardware disagree */
1651 if (((ioapic_i8259
.apic
!= i8259_apic
) || (ioapic_i8259
.pin
!= i8259_pin
)) &&
1652 (i8259_pin
>= 0) && (ioapic_i8259
.pin
>= 0))
1654 printk(KERN_WARNING
"ExtINT in hardware and MP table differ\n");
1658 * Do not trust the IO-APIC being empty at bootup
1664 * Not an __init, needed by the reboot code
1666 void disable_IO_APIC(void)
1669 * Clear the IO-APIC before rebooting:
1674 * If the i8259 is routed through an IOAPIC
1675 * Put that IOAPIC in virtual wire mode
1676 * so legacy interrupts can be delivered.
1678 if (ioapic_i8259
.pin
!= -1) {
1679 struct IO_APIC_route_entry entry
;
1681 memset(&entry
, 0, sizeof(entry
));
1682 entry
.mask
= 0; /* Enabled */
1683 entry
.trigger
= 0; /* Edge */
1685 entry
.polarity
= 0; /* High */
1686 entry
.delivery_status
= 0;
1687 entry
.dest_mode
= 0; /* Physical */
1688 entry
.delivery_mode
= dest_ExtINT
; /* ExtInt */
1690 entry
.dest
.physical
.physical_dest
=
1691 GET_APIC_ID(apic_read(APIC_ID
));
1694 * Add it to the IO-APIC irq-routing table:
1696 ioapic_write_entry(ioapic_i8259
.apic
, ioapic_i8259
.pin
, entry
);
1698 disconnect_bsp_APIC(ioapic_i8259
.pin
!= -1);
1702 * function to set the IO-APIC physical IDs based on the
1703 * values stored in the MPC table.
1705 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1708 #ifndef CONFIG_X86_NUMAQ
1709 static void __init
setup_ioapic_ids_from_mpc(void)
1711 union IO_APIC_reg_00 reg_00
;
1712 physid_mask_t phys_id_present_map
;
1715 unsigned char old_id
;
1716 unsigned long flags
;
1719 * Don't check I/O APIC IDs for xAPIC systems. They have
1720 * no meaning without the serial APIC bus.
1722 if (!(boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
)
1723 || APIC_XAPIC(apic_version
[boot_cpu_physical_apicid
]))
1726 * This is broken; anything with a real cpu count has to
1727 * circumvent this idiocy regardless.
1729 phys_id_present_map
= ioapic_phys_id_map(phys_cpu_present_map
);
1732 * Set the IOAPIC ID to the value stored in the MPC table.
1734 for (apic
= 0; apic
< nr_ioapics
; apic
++) {
1736 /* Read the register 0 value */
1737 spin_lock_irqsave(&ioapic_lock
, flags
);
1738 reg_00
.raw
= io_apic_read(apic
, 0);
1739 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1741 old_id
= mp_ioapics
[apic
].mpc_apicid
;
1743 if (mp_ioapics
[apic
].mpc_apicid
>= get_physical_broadcast()) {
1744 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1745 apic
, mp_ioapics
[apic
].mpc_apicid
);
1746 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1748 mp_ioapics
[apic
].mpc_apicid
= reg_00
.bits
.ID
;
1752 * Sanity check, is the ID really free? Every APIC in a
1753 * system must have a unique ID or we get lots of nice
1754 * 'stuck on smp_invalidate_needed IPI wait' messages.
1756 if (check_apicid_used(phys_id_present_map
,
1757 mp_ioapics
[apic
].mpc_apicid
)) {
1758 printk(KERN_ERR
"BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1759 apic
, mp_ioapics
[apic
].mpc_apicid
);
1760 for (i
= 0; i
< get_physical_broadcast(); i
++)
1761 if (!physid_isset(i
, phys_id_present_map
))
1763 if (i
>= get_physical_broadcast())
1764 panic("Max APIC ID exceeded!\n");
1765 printk(KERN_ERR
"... fixing up to %d. (tell your hw vendor)\n",
1767 physid_set(i
, phys_id_present_map
);
1768 mp_ioapics
[apic
].mpc_apicid
= i
;
1771 tmp
= apicid_to_cpu_present(mp_ioapics
[apic
].mpc_apicid
);
1772 apic_printk(APIC_VERBOSE
, "Setting %d in the "
1773 "phys_id_present_map\n",
1774 mp_ioapics
[apic
].mpc_apicid
);
1775 physids_or(phys_id_present_map
, phys_id_present_map
, tmp
);
1780 * We need to adjust the IRQ routing table
1781 * if the ID changed.
1783 if (old_id
!= mp_ioapics
[apic
].mpc_apicid
)
1784 for (i
= 0; i
< mp_irq_entries
; i
++)
1785 if (mp_irqs
[i
].mpc_dstapic
== old_id
)
1786 mp_irqs
[i
].mpc_dstapic
1787 = mp_ioapics
[apic
].mpc_apicid
;
1790 * Read the right value from the MPC table and
1791 * write it into the ID register.
1793 apic_printk(APIC_VERBOSE
, KERN_INFO
1794 "...changing IO-APIC physical APIC ID to %d ...",
1795 mp_ioapics
[apic
].mpc_apicid
);
1797 reg_00
.bits
.ID
= mp_ioapics
[apic
].mpc_apicid
;
1798 spin_lock_irqsave(&ioapic_lock
, flags
);
1799 io_apic_write(apic
, 0, reg_00
.raw
);
1800 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1805 spin_lock_irqsave(&ioapic_lock
, flags
);
1806 reg_00
.raw
= io_apic_read(apic
, 0);
1807 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1808 if (reg_00
.bits
.ID
!= mp_ioapics
[apic
].mpc_apicid
)
1809 printk("could not set ID!\n");
1811 apic_printk(APIC_VERBOSE
, " ok.\n");
1815 static void __init
setup_ioapic_ids_from_mpc(void) { }
1818 int no_timer_check __initdata
;
1820 static int __init
notimercheck(char *s
)
1825 __setup("no_timer_check", notimercheck
);
1828 * There is a nasty bug in some older SMP boards, their mptable lies
1829 * about the timer IRQ. We do the following to work around the situation:
1831 * - timer IRQ defaults to IO-APIC IRQ
1832 * - if this function detects that timer IRQs are defunct, then we fall
1833 * back to ISA timer IRQs
1835 static int __init
timer_irq_works(void)
1837 unsigned long t1
= jiffies
;
1838 unsigned long flags
;
1843 local_save_flags(flags
);
1845 /* Let ten ticks pass... */
1846 mdelay((10 * 1000) / HZ
);
1847 local_irq_restore(flags
);
1850 * Expect a few ticks at least, to be sure some possible
1851 * glue logic does not lock up after one or two first
1852 * ticks in a non-ExtINT mode. Also the local APIC
1853 * might have cached one ExtINT interrupt. Finally, at
1854 * least one tick may be lost due to delays.
1856 if (time_after(jiffies
, t1
+ 4))
1863 * In the SMP+IOAPIC case it might happen that there are an unspecified
1864 * number of pending IRQ events unhandled. These cases are very rare,
1865 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1866 * better to do it this way as thus we do not have to be aware of
1867 * 'pending' interrupts in the IRQ path, except at this point.
1870 * Edge triggered needs to resend any interrupt
1871 * that was delayed but this is now handled in the device
1878 * Starting up a edge-triggered IO-APIC interrupt is
1879 * nasty - we need to make sure that we get the edge.
1880 * If it is already asserted for some reason, we need
1881 * return 1 to indicate that is was pending.
1883 * This is not complete - we should be able to fake
1884 * an edge even if it isn't on the 8259A...
1886 * (We do this for level-triggered IRQs too - it cannot hurt.)
1888 static unsigned int startup_ioapic_irq(unsigned int irq
)
1890 int was_pending
= 0;
1891 unsigned long flags
;
1893 spin_lock_irqsave(&ioapic_lock
, flags
);
1895 disable_8259A_irq(irq
);
1896 if (i8259A_irq_pending(irq
))
1899 __unmask_IO_APIC_irq(irq
);
1900 spin_unlock_irqrestore(&ioapic_lock
, flags
);
1905 static void ack_ioapic_irq(unsigned int irq
)
1907 move_native_irq(irq
);
1911 static void ack_ioapic_quirk_irq(unsigned int irq
)
1916 move_native_irq(irq
);
1918 * It appears there is an erratum which affects at least version 0x11
1919 * of I/O APIC (that's the 82093AA and cores integrated into various
1920 * chipsets). Under certain conditions a level-triggered interrupt is
1921 * erroneously delivered as edge-triggered one but the respective IRR
1922 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1923 * message but it will never arrive and further interrupts are blocked
1924 * from the source. The exact reason is so far unknown, but the
1925 * phenomenon was observed when two consecutive interrupt requests
1926 * from a given source get delivered to the same CPU and the source is
1927 * temporarily disabled in between.
1929 * A workaround is to simulate an EOI message manually. We achieve it
1930 * by setting the trigger mode to edge and then to level when the edge
1931 * trigger mode gets detected in the TMR of a local APIC for a
1932 * level-triggered interrupt. We mask the source for the time of the
1933 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1934 * The idea is from Manfred Spraul. --macro
1936 i
= irq_vector
[irq
];
1938 v
= apic_read(APIC_TMR
+ ((i
& ~0x1f) >> 1));
1942 if (!(v
& (1 << (i
& 0x1f)))) {
1943 atomic_inc(&irq_mis_count
);
1944 spin_lock(&ioapic_lock
);
1945 __mask_and_edge_IO_APIC_irq(irq
);
1946 __unmask_and_level_IO_APIC_irq(irq
);
1947 spin_unlock(&ioapic_lock
);
1951 static int ioapic_retrigger_irq(unsigned int irq
)
1953 send_IPI_self(irq_vector
[irq
]);
1958 static struct irq_chip ioapic_chip __read_mostly
= {
1960 .startup
= startup_ioapic_irq
,
1961 .mask
= mask_IO_APIC_irq
,
1962 .unmask
= unmask_IO_APIC_irq
,
1963 .ack
= ack_ioapic_irq
,
1964 .eoi
= ack_ioapic_quirk_irq
,
1966 .set_affinity
= set_ioapic_affinity_irq
,
1968 .retrigger
= ioapic_retrigger_irq
,
1972 static inline void init_IO_APIC_traps(void)
1977 * NOTE! The local APIC isn't very good at handling
1978 * multiple interrupts at the same interrupt level.
1979 * As the interrupt level is determined by taking the
1980 * vector number and shifting that right by 4, we
1981 * want to spread these out a bit so that they don't
1982 * all fall in the same interrupt level.
1984 * Also, we've got to be careful not to trash gate
1985 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1987 for (irq
= 0; irq
< NR_IRQS
; irq
++) {
1989 if (IO_APIC_IRQ(tmp
) && !irq_vector
[tmp
]) {
1991 * Hmm.. We don't have an entry for this,
1992 * so default to an old-fashioned 8259
1993 * interrupt if we can..
1996 make_8259A_irq(irq
);
1998 /* Strange. Oh, well.. */
1999 irq_desc
[irq
].chip
= &no_irq_chip
;
2005 * The local APIC irq-chip implementation:
2008 static void ack_apic(unsigned int irq
)
2013 static void mask_lapic_irq (unsigned int irq
)
2017 v
= apic_read(APIC_LVT0
);
2018 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
2021 static void unmask_lapic_irq (unsigned int irq
)
2025 v
= apic_read(APIC_LVT0
);
2026 apic_write_around(APIC_LVT0
, v
& ~APIC_LVT_MASKED
);
2029 static struct irq_chip lapic_chip __read_mostly
= {
2030 .name
= "local-APIC-edge",
2031 .mask
= mask_lapic_irq
,
2032 .unmask
= unmask_lapic_irq
,
2036 static void __init
setup_nmi(void)
2039 * Dirty trick to enable the NMI watchdog ...
2040 * We put the 8259A master into AEOI mode and
2041 * unmask on all local APICs LVT0 as NMI.
2043 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2044 * is from Maciej W. Rozycki - so we do not have to EOI from
2045 * the NMI handler or the timer interrupt.
2047 apic_printk(APIC_VERBOSE
, KERN_INFO
"activating NMI Watchdog ...");
2049 enable_NMI_through_LVT0();
2051 apic_printk(APIC_VERBOSE
, " done.\n");
2055 * This looks a bit hackish but it's about the only one way of sending
2056 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2057 * not support the ExtINT mode, unfortunately. We need to send these
2058 * cycles as some i82489DX-based boards have glue logic that keeps the
2059 * 8259A interrupt line asserted until INTA. --macro
2061 static inline void unlock_ExtINT_logic(void)
2064 struct IO_APIC_route_entry entry0
, entry1
;
2065 unsigned char save_control
, save_freq_select
;
2067 pin
= find_isa_irq_pin(8, mp_INT
);
2072 apic
= find_isa_irq_apic(8, mp_INT
);
2078 entry0
= ioapic_read_entry(apic
, pin
);
2079 clear_IO_APIC_pin(apic
, pin
);
2081 memset(&entry1
, 0, sizeof(entry1
));
2083 entry1
.dest_mode
= 0; /* physical delivery */
2084 entry1
.mask
= 0; /* unmask IRQ now */
2085 entry1
.dest
.physical
.physical_dest
= hard_smp_processor_id();
2086 entry1
.delivery_mode
= dest_ExtINT
;
2087 entry1
.polarity
= entry0
.polarity
;
2091 ioapic_write_entry(apic
, pin
, entry1
);
2093 save_control
= CMOS_READ(RTC_CONTROL
);
2094 save_freq_select
= CMOS_READ(RTC_FREQ_SELECT
);
2095 CMOS_WRITE((save_freq_select
& ~RTC_RATE_SELECT
) | 0x6,
2097 CMOS_WRITE(save_control
| RTC_PIE
, RTC_CONTROL
);
2102 if ((CMOS_READ(RTC_INTR_FLAGS
) & RTC_PF
) == RTC_PF
)
2106 CMOS_WRITE(save_control
, RTC_CONTROL
);
2107 CMOS_WRITE(save_freq_select
, RTC_FREQ_SELECT
);
2108 clear_IO_APIC_pin(apic
, pin
);
2110 ioapic_write_entry(apic
, pin
, entry0
);
2113 int timer_uses_ioapic_pin_0
;
2116 * This code may look a bit paranoid, but it's supposed to cooperate with
2117 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2118 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2119 * fanatically on his truly buggy board.
2121 static inline void __init
check_timer(void)
2123 int apic1
, pin1
, apic2
, pin2
;
2125 unsigned long flags
;
2127 local_irq_save(flags
);
2130 * get/set the timer IRQ vector:
2132 disable_8259A_irq(0);
2133 vector
= assign_irq_vector(0);
2134 set_intr_gate(vector
, interrupt
[0]);
2137 * Subtle, code in do_timer_interrupt() expects an AEOI
2138 * mode for the 8259A whenever interrupts are routed
2139 * through I/O APICs. Also IRQ0 has to be enabled in
2140 * the 8259A which implies the virtual wire has to be
2141 * disabled in the local APIC.
2143 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_EXTINT
);
2146 if (timer_over_8254
> 0)
2147 enable_8259A_irq(0);
2149 pin1
= find_isa_irq_pin(0, mp_INT
);
2150 apic1
= find_isa_irq_apic(0, mp_INT
);
2151 pin2
= ioapic_i8259
.pin
;
2152 apic2
= ioapic_i8259
.apic
;
2155 timer_uses_ioapic_pin_0
= 1;
2157 printk(KERN_INFO
"..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
2158 vector
, apic1
, pin1
, apic2
, pin2
);
2162 * Ok, does IRQ0 through the IOAPIC work?
2164 unmask_IO_APIC_irq(0);
2165 if (timer_irq_works()) {
2166 if (nmi_watchdog
== NMI_IO_APIC
) {
2167 disable_8259A_irq(0);
2169 enable_8259A_irq(0);
2171 if (disable_timer_pin_1
> 0)
2172 clear_IO_APIC_pin(0, pin1
);
2175 clear_IO_APIC_pin(apic1
, pin1
);
2176 printk(KERN_ERR
"..MP-BIOS bug: 8254 timer not connected to "
2180 printk(KERN_INFO
"...trying to set up timer (IRQ0) through the 8259A ... ");
2182 printk("\n..... (found pin %d) ...", pin2
);
2184 * legacy devices should be connected to IO APIC #0
2186 setup_ExtINT_IRQ0_pin(apic2
, pin2
, vector
);
2187 if (timer_irq_works()) {
2190 replace_pin_at_irq(0, apic1
, pin1
, apic2
, pin2
);
2192 add_pin_to_irq(0, apic2
, pin2
);
2193 if (nmi_watchdog
== NMI_IO_APIC
) {
2199 * Cleanup, just in case ...
2201 clear_IO_APIC_pin(apic2
, pin2
);
2203 printk(" failed.\n");
2205 if (nmi_watchdog
== NMI_IO_APIC
) {
2206 printk(KERN_WARNING
"timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2210 printk(KERN_INFO
"...trying to set up timer as Virtual Wire IRQ...");
2212 disable_8259A_irq(0);
2213 set_irq_chip_and_handler_name(0, &lapic_chip
, handle_fasteoi_irq
,
2215 apic_write_around(APIC_LVT0
, APIC_DM_FIXED
| vector
); /* Fixed mode */
2216 enable_8259A_irq(0);
2218 if (timer_irq_works()) {
2219 printk(" works.\n");
2222 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
| APIC_DM_FIXED
| vector
);
2223 printk(" failed.\n");
2225 printk(KERN_INFO
"...trying to set up timer as ExtINT IRQ...");
2230 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
2232 unlock_ExtINT_logic();
2234 if (timer_irq_works()) {
2235 printk(" works.\n");
2238 printk(" failed :(.\n");
2239 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2240 "report. Then try booting with the 'noapic' option");
2242 local_irq_restore(flags
);
2247 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2248 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2249 * Linux doesn't really care, as it's not actually used
2250 * for any interrupt handling anyway.
2252 #define PIC_IRQS (1 << PIC_CASCADE_IR)
2254 void __init
setup_IO_APIC(void)
2258 /* Reserve all the system vectors. */
2259 for (i
= FIRST_SYSTEM_VECTOR
; i
< NR_VECTORS
; i
++)
2260 set_bit(i
, used_vectors
);
2265 io_apic_irqs
= ~0; /* all IRQs go through IOAPIC */
2267 io_apic_irqs
= ~PIC_IRQS
;
2269 printk("ENABLING IO-APIC IRQs\n");
2272 * Set up IO-APIC IRQ routing.
2275 setup_ioapic_ids_from_mpc();
2277 setup_IO_APIC_irqs();
2278 init_IO_APIC_traps();
2284 static int __init
setup_disable_8254_timer(char *s
)
2286 timer_over_8254
= -1;
2289 static int __init
setup_enable_8254_timer(char *s
)
2291 timer_over_8254
= 2;
2295 __setup("disable_8254_timer", setup_disable_8254_timer
);
2296 __setup("enable_8254_timer", setup_enable_8254_timer
);
2299 * Called after all the initialization is done. If we didnt find any
2300 * APIC bugs then we can allow the modify fast path
2303 static int __init
io_apic_bug_finalize(void)
2305 if(sis_apic_bug
== -1)
2310 late_initcall(io_apic_bug_finalize
);
2312 struct sysfs_ioapic_data
{
2313 struct sys_device dev
;
2314 struct IO_APIC_route_entry entry
[0];
2316 static struct sysfs_ioapic_data
* mp_ioapic_data
[MAX_IO_APICS
];
2318 static int ioapic_suspend(struct sys_device
*dev
, pm_message_t state
)
2320 struct IO_APIC_route_entry
*entry
;
2321 struct sysfs_ioapic_data
*data
;
2324 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2325 entry
= data
->entry
;
2326 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2327 entry
[i
] = ioapic_read_entry(dev
->id
, i
);
2332 static int ioapic_resume(struct sys_device
*dev
)
2334 struct IO_APIC_route_entry
*entry
;
2335 struct sysfs_ioapic_data
*data
;
2336 unsigned long flags
;
2337 union IO_APIC_reg_00 reg_00
;
2340 data
= container_of(dev
, struct sysfs_ioapic_data
, dev
);
2341 entry
= data
->entry
;
2343 spin_lock_irqsave(&ioapic_lock
, flags
);
2344 reg_00
.raw
= io_apic_read(dev
->id
, 0);
2345 if (reg_00
.bits
.ID
!= mp_ioapics
[dev
->id
].mpc_apicid
) {
2346 reg_00
.bits
.ID
= mp_ioapics
[dev
->id
].mpc_apicid
;
2347 io_apic_write(dev
->id
, 0, reg_00
.raw
);
2349 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2350 for (i
= 0; i
< nr_ioapic_registers
[dev
->id
]; i
++)
2351 ioapic_write_entry(dev
->id
, i
, entry
[i
]);
2356 static struct sysdev_class ioapic_sysdev_class
= {
2358 .suspend
= ioapic_suspend
,
2359 .resume
= ioapic_resume
,
2362 static int __init
ioapic_init_sysfs(void)
2364 struct sys_device
* dev
;
2365 int i
, size
, error
= 0;
2367 error
= sysdev_class_register(&ioapic_sysdev_class
);
2371 for (i
= 0; i
< nr_ioapics
; i
++ ) {
2372 size
= sizeof(struct sys_device
) + nr_ioapic_registers
[i
]
2373 * sizeof(struct IO_APIC_route_entry
);
2374 mp_ioapic_data
[i
] = kmalloc(size
, GFP_KERNEL
);
2375 if (!mp_ioapic_data
[i
]) {
2376 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2379 memset(mp_ioapic_data
[i
], 0, size
);
2380 dev
= &mp_ioapic_data
[i
]->dev
;
2382 dev
->cls
= &ioapic_sysdev_class
;
2383 error
= sysdev_register(dev
);
2385 kfree(mp_ioapic_data
[i
]);
2386 mp_ioapic_data
[i
] = NULL
;
2387 printk(KERN_ERR
"Can't suspend/resume IOAPIC %d\n", i
);
2395 device_initcall(ioapic_init_sysfs
);
2398 * Dynamic irq allocate and deallocation
2400 int create_irq(void)
2402 /* Allocate an unused irq */
2403 int irq
, new, vector
= 0;
2404 unsigned long flags
;
2407 spin_lock_irqsave(&vector_lock
, flags
);
2408 for (new = (NR_IRQS
- 1); new >= 0; new--) {
2409 if (platform_legacy_irq(new))
2411 if (irq_vector
[new] != 0)
2413 vector
= __assign_irq_vector(new);
2414 if (likely(vector
> 0))
2418 spin_unlock_irqrestore(&vector_lock
, flags
);
2421 set_intr_gate(vector
, interrupt
[irq
]);
2422 dynamic_irq_init(irq
);
2427 void destroy_irq(unsigned int irq
)
2429 unsigned long flags
;
2431 dynamic_irq_cleanup(irq
);
2433 spin_lock_irqsave(&vector_lock
, flags
);
2434 irq_vector
[irq
] = 0;
2435 spin_unlock_irqrestore(&vector_lock
, flags
);
2439 * MSI message composition
2441 #ifdef CONFIG_PCI_MSI
2442 static int msi_compose_msg(struct pci_dev
*pdev
, unsigned int irq
, struct msi_msg
*msg
)
2447 vector
= assign_irq_vector(irq
);
2449 dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2451 msg
->address_hi
= MSI_ADDR_BASE_HI
;
2454 ((INT_DEST_MODE
== 0) ?
2455 MSI_ADDR_DEST_MODE_PHYSICAL
:
2456 MSI_ADDR_DEST_MODE_LOGICAL
) |
2457 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2458 MSI_ADDR_REDIRECTION_CPU
:
2459 MSI_ADDR_REDIRECTION_LOWPRI
) |
2460 MSI_ADDR_DEST_ID(dest
);
2463 MSI_DATA_TRIGGER_EDGE
|
2464 MSI_DATA_LEVEL_ASSERT
|
2465 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2466 MSI_DATA_DELIVERY_FIXED
:
2467 MSI_DATA_DELIVERY_LOWPRI
) |
2468 MSI_DATA_VECTOR(vector
);
2474 static void set_msi_irq_affinity(unsigned int irq
, cpumask_t mask
)
2481 cpus_and(tmp
, mask
, cpu_online_map
);
2482 if (cpus_empty(tmp
))
2485 vector
= assign_irq_vector(irq
);
2489 dest
= cpu_mask_to_apicid(mask
);
2491 read_msi_msg(irq
, &msg
);
2493 msg
.data
&= ~MSI_DATA_VECTOR_MASK
;
2494 msg
.data
|= MSI_DATA_VECTOR(vector
);
2495 msg
.address_lo
&= ~MSI_ADDR_DEST_ID_MASK
;
2496 msg
.address_lo
|= MSI_ADDR_DEST_ID(dest
);
2498 write_msi_msg(irq
, &msg
);
2499 irq_desc
[irq
].affinity
= mask
;
2501 #endif /* CONFIG_SMP */
2504 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2505 * which implement the MSI or MSI-X Capability Structure.
2507 static struct irq_chip msi_chip
= {
2509 .unmask
= unmask_msi_irq
,
2510 .mask
= mask_msi_irq
,
2511 .ack
= ack_ioapic_irq
,
2513 .set_affinity
= set_msi_irq_affinity
,
2515 .retrigger
= ioapic_retrigger_irq
,
2518 int arch_setup_msi_irq(struct pci_dev
*dev
, struct msi_desc
*desc
)
2526 ret
= msi_compose_msg(dev
, irq
, &msg
);
2532 set_irq_msi(irq
, desc
);
2533 write_msi_msg(irq
, &msg
);
2535 set_irq_chip_and_handler_name(irq
, &msi_chip
, handle_edge_irq
,
2541 void arch_teardown_msi_irq(unsigned int irq
)
2546 #endif /* CONFIG_PCI_MSI */
2549 * Hypertransport interrupt support
2551 #ifdef CONFIG_HT_IRQ
2555 static void target_ht_irq(unsigned int irq
, unsigned int dest
)
2557 struct ht_irq_msg msg
;
2558 fetch_ht_irq_msg(irq
, &msg
);
2560 msg
.address_lo
&= ~(HT_IRQ_LOW_DEST_ID_MASK
);
2561 msg
.address_hi
&= ~(HT_IRQ_HIGH_DEST_ID_MASK
);
2563 msg
.address_lo
|= HT_IRQ_LOW_DEST_ID(dest
);
2564 msg
.address_hi
|= HT_IRQ_HIGH_DEST_ID(dest
);
2566 write_ht_irq_msg(irq
, &msg
);
2569 static void set_ht_irq_affinity(unsigned int irq
, cpumask_t mask
)
2574 cpus_and(tmp
, mask
, cpu_online_map
);
2575 if (cpus_empty(tmp
))
2578 cpus_and(mask
, tmp
, CPU_MASK_ALL
);
2580 dest
= cpu_mask_to_apicid(mask
);
2582 target_ht_irq(irq
, dest
);
2583 irq_desc
[irq
].affinity
= mask
;
2587 static struct irq_chip ht_irq_chip
= {
2589 .mask
= mask_ht_irq
,
2590 .unmask
= unmask_ht_irq
,
2591 .ack
= ack_ioapic_irq
,
2593 .set_affinity
= set_ht_irq_affinity
,
2595 .retrigger
= ioapic_retrigger_irq
,
2598 int arch_setup_ht_irq(unsigned int irq
, struct pci_dev
*dev
)
2602 vector
= assign_irq_vector(irq
);
2604 struct ht_irq_msg msg
;
2609 cpu_set(vector
>> 8, tmp
);
2610 dest
= cpu_mask_to_apicid(tmp
);
2612 msg
.address_hi
= HT_IRQ_HIGH_DEST_ID(dest
);
2616 HT_IRQ_LOW_DEST_ID(dest
) |
2617 HT_IRQ_LOW_VECTOR(vector
) |
2618 ((INT_DEST_MODE
== 0) ?
2619 HT_IRQ_LOW_DM_PHYSICAL
:
2620 HT_IRQ_LOW_DM_LOGICAL
) |
2621 HT_IRQ_LOW_RQEOI_EDGE
|
2622 ((INT_DELIVERY_MODE
!= dest_LowestPrio
) ?
2623 HT_IRQ_LOW_MT_FIXED
:
2624 HT_IRQ_LOW_MT_ARBITRATED
) |
2625 HT_IRQ_LOW_IRQ_MASKED
;
2627 write_ht_irq_msg(irq
, &msg
);
2629 set_irq_chip_and_handler_name(irq
, &ht_irq_chip
,
2630 handle_edge_irq
, "edge");
2634 #endif /* CONFIG_HT_IRQ */
2636 /* --------------------------------------------------------------------------
2637 ACPI-based IOAPIC Configuration
2638 -------------------------------------------------------------------------- */
2642 int __init
io_apic_get_unique_id (int ioapic
, int apic_id
)
2644 union IO_APIC_reg_00 reg_00
;
2645 static physid_mask_t apic_id_map
= PHYSID_MASK_NONE
;
2647 unsigned long flags
;
2651 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2652 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2653 * supports up to 16 on one shared APIC bus.
2655 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2656 * advantage of new APIC bus architecture.
2659 if (physids_empty(apic_id_map
))
2660 apic_id_map
= ioapic_phys_id_map(phys_cpu_present_map
);
2662 spin_lock_irqsave(&ioapic_lock
, flags
);
2663 reg_00
.raw
= io_apic_read(ioapic
, 0);
2664 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2666 if (apic_id
>= get_physical_broadcast()) {
2667 printk(KERN_WARNING
"IOAPIC[%d]: Invalid apic_id %d, trying "
2668 "%d\n", ioapic
, apic_id
, reg_00
.bits
.ID
);
2669 apic_id
= reg_00
.bits
.ID
;
2673 * Every APIC in a system must have a unique ID or we get lots of nice
2674 * 'stuck on smp_invalidate_needed IPI wait' messages.
2676 if (check_apicid_used(apic_id_map
, apic_id
)) {
2678 for (i
= 0; i
< get_physical_broadcast(); i
++) {
2679 if (!check_apicid_used(apic_id_map
, i
))
2683 if (i
== get_physical_broadcast())
2684 panic("Max apic_id exceeded!\n");
2686 printk(KERN_WARNING
"IOAPIC[%d]: apic_id %d already used, "
2687 "trying %d\n", ioapic
, apic_id
, i
);
2692 tmp
= apicid_to_cpu_present(apic_id
);
2693 physids_or(apic_id_map
, apic_id_map
, tmp
);
2695 if (reg_00
.bits
.ID
!= apic_id
) {
2696 reg_00
.bits
.ID
= apic_id
;
2698 spin_lock_irqsave(&ioapic_lock
, flags
);
2699 io_apic_write(ioapic
, 0, reg_00
.raw
);
2700 reg_00
.raw
= io_apic_read(ioapic
, 0);
2701 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2704 if (reg_00
.bits
.ID
!= apic_id
) {
2705 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic
);
2710 apic_printk(APIC_VERBOSE
, KERN_INFO
2711 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic
, apic_id
);
2717 int __init
io_apic_get_version (int ioapic
)
2719 union IO_APIC_reg_01 reg_01
;
2720 unsigned long flags
;
2722 spin_lock_irqsave(&ioapic_lock
, flags
);
2723 reg_01
.raw
= io_apic_read(ioapic
, 1);
2724 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2726 return reg_01
.bits
.version
;
2730 int __init
io_apic_get_redir_entries (int ioapic
)
2732 union IO_APIC_reg_01 reg_01
;
2733 unsigned long flags
;
2735 spin_lock_irqsave(&ioapic_lock
, flags
);
2736 reg_01
.raw
= io_apic_read(ioapic
, 1);
2737 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2739 return reg_01
.bits
.entries
;
2743 int io_apic_set_pci_routing (int ioapic
, int pin
, int irq
, int edge_level
, int active_high_low
)
2745 struct IO_APIC_route_entry entry
;
2746 unsigned long flags
;
2748 if (!IO_APIC_IRQ(irq
)) {
2749 printk(KERN_ERR
"IOAPIC[%d]: Invalid reference to IRQ 0\n",
2755 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2756 * Note that we mask (disable) IRQs now -- these get enabled when the
2757 * corresponding device driver registers for this IRQ.
2760 memset(&entry
,0,sizeof(entry
));
2762 entry
.delivery_mode
= INT_DELIVERY_MODE
;
2763 entry
.dest_mode
= INT_DEST_MODE
;
2764 entry
.dest
.logical
.logical_dest
= cpu_mask_to_apicid(TARGET_CPUS
);
2765 entry
.trigger
= edge_level
;
2766 entry
.polarity
= active_high_low
;
2770 * IRQs < 16 are already in the irq_2_pin[] map
2773 add_pin_to_irq(irq
, ioapic
, pin
);
2775 entry
.vector
= assign_irq_vector(irq
);
2777 apic_printk(APIC_DEBUG
, KERN_DEBUG
"IOAPIC[%d]: Set PCI routing entry "
2778 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic
,
2779 mp_ioapics
[ioapic
].mpc_apicid
, pin
, entry
.vector
, irq
,
2780 edge_level
, active_high_low
);
2782 ioapic_register_intr(irq
, entry
.vector
, edge_level
);
2784 if (!ioapic
&& (irq
< 16))
2785 disable_8259A_irq(irq
);
2787 spin_lock_irqsave(&ioapic_lock
, flags
);
2788 __ioapic_write_entry(ioapic
, pin
, entry
);
2789 spin_unlock_irqrestore(&ioapic_lock
, flags
);
2794 int acpi_get_override_irq(int bus_irq
, int *trigger
, int *polarity
)
2798 if (skip_ioapic_setup
)
2801 for (i
= 0; i
< mp_irq_entries
; i
++)
2802 if (mp_irqs
[i
].mpc_irqtype
== mp_INT
&&
2803 mp_irqs
[i
].mpc_srcbusirq
== bus_irq
)
2805 if (i
>= mp_irq_entries
)
2808 *trigger
= irq_trigger(i
);
2809 *polarity
= irq_polarity(i
);
2813 #endif /* CONFIG_ACPI */
2815 static int __init
parse_disable_timer_pin_1(char *arg
)
2817 disable_timer_pin_1
= 1;
2820 early_param("disable_timer_pin_1", parse_disable_timer_pin_1
);
2822 static int __init
parse_enable_timer_pin_1(char *arg
)
2824 disable_timer_pin_1
= -1;
2827 early_param("enable_timer_pin_1", parse_enable_timer_pin_1
);
2829 static int __init
parse_noapic(char *arg
)
2831 /* disable IO-APIC */
2832 disable_ioapic_setup();
2835 early_param("noapic", parse_noapic
);