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[PATCH] typo fix in last cpufreq powernow patch
[linux-2.6/mini2440.git] / drivers / ide / pci / amd74xx.c
blob844a6c9fb9490e585fc5371d759840b9e7ae327c
1 /*
2 * Version 2.13
3 *
4 * AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04
5 * IDE driver for Linux.
6 *
7 * Copyright (c) 2000-2002 Vojtech Pavlik
8 *
9 * Based on the work of:
10 * Andre Hedrick
11 */
12
13 /*
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License version 2 as published by
16 * the Free Software Foundation.
17 */
18
19 #include <linux/config.h>
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/ioport.h>
23 #include <linux/blkdev.h>
24 #include <linux/pci.h>
25 #include <linux/init.h>
26 #include <linux/ide.h>
27 #include <asm/io.h>
28
29 #include "ide-timing.h"
30
31 #define DISPLAY_AMD_TIMINGS
32
33 #define AMD_IDE_ENABLE (0x00 + amd_config->base)
34 #define AMD_IDE_CONFIG (0x01 + amd_config->base)
35 #define AMD_CABLE_DETECT (0x02 + amd_config->base)
36 #define AMD_DRIVE_TIMING (0x08 + amd_config->base)
37 #define AMD_8BIT_TIMING (0x0e + amd_config->base)
38 #define AMD_ADDRESS_SETUP (0x0c + amd_config->base)
39 #define AMD_UDMA_TIMING (0x10 + amd_config->base)
40
41 #define AMD_UDMA 0x07
42 #define AMD_UDMA_33 0x01
43 #define AMD_UDMA_66 0x02
44 #define AMD_UDMA_100 0x03
45 #define AMD_UDMA_133 0x04
46 #define AMD_CHECK_SWDMA 0x08
47 #define AMD_BAD_SWDMA 0x10
48 #define AMD_BAD_FIFO 0x20
49 #define AMD_CHECK_SERENADE 0x40
50
51 /*
52 * AMD SouthBridge chips.
53 */
54
55 static struct amd_ide_chip {
56 unsigned short id;
57 unsigned long base;
58 unsigned char flags;
59 } amd_ide_chips[] = {
60 { PCI_DEVICE_ID_AMD_COBRA_7401, 0x40, AMD_UDMA_33 | AMD_BAD_SWDMA },
61 { PCI_DEVICE_ID_AMD_VIPER_7409, 0x40, AMD_UDMA_66 | AMD_CHECK_SWDMA },
62 { PCI_DEVICE_ID_AMD_VIPER_7411, 0x40, AMD_UDMA_100 | AMD_BAD_FIFO },
63 { PCI_DEVICE_ID_AMD_OPUS_7441, 0x40, AMD_UDMA_100 },
64 { PCI_DEVICE_ID_AMD_8111_IDE, 0x40, AMD_UDMA_133 | AMD_CHECK_SERENADE },
65 { PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, 0x50, AMD_UDMA_100 },
66 { PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, 0x50, AMD_UDMA_133 },
67 { PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE, 0x50, AMD_UDMA_133 },
68 { PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA, 0x50, AMD_UDMA_133 },
69 { PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE, 0x50, AMD_UDMA_133 },
70 { PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE, 0x50, AMD_UDMA_133 },
71 { PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA, 0x50, AMD_UDMA_133 },
72 { PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2, 0x50, AMD_UDMA_133 },
73 { PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE, 0x50, AMD_UDMA_133 },
74 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE, 0x50, AMD_UDMA_133 },
75 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE, 0x50, AMD_UDMA_133 },
76 { PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE, 0x50, AMD_UDMA_133 },
77 { 0 }
78 };
79
80 static struct amd_ide_chip *amd_config;
81 static ide_pci_device_t *amd_chipset;
82 static unsigned int amd_80w;
83 static unsigned int amd_clock;
84
85 static char *amd_dma[] = { "MWDMA16", "UDMA33", "UDMA66", "UDMA100", "UDMA133" };
86 static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 };
87
88 /*
89 * AMD /proc entry.
90 */
91
92 #ifdef CONFIG_PROC_FS
93
94 #include <linux/stat.h>
95 #include <linux/proc_fs.h>
96
97 static u8 amd74xx_proc;
98
99 static unsigned char amd_udma2cyc[] = { 4, 6, 8, 10, 3, 2, 1, 15 };
100 static unsigned long amd_base;
101 static struct pci_dev *bmide_dev;
102 extern int (*amd74xx_display_info)(char *, char **, off_t, int); /* ide-proc.c */
103
104 #define amd_print(format, arg...) p += sprintf(p, format "\n" , ## arg)
105 #define amd_print_drive(name, format, arg...)\
106 p += sprintf(p, name); for (i = 0; i < 4; i++) p += sprintf(p, format, ## arg); p += sprintf(p, "\n");
107
108 static int amd74xx_get_info(char *buffer, char **addr, off_t offset, int count)
109 {
110 int speed[4], cycle[4], setup[4], active[4], recover[4], den[4],
111 uen[4], udma[4], active8b[4], recover8b[4];
112 struct pci_dev *dev = bmide_dev;
113 unsigned int v, u, i;
114 unsigned short c, w;
115 unsigned char t;
116 int len;
117 char *p = buffer;
118
119 amd_print("----------AMD BusMastering IDE Configuration----------------");
120
121 amd_print("Driver Version: 2.13");
122 amd_print("South Bridge: %s", pci_name(bmide_dev));
123
124 pci_read_config_byte(dev, PCI_REVISION_ID, &t);
125 amd_print("Revision: IDE %#x", t);
126 amd_print("Highest DMA rate: %s", amd_dma[amd_config->flags & AMD_UDMA]);
127
128 amd_print("BM-DMA base: %#lx", amd_base);
129 amd_print("PCI clock: %d.%dMHz", amd_clock / 1000, amd_clock / 100 % 10);
130
131 amd_print("-----------------------Primary IDE-------Secondary IDE------");
132
133 pci_read_config_byte(dev, AMD_IDE_CONFIG, &t);
134 amd_print("Prefetch Buffer: %10s%20s", (t & 0x80) ? "yes" : "no", (t & 0x20) ? "yes" : "no");
135 amd_print("Post Write Buffer: %10s%20s", (t & 0x40) ? "yes" : "no", (t & 0x10) ? "yes" : "no");
136
137 pci_read_config_byte(dev, AMD_IDE_ENABLE, &t);
138 amd_print("Enabled: %10s%20s", (t & 0x02) ? "yes" : "no", (t & 0x01) ? "yes" : "no");
139
140 c = inb(amd_base + 0x02) | (inb(amd_base + 0x0a) << 8);
141 amd_print("Simplex only: %10s%20s", (c & 0x80) ? "yes" : "no", (c & 0x8000) ? "yes" : "no");
142
143 amd_print("Cable Type: %10s%20s", (amd_80w & 1) ? "80w" : "40w", (amd_80w & 2) ? "80w" : "40w");
144
145 if (!amd_clock)
146 return p - buffer;
147
148 amd_print("-------------------drive0----drive1----drive2----drive3-----");
149
150 pci_read_config_byte(dev, AMD_ADDRESS_SETUP, &t);
151 pci_read_config_dword(dev, AMD_DRIVE_TIMING, &v);
152 pci_read_config_word(dev, AMD_8BIT_TIMING, &w);
153 pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
154
155 for (i = 0; i < 4; i++) {
156 setup[i] = ((t >> ((3 - i) << 1)) & 0x3) + 1;
157 recover8b[i] = ((w >> ((1 - (i >> 1)) << 3)) & 0xf) + 1;
158 active8b[i] = ((w >> (((1 - (i >> 1)) << 3) + 4)) & 0xf) + 1;
159 active[i] = ((v >> (((3 - i) << 3) + 4)) & 0xf) + 1;
160 recover[i] = ((v >> ((3 - i) << 3)) & 0xf) + 1;
161
162 udma[i] = amd_udma2cyc[((u >> ((3 - i) << 3)) & 0x7)];
163 uen[i] = ((u >> ((3 - i) << 3)) & 0x40) ? 1 : 0;
164 den[i] = (c & ((i & 1) ? 0x40 : 0x20) << ((i & 2) << 2));
165
166 if (den[i] && uen[i] && udma[i] == 1) {
167 speed[i] = amd_clock * 3;
168 cycle[i] = 666666 / amd_clock;
169 continue;
170 }
171
172 if (den[i] && uen[i] && udma[i] == 15) {
173 speed[i] = amd_clock * 4;
174 cycle[i] = 500000 / amd_clock;
175 continue;
176 }
177
178 speed[i] = 4 * amd_clock / ((den[i] && uen[i]) ? udma[i] : (active[i] + recover[i]) * 2);
179 cycle[i] = 1000000 * ((den[i] && uen[i]) ? udma[i] : (active[i] + recover[i]) * 2) / amd_clock / 2;
180 }
181
182 amd_print_drive("Transfer Mode: ", "%10s", den[i] ? (uen[i] ? "UDMA" : "DMA") : "PIO");
183
184 amd_print_drive("Address Setup: ", "%8dns", 1000000 * setup[i] / amd_clock);
185 amd_print_drive("Cmd Active: ", "%8dns", 1000000 * active8b[i] / amd_clock);
186 amd_print_drive("Cmd Recovery: ", "%8dns", 1000000 * recover8b[i] / amd_clock);
187 amd_print_drive("Data Active: ", "%8dns", 1000000 * active[i] / amd_clock);
188 amd_print_drive("Data Recovery: ", "%8dns", 1000000 * recover[i] / amd_clock);
189 amd_print_drive("Cycle Time: ", "%8dns", cycle[i]);
190 amd_print_drive("Transfer Rate: ", "%4d.%dMB/s", speed[i] / 1000, speed[i] / 100 % 10);
191
192 /* hoping p - buffer is less than 4K... */
193 len = (p - buffer) - offset;
194 *addr = buffer + offset;
195
196 return len > count ? count : len;
197 }
198
199 #endif
200
201 /*
202 * amd_set_speed() writes timing values to the chipset registers
203 */
204
205 static void amd_set_speed(struct pci_dev *dev, unsigned char dn, struct ide_timing *timing)
206 {
207 unsigned char t;
208
209 pci_read_config_byte(dev, AMD_ADDRESS_SETUP, &t);
210 t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
211 pci_write_config_byte(dev, AMD_ADDRESS_SETUP, t);
212
213 pci_write_config_byte(dev, AMD_8BIT_TIMING + (1 - (dn >> 1)),
214 ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));
215
216 pci_write_config_byte(dev, AMD_DRIVE_TIMING + (3 - dn),
217 ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));
218
219 switch (amd_config->flags & AMD_UDMA) {
220 case AMD_UDMA_33: t = timing->udma ? (0xc0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
221 case AMD_UDMA_66: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 2, 10)]) : 0x03; break;
222 case AMD_UDMA_100: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 10)]) : 0x03; break;
223 case AMD_UDMA_133: t = timing->udma ? (0xc0 | amd_cyc2udma[FIT(timing->udma, 1, 15)]) : 0x03; break;
224 default: return;
225 }
226
227 pci_write_config_byte(dev, AMD_UDMA_TIMING + (3 - dn), t);
228 }
229
230 /*
231 * amd_set_drive() computes timing values configures the drive and
232 * the chipset to a desired transfer mode. It also can be called
233 * by upper layers.
234 */
235
236 static int amd_set_drive(ide_drive_t *drive, u8 speed)
237 {
238 ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
239 struct ide_timing t, p;
240 int T, UT;
241
242 if (speed != XFER_PIO_SLOW && speed != drive->current_speed)
243 if (ide_config_drive_speed(drive, speed))
244 printk(KERN_WARNING "ide%d: Drive %d didn't accept speed setting. Oh, well.\n",
245 drive->dn >> 1, drive->dn & 1);
246
247 T = 1000000000 / amd_clock;
248 UT = T / min_t(int, max_t(int, amd_config->flags & AMD_UDMA, 1), 2);
249
250 ide_timing_compute(drive, speed, &t, T, UT);
251
252 if (peer->present) {
253 ide_timing_compute(peer, peer->current_speed, &p, T, UT);
254 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
255 }
256
257 if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1;
258 if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15;
259
260 amd_set_speed(HWIF(drive)->pci_dev, drive->dn, &t);
261
262 if (!drive->init_speed)
263 drive->init_speed = speed;
264 drive->current_speed = speed;
265
266 return 0;
267 }
268
269 /*
270 * amd74xx_tune_drive() is a callback from upper layers for
271 * PIO-only tuning.
272 */
273
274 static void amd74xx_tune_drive(ide_drive_t *drive, u8 pio)
275 {
276 if (pio == 255) {
277 amd_set_drive(drive, ide_find_best_mode(drive, XFER_PIO | XFER_EPIO));
278 return;
279 }
280
281 amd_set_drive(drive, XFER_PIO_0 + min_t(byte, pio, 5));
282 }
283
284 /*
285 * amd74xx_dmaproc() is a callback from upper layers that can do
286 * a lot, but we use it for DMA/PIO tuning only, delegating everything
287 * else to the default ide_dmaproc().
288 */
289
290 static int amd74xx_ide_dma_check(ide_drive_t *drive)
291 {
292 int w80 = HWIF(drive)->udma_four;
293
294 u8 speed = ide_find_best_mode(drive,
295 XFER_PIO | XFER_EPIO | XFER_MWDMA | XFER_UDMA |
296 ((amd_config->flags & AMD_BAD_SWDMA) ? 0 : XFER_SWDMA) |
297 (w80 && (amd_config->flags & AMD_UDMA) >= AMD_UDMA_66 ? XFER_UDMA_66 : 0) |
298 (w80 && (amd_config->flags & AMD_UDMA) >= AMD_UDMA_100 ? XFER_UDMA_100 : 0) |
299 (w80 && (amd_config->flags & AMD_UDMA) >= AMD_UDMA_133 ? XFER_UDMA_133 : 0));
300
301 amd_set_drive(drive, speed);
302
303 if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
304 return HWIF(drive)->ide_dma_on(drive);
305 return HWIF(drive)->ide_dma_off_quietly(drive);
306 }
307
308 /*
309 * The initialization callback. Here we determine the IDE chip type
310 * and initialize its drive independent registers.
311 */
312
313 static unsigned int __devinit init_chipset_amd74xx(struct pci_dev *dev, const char *name)
314 {
315 unsigned char t;
316 unsigned int u;
317 int i;
318
319 /*
320 * Check for bad SWDMA.
321 */
322
323 if (amd_config->flags & AMD_CHECK_SWDMA) {
324 pci_read_config_byte(dev, PCI_REVISION_ID, &t);
325 if (t <= 7)
326 amd_config->flags |= AMD_BAD_SWDMA;
327 }
328
329 /*
330 * Check 80-wire cable presence.
331 */
332
333 switch (amd_config->flags & AMD_UDMA) {
334
335 case AMD_UDMA_133:
336 case AMD_UDMA_100:
337 pci_read_config_byte(dev, AMD_CABLE_DETECT, &t);
338 pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
339 amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0);
340 for (i = 24; i >= 0; i -= 8)
341 if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) {
342 printk(KERN_WARNING "%s: BIOS didn't set cable bits correctly. Enabling workaround.\n",
343 amd_chipset->name);
344 amd_80w |= (1 << (1 - (i >> 4)));
345 }
346 break;
347
348 case AMD_UDMA_66:
349 pci_read_config_dword(dev, AMD_UDMA_TIMING, &u);
350 for (i = 24; i >= 0; i -= 8)
351 if ((u >> i) & 4)
352 amd_80w |= (1 << (1 - (i >> 4)));
353 break;
354 }
355
356 /*
357 * Take care of prefetch & postwrite.
358 */
359
360 pci_read_config_byte(dev, AMD_IDE_CONFIG, &t);
361 pci_write_config_byte(dev, AMD_IDE_CONFIG,
362 (amd_config->flags & AMD_BAD_FIFO) ? (t & 0x0f) : (t | 0xf0));
363
364 /*
365 * Take care of incorrectly wired Serenade mainboards.
366 */
367
368 if ((amd_config->flags & AMD_CHECK_SERENADE) &&
369 dev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
370 dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
371 amd_config->flags = AMD_UDMA_100;
372
373 /*
374 * Determine the system bus clock.
375 */
376
377 amd_clock = system_bus_clock() * 1000;
378
379 switch (amd_clock) {
380 case 33000: amd_clock = 33333; break;
381 case 37000: amd_clock = 37500; break;
382 case 41000: amd_clock = 41666; break;
383 }
384
385 if (amd_clock < 20000 || amd_clock > 50000) {
386 printk(KERN_WARNING "%s: User given PCI clock speed impossible (%d), using 33 MHz instead.\n",
387 amd_chipset->name, amd_clock);
388 printk(KERN_WARNING "%s: Use ide0=ata66 if you want to assume 80-wire cable\n",
389 amd_chipset->name);
390 amd_clock = 33333;
391 }
392
393 /*
394 * Print the boot message.
395 */
396
397 pci_read_config_byte(dev, PCI_REVISION_ID, &t);
398 printk(KERN_INFO "%s: %s (rev %02x) %s controller\n",
399 amd_chipset->name, pci_name(dev), t, amd_dma[amd_config->flags & AMD_UDMA]);
400
401 /*
402 * Register /proc/ide/amd74xx entry
403 */
404
405 #if defined(DISPLAY_AMD_TIMINGS) && defined(CONFIG_PROC_FS)
406 if (!amd74xx_proc) {
407 amd_base = pci_resource_start(dev, 4);
408 bmide_dev = dev;
409 ide_pci_create_host_proc("amd74xx", amd74xx_get_info);
410 amd74xx_proc = 1;
411 }
412 #endif /* DISPLAY_AMD_TIMINGS && CONFIG_PROC_FS */
413
414 return dev->irq;
415 }
416
417 static void __devinit init_hwif_amd74xx(ide_hwif_t *hwif)
418 {
419 int i;
420
421 if (hwif->irq == 0) /* 0 is bogus but will do for now */
422 hwif->irq = pci_get_legacy_ide_irq(hwif->pci_dev, hwif->channel);
423
424 hwif->autodma = 0;
425
426 hwif->tuneproc = &amd74xx_tune_drive;
427 hwif->speedproc = &amd_set_drive;
428
429 for (i = 0; i < 2; i++) {
430 hwif->drives[i].io_32bit = 1;
431 hwif->drives[i].unmask = 1;
432 hwif->drives[i].autotune = 1;
433 hwif->drives[i].dn = hwif->channel * 2 + i;
434 }
435
436 if (!hwif->dma_base)
437 return;
438
439 hwif->atapi_dma = 1;
440 hwif->ultra_mask = 0x7f;
441 hwif->mwdma_mask = 0x07;
442 hwif->swdma_mask = 0x07;
443
444 if (!hwif->udma_four)
445 hwif->udma_four = (amd_80w >> hwif->channel) & 1;
446 hwif->ide_dma_check = &amd74xx_ide_dma_check;
447 if (!noautodma)
448 hwif->autodma = 1;
449 hwif->drives[0].autodma = hwif->autodma;
450 hwif->drives[1].autodma = hwif->autodma;
451 }
452
453 #define DECLARE_AMD_DEV(name_str) \
454 { \
455 .name = name_str, \
456 .init_chipset = init_chipset_amd74xx, \
457 .init_hwif = init_hwif_amd74xx, \
458 .channels = 2, \
459 .autodma = AUTODMA, \
460 .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, \
461 .bootable = ON_BOARD, \
462 }
463
464 #define DECLARE_NV_DEV(name_str) \
465 { \
466 .name = name_str, \
467 .init_chipset = init_chipset_amd74xx, \
468 .init_hwif = init_hwif_amd74xx, \
469 .channels = 2, \
470 .autodma = AUTODMA, \
471 .enablebits = {{0x50,0x02,0x02}, {0x50,0x01,0x01}}, \
472 .bootable = ON_BOARD, \
473 }
474
475 static ide_pci_device_t amd74xx_chipsets[] __devinitdata = {
476 /* 0 */ DECLARE_AMD_DEV("AMD7401"),
477 /* 1 */ DECLARE_AMD_DEV("AMD7409"),
478 /* 2 */ DECLARE_AMD_DEV("AMD7411"),
479 /* 3 */ DECLARE_AMD_DEV("AMD7441"),
480 /* 4 */ DECLARE_AMD_DEV("AMD8111"),
481
482 /* 5 */ DECLARE_NV_DEV("NFORCE"),
483 /* 6 */ DECLARE_NV_DEV("NFORCE2"),
484 /* 7 */ DECLARE_NV_DEV("NFORCE2-U400R"),
485 /* 8 */ DECLARE_NV_DEV("NFORCE2-U400R-SATA"),
486 /* 9 */ DECLARE_NV_DEV("NFORCE3-150"),
487 /* 10 */ DECLARE_NV_DEV("NFORCE3-250"),
488 /* 11 */ DECLARE_NV_DEV("NFORCE3-250-SATA"),
489 /* 12 */ DECLARE_NV_DEV("NFORCE3-250-SATA2"),
490 /* 13 */ DECLARE_NV_DEV("NFORCE-CK804"),
491 /* 14 */ DECLARE_NV_DEV("NFORCE-MCP04"),
492 /* 15 */ DECLARE_NV_DEV("NFORCE-MCP51"),
493 /* 16 */ DECLARE_NV_DEV("NFORCE-MCP55"),
494 };
495
496 static int __devinit amd74xx_probe(struct pci_dev *dev, const struct pci_device_id *id)
497 {
498 amd_chipset = amd74xx_chipsets + id->driver_data;
499 amd_config = amd_ide_chips + id->driver_data;
500 if (dev->device != amd_config->id) {
501 printk(KERN_ERR "%s: assertion 0x%02x == 0x%02x failed !\n",
502 pci_name(dev), dev->device, amd_config->id);
503 return -ENODEV;
504 }
505 return ide_setup_pci_device(dev, amd_chipset);
506 }
507
508 static struct pci_device_id amd74xx_pci_tbl[] = {
509 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_COBRA_7401, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
510 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7409, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
511 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
512 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_OPUS_7441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
513 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
514 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
515 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6 },
516 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 7 },
517 #ifdef CONFIG_BLK_DEV_IDE_SATA
518 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 },
519 #endif
520 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 9 },
521 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 10 },
522 #ifdef CONFIG_BLK_DEV_IDE_SATA
523 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 11 },
524 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 12 },
525 #endif
526 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 13 },
527 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 14 },
528 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 15 },
529 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 16 },
530 { 0, },
531 };
532 MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl);
533
534 static struct pci_driver driver = {
535 .name = "AMD_IDE",
536 .id_table = amd74xx_pci_tbl,
537 .probe = amd74xx_probe,
538 };
539
540 static int amd74xx_ide_init(void)
541 {
542 return ide_pci_register_driver(&driver);
543 }
544
545 module_init(amd74xx_ide_init);
546
547 MODULE_AUTHOR("Vojtech Pavlik");
548 MODULE_DESCRIPTION("AMD PCI IDE driver");
549 MODULE_LICENSE("GPL");
Support for the Chinese Samsung S3C2440 based development boards