2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
32 extern int atom_debug
;
35 radeon_get_encoder_id(struct drm_device
*dev
, uint32_t supported_device
, uint8_t dac
)
37 struct radeon_device
*rdev
= dev
->dev_private
;
40 switch (supported_device
) {
41 case ATOM_DEVICE_CRT1_SUPPORT
:
42 case ATOM_DEVICE_TV1_SUPPORT
:
43 case ATOM_DEVICE_TV2_SUPPORT
:
44 case ATOM_DEVICE_CRT2_SUPPORT
:
45 case ATOM_DEVICE_CV_SUPPORT
:
48 if ((rdev
->family
== CHIP_RS300
) ||
49 (rdev
->family
== CHIP_RS400
) ||
50 (rdev
->family
== CHIP_RS480
))
51 ret
= ENCODER_OBJECT_ID_INTERNAL_DAC2
;
52 else if (ASIC_IS_AVIVO(rdev
))
53 ret
= ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
;
55 ret
= ENCODER_OBJECT_ID_INTERNAL_DAC1
;
58 if (ASIC_IS_AVIVO(rdev
))
59 ret
= ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
;
61 /*if (rdev->family == CHIP_R200)
62 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
64 ret
= ENCODER_OBJECT_ID_INTERNAL_DAC2
;
67 case 3: /* external dac */
68 if (ASIC_IS_AVIVO(rdev
))
69 ret
= ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
;
71 ret
= ENCODER_OBJECT_ID_INTERNAL_DVO1
;
75 case ATOM_DEVICE_LCD1_SUPPORT
:
76 if (ASIC_IS_AVIVO(rdev
))
77 ret
= ENCODER_OBJECT_ID_INTERNAL_LVTM1
;
79 ret
= ENCODER_OBJECT_ID_INTERNAL_LVDS
;
81 case ATOM_DEVICE_DFP1_SUPPORT
:
82 if ((rdev
->family
== CHIP_RS300
) ||
83 (rdev
->family
== CHIP_RS400
) ||
84 (rdev
->family
== CHIP_RS480
))
85 ret
= ENCODER_OBJECT_ID_INTERNAL_DVO1
;
86 else if (ASIC_IS_AVIVO(rdev
))
87 ret
= ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
;
89 ret
= ENCODER_OBJECT_ID_INTERNAL_TMDS1
;
91 case ATOM_DEVICE_LCD2_SUPPORT
:
92 case ATOM_DEVICE_DFP2_SUPPORT
:
93 if ((rdev
->family
== CHIP_RS600
) ||
94 (rdev
->family
== CHIP_RS690
) ||
95 (rdev
->family
== CHIP_RS740
))
96 ret
= ENCODER_OBJECT_ID_INTERNAL_DDI
;
97 else if (ASIC_IS_AVIVO(rdev
))
98 ret
= ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
;
100 ret
= ENCODER_OBJECT_ID_INTERNAL_DVO1
;
102 case ATOM_DEVICE_DFP3_SUPPORT
:
103 ret
= ENCODER_OBJECT_ID_INTERNAL_LVTM1
;
111 radeon_link_encoder_connector(struct drm_device
*dev
)
113 struct drm_connector
*connector
;
114 struct radeon_connector
*radeon_connector
;
115 struct drm_encoder
*encoder
;
116 struct radeon_encoder
*radeon_encoder
;
118 /* walk the list and link encoders to connectors */
119 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
120 radeon_connector
= to_radeon_connector(connector
);
121 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
122 radeon_encoder
= to_radeon_encoder(encoder
);
123 if (radeon_encoder
->devices
& radeon_connector
->devices
)
124 drm_mode_connector_attach_encoder(connector
, encoder
);
129 void radeon_encoder_set_active_device(struct drm_encoder
*encoder
)
131 struct drm_device
*dev
= encoder
->dev
;
132 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
133 struct drm_connector
*connector
;
135 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
136 if (connector
->encoder
== encoder
) {
137 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
138 radeon_encoder
->active_device
= radeon_encoder
->devices
& radeon_connector
->devices
;
139 DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
140 radeon_encoder
->active_device
, radeon_encoder
->devices
,
141 radeon_connector
->devices
, encoder
->encoder_type
);
146 static struct drm_connector
*
147 radeon_get_connector_for_encoder(struct drm_encoder
*encoder
)
149 struct drm_device
*dev
= encoder
->dev
;
150 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
151 struct drm_connector
*connector
;
152 struct radeon_connector
*radeon_connector
;
154 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
155 radeon_connector
= to_radeon_connector(connector
);
156 if (radeon_encoder
->devices
& radeon_connector
->devices
)
162 /* used for both atom and legacy */
163 void radeon_rmx_mode_fixup(struct drm_encoder
*encoder
,
164 struct drm_display_mode
*mode
,
165 struct drm_display_mode
*adjusted_mode
)
167 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
168 struct drm_device
*dev
= encoder
->dev
;
169 struct radeon_device
*rdev
= dev
->dev_private
;
170 struct radeon_native_mode
*native_mode
= &radeon_encoder
->native_mode
;
172 if (mode
->hdisplay
< native_mode
->panel_xres
||
173 mode
->vdisplay
< native_mode
->panel_yres
) {
174 if (ASIC_IS_AVIVO(rdev
)) {
175 adjusted_mode
->hdisplay
= native_mode
->panel_xres
;
176 adjusted_mode
->vdisplay
= native_mode
->panel_yres
;
177 adjusted_mode
->htotal
= native_mode
->panel_xres
+ native_mode
->hblank
;
178 adjusted_mode
->hsync_start
= native_mode
->panel_xres
+ native_mode
->hoverplus
;
179 adjusted_mode
->hsync_end
= adjusted_mode
->hsync_start
+ native_mode
->hsync_width
;
180 adjusted_mode
->vtotal
= native_mode
->panel_yres
+ native_mode
->vblank
;
181 adjusted_mode
->vsync_start
= native_mode
->panel_yres
+ native_mode
->voverplus
;
182 adjusted_mode
->vsync_end
= adjusted_mode
->vsync_start
+ native_mode
->vsync_width
;
183 /* update crtc values */
184 drm_mode_set_crtcinfo(adjusted_mode
, CRTC_INTERLACE_HALVE_V
);
185 /* adjust crtc values */
186 adjusted_mode
->crtc_hdisplay
= native_mode
->panel_xres
;
187 adjusted_mode
->crtc_vdisplay
= native_mode
->panel_yres
;
188 adjusted_mode
->crtc_htotal
= adjusted_mode
->crtc_hdisplay
+ native_mode
->hblank
;
189 adjusted_mode
->crtc_hsync_start
= adjusted_mode
->crtc_hdisplay
+ native_mode
->hoverplus
;
190 adjusted_mode
->crtc_hsync_end
= adjusted_mode
->crtc_hsync_start
+ native_mode
->hsync_width
;
191 adjusted_mode
->crtc_vtotal
= adjusted_mode
->crtc_vdisplay
+ native_mode
->vblank
;
192 adjusted_mode
->crtc_vsync_start
= adjusted_mode
->crtc_vdisplay
+ native_mode
->voverplus
;
193 adjusted_mode
->crtc_vsync_end
= adjusted_mode
->crtc_vsync_start
+ native_mode
->vsync_width
;
195 adjusted_mode
->htotal
= native_mode
->panel_xres
+ native_mode
->hblank
;
196 adjusted_mode
->hsync_start
= native_mode
->panel_xres
+ native_mode
->hoverplus
;
197 adjusted_mode
->hsync_end
= adjusted_mode
->hsync_start
+ native_mode
->hsync_width
;
198 adjusted_mode
->vtotal
= native_mode
->panel_yres
+ native_mode
->vblank
;
199 adjusted_mode
->vsync_start
= native_mode
->panel_yres
+ native_mode
->voverplus
;
200 adjusted_mode
->vsync_end
= adjusted_mode
->vsync_start
+ native_mode
->vsync_width
;
201 /* update crtc values */
202 drm_mode_set_crtcinfo(adjusted_mode
, CRTC_INTERLACE_HALVE_V
);
203 /* adjust crtc values */
204 adjusted_mode
->crtc_htotal
= adjusted_mode
->crtc_hdisplay
+ native_mode
->hblank
;
205 adjusted_mode
->crtc_hsync_start
= adjusted_mode
->crtc_hdisplay
+ native_mode
->hoverplus
;
206 adjusted_mode
->crtc_hsync_end
= adjusted_mode
->crtc_hsync_start
+ native_mode
->hsync_width
;
207 adjusted_mode
->crtc_vtotal
= adjusted_mode
->crtc_vdisplay
+ native_mode
->vblank
;
208 adjusted_mode
->crtc_vsync_start
= adjusted_mode
->crtc_vdisplay
+ native_mode
->voverplus
;
209 adjusted_mode
->crtc_vsync_end
= adjusted_mode
->crtc_vsync_start
+ native_mode
->vsync_width
;
211 adjusted_mode
->flags
= native_mode
->flags
;
212 adjusted_mode
->clock
= native_mode
->dotclock
;
217 static bool radeon_atom_mode_fixup(struct drm_encoder
*encoder
,
218 struct drm_display_mode
*mode
,
219 struct drm_display_mode
*adjusted_mode
)
221 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
223 drm_mode_set_crtcinfo(adjusted_mode
, 0);
225 if (radeon_encoder
->rmx_type
!= RMX_OFF
)
226 radeon_rmx_mode_fixup(encoder
, mode
, adjusted_mode
);
229 if ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
230 && (mode
->crtc_vsync_start
< (mode
->crtc_vdisplay
+ 2)))
231 adjusted_mode
->crtc_vsync_start
= adjusted_mode
->crtc_vdisplay
+ 2;
237 atombios_dac_setup(struct drm_encoder
*encoder
, int action
)
239 struct drm_device
*dev
= encoder
->dev
;
240 struct radeon_device
*rdev
= dev
->dev_private
;
241 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
242 DAC_ENCODER_CONTROL_PS_ALLOCATION args
;
243 int index
= 0, num
= 0;
244 /* fixme - fill in enc_priv for atom dac */
245 enum radeon_tv_std tv_std
= TV_STD_NTSC
;
247 memset(&args
, 0, sizeof(args
));
249 switch (radeon_encoder
->encoder_id
) {
250 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
251 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
252 index
= GetIndexIntoMasterTable(COMMAND
, DAC1EncoderControl
);
255 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
256 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
257 index
= GetIndexIntoMasterTable(COMMAND
, DAC2EncoderControl
);
262 args
.ucAction
= action
;
264 if (radeon_encoder
->active_device
& (ATOM_DEVICE_CRT_SUPPORT
))
265 args
.ucDacStandard
= ATOM_DAC1_PS2
;
266 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
267 args
.ucDacStandard
= ATOM_DAC1_CV
;
272 case TV_STD_SCART_PAL
:
275 args
.ucDacStandard
= ATOM_DAC1_PAL
;
281 args
.ucDacStandard
= ATOM_DAC1_NTSC
;
285 args
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
287 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
292 atombios_tv_setup(struct drm_encoder
*encoder
, int action
)
294 struct drm_device
*dev
= encoder
->dev
;
295 struct radeon_device
*rdev
= dev
->dev_private
;
296 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
297 TV_ENCODER_CONTROL_PS_ALLOCATION args
;
299 /* fixme - fill in enc_priv for atom dac */
300 enum radeon_tv_std tv_std
= TV_STD_NTSC
;
302 memset(&args
, 0, sizeof(args
));
304 index
= GetIndexIntoMasterTable(COMMAND
, TVEncoderControl
);
306 args
.sTVEncoder
.ucAction
= action
;
308 if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
309 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_CV
;
313 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_NTSC
;
316 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PAL
;
319 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PALM
;
322 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PAL60
;
325 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_NTSCJ
;
327 case TV_STD_SCART_PAL
:
328 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PAL
; /* ??? */
331 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_SECAM
;
334 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_PALCN
;
337 args
.sTVEncoder
.ucTvStandard
= ATOM_TV_NTSC
;
342 args
.sTVEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
344 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
349 atombios_external_tmds_setup(struct drm_encoder
*encoder
, int action
)
351 struct drm_device
*dev
= encoder
->dev
;
352 struct radeon_device
*rdev
= dev
->dev_private
;
353 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
354 ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args
;
357 memset(&args
, 0, sizeof(args
));
359 index
= GetIndexIntoMasterTable(COMMAND
, DVOEncoderControl
);
361 args
.sXTmdsEncoder
.ucEnable
= action
;
363 if (radeon_encoder
->pixel_clock
> 165000)
364 args
.sXTmdsEncoder
.ucMisc
= PANEL_ENCODER_MISC_DUAL
;
366 /*if (pScrn->rgbBits == 8)*/
367 args
.sXTmdsEncoder
.ucMisc
|= (1 << 1);
369 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
374 atombios_ddia_setup(struct drm_encoder
*encoder
, int action
)
376 struct drm_device
*dev
= encoder
->dev
;
377 struct radeon_device
*rdev
= dev
->dev_private
;
378 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
379 DVO_ENCODER_CONTROL_PS_ALLOCATION args
;
382 memset(&args
, 0, sizeof(args
));
384 index
= GetIndexIntoMasterTable(COMMAND
, DVOEncoderControl
);
386 args
.sDVOEncoder
.ucAction
= action
;
387 args
.sDVOEncoder
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
389 if (radeon_encoder
->pixel_clock
> 165000)
390 args
.sDVOEncoder
.usDevAttr
.sDigAttrib
.ucAttribute
= PANEL_ENCODER_MISC_DUAL
;
392 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
396 union lvds_encoder_control
{
397 LVDS_ENCODER_CONTROL_PS_ALLOCATION v1
;
398 LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2
;
402 atombios_digital_setup(struct drm_encoder
*encoder
, int action
)
404 struct drm_device
*dev
= encoder
->dev
;
405 struct radeon_device
*rdev
= dev
->dev_private
;
406 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
407 union lvds_encoder_control args
;
410 struct radeon_encoder_atom_dig
*dig
;
411 struct drm_connector
*connector
;
412 struct radeon_connector
*radeon_connector
;
413 struct radeon_connector_atom_dig
*dig_connector
;
415 connector
= radeon_get_connector_for_encoder(encoder
);
419 radeon_connector
= to_radeon_connector(connector
);
421 if (!radeon_encoder
->enc_priv
)
424 dig
= radeon_encoder
->enc_priv
;
426 if (!radeon_connector
->con_priv
)
429 dig_connector
= radeon_connector
->con_priv
;
431 memset(&args
, 0, sizeof(args
));
433 switch (radeon_encoder
->encoder_id
) {
434 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
435 index
= GetIndexIntoMasterTable(COMMAND
, LVDSEncoderControl
);
437 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
438 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
439 index
= GetIndexIntoMasterTable(COMMAND
, TMDS1EncoderControl
);
441 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
442 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
443 index
= GetIndexIntoMasterTable(COMMAND
, LVDSEncoderControl
);
445 index
= GetIndexIntoMasterTable(COMMAND
, TMDS2EncoderControl
);
449 atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
);
457 args
.v1
.ucAction
= action
;
458 if (drm_detect_hdmi_monitor((struct edid
*)connector
->edid_blob_ptr
))
459 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_HDMI_TYPE
;
460 args
.v1
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
461 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
462 if (dig
->lvds_misc
& (1 << 0))
463 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
464 if (dig
->lvds_misc
& (1 << 1))
465 args
.v1
.ucMisc
|= (1 << 1);
467 if (dig_connector
->linkb
)
468 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_TMDS_LINKB
;
469 if (radeon_encoder
->pixel_clock
> 165000)
470 args
.v1
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
471 /*if (pScrn->rgbBits == 8) */
472 args
.v1
.ucMisc
|= (1 << 1);
478 args
.v2
.ucAction
= action
;
480 if (dig
->coherent_mode
)
481 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_COHERENT
;
483 if (drm_detect_hdmi_monitor((struct edid
*)connector
->edid_blob_ptr
))
484 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_HDMI_TYPE
;
485 args
.v2
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
486 args
.v2
.ucTruncate
= 0;
487 args
.v2
.ucSpatial
= 0;
488 args
.v2
.ucTemporal
= 0;
490 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
491 if (dig
->lvds_misc
& (1 << 0))
492 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
493 if (dig
->lvds_misc
& (1 << 5)) {
494 args
.v2
.ucSpatial
= PANEL_ENCODER_SPATIAL_DITHER_EN
;
495 if (dig
->lvds_misc
& (1 << 1))
496 args
.v2
.ucSpatial
|= PANEL_ENCODER_SPATIAL_DITHER_DEPTH
;
498 if (dig
->lvds_misc
& (1 << 6)) {
499 args
.v2
.ucTemporal
= PANEL_ENCODER_TEMPORAL_DITHER_EN
;
500 if (dig
->lvds_misc
& (1 << 1))
501 args
.v2
.ucTemporal
|= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH
;
502 if (((dig
->lvds_misc
>> 2) & 0x3) == 2)
503 args
.v2
.ucTemporal
|= PANEL_ENCODER_TEMPORAL_LEVEL_4
;
506 if (dig_connector
->linkb
)
507 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_TMDS_LINKB
;
508 if (radeon_encoder
->pixel_clock
> 165000)
509 args
.v2
.ucMisc
|= PANEL_ENCODER_MISC_DUAL
;
513 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
518 DRM_ERROR("Unknown table version %d, %d\n", frev
, crev
);
522 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
527 atombios_get_encoder_mode(struct drm_encoder
*encoder
)
529 struct drm_connector
*connector
;
530 struct radeon_connector
*radeon_connector
;
532 connector
= radeon_get_connector_for_encoder(encoder
);
536 radeon_connector
= to_radeon_connector(connector
);
538 switch (connector
->connector_type
) {
539 case DRM_MODE_CONNECTOR_DVII
:
540 if (drm_detect_hdmi_monitor((struct edid
*)connector
->edid_blob_ptr
))
541 return ATOM_ENCODER_MODE_HDMI
;
542 else if (radeon_connector
->use_digital
)
543 return ATOM_ENCODER_MODE_DVI
;
545 return ATOM_ENCODER_MODE_CRT
;
547 case DRM_MODE_CONNECTOR_DVID
:
548 case DRM_MODE_CONNECTOR_HDMIA
:
549 case DRM_MODE_CONNECTOR_HDMIB
:
551 if (drm_detect_hdmi_monitor((struct edid
*)connector
->edid_blob_ptr
))
552 return ATOM_ENCODER_MODE_HDMI
;
554 return ATOM_ENCODER_MODE_DVI
;
556 case DRM_MODE_CONNECTOR_LVDS
:
557 return ATOM_ENCODER_MODE_LVDS
;
559 case DRM_MODE_CONNECTOR_DisplayPort
:
560 /*if (radeon_output->MonType == MT_DP)
561 return ATOM_ENCODER_MODE_DP;
563 if (drm_detect_hdmi_monitor((struct edid
*)connector
->edid_blob_ptr
))
564 return ATOM_ENCODER_MODE_HDMI
;
566 return ATOM_ENCODER_MODE_DVI
;
568 case CONNECTOR_DVI_A
:
570 return ATOM_ENCODER_MODE_CRT
;
576 return ATOM_ENCODER_MODE_TV
;
577 /*return ATOM_ENCODER_MODE_CV;*/
583 atombios_dig_encoder_setup(struct drm_encoder
*encoder
, int action
)
585 struct drm_device
*dev
= encoder
->dev
;
586 struct radeon_device
*rdev
= dev
->dev_private
;
587 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
588 DIG_ENCODER_CONTROL_PS_ALLOCATION args
;
589 int index
= 0, num
= 0;
591 struct radeon_encoder_atom_dig
*dig
;
592 struct drm_connector
*connector
;
593 struct radeon_connector
*radeon_connector
;
594 struct radeon_connector_atom_dig
*dig_connector
;
596 connector
= radeon_get_connector_for_encoder(encoder
);
600 radeon_connector
= to_radeon_connector(connector
);
602 if (!radeon_connector
->con_priv
)
605 dig_connector
= radeon_connector
->con_priv
;
607 if (!radeon_encoder
->enc_priv
)
610 dig
= radeon_encoder
->enc_priv
;
612 memset(&args
, 0, sizeof(args
));
614 if (ASIC_IS_DCE32(rdev
)) {
616 index
= GetIndexIntoMasterTable(COMMAND
, DIG2EncoderControl
);
618 index
= GetIndexIntoMasterTable(COMMAND
, DIG1EncoderControl
);
619 num
= dig
->dig_block
+ 1;
621 switch (radeon_encoder
->encoder_id
) {
622 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
623 index
= GetIndexIntoMasterTable(COMMAND
, DIG1EncoderControl
);
626 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
627 index
= GetIndexIntoMasterTable(COMMAND
, DIG2EncoderControl
);
633 atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
);
635 args
.ucAction
= action
;
636 args
.usPixelClock
= cpu_to_le16(radeon_encoder
->pixel_clock
/ 10);
638 if (ASIC_IS_DCE32(rdev
)) {
639 switch (radeon_encoder
->encoder_id
) {
640 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
641 args
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER1
;
643 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
644 args
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER2
;
646 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
647 args
.ucConfig
= ATOM_ENCODER_CONFIG_V2_TRANSMITTER3
;
651 switch (radeon_encoder
->encoder_id
) {
652 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
653 args
.ucConfig
= ATOM_ENCODER_CONFIG_TRANSMITTER1
;
655 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
656 args
.ucConfig
= ATOM_ENCODER_CONFIG_TRANSMITTER2
;
661 if (radeon_encoder
->pixel_clock
> 165000) {
662 args
.ucConfig
|= ATOM_ENCODER_CONFIG_LINKA_B
;
665 if (dig_connector
->linkb
)
666 args
.ucConfig
|= ATOM_ENCODER_CONFIG_LINKB
;
668 args
.ucConfig
|= ATOM_ENCODER_CONFIG_LINKA
;
672 args
.ucEncoderMode
= atombios_get_encoder_mode(encoder
);
674 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
678 union dig_transmitter_control
{
679 DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1
;
680 DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2
;
684 atombios_dig_transmitter_setup(struct drm_encoder
*encoder
, int action
)
686 struct drm_device
*dev
= encoder
->dev
;
687 struct radeon_device
*rdev
= dev
->dev_private
;
688 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
689 union dig_transmitter_control args
;
690 int index
= 0, num
= 0;
692 struct radeon_encoder_atom_dig
*dig
;
693 struct drm_connector
*connector
;
694 struct radeon_connector
*radeon_connector
;
695 struct radeon_connector_atom_dig
*dig_connector
;
697 connector
= radeon_get_connector_for_encoder(encoder
);
701 radeon_connector
= to_radeon_connector(connector
);
703 if (!radeon_encoder
->enc_priv
)
706 dig
= radeon_encoder
->enc_priv
;
708 if (!radeon_connector
->con_priv
)
711 dig_connector
= radeon_connector
->con_priv
;
713 memset(&args
, 0, sizeof(args
));
715 if (ASIC_IS_DCE32(rdev
))
716 index
= GetIndexIntoMasterTable(COMMAND
, UNIPHYTransmitterControl
);
718 switch (radeon_encoder
->encoder_id
) {
719 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
720 index
= GetIndexIntoMasterTable(COMMAND
, DIG1TransmitterControl
);
722 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
723 index
= GetIndexIntoMasterTable(COMMAND
, DIG2TransmitterControl
);
728 atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
);
730 args
.v1
.ucAction
= action
;
732 if (ASIC_IS_DCE32(rdev
)) {
733 if (radeon_encoder
->pixel_clock
> 165000) {
734 args
.v2
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
* 10 * 2) / 100);
735 args
.v2
.acConfig
.fDualLinkConnector
= 1;
737 args
.v2
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
* 10 * 4) / 100);
740 args
.v2
.acConfig
.ucEncoderSel
= 1;
742 switch (radeon_encoder
->encoder_id
) {
743 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
744 args
.v2
.acConfig
.ucTransmitterSel
= 0;
747 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
748 args
.v2
.acConfig
.ucTransmitterSel
= 1;
751 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
752 args
.v2
.acConfig
.ucTransmitterSel
= 2;
757 if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
758 if (dig
->coherent_mode
)
759 args
.v2
.acConfig
.fCoherentMode
= 1;
762 args
.v1
.ucConfig
= ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL
;
763 args
.v1
.usPixelClock
= cpu_to_le16((radeon_encoder
->pixel_clock
) / 10);
765 switch (radeon_encoder
->encoder_id
) {
766 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
767 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER
;
768 if (rdev
->flags
& RADEON_IS_IGP
) {
769 if (radeon_encoder
->pixel_clock
> 165000) {
770 args
.v1
.ucConfig
|= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK
|
771 ATOM_TRANSMITTER_CONFIG_LINKA_B
);
772 if (dig_connector
->igp_lane_info
& 0x3)
773 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_0_7
;
774 else if (dig_connector
->igp_lane_info
& 0xc)
775 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_8_15
;
777 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKA
;
778 if (dig_connector
->igp_lane_info
& 0x1)
779 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_0_3
;
780 else if (dig_connector
->igp_lane_info
& 0x2)
781 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_4_7
;
782 else if (dig_connector
->igp_lane_info
& 0x4)
783 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_8_11
;
784 else if (dig_connector
->igp_lane_info
& 0x8)
785 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LANE_12_15
;
788 if (radeon_encoder
->pixel_clock
> 165000)
789 args
.v1
.ucConfig
|= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK
|
790 ATOM_TRANSMITTER_CONFIG_LINKA_B
|
791 ATOM_TRANSMITTER_CONFIG_LANE_0_7
);
793 if (dig_connector
->linkb
)
794 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKB
| ATOM_TRANSMITTER_CONFIG_LANE_0_3
;
796 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKA
| ATOM_TRANSMITTER_CONFIG_LANE_0_3
;
800 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
801 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER
;
802 if (radeon_encoder
->pixel_clock
> 165000)
803 args
.v1
.ucConfig
|= (ATOM_TRANSMITTER_CONFIG_8LANE_LINK
|
804 ATOM_TRANSMITTER_CONFIG_LINKA_B
|
805 ATOM_TRANSMITTER_CONFIG_LANE_0_7
);
807 if (dig_connector
->linkb
)
808 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKB
| ATOM_TRANSMITTER_CONFIG_LANE_0_3
;
810 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_LINKA
| ATOM_TRANSMITTER_CONFIG_LANE_0_3
;
815 if (radeon_encoder
->devices
& (ATOM_DEVICE_DFP_SUPPORT
)) {
816 if (dig
->coherent_mode
)
817 args
.v1
.ucConfig
|= ATOM_TRANSMITTER_CONFIG_COHERENT
;
821 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
826 atombios_yuv_setup(struct drm_encoder
*encoder
, bool enable
)
828 struct drm_device
*dev
= encoder
->dev
;
829 struct radeon_device
*rdev
= dev
->dev_private
;
830 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
831 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
832 ENABLE_YUV_PS_ALLOCATION args
;
833 int index
= GetIndexIntoMasterTable(COMMAND
, EnableYUV
);
836 memset(&args
, 0, sizeof(args
));
838 if (rdev
->family
>= CHIP_R600
)
839 reg
= R600_BIOS_3_SCRATCH
;
841 reg
= RADEON_BIOS_3_SCRATCH
;
843 /* XXX: fix up scratch reg handling */
845 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
846 WREG32(reg
, (ATOM_S3_TV1_ACTIVE
|
847 (radeon_crtc
->crtc_id
<< 18)));
848 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
849 WREG32(reg
, (ATOM_S3_CV_ACTIVE
| (radeon_crtc
->crtc_id
<< 24)));
854 args
.ucEnable
= ATOM_ENABLE
;
855 args
.ucCRTC
= radeon_crtc
->crtc_id
;
857 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
863 radeon_atom_encoder_dpms(struct drm_encoder
*encoder
, int mode
)
865 struct drm_device
*dev
= encoder
->dev
;
866 struct radeon_device
*rdev
= dev
->dev_private
;
867 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
868 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args
;
873 memset(&args
, 0, sizeof(args
));
875 /* on DPMS off we have no idea if active device is meaningful */
876 if (mode
!= DRM_MODE_DPMS_ON
&& !radeon_encoder
->active_device
)
877 devices
= radeon_encoder
->devices
;
879 devices
= radeon_encoder
->active_device
;
881 DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
882 radeon_encoder
->encoder_id
, mode
, radeon_encoder
->devices
,
883 radeon_encoder
->active_device
);
884 switch (radeon_encoder
->encoder_id
) {
885 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
886 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
887 index
= GetIndexIntoMasterTable(COMMAND
, TMDSAOutputControl
);
889 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
890 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
891 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
892 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
895 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
896 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
897 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
898 index
= GetIndexIntoMasterTable(COMMAND
, DVOOutputControl
);
900 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
901 index
= GetIndexIntoMasterTable(COMMAND
, LCD1OutputControl
);
903 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
904 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
))
905 index
= GetIndexIntoMasterTable(COMMAND
, LCD1OutputControl
);
907 index
= GetIndexIntoMasterTable(COMMAND
, LVTMAOutputControl
);
909 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
910 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
911 if (devices
& (ATOM_DEVICE_TV_SUPPORT
))
912 index
= GetIndexIntoMasterTable(COMMAND
, TV1OutputControl
);
913 else if (devices
& (ATOM_DEVICE_CV_SUPPORT
))
914 index
= GetIndexIntoMasterTable(COMMAND
, CV1OutputControl
);
916 index
= GetIndexIntoMasterTable(COMMAND
, DAC1OutputControl
);
918 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
919 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
920 if (devices
& (ATOM_DEVICE_TV_SUPPORT
))
921 index
= GetIndexIntoMasterTable(COMMAND
, TV1OutputControl
);
922 else if (devices
& (ATOM_DEVICE_CV_SUPPORT
))
923 index
= GetIndexIntoMasterTable(COMMAND
, CV1OutputControl
);
925 index
= GetIndexIntoMasterTable(COMMAND
, DAC2OutputControl
);
931 case DRM_MODE_DPMS_ON
:
932 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_ENABLE
);
934 case DRM_MODE_DPMS_STANDBY
:
935 case DRM_MODE_DPMS_SUSPEND
:
936 case DRM_MODE_DPMS_OFF
:
937 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_DISABLE
);
942 case DRM_MODE_DPMS_ON
:
943 args
.ucAction
= ATOM_ENABLE
;
945 case DRM_MODE_DPMS_STANDBY
:
946 case DRM_MODE_DPMS_SUSPEND
:
947 case DRM_MODE_DPMS_OFF
:
948 args
.ucAction
= ATOM_DISABLE
;
951 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
953 radeon_atombios_encoder_dpms_scratch_regs(encoder
, (mode
== DRM_MODE_DPMS_ON
) ? true : false);
956 union crtc_sourc_param
{
957 SELECT_CRTC_SOURCE_PS_ALLOCATION v1
;
958 SELECT_CRTC_SOURCE_PARAMETERS_V2 v2
;
962 atombios_set_encoder_crtc_source(struct drm_encoder
*encoder
)
964 struct drm_device
*dev
= encoder
->dev
;
965 struct radeon_device
*rdev
= dev
->dev_private
;
966 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
967 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
968 union crtc_sourc_param args
;
969 int index
= GetIndexIntoMasterTable(COMMAND
, SelectCRTC_Source
);
972 memset(&args
, 0, sizeof(args
));
974 atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
);
981 if (ASIC_IS_AVIVO(rdev
))
982 args
.v1
.ucCRTC
= radeon_crtc
->crtc_id
;
984 if (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DAC1
) {
985 args
.v1
.ucCRTC
= radeon_crtc
->crtc_id
;
987 args
.v1
.ucCRTC
= radeon_crtc
->crtc_id
<< 2;
990 switch (radeon_encoder
->encoder_id
) {
991 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
992 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
993 args
.v1
.ucDevice
= ATOM_DEVICE_DFP1_INDEX
;
995 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
996 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
997 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
)
998 args
.v1
.ucDevice
= ATOM_DEVICE_LCD1_INDEX
;
1000 args
.v1
.ucDevice
= ATOM_DEVICE_DFP3_INDEX
;
1002 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1003 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1004 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1005 args
.v1
.ucDevice
= ATOM_DEVICE_DFP2_INDEX
;
1007 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1008 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1009 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1010 args
.v1
.ucDevice
= ATOM_DEVICE_TV1_INDEX
;
1011 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1012 args
.v1
.ucDevice
= ATOM_DEVICE_CV_INDEX
;
1014 args
.v1
.ucDevice
= ATOM_DEVICE_CRT1_INDEX
;
1016 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1017 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1018 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1019 args
.v1
.ucDevice
= ATOM_DEVICE_TV1_INDEX
;
1020 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1021 args
.v1
.ucDevice
= ATOM_DEVICE_CV_INDEX
;
1023 args
.v1
.ucDevice
= ATOM_DEVICE_CRT2_INDEX
;
1028 args
.v2
.ucCRTC
= radeon_crtc
->crtc_id
;
1029 args
.v2
.ucEncodeMode
= atombios_get_encoder_mode(encoder
);
1030 switch (radeon_encoder
->encoder_id
) {
1031 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1032 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1033 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1034 if (ASIC_IS_DCE32(rdev
)) {
1035 if (radeon_crtc
->crtc_id
)
1036 args
.v2
.ucEncoderID
= ASIC_INT_DIG2_ENCODER_ID
;
1038 args
.v2
.ucEncoderID
= ASIC_INT_DIG1_ENCODER_ID
;
1040 args
.v2
.ucEncoderID
= ASIC_INT_DIG1_ENCODER_ID
;
1042 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1043 args
.v2
.ucEncoderID
= ASIC_INT_DVO_ENCODER_ID
;
1045 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1046 args
.v2
.ucEncoderID
= ASIC_INT_DIG2_ENCODER_ID
;
1048 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1049 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1050 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1051 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1052 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1054 args
.v2
.ucEncoderID
= ASIC_INT_DAC1_ENCODER_ID
;
1056 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1057 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
))
1058 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1059 else if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
))
1060 args
.v2
.ucEncoderID
= ASIC_INT_TV_ENCODER_ID
;
1062 args
.v2
.ucEncoderID
= ASIC_INT_DAC2_ENCODER_ID
;
1069 DRM_ERROR("Unknown table version: %d, %d\n", frev
, crev
);
1073 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1078 atombios_apply_encoder_quirks(struct drm_encoder
*encoder
,
1079 struct drm_display_mode
*mode
)
1081 struct drm_device
*dev
= encoder
->dev
;
1082 struct radeon_device
*rdev
= dev
->dev_private
;
1083 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1084 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1086 /* Funky macbooks */
1087 if ((dev
->pdev
->device
== 0x71C5) &&
1088 (dev
->pdev
->subsystem_vendor
== 0x106b) &&
1089 (dev
->pdev
->subsystem_device
== 0x0080)) {
1090 if (radeon_encoder
->devices
& ATOM_DEVICE_LCD1_SUPPORT
) {
1091 uint32_t lvtma_bit_depth_control
= RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL
);
1093 lvtma_bit_depth_control
&= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN
;
1094 lvtma_bit_depth_control
&= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN
;
1096 WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL
, lvtma_bit_depth_control
);
1100 /* set scaler clears this on some chips */
1101 if (ASIC_IS_AVIVO(rdev
) && (mode
->flags
& DRM_MODE_FLAG_INTERLACE
))
1102 WREG32(AVIVO_D1MODE_DATA_FORMAT
+ radeon_crtc
->crtc_offset
, AVIVO_D1MODE_INTERLEAVE_EN
);
1106 radeon_atom_encoder_mode_set(struct drm_encoder
*encoder
,
1107 struct drm_display_mode
*mode
,
1108 struct drm_display_mode
*adjusted_mode
)
1110 struct drm_device
*dev
= encoder
->dev
;
1111 struct radeon_device
*rdev
= dev
->dev_private
;
1112 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1113 struct radeon_crtc
*radeon_crtc
= to_radeon_crtc(encoder
->crtc
);
1115 if (radeon_encoder
->enc_priv
) {
1116 struct radeon_encoder_atom_dig
*dig
;
1118 dig
= radeon_encoder
->enc_priv
;
1119 dig
->dig_block
= radeon_crtc
->crtc_id
;
1121 radeon_encoder
->pixel_clock
= adjusted_mode
->clock
;
1123 radeon_atombios_encoder_crtc_scratch_regs(encoder
, radeon_crtc
->crtc_id
);
1124 atombios_set_encoder_crtc_source(encoder
);
1126 if (ASIC_IS_AVIVO(rdev
)) {
1127 if (radeon_encoder
->active_device
& (ATOM_DEVICE_CV_SUPPORT
| ATOM_DEVICE_TV_SUPPORT
))
1128 atombios_yuv_setup(encoder
, true);
1130 atombios_yuv_setup(encoder
, false);
1133 switch (radeon_encoder
->encoder_id
) {
1134 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1135 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1136 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1137 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1138 atombios_digital_setup(encoder
, PANEL_ENCODER_ACTION_ENABLE
);
1140 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1141 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1142 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1143 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1144 /* disable the encoder and transmitter */
1145 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_DISABLE
);
1146 atombios_dig_encoder_setup(encoder
, ATOM_DISABLE
);
1148 /* setup and enable the encoder and transmitter */
1149 atombios_dig_encoder_setup(encoder
, ATOM_ENABLE
);
1150 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_SETUP
);
1151 atombios_dig_transmitter_setup(encoder
, ATOM_TRANSMITTER_ACTION_ENABLE
);
1153 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1154 atombios_ddia_setup(encoder
, ATOM_ENABLE
);
1156 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1157 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1158 atombios_external_tmds_setup(encoder
, ATOM_ENABLE
);
1160 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1161 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1162 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1163 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1164 atombios_dac_setup(encoder
, ATOM_ENABLE
);
1165 if (radeon_encoder
->active_device
& (ATOM_DEVICE_TV_SUPPORT
| ATOM_DEVICE_CV_SUPPORT
))
1166 atombios_tv_setup(encoder
, ATOM_ENABLE
);
1169 atombios_apply_encoder_quirks(encoder
, adjusted_mode
);
1173 atombios_dac_load_detect(struct drm_encoder
*encoder
, struct drm_connector
*connector
)
1175 struct drm_device
*dev
= encoder
->dev
;
1176 struct radeon_device
*rdev
= dev
->dev_private
;
1177 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1178 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1180 if (radeon_encoder
->devices
& (ATOM_DEVICE_TV_SUPPORT
|
1181 ATOM_DEVICE_CV_SUPPORT
|
1182 ATOM_DEVICE_CRT_SUPPORT
)) {
1183 DAC_LOAD_DETECTION_PS_ALLOCATION args
;
1184 int index
= GetIndexIntoMasterTable(COMMAND
, DAC_LoadDetection
);
1187 memset(&args
, 0, sizeof(args
));
1189 atom_parse_cmd_header(rdev
->mode_info
.atom_context
, index
, &frev
, &crev
);
1191 args
.sDacload
.ucMisc
= 0;
1193 if ((radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_DAC1
) ||
1194 (radeon_encoder
->encoder_id
== ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
))
1195 args
.sDacload
.ucDacType
= ATOM_DAC_A
;
1197 args
.sDacload
.ucDacType
= ATOM_DAC_B
;
1199 if (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
)
1200 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT
);
1201 else if (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
)
1202 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT
);
1203 else if (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
1204 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_CV_SUPPORT
);
1206 args
.sDacload
.ucMisc
= DAC_LOAD_MISC_YPrPb
;
1207 } else if (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
1208 args
.sDacload
.usDeviceID
= cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT
);
1210 args
.sDacload
.ucMisc
= DAC_LOAD_MISC_YPrPb
;
1213 atom_execute_table(rdev
->mode_info
.atom_context
, index
, (uint32_t *)&args
);
1220 static enum drm_connector_status
1221 radeon_atom_dac_detect(struct drm_encoder
*encoder
, struct drm_connector
*connector
)
1223 struct drm_device
*dev
= encoder
->dev
;
1224 struct radeon_device
*rdev
= dev
->dev_private
;
1225 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1226 struct radeon_connector
*radeon_connector
= to_radeon_connector(connector
);
1227 uint32_t bios_0_scratch
;
1229 if (!atombios_dac_load_detect(encoder
, connector
)) {
1230 DRM_DEBUG("detect returned false \n");
1231 return connector_status_unknown
;
1234 if (rdev
->family
>= CHIP_R600
)
1235 bios_0_scratch
= RREG32(R600_BIOS_0_SCRATCH
);
1237 bios_0_scratch
= RREG32(RADEON_BIOS_0_SCRATCH
);
1239 DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch
, radeon_encoder
->devices
);
1240 if (radeon_connector
->devices
& ATOM_DEVICE_CRT1_SUPPORT
) {
1241 if (bios_0_scratch
& ATOM_S0_CRT1_MASK
)
1242 return connector_status_connected
;
1244 if (radeon_connector
->devices
& ATOM_DEVICE_CRT2_SUPPORT
) {
1245 if (bios_0_scratch
& ATOM_S0_CRT2_MASK
)
1246 return connector_status_connected
;
1248 if (radeon_connector
->devices
& ATOM_DEVICE_CV_SUPPORT
) {
1249 if (bios_0_scratch
& (ATOM_S0_CV_MASK
|ATOM_S0_CV_MASK_A
))
1250 return connector_status_connected
;
1252 if (radeon_connector
->devices
& ATOM_DEVICE_TV1_SUPPORT
) {
1253 if (bios_0_scratch
& (ATOM_S0_TV1_COMPOSITE
| ATOM_S0_TV1_COMPOSITE_A
))
1254 return connector_status_connected
; /* CTV */
1255 else if (bios_0_scratch
& (ATOM_S0_TV1_SVIDEO
| ATOM_S0_TV1_SVIDEO_A
))
1256 return connector_status_connected
; /* STV */
1258 return connector_status_disconnected
;
1261 static void radeon_atom_encoder_prepare(struct drm_encoder
*encoder
)
1263 radeon_atom_output_lock(encoder
, true);
1264 radeon_atom_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
1266 radeon_encoder_set_active_device(encoder
);
1269 static void radeon_atom_encoder_commit(struct drm_encoder
*encoder
)
1271 radeon_atom_encoder_dpms(encoder
, DRM_MODE_DPMS_ON
);
1272 radeon_atom_output_lock(encoder
, false);
1275 static void radeon_atom_encoder_disable(struct drm_encoder
*encoder
)
1277 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1278 radeon_atom_encoder_dpms(encoder
, DRM_MODE_DPMS_OFF
);
1279 radeon_encoder
->active_device
= 0;
1282 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs
= {
1283 .dpms
= radeon_atom_encoder_dpms
,
1284 .mode_fixup
= radeon_atom_mode_fixup
,
1285 .prepare
= radeon_atom_encoder_prepare
,
1286 .mode_set
= radeon_atom_encoder_mode_set
,
1287 .commit
= radeon_atom_encoder_commit
,
1288 .disable
= radeon_atom_encoder_disable
,
1289 /* no detect for TMDS/LVDS yet */
1292 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs
= {
1293 .dpms
= radeon_atom_encoder_dpms
,
1294 .mode_fixup
= radeon_atom_mode_fixup
,
1295 .prepare
= radeon_atom_encoder_prepare
,
1296 .mode_set
= radeon_atom_encoder_mode_set
,
1297 .commit
= radeon_atom_encoder_commit
,
1298 .detect
= radeon_atom_dac_detect
,
1301 void radeon_enc_destroy(struct drm_encoder
*encoder
)
1303 struct radeon_encoder
*radeon_encoder
= to_radeon_encoder(encoder
);
1304 kfree(radeon_encoder
->enc_priv
);
1305 drm_encoder_cleanup(encoder
);
1306 kfree(radeon_encoder
);
1309 static const struct drm_encoder_funcs radeon_atom_enc_funcs
= {
1310 .destroy
= radeon_enc_destroy
,
1313 struct radeon_encoder_atom_dac
*
1314 radeon_atombios_set_dac_info(struct radeon_encoder
*radeon_encoder
)
1316 struct radeon_encoder_atom_dac
*dac
= kzalloc(sizeof(struct radeon_encoder_atom_dac
), GFP_KERNEL
);
1321 dac
->tv_std
= TV_STD_NTSC
;
1325 struct radeon_encoder_atom_dig
*
1326 radeon_atombios_set_dig_info(struct radeon_encoder
*radeon_encoder
)
1328 struct radeon_encoder_atom_dig
*dig
= kzalloc(sizeof(struct radeon_encoder_atom_dig
), GFP_KERNEL
);
1333 /* coherent mode by default */
1334 dig
->coherent_mode
= true;
1340 radeon_add_atom_encoder(struct drm_device
*dev
, uint32_t encoder_id
, uint32_t supported_device
)
1342 struct drm_encoder
*encoder
;
1343 struct radeon_encoder
*radeon_encoder
;
1345 /* see if we already added it */
1346 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
1347 radeon_encoder
= to_radeon_encoder(encoder
);
1348 if (radeon_encoder
->encoder_id
== encoder_id
) {
1349 radeon_encoder
->devices
|= supported_device
;
1356 radeon_encoder
= kzalloc(sizeof(struct radeon_encoder
), GFP_KERNEL
);
1357 if (!radeon_encoder
)
1360 encoder
= &radeon_encoder
->base
;
1361 encoder
->possible_crtcs
= 0x3;
1362 encoder
->possible_clones
= 0;
1364 radeon_encoder
->enc_priv
= NULL
;
1366 radeon_encoder
->encoder_id
= encoder_id
;
1367 radeon_encoder
->devices
= supported_device
;
1368 radeon_encoder
->rmx_type
= RMX_OFF
;
1370 switch (radeon_encoder
->encoder_id
) {
1371 case ENCODER_OBJECT_ID_INTERNAL_LVDS
:
1372 case ENCODER_OBJECT_ID_INTERNAL_TMDS1
:
1373 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1
:
1374 case ENCODER_OBJECT_ID_INTERNAL_LVTM1
:
1375 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1376 radeon_encoder
->rmx_type
= RMX_FULL
;
1377 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_LVDS
);
1378 radeon_encoder
->enc_priv
= radeon_atombios_get_lvds_info(radeon_encoder
);
1380 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TMDS
);
1381 radeon_encoder
->enc_priv
= radeon_atombios_set_dig_info(radeon_encoder
);
1383 drm_encoder_helper_add(encoder
, &radeon_atom_dig_helper_funcs
);
1385 case ENCODER_OBJECT_ID_INTERNAL_DAC1
:
1386 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_DAC
);
1387 drm_encoder_helper_add(encoder
, &radeon_atom_dac_helper_funcs
);
1389 case ENCODER_OBJECT_ID_INTERNAL_DAC2
:
1390 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1
:
1391 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2
:
1392 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TVDAC
);
1393 radeon_encoder
->enc_priv
= radeon_atombios_set_dac_info(radeon_encoder
);
1394 drm_encoder_helper_add(encoder
, &radeon_atom_dac_helper_funcs
);
1396 case ENCODER_OBJECT_ID_INTERNAL_DVO1
:
1397 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1
:
1398 case ENCODER_OBJECT_ID_INTERNAL_DDI
:
1399 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY
:
1400 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA
:
1401 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1
:
1402 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2
:
1403 if (radeon_encoder
->devices
& (ATOM_DEVICE_LCD_SUPPORT
)) {
1404 radeon_encoder
->rmx_type
= RMX_FULL
;
1405 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_LVDS
);
1406 radeon_encoder
->enc_priv
= radeon_atombios_get_lvds_info(radeon_encoder
);
1408 drm_encoder_init(dev
, encoder
, &radeon_atom_enc_funcs
, DRM_MODE_ENCODER_TMDS
);
1409 radeon_encoder
->enc_priv
= radeon_atombios_set_dig_info(radeon_encoder
);
1411 drm_encoder_helper_add(encoder
, &radeon_atom_dig_helper_funcs
);