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Staging: rt2870: add Antenna Diversity support
[linux-2.6/mini2440.git] / drivers / staging / rt2860 / common / rtmp_init.c
blobe6a43b64502263531fba0511aeb883b526c6a7fc
1 /*
2 *************************************************************************
3 * Ralink Tech Inc.
4 * 5F., No.36, Taiyuan St., Jhubei City,
5 * Hsinchu County 302,
6 * Taiwan, R.O.C.
7 *
8 * (c) Copyright 2002-2007, Ralink Technology, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
14 * *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
19 * *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 * *
25 *************************************************************************
26
27 Module Name:
28 rtmp_init.c
29
30 Abstract:
31 Miniport generic portion header file
32
33 Revision History:
34 Who When What
35 -------- ---------- ----------------------------------------------
36 Paul Lin 2002-08-01 created
37 John Chang 2004-08-20 RT2561/2661 use scatter-gather scheme
38 Jan Lee 2006-09-15 RT2860. Change for 802.11n , EEPROM, Led, BA, HT.
39 */
40 #include "../rt_config.h"
41 #ifndef RT30xx
42 #ifdef RT2860
43 #include "firmware.h"
44 #include <linux/bitrev.h>
45 #endif
46 #ifdef RT2870
47 #include "../../rt2870/common/firmware.h"
48 #endif
49 #endif
50 #ifdef RT30xx
51 #include "../../rt3070/firmware.h"
52 #endif
53
54 UCHAR BIT8[] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80};
55 ULONG BIT32[] = {0x00000001, 0x00000002, 0x00000004, 0x00000008,
56 0x00000010, 0x00000020, 0x00000040, 0x00000080,
57 0x00000100, 0x00000200, 0x00000400, 0x00000800,
58 0x00001000, 0x00002000, 0x00004000, 0x00008000,
59 0x00010000, 0x00020000, 0x00040000, 0x00080000,
60 0x00100000, 0x00200000, 0x00400000, 0x00800000,
61 0x01000000, 0x02000000, 0x04000000, 0x08000000,
62 0x10000000, 0x20000000, 0x40000000, 0x80000000};
63
64 char* CipherName[] = {"none","wep64","wep128","TKIP","AES","CKIP64","CKIP128"};
65
66 const unsigned short ccitt_16Table[] = {
67 0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7,
68 0x8108, 0x9129, 0xA14A, 0xB16B, 0xC18C, 0xD1AD, 0xE1CE, 0xF1EF,
69 0x1231, 0x0210, 0x3273, 0x2252, 0x52B5, 0x4294, 0x72F7, 0x62D6,
70 0x9339, 0x8318, 0xB37B, 0xA35A, 0xD3BD, 0xC39C, 0xF3FF, 0xE3DE,
71 0x2462, 0x3443, 0x0420, 0x1401, 0x64E6, 0x74C7, 0x44A4, 0x5485,
72 0xA56A, 0xB54B, 0x8528, 0x9509, 0xE5EE, 0xF5CF, 0xC5AC, 0xD58D,
73 0x3653, 0x2672, 0x1611, 0x0630, 0x76D7, 0x66F6, 0x5695, 0x46B4,
74 0xB75B, 0xA77A, 0x9719, 0x8738, 0xF7DF, 0xE7FE, 0xD79D, 0xC7BC,
75 0x48C4, 0x58E5, 0x6886, 0x78A7, 0x0840, 0x1861, 0x2802, 0x3823,
76 0xC9CC, 0xD9ED, 0xE98E, 0xF9AF, 0x8948, 0x9969, 0xA90A, 0xB92B,
77 0x5AF5, 0x4AD4, 0x7AB7, 0x6A96, 0x1A71, 0x0A50, 0x3A33, 0x2A12,
78 0xDBFD, 0xCBDC, 0xFBBF, 0xEB9E, 0x9B79, 0x8B58, 0xBB3B, 0xAB1A,
79 0x6CA6, 0x7C87, 0x4CE4, 0x5CC5, 0x2C22, 0x3C03, 0x0C60, 0x1C41,
80 0xEDAE, 0xFD8F, 0xCDEC, 0xDDCD, 0xAD2A, 0xBD0B, 0x8D68, 0x9D49,
81 0x7E97, 0x6EB6, 0x5ED5, 0x4EF4, 0x3E13, 0x2E32, 0x1E51, 0x0E70,
82 0xFF9F, 0xEFBE, 0xDFDD, 0xCFFC, 0xBF1B, 0xAF3A, 0x9F59, 0x8F78,
83 0x9188, 0x81A9, 0xB1CA, 0xA1EB, 0xD10C, 0xC12D, 0xF14E, 0xE16F,
84 0x1080, 0x00A1, 0x30C2, 0x20E3, 0x5004, 0x4025, 0x7046, 0x6067,
85 0x83B9, 0x9398, 0xA3FB, 0xB3DA, 0xC33D, 0xD31C, 0xE37F, 0xF35E,
86 0x02B1, 0x1290, 0x22F3, 0x32D2, 0x4235, 0x5214, 0x6277, 0x7256,
87 0xB5EA, 0xA5CB, 0x95A8, 0x8589, 0xF56E, 0xE54F, 0xD52C, 0xC50D,
88 0x34E2, 0x24C3, 0x14A0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
89 0xA7DB, 0xB7FA, 0x8799, 0x97B8, 0xE75F, 0xF77E, 0xC71D, 0xD73C,
90 0x26D3, 0x36F2, 0x0691, 0x16B0, 0x6657, 0x7676, 0x4615, 0x5634,
91 0xD94C, 0xC96D, 0xF90E, 0xE92F, 0x99C8, 0x89E9, 0xB98A, 0xA9AB,
92 0x5844, 0x4865, 0x7806, 0x6827, 0x18C0, 0x08E1, 0x3882, 0x28A3,
93 0xCB7D, 0xDB5C, 0xEB3F, 0xFB1E, 0x8BF9, 0x9BD8, 0xABBB, 0xBB9A,
94 0x4A75, 0x5A54, 0x6A37, 0x7A16, 0x0AF1, 0x1AD0, 0x2AB3, 0x3A92,
95 0xFD2E, 0xED0F, 0xDD6C, 0xCD4D, 0xBDAA, 0xAD8B, 0x9DE8, 0x8DC9,
96 0x7C26, 0x6C07, 0x5C64, 0x4C45, 0x3CA2, 0x2C83, 0x1CE0, 0x0CC1,
97 0xEF1F, 0xFF3E, 0xCF5D, 0xDF7C, 0xAF9B, 0xBFBA, 0x8FD9, 0x9FF8,
98 0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0
99 };
100 #define ByteCRC16(v, crc) \
101 (unsigned short)((crc << 8) ^ ccitt_16Table[((crc >> 8) ^ (v)) & 255])
102
103 #ifdef RT2870
104 unsigned char BitReverse(unsigned char x)
105 {
106 int i;
107 unsigned char Temp=0;
108 for(i=0; ; i++)
109 {
110 if(x & 0x80) Temp |= 0x80;
111 if(i==7) break;
112 x <<= 1;
113 Temp >>= 1;
114 }
115 return Temp;
116 }
117 #endif
118
119 //
120 // BBP register initialization set
121 //
122 REG_PAIR BBPRegTable[] = {
123 {BBP_R65, 0x2C}, // fix rssi issue
124 {BBP_R66, 0x38}, // Also set this default value to pAd->BbpTuning.R66CurrentValue at initial
125 {BBP_R69, 0x12},
126 {BBP_R70, 0xa}, // BBP_R70 will change to 0x8 in ApStartUp and LinkUp for rt2860C, otherwise value is 0xa
127 {BBP_R73, 0x10},
128 {BBP_R81, 0x37},
129 {BBP_R82, 0x62},
130 {BBP_R83, 0x6A},
131 {BBP_R84, 0x99}, // 0x19 is for rt2860E and after. This is for extension channel overlapping IOT. 0x99 is for rt2860D and before
132 {BBP_R86, 0x00}, // middle range issue, Rory @2008-01-28
133 {BBP_R91, 0x04}, // middle range issue, Rory @2008-01-28
134 {BBP_R92, 0x00}, // middle range issue, Rory @2008-01-28
135 {BBP_R103, 0x00}, // near range high-power issue, requested from Gary @2008-0528
136 {BBP_R105, 0x05}, // 0x05 is for rt2860E to turn on FEQ control. It is safe for rt2860D and before, because Bit 7:2 are reserved in rt2860D and before.
137 };
138 #define NUM_BBP_REG_PARMS (sizeof(BBPRegTable) / sizeof(REG_PAIR))
139
140 //
141 // RF register initialization set
142 //
143 #ifdef RT2870
144 REG_PAIR RT30xx_RFRegTable[] = {
145 {RF_R04, 0x40},
146 {RF_R05, 0x03},
147 {RF_R06, 0x02},
148 {RF_R07, 0x70},
149 {RF_R09, 0x0F},
150 #ifndef RT30xx
151 {RF_R10, 0x71},
152 #endif
153 #ifdef RT30xx
154 {RF_R10, 0x41},
155 #endif
156 {RF_R11, 0x21},
157 {RF_R12, 0x7B},
158 {RF_R14, 0x90},
159 {RF_R15, 0x58},
160 {RF_R16, 0xB3},
161 {RF_R17, 0x92},
162 {RF_R18, 0x2C},
163 {RF_R19, 0x02},
164 {RF_R20, 0xBA},
165 {RF_R21, 0xDB},
166 {RF_R24, 0x16},
167 {RF_R25, 0x01},
168 #ifndef RT30xx
169 {RF_R27, 0x03},
170 #endif
171 {RF_R29, 0x1F},
172 };
173 #define NUM_RF_REG_PARMS (sizeof(RT30xx_RFRegTable) / sizeof(REG_PAIR))
174 #endif // RT2870 //
175
176 //
177 // ASIC register initialization sets
178 //
179
180 RTMP_REG_PAIR MACRegTable[] = {
181 #if defined(HW_BEACON_OFFSET) && (HW_BEACON_OFFSET == 0x200)
182 {BCN_OFFSET0, 0xf8f0e8e0}, /* 0x3800(e0), 0x3A00(e8), 0x3C00(f0), 0x3E00(f8), 512B for each beacon */
183 {BCN_OFFSET1, 0x6f77d0c8}, /* 0x3200(c8), 0x3400(d0), 0x1DC0(77), 0x1BC0(6f), 512B for each beacon */
184 #elif defined(HW_BEACON_OFFSET) && (HW_BEACON_OFFSET == 0x100)
185 {BCN_OFFSET0, 0xece8e4e0}, /* 0x3800, 0x3A00, 0x3C00, 0x3E00, 512B for each beacon */
186 {BCN_OFFSET1, 0xfcf8f4f0}, /* 0x3800, 0x3A00, 0x3C00, 0x3E00, 512B for each beacon */
187 #else
188 #error You must re-calculate new value for BCN_OFFSET0 & BCN_OFFSET1 in MACRegTable[]!!!
189 #endif // HW_BEACON_OFFSET //
190
191 {LEGACY_BASIC_RATE, 0x0000013f}, // Basic rate set bitmap
192 {HT_BASIC_RATE, 0x00008003}, // Basic HT rate set , 20M, MCS=3, MM. Format is the same as in TXWI.
193 {MAC_SYS_CTRL, 0x00}, // 0x1004, , default Disable RX
194 {RX_FILTR_CFG, 0x17f97}, //0x1400 , RX filter control,
195 {BKOFF_SLOT_CFG, 0x209}, // default set short slot time, CC_DELAY_TIME should be 2
196 {TX_SW_CFG0, 0x0}, // Gary,2008-05-21 for CWC test
197 {TX_SW_CFG1, 0x80606}, // Gary,2006-08-23
198 {TX_LINK_CFG, 0x1020}, // Gary,2006-08-23
199 {TX_TIMEOUT_CFG, 0x000a2090}, // CCK has some problem. So increase timieout value. 2006-10-09// MArvek RT , Modify for 2860E ,2007-08-01
200 {MAX_LEN_CFG, MAX_AGGREGATION_SIZE | 0x00001000}, // 0x3018, MAX frame length. Max PSDU = 16kbytes.
201 {LED_CFG, 0x7f031e46}, // Gary, 2006-08-23
202 {PBF_MAX_PCNT, 0x1F3FBF9F}, //0x1F3f7f9f}, //Jan, 2006/04/20
203 {TX_RTY_CFG, 0x47d01f0f}, // Jan, 2006/11/16, Set TxWI->ACK =0 in Probe Rsp Modify for 2860E ,2007-08-03
204 {AUTO_RSP_CFG, 0x00000013}, // Initial Auto_Responder, because QA will turn off Auto-Responder
205 {CCK_PROT_CFG, 0x05740003 /*0x01740003*/}, // Initial Auto_Responder, because QA will turn off Auto-Responder. And RTS threshold is enabled.
206 {OFDM_PROT_CFG, 0x05740003 /*0x01740003*/}, // Initial Auto_Responder, because QA will turn off Auto-Responder. And RTS threshold is enabled.
207 //PS packets use Tx1Q (for HCCA) when dequeue from PS unicast queue (WiFi WPA2 MA9_DT1 for Marvell B STA)
208 #ifdef RT2870
209 {PBF_CFG, 0xf40006}, // Only enable Queue 2
210 {MM40_PROT_CFG, 0x3F44084}, // Initial Auto_Responder, because QA will turn off Auto-Responder
211 {WPDMA_GLO_CFG, 0x00000030},
212 #endif // RT2870 //
213 {GF20_PROT_CFG, 0x01744004}, // set 19:18 --> Short NAV for MIMO PS
214 {GF40_PROT_CFG, 0x03F44084},
215 {MM20_PROT_CFG, 0x01744004},
216 #ifdef RT2860
217 {MM40_PROT_CFG, 0x03F54084},
218 #endif
219 {TXOP_CTRL_CFG, 0x0000583f, /*0x0000243f*/ /*0x000024bf*/}, //Extension channel backoff.
220 {TX_RTS_CFG, 0x00092b20},
221 {EXP_ACK_TIME, 0x002400ca}, // default value
222 {TXOP_HLDR_ET, 0x00000002},
223
224 /* Jerry comments 2008/01/16: we use SIFS = 10us in CCK defaultly, but it seems that 10us
225 is too small for INTEL 2200bg card, so in MBSS mode, the delta time between beacon0
226 and beacon1 is SIFS (10us), so if INTEL 2200bg card connects to BSS0, the ping
227 will always lost. So we change the SIFS of CCK from 10us to 16us. */
228 {XIFS_TIME_CFG, 0x33a41010},
229 {PWR_PIN_CFG, 0x00000003}, // patch for 2880-E
230 };
231
232 RTMP_REG_PAIR STAMACRegTable[] = {
233 {WMM_AIFSN_CFG, 0x00002273},
234 {WMM_CWMIN_CFG, 0x00002344},
235 {WMM_CWMAX_CFG, 0x000034aa},
236 };
237
238 #define NUM_MAC_REG_PARMS (sizeof(MACRegTable) / sizeof(RTMP_REG_PAIR))
239 #define NUM_STA_MAC_REG_PARMS (sizeof(STAMACRegTable) / sizeof(RTMP_REG_PAIR))
240
241 #ifdef RT2870
242 //
243 // RT2870 Firmware Spec only used 1 oct for version expression
244 //
245 #define FIRMWARE_MINOR_VERSION 7
246
247 #endif // RT2870 //
248
249 // New 8k byte firmware size for RT3071/RT3072
250 #define FIRMWAREIMAGE_MAX_LENGTH 0x2000
251 #define FIRMWAREIMAGE_LENGTH (sizeof (FirmwareImage) / sizeof(UCHAR))
252 #define FIRMWARE_MAJOR_VERSION 0
253
254 #define FIRMWAREIMAGEV1_LENGTH 0x1000
255 #define FIRMWAREIMAGEV2_LENGTH 0x1000
256
257 #ifdef RT2860
258 #define FIRMWARE_MINOR_VERSION 2
259 #endif
260
261
262 /*
263 ========================================================================
264
265 Routine Description:
266 Allocate RTMP_ADAPTER data block and do some initialization
267
268 Arguments:
269 Adapter Pointer to our adapter
270
271 Return Value:
272 NDIS_STATUS_SUCCESS
273 NDIS_STATUS_FAILURE
274
275 IRQL = PASSIVE_LEVEL
276
277 Note:
278
279 ========================================================================
280 */
281 NDIS_STATUS RTMPAllocAdapterBlock(
282 IN PVOID handle,
283 OUT PRTMP_ADAPTER *ppAdapter)
284 {
285 PRTMP_ADAPTER pAd;
286 NDIS_STATUS Status;
287 INT index;
288 UCHAR *pBeaconBuf = NULL;
289
290 DBGPRINT(RT_DEBUG_TRACE, ("--> RTMPAllocAdapterBlock\n"));
291
292 *ppAdapter = NULL;
293
294 do
295 {
296 // Allocate RTMP_ADAPTER memory block
297 pBeaconBuf = kmalloc(MAX_BEACON_SIZE, MEM_ALLOC_FLAG);
298 if (pBeaconBuf == NULL)
299 {
300 Status = NDIS_STATUS_FAILURE;
301 DBGPRINT_ERR(("Failed to allocate memory - BeaconBuf!\n"));
302 break;
303 }
304
305 Status = AdapterBlockAllocateMemory(handle, (PVOID *)&pAd);
306 if (Status != NDIS_STATUS_SUCCESS)
307 {
308 DBGPRINT_ERR(("Failed to allocate memory - ADAPTER\n"));
309 break;
310 }
311 pAd->BeaconBuf = pBeaconBuf;
312 printk("\n\n=== pAd = %p, size = %d ===\n\n", pAd, (UINT32)sizeof(RTMP_ADAPTER));
313
314
315 // Init spin locks
316 NdisAllocateSpinLock(&pAd->MgmtRingLock);
317 #ifdef RT2860
318 NdisAllocateSpinLock(&pAd->RxRingLock);
319 #endif
320
321 for (index =0 ; index < NUM_OF_TX_RING; index++)
322 {
323 NdisAllocateSpinLock(&pAd->TxSwQueueLock[index]);
324 NdisAllocateSpinLock(&pAd->DeQueueLock[index]);
325 pAd->DeQueueRunning[index] = FALSE;
326 }
327
328 NdisAllocateSpinLock(&pAd->irq_lock);
329
330 } while (FALSE);
331
332 if ((Status != NDIS_STATUS_SUCCESS) && (pBeaconBuf))
333 kfree(pBeaconBuf);
334
335 *ppAdapter = pAd;
336
337 DBGPRINT_S(Status, ("<-- RTMPAllocAdapterBlock, Status=%x\n", Status));
338 return Status;
339 }
340
341 /*
342 ========================================================================
343
344 Routine Description:
345 Read initial Tx power per MCS and BW from EEPROM
346
347 Arguments:
348 Adapter Pointer to our adapter
349
350 Return Value:
351 None
352
353 IRQL = PASSIVE_LEVEL
354
355 Note:
356
357 ========================================================================
358 */
359 VOID RTMPReadTxPwrPerRate(
360 IN PRTMP_ADAPTER pAd)
361 {
362 ULONG data, Adata, Gdata;
363 USHORT i, value, value2;
364 INT Apwrdelta, Gpwrdelta;
365 UCHAR t1,t2,t3,t4;
366 BOOLEAN bValid, bApwrdeltaMinus = TRUE, bGpwrdeltaMinus = TRUE;
367
368 //
369 // Get power delta for 20MHz and 40MHz.
370 //
371 DBGPRINT(RT_DEBUG_TRACE, ("Txpower per Rate\n"));
372 RT28xx_EEPROM_READ16(pAd, EEPROM_TXPOWER_DELTA, value2);
373 Apwrdelta = 0;
374 Gpwrdelta = 0;
375
376 if ((value2 & 0xff) != 0xff)
377 {
378 if ((value2 & 0x80))
379 Gpwrdelta = (value2&0xf);
380
381 if ((value2 & 0x40))
382 bGpwrdeltaMinus = FALSE;
383 else
384 bGpwrdeltaMinus = TRUE;
385 }
386 if ((value2 & 0xff00) != 0xff00)
387 {
388 if ((value2 & 0x8000))
389 Apwrdelta = ((value2&0xf00)>>8);
390
391 if ((value2 & 0x4000))
392 bApwrdeltaMinus = FALSE;
393 else
394 bApwrdeltaMinus = TRUE;
395 }
396 DBGPRINT(RT_DEBUG_TRACE, ("Gpwrdelta = %x, Apwrdelta = %x .\n", Gpwrdelta, Apwrdelta));
397
398 //
399 // Get Txpower per MCS for 20MHz in 2.4G.
400 //
401 for (i=0; i<5; i++)
402 {
403 RT28xx_EEPROM_READ16(pAd, EEPROM_TXPOWER_BYRATE_20MHZ_2_4G + i*4, value);
404 data = value;
405 if (bApwrdeltaMinus == FALSE)
406 {
407 t1 = (value&0xf)+(Apwrdelta);
408 if (t1 > 0xf)
409 t1 = 0xf;
410 t2 = ((value&0xf0)>>4)+(Apwrdelta);
411 if (t2 > 0xf)
412 t2 = 0xf;
413 t3 = ((value&0xf00)>>8)+(Apwrdelta);
414 if (t3 > 0xf)
415 t3 = 0xf;
416 t4 = ((value&0xf000)>>12)+(Apwrdelta);
417 if (t4 > 0xf)
418 t4 = 0xf;
419 }
420 else
421 {
422 if ((value&0xf) > Apwrdelta)
423 t1 = (value&0xf)-(Apwrdelta);
424 else
425 t1 = 0;
426 if (((value&0xf0)>>4) > Apwrdelta)
427 t2 = ((value&0xf0)>>4)-(Apwrdelta);
428 else
429 t2 = 0;
430 if (((value&0xf00)>>8) > Apwrdelta)
431 t3 = ((value&0xf00)>>8)-(Apwrdelta);
432 else
433 t3 = 0;
434 if (((value&0xf000)>>12) > Apwrdelta)
435 t4 = ((value&0xf000)>>12)-(Apwrdelta);
436 else
437 t4 = 0;
438 }
439 Adata = t1 + (t2<<4) + (t3<<8) + (t4<<12);
440 if (bGpwrdeltaMinus == FALSE)
441 {
442 t1 = (value&0xf)+(Gpwrdelta);
443 if (t1 > 0xf)
444 t1 = 0xf;
445 t2 = ((value&0xf0)>>4)+(Gpwrdelta);
446 if (t2 > 0xf)
447 t2 = 0xf;
448 t3 = ((value&0xf00)>>8)+(Gpwrdelta);
449 if (t3 > 0xf)
450 t3 = 0xf;
451 t4 = ((value&0xf000)>>12)+(Gpwrdelta);
452 if (t4 > 0xf)
453 t4 = 0xf;
454 }
455 else
456 {
457 if ((value&0xf) > Gpwrdelta)
458 t1 = (value&0xf)-(Gpwrdelta);
459 else
460 t1 = 0;
461 if (((value&0xf0)>>4) > Gpwrdelta)
462 t2 = ((value&0xf0)>>4)-(Gpwrdelta);
463 else
464 t2 = 0;
465 if (((value&0xf00)>>8) > Gpwrdelta)
466 t3 = ((value&0xf00)>>8)-(Gpwrdelta);
467 else
468 t3 = 0;
469 if (((value&0xf000)>>12) > Gpwrdelta)
470 t4 = ((value&0xf000)>>12)-(Gpwrdelta);
471 else
472 t4 = 0;
473 }
474 Gdata = t1 + (t2<<4) + (t3<<8) + (t4<<12);
475
476 RT28xx_EEPROM_READ16(pAd, EEPROM_TXPOWER_BYRATE_20MHZ_2_4G + i*4 + 2, value);
477 if (bApwrdeltaMinus == FALSE)
478 {
479 t1 = (value&0xf)+(Apwrdelta);
480 if (t1 > 0xf)
481 t1 = 0xf;
482 t2 = ((value&0xf0)>>4)+(Apwrdelta);
483 if (t2 > 0xf)
484 t2 = 0xf;
485 t3 = ((value&0xf00)>>8)+(Apwrdelta);
486 if (t3 > 0xf)
487 t3 = 0xf;
488 t4 = ((value&0xf000)>>12)+(Apwrdelta);
489 if (t4 > 0xf)
490 t4 = 0xf;
491 }
492 else
493 {
494 if ((value&0xf) > Apwrdelta)
495 t1 = (value&0xf)-(Apwrdelta);
496 else
497 t1 = 0;
498 if (((value&0xf0)>>4) > Apwrdelta)
499 t2 = ((value&0xf0)>>4)-(Apwrdelta);
500 else
501 t2 = 0;
502 if (((value&0xf00)>>8) > Apwrdelta)
503 t3 = ((value&0xf00)>>8)-(Apwrdelta);
504 else
505 t3 = 0;
506 if (((value&0xf000)>>12) > Apwrdelta)
507 t4 = ((value&0xf000)>>12)-(Apwrdelta);
508 else
509 t4 = 0;
510 }
511 Adata |= ((t1<<16) + (t2<<20) + (t3<<24) + (t4<<28));
512 if (bGpwrdeltaMinus == FALSE)
513 {
514 t1 = (value&0xf)+(Gpwrdelta);
515 if (t1 > 0xf)
516 t1 = 0xf;
517 t2 = ((value&0xf0)>>4)+(Gpwrdelta);
518 if (t2 > 0xf)
519 t2 = 0xf;
520 t3 = ((value&0xf00)>>8)+(Gpwrdelta);
521 if (t3 > 0xf)
522 t3 = 0xf;
523 t4 = ((value&0xf000)>>12)+(Gpwrdelta);
524 if (t4 > 0xf)
525 t4 = 0xf;
526 }
527 else
528 {
529 if ((value&0xf) > Gpwrdelta)
530 t1 = (value&0xf)-(Gpwrdelta);
531 else
532 t1 = 0;
533 if (((value&0xf0)>>4) > Gpwrdelta)
534 t2 = ((value&0xf0)>>4)-(Gpwrdelta);
535 else
536 t2 = 0;
537 if (((value&0xf00)>>8) > Gpwrdelta)
538 t3 = ((value&0xf00)>>8)-(Gpwrdelta);
539 else
540 t3 = 0;
541 if (((value&0xf000)>>12) > Gpwrdelta)
542 t4 = ((value&0xf000)>>12)-(Gpwrdelta);
543 else
544 t4 = 0;
545 }
546 Gdata |= ((t1<<16) + (t2<<20) + (t3<<24) + (t4<<28));
547 data |= (value<<16);
548
549 pAd->Tx20MPwrCfgABand[i] = pAd->Tx40MPwrCfgABand[i] = Adata;
550 pAd->Tx20MPwrCfgGBand[i] = pAd->Tx40MPwrCfgGBand[i] = Gdata;
551
552 if (data != 0xffffffff)
553 RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + i*4, data);
554 DBGPRINT_RAW(RT_DEBUG_TRACE, ("20MHz BW, 2.4G band-%lx, Adata = %lx, Gdata = %lx \n", data, Adata, Gdata));
555 }
556
557 //
558 // Check this block is valid for 40MHz in 2.4G. If invalid, use parameter for 20MHz in 2.4G
559 //
560 bValid = TRUE;
561 for (i=0; i<6; i++)
562 {
563 RT28xx_EEPROM_READ16(pAd, EEPROM_TXPOWER_BYRATE_40MHZ_2_4G + 2 + i*2, value);
564 if (((value & 0x00FF) == 0x00FF) || ((value & 0xFF00) == 0xFF00))
565 {
566 bValid = FALSE;
567 break;
568 }
569 }
570
571 //
572 // Get Txpower per MCS for 40MHz in 2.4G.
573 //
574 if (bValid)
575 {
576 for (i=0; i<4; i++)
577 {
578 RT28xx_EEPROM_READ16(pAd, EEPROM_TXPOWER_BYRATE_40MHZ_2_4G + i*4, value);
579 if (bGpwrdeltaMinus == FALSE)
580 {
581 t1 = (value&0xf)+(Gpwrdelta);
582 if (t1 > 0xf)
583 t1 = 0xf;
584 t2 = ((value&0xf0)>>4)+(Gpwrdelta);
585 if (t2 > 0xf)
586 t2 = 0xf;
587 t3 = ((value&0xf00)>>8)+(Gpwrdelta);
588 if (t3 > 0xf)
589 t3 = 0xf;
590 t4 = ((value&0xf000)>>12)+(Gpwrdelta);
591 if (t4 > 0xf)
592 t4 = 0xf;
593 }
594 else
595 {
596 if ((value&0xf) > Gpwrdelta)
597 t1 = (value&0xf)-(Gpwrdelta);
598 else
599 t1 = 0;
600 if (((value&0xf0)>>4) > Gpwrdelta)
601 t2 = ((value&0xf0)>>4)-(Gpwrdelta);
602 else
603 t2 = 0;
604 if (((value&0xf00)>>8) > Gpwrdelta)
605 t3 = ((value&0xf00)>>8)-(Gpwrdelta);
606 else
607 t3 = 0;
608 if (((value&0xf000)>>12) > Gpwrdelta)
609 t4 = ((value&0xf000)>>12)-(Gpwrdelta);
610 else
611 t4 = 0;
612 }
613 Gdata = t1 + (t2<<4) + (t3<<8) + (t4<<12);
614
615 RT28xx_EEPROM_READ16(pAd, EEPROM_TXPOWER_BYRATE_40MHZ_2_4G + i*4 + 2, value);
616 if (bGpwrdeltaMinus == FALSE)
617 {
618 t1 = (value&0xf)+(Gpwrdelta);
619 if (t1 > 0xf)
620 t1 = 0xf;
621 t2 = ((value&0xf0)>>4)+(Gpwrdelta);
622 if (t2 > 0xf)
623 t2 = 0xf;
624 t3 = ((value&0xf00)>>8)+(Gpwrdelta);
625 if (t3 > 0xf)
626 t3 = 0xf;
627 t4 = ((value&0xf000)>>12)+(Gpwrdelta);
628 if (t4 > 0xf)
629 t4 = 0xf;
630 }
631 else
632 {
633 if ((value&0xf) > Gpwrdelta)
634 t1 = (value&0xf)-(Gpwrdelta);
635 else
636 t1 = 0;
637 if (((value&0xf0)>>4) > Gpwrdelta)
638 t2 = ((value&0xf0)>>4)-(Gpwrdelta);
639 else
640 t2 = 0;
641 if (((value&0xf00)>>8) > Gpwrdelta)
642 t3 = ((value&0xf00)>>8)-(Gpwrdelta);
643 else
644 t3 = 0;
645 if (((value&0xf000)>>12) > Gpwrdelta)
646 t4 = ((value&0xf000)>>12)-(Gpwrdelta);
647 else
648 t4 = 0;
649 }
650 Gdata |= ((t1<<16) + (t2<<20) + (t3<<24) + (t4<<28));
651
652 if (i == 0)
653 pAd->Tx40MPwrCfgGBand[i+1] = (pAd->Tx40MPwrCfgGBand[i+1] & 0x0000FFFF) | (Gdata & 0xFFFF0000);
654 else
655 pAd->Tx40MPwrCfgGBand[i+1] = Gdata;
656
657 DBGPRINT_RAW(RT_DEBUG_TRACE, ("40MHz BW, 2.4G band, Gdata = %lx \n", Gdata));
658 }
659 }
660
661 //
662 // Check this block is valid for 20MHz in 5G. If invalid, use parameter for 20MHz in 2.4G
663 //
664 bValid = TRUE;
665 for (i=0; i<8; i++)
666 {
667 RT28xx_EEPROM_READ16(pAd, EEPROM_TXPOWER_BYRATE_20MHZ_5G + 2 + i*2, value);
668 if (((value & 0x00FF) == 0x00FF) || ((value & 0xFF00) == 0xFF00))
669 {
670 bValid = FALSE;
671 break;
672 }
673 }
674
675 //
676 // Get Txpower per MCS for 20MHz in 5G.
677 //
678 if (bValid)
679 {
680 for (i=0; i<5; i++)
681 {
682 RT28xx_EEPROM_READ16(pAd, EEPROM_TXPOWER_BYRATE_20MHZ_5G + i*4, value);
683 if (bApwrdeltaMinus == FALSE)
684 {
685 t1 = (value&0xf)+(Apwrdelta);
686 if (t1 > 0xf)
687 t1 = 0xf;
688 t2 = ((value&0xf0)>>4)+(Apwrdelta);
689 if (t2 > 0xf)
690 t2 = 0xf;
691 t3 = ((value&0xf00)>>8)+(Apwrdelta);
692 if (t3 > 0xf)
693 t3 = 0xf;
694 t4 = ((value&0xf000)>>12)+(Apwrdelta);
695 if (t4 > 0xf)
696 t4 = 0xf;
697 }
698 else
699 {
700 if ((value&0xf) > Apwrdelta)
701 t1 = (value&0xf)-(Apwrdelta);
702 else
703 t1 = 0;
704 if (((value&0xf0)>>4) > Apwrdelta)
705 t2 = ((value&0xf0)>>4)-(Apwrdelta);
706 else
707 t2 = 0;
708 if (((value&0xf00)>>8) > Apwrdelta)
709 t3 = ((value&0xf00)>>8)-(Apwrdelta);
710 else
711 t3 = 0;
712 if (((value&0xf000)>>12) > Apwrdelta)
713 t4 = ((value&0xf000)>>12)-(Apwrdelta);
714 else
715 t4 = 0;
716 }
717 Adata = t1 + (t2<<4) + (t3<<8) + (t4<<12);
718
719 RT28xx_EEPROM_READ16(pAd, EEPROM_TXPOWER_BYRATE_20MHZ_5G + i*4 + 2, value);
720 if (bApwrdeltaMinus == FALSE)
721 {
722 t1 = (value&0xf)+(Apwrdelta);
723 if (t1 > 0xf)
724 t1 = 0xf;
725 t2 = ((value&0xf0)>>4)+(Apwrdelta);
726 if (t2 > 0xf)
727 t2 = 0xf;
728 t3 = ((value&0xf00)>>8)+(Apwrdelta);
729 if (t3 > 0xf)
730 t3 = 0xf;
731 t4 = ((value&0xf000)>>12)+(Apwrdelta);
732 if (t4 > 0xf)
733 t4 = 0xf;
734 }
735 else
736 {
737 if ((value&0xf) > Apwrdelta)
738 t1 = (value&0xf)-(Apwrdelta);
739 else
740 t1 = 0;
741 if (((value&0xf0)>>4) > Apwrdelta)
742 t2 = ((value&0xf0)>>4)-(Apwrdelta);
743 else
744 t2 = 0;
745 if (((value&0xf00)>>8) > Apwrdelta)
746 t3 = ((value&0xf00)>>8)-(Apwrdelta);
747 else
748 t3 = 0;
749 if (((value&0xf000)>>12) > Apwrdelta)
750 t4 = ((value&0xf000)>>12)-(Apwrdelta);
751 else
752 t4 = 0;
753 }
754 Adata |= ((t1<<16) + (t2<<20) + (t3<<24) + (t4<<28));
755
756 if (i == 0)
757 pAd->Tx20MPwrCfgABand[i] = (pAd->Tx20MPwrCfgABand[i] & 0x0000FFFF) | (Adata & 0xFFFF0000);
758 else
759 pAd->Tx20MPwrCfgABand[i] = Adata;
760
761 DBGPRINT_RAW(RT_DEBUG_TRACE, ("20MHz BW, 5GHz band, Adata = %lx \n", Adata));
762 }
763 }
764
765 //
766 // Check this block is valid for 40MHz in 5G. If invalid, use parameter for 20MHz in 2.4G
767 //
768 bValid = TRUE;
769 for (i=0; i<6; i++)
770 {
771 RT28xx_EEPROM_READ16(pAd, EEPROM_TXPOWER_BYRATE_40MHZ_5G + 2 + i*2, value);
772 if (((value & 0x00FF) == 0x00FF) || ((value & 0xFF00) == 0xFF00))
773 {
774 bValid = FALSE;
775 break;
776 }
777 }
778
779 //
780 // Get Txpower per MCS for 40MHz in 5G.
781 //
782 if (bValid)
783 {
784 for (i=0; i<4; i++)
785 {
786 RT28xx_EEPROM_READ16(pAd, EEPROM_TXPOWER_BYRATE_40MHZ_5G + i*4, value);
787 if (bApwrdeltaMinus == FALSE)
788 {
789 t1 = (value&0xf)+(Apwrdelta);
790 if (t1 > 0xf)
791 t1 = 0xf;
792 t2 = ((value&0xf0)>>4)+(Apwrdelta);
793 if (t2 > 0xf)
794 t2 = 0xf;
795 t3 = ((value&0xf00)>>8)+(Apwrdelta);
796 if (t3 > 0xf)
797 t3 = 0xf;
798 t4 = ((value&0xf000)>>12)+(Apwrdelta);
799 if (t4 > 0xf)
800 t4 = 0xf;
801 }
802 else
803 {
804 if ((value&0xf) > Apwrdelta)
805 t1 = (value&0xf)-(Apwrdelta);
806 else
807 t1 = 0;
808 if (((value&0xf0)>>4) > Apwrdelta)
809 t2 = ((value&0xf0)>>4)-(Apwrdelta);
810 else
811 t2 = 0;
812 if (((value&0xf00)>>8) > Apwrdelta)
813 t3 = ((value&0xf00)>>8)-(Apwrdelta);
814 else
815 t3 = 0;
816 if (((value&0xf000)>>12) > Apwrdelta)
817 t4 = ((value&0xf000)>>12)-(Apwrdelta);
818 else
819 t4 = 0;
820 }
821 Adata = t1 + (t2<<4) + (t3<<8) + (t4<<12);
822
823 RT28xx_EEPROM_READ16(pAd, EEPROM_TXPOWER_BYRATE_40MHZ_5G + i*4 + 2, value);
824 if (bApwrdeltaMinus == FALSE)
825 {
826 t1 = (value&0xf)+(Apwrdelta);
827 if (t1 > 0xf)
828 t1 = 0xf;
829 t2 = ((value&0xf0)>>4)+(Apwrdelta);
830 if (t2 > 0xf)
831 t2 = 0xf;
832 t3 = ((value&0xf00)>>8)+(Apwrdelta);
833 if (t3 > 0xf)
834 t3 = 0xf;
835 t4 = ((value&0xf000)>>12)+(Apwrdelta);
836 if (t4 > 0xf)
837 t4 = 0xf;
838 }
839 else
840 {
841 if ((value&0xf) > Apwrdelta)
842 t1 = (value&0xf)-(Apwrdelta);
843 else
844 t1 = 0;
845 if (((value&0xf0)>>4) > Apwrdelta)
846 t2 = ((value&0xf0)>>4)-(Apwrdelta);
847 else
848 t2 = 0;
849 if (((value&0xf00)>>8) > Apwrdelta)
850 t3 = ((value&0xf00)>>8)-(Apwrdelta);
851 else
852 t3 = 0;
853 if (((value&0xf000)>>12) > Apwrdelta)
854 t4 = ((value&0xf000)>>12)-(Apwrdelta);
855 else
856 t4 = 0;
857 }
858 Adata |= ((t1<<16) + (t2<<20) + (t3<<24) + (t4<<28));
859
860 if (i == 0)
861 pAd->Tx40MPwrCfgABand[i+1] = (pAd->Tx40MPwrCfgABand[i+1] & 0x0000FFFF) | (Adata & 0xFFFF0000);
862 else
863 pAd->Tx40MPwrCfgABand[i+1] = Adata;
864
865 DBGPRINT_RAW(RT_DEBUG_TRACE, ("40MHz BW, 5GHz band, Adata = %lx \n", Adata));
866 }
867 }
868 }
869
870
871 /*
872 ========================================================================
873
874 Routine Description:
875 Read initial channel power parameters from EEPROM
876
877 Arguments:
878 Adapter Pointer to our adapter
879
880 Return Value:
881 None
882
883 IRQL = PASSIVE_LEVEL
884
885 Note:
886
887 ========================================================================
888 */
889 VOID RTMPReadChannelPwr(
890 IN PRTMP_ADAPTER pAd)
891 {
892 UCHAR i, choffset;
893 EEPROM_TX_PWR_STRUC Power;
894 EEPROM_TX_PWR_STRUC Power2;
895
896 // Read Tx power value for all channels
897 // Value from 1 - 0x7f. Default value is 24.
898 // Power value : 2.4G 0x00 (0) ~ 0x1F (31)
899 // : 5.5G 0xF9 (-7) ~ 0x0F (15)
900
901 // 0. 11b/g, ch1 - ch 14
902 for (i = 0; i < 7; i++)
903 {
904 RT28xx_EEPROM_READ16(pAd, EEPROM_G_TX_PWR_OFFSET + i * 2, Power.word);
905 RT28xx_EEPROM_READ16(pAd, EEPROM_G_TX2_PWR_OFFSET + i * 2, Power2.word);
906 pAd->TxPower[i * 2].Channel = i * 2 + 1;
907 pAd->TxPower[i * 2 + 1].Channel = i * 2 + 2;
908
909 if ((Power.field.Byte0 > 31) || (Power.field.Byte0 < 0))
910 pAd->TxPower[i * 2].Power = DEFAULT_RF_TX_POWER;
911 else
912 pAd->TxPower[i * 2].Power = Power.field.Byte0;
913
914 if ((Power.field.Byte1 > 31) || (Power.field.Byte1 < 0))
915 pAd->TxPower[i * 2 + 1].Power = DEFAULT_RF_TX_POWER;
916 else
917 pAd->TxPower[i * 2 + 1].Power = Power.field.Byte1;
918
919 if ((Power2.field.Byte0 > 31) || (Power2.field.Byte0 < 0))
920 pAd->TxPower[i * 2].Power2 = DEFAULT_RF_TX_POWER;
921 else
922 pAd->TxPower[i * 2].Power2 = Power2.field.Byte0;
923
924 if ((Power2.field.Byte1 > 31) || (Power2.field.Byte1 < 0))
925 pAd->TxPower[i * 2 + 1].Power2 = DEFAULT_RF_TX_POWER;
926 else
927 pAd->TxPower[i * 2 + 1].Power2 = Power2.field.Byte1;
928 }
929
930 // 1. U-NII lower/middle band: 36, 38, 40; 44, 46, 48; 52, 54, 56; 60, 62, 64 (including central frequency in BW 40MHz)
931 // 1.1 Fill up channel
932 choffset = 14;
933 for (i = 0; i < 4; i++)
934 {
935 pAd->TxPower[3 * i + choffset + 0].Channel = 36 + i * 8 + 0;
936 pAd->TxPower[3 * i + choffset + 0].Power = DEFAULT_RF_TX_POWER;
937 pAd->TxPower[3 * i + choffset + 0].Power2 = DEFAULT_RF_TX_POWER;
938
939 pAd->TxPower[3 * i + choffset + 1].Channel = 36 + i * 8 + 2;
940 pAd->TxPower[3 * i + choffset + 1].Power = DEFAULT_RF_TX_POWER;
941 pAd->TxPower[3 * i + choffset + 1].Power2 = DEFAULT_RF_TX_POWER;
942
943 pAd->TxPower[3 * i + choffset + 2].Channel = 36 + i * 8 + 4;
944 pAd->TxPower[3 * i + choffset + 2].Power = DEFAULT_RF_TX_POWER;
945 pAd->TxPower[3 * i + choffset + 2].Power2 = DEFAULT_RF_TX_POWER;
946 }
947
948 // 1.2 Fill up power
949 for (i = 0; i < 6; i++)
950 {
951 RT28xx_EEPROM_READ16(pAd, EEPROM_A_TX_PWR_OFFSET + i * 2, Power.word);
952 RT28xx_EEPROM_READ16(pAd, EEPROM_A_TX2_PWR_OFFSET + i * 2, Power2.word);
953
954 if ((Power.field.Byte0 < 16) && (Power.field.Byte0 >= -7))
955 pAd->TxPower[i * 2 + choffset + 0].Power = Power.field.Byte0;
956
957 if ((Power.field.Byte1 < 16) && (Power.field.Byte1 >= -7))
958 pAd->TxPower[i * 2 + choffset + 1].Power = Power.field.Byte1;
959
960 if ((Power2.field.Byte0 < 16) && (Power2.field.Byte0 >= -7))
961 pAd->TxPower[i * 2 + choffset + 0].Power2 = Power2.field.Byte0;
962
963 if ((Power2.field.Byte1 < 16) && (Power2.field.Byte1 >= -7))
964 pAd->TxPower[i * 2 + choffset + 1].Power2 = Power2.field.Byte1;
965 }
966
967 // 2. HipperLAN 2 100, 102 ,104; 108, 110, 112; 116, 118, 120; 124, 126, 128; 132, 134, 136; 140 (including central frequency in BW 40MHz)
968 // 2.1 Fill up channel
969 choffset = 14 + 12;
970 for (i = 0; i < 5; i++)
971 {
972 pAd->TxPower[3 * i + choffset + 0].Channel = 100 + i * 8 + 0;
973 pAd->TxPower[3 * i + choffset + 0].Power = DEFAULT_RF_TX_POWER;
974 pAd->TxPower[3 * i + choffset + 0].Power2 = DEFAULT_RF_TX_POWER;
975
976 pAd->TxPower[3 * i + choffset + 1].Channel = 100 + i * 8 + 2;
977 pAd->TxPower[3 * i + choffset + 1].Power = DEFAULT_RF_TX_POWER;
978 pAd->TxPower[3 * i + choffset + 1].Power2 = DEFAULT_RF_TX_POWER;
979
980 pAd->TxPower[3 * i + choffset + 2].Channel = 100 + i * 8 + 4;
981 pAd->TxPower[3 * i + choffset + 2].Power = DEFAULT_RF_TX_POWER;
982 pAd->TxPower[3 * i + choffset + 2].Power2 = DEFAULT_RF_TX_POWER;
983 }
984 pAd->TxPower[3 * 5 + choffset + 0].Channel = 140;
985 pAd->TxPower[3 * 5 + choffset + 0].Power = DEFAULT_RF_TX_POWER;
986 pAd->TxPower[3 * 5 + choffset + 0].Power2 = DEFAULT_RF_TX_POWER;
987
988 // 2.2 Fill up power
989 for (i = 0; i < 8; i++)
990 {
991 RT28xx_EEPROM_READ16(pAd, EEPROM_A_TX_PWR_OFFSET + (choffset - 14) + i * 2, Power.word);
992 RT28xx_EEPROM_READ16(pAd, EEPROM_A_TX2_PWR_OFFSET + (choffset - 14) + i * 2, Power2.word);
993
994 if ((Power.field.Byte0 < 16) && (Power.field.Byte0 >= -7))
995 pAd->TxPower[i * 2 + choffset + 0].Power = Power.field.Byte0;
996
997 if ((Power.field.Byte1 < 16) && (Power.field.Byte1 >= -7))
998 pAd->TxPower[i * 2 + choffset + 1].Power = Power.field.Byte1;
999
1000 if ((Power2.field.Byte0 < 16) && (Power2.field.Byte0 >= -7))
1001 pAd->TxPower[i * 2 + choffset + 0].Power2 = Power2.field.Byte0;
1002
1003 if ((Power2.field.Byte1 < 16) && (Power2.field.Byte1 >= -7))
1004 pAd->TxPower[i * 2 + choffset + 1].Power2 = Power2.field.Byte1;
1005 }
1006
1007 // 3. U-NII upper band: 149, 151, 153; 157, 159, 161; 165 (including central frequency in BW 40MHz)
1008 // 3.1 Fill up channel
1009 choffset = 14 + 12 + 16;
1010 for (i = 0; i < 2; i++)
1011 {
1012 pAd->TxPower[3 * i + choffset + 0].Channel = 149 + i * 8 + 0;
1013 pAd->TxPower[3 * i + choffset + 0].Power = DEFAULT_RF_TX_POWER;
1014 pAd->TxPower[3 * i + choffset + 0].Power2 = DEFAULT_RF_TX_POWER;
1015
1016 pAd->TxPower[3 * i + choffset + 1].Channel = 149 + i * 8 + 2;
1017 pAd->TxPower[3 * i + choffset + 1].Power = DEFAULT_RF_TX_POWER;
1018 pAd->TxPower[3 * i + choffset + 1].Power2 = DEFAULT_RF_TX_POWER;
1019
1020 pAd->TxPower[3 * i + choffset + 2].Channel = 149 + i * 8 + 4;
1021 pAd->TxPower[3 * i + choffset + 2].Power = DEFAULT_RF_TX_POWER;
1022 pAd->TxPower[3 * i + choffset + 2].Power2 = DEFAULT_RF_TX_POWER;
1023 }
1024 pAd->TxPower[3 * 2 + choffset + 0].Channel = 165;
1025 pAd->TxPower[3 * 2 + choffset + 0].Power = DEFAULT_RF_TX_POWER;
1026 pAd->TxPower[3 * 2 + choffset + 0].Power2 = DEFAULT_RF_TX_POWER;
1027
1028 // 3.2 Fill up power
1029 for (i = 0; i < 4; i++)
1030 {
1031 RT28xx_EEPROM_READ16(pAd, EEPROM_A_TX_PWR_OFFSET + (choffset - 14) + i * 2, Power.word);
1032 RT28xx_EEPROM_READ16(pAd, EEPROM_A_TX2_PWR_OFFSET + (choffset - 14) + i * 2, Power2.word);
1033
1034 if ((Power.field.Byte0 < 16) && (Power.field.Byte0 >= -7))
1035 pAd->TxPower[i * 2 + choffset + 0].Power = Power.field.Byte0;
1036
1037 if ((Power.field.Byte1 < 16) && (Power.field.Byte1 >= -7))
1038 pAd->TxPower[i * 2 + choffset + 1].Power = Power.field.Byte1;
1039
1040 if ((Power2.field.Byte0 < 16) && (Power2.field.Byte0 >= -7))
1041 pAd->TxPower[i * 2 + choffset + 0].Power2 = Power2.field.Byte0;
1042
1043 if ((Power2.field.Byte1 < 16) && (Power2.field.Byte1 >= -7))
1044 pAd->TxPower[i * 2 + choffset + 1].Power2 = Power2.field.Byte1;
1045 }
1046
1047 // 4. Print and Debug
1048 choffset = 14 + 12 + 16 + 7;
1049 }
1050
1051 /*
1052 ========================================================================
1053
1054 Routine Description:
1055 Read the following from the registry
1056 1. All the parameters
1057 2. NetworkAddres
1058
1059 Arguments:
1060 Adapter Pointer to our adapter
1061 WrapperConfigurationContext For use by NdisOpenConfiguration
1062
1063 Return Value:
1064 NDIS_STATUS_SUCCESS
1065 NDIS_STATUS_FAILURE
1066 NDIS_STATUS_RESOURCES
1067
1068 IRQL = PASSIVE_LEVEL
1069
1070 Note:
1071
1072 ========================================================================
1073 */
1074 NDIS_STATUS NICReadRegParameters(
1075 IN PRTMP_ADAPTER pAd,
1076 IN NDIS_HANDLE WrapperConfigurationContext
1077 )
1078 {
1079 NDIS_STATUS Status = NDIS_STATUS_SUCCESS;
1080 DBGPRINT_S(Status, ("<-- NICReadRegParameters, Status=%x\n", Status));
1081 return Status;
1082 }
1083
1084
1085 #ifdef RT2870
1086 /*
1087 ========================================================================
1088
1089 Routine Description:
1090 For RF filter calibration purpose
1091
1092 Arguments:
1093 pAd Pointer to our adapter
1094
1095 Return Value:
1096 None
1097
1098 IRQL = PASSIVE_LEVEL
1099
1100 ========================================================================
1101 */
1102 VOID RTMPFilterCalibration(
1103 IN PRTMP_ADAPTER pAd)
1104 {
1105 UCHAR R55x = 0, value, FilterTarget = 0x1E, BBPValue=0;
1106 UINT loop = 0, count = 0, loopcnt = 0, ReTry = 0;
1107 UCHAR RF_R24_Value = 0;
1108
1109 // Give bbp filter initial value
1110 #ifndef RT30xx
1111 pAd->Mlme.CaliBW20RfR24 = 0x16;
1112 pAd->Mlme.CaliBW40RfR24 = 0x36; //Bit[5] must be 1 for BW 40
1113 #else
1114 pAd->Mlme.CaliBW20RfR24 = 0x1F;
1115 pAd->Mlme.CaliBW40RfR24 = 0x2F; //Bit[5] must be 1 for BW 40
1116 #endif
1117 do
1118 {
1119 if (loop == 1) //BandWidth = 40 MHz
1120 {
1121 // Write 0x27 to RF_R24 to program filter
1122 RF_R24_Value = 0x27;
1123 RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
1124 if (IS_RT3090(pAd))
1125 FilterTarget = 0x15;
1126 else
1127 FilterTarget = 0x19;
1128
1129 // when calibrate BW40, BBP mask must set to BW40.
1130 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
1131 BBPValue&= (~0x18);
1132 BBPValue|= (0x10);
1133 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);
1134 #ifdef RT30xx
1135 // set to BW40
1136 RT30xxReadRFRegister(pAd, RF_R31, &value);
1137 value |= 0x20;
1138 RT30xxWriteRFRegister(pAd, RF_R31, value);
1139 #endif
1140 }
1141 else //BandWidth = 20 MHz
1142 {
1143 // Write 0x07 to RF_R24 to program filter
1144 RF_R24_Value = 0x07;
1145 RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
1146 if (IS_RT3090(pAd))
1147 FilterTarget = 0x13;
1148 else
1149 FilterTarget = 0x16;
1150 #ifdef RT30xx
1151 // set to BW20
1152 RT30xxReadRFRegister(pAd, RF_R31, &value);
1153 value &= (~0x20);
1154 RT30xxWriteRFRegister(pAd, RF_R31, value);
1155 #endif
1156 }
1157
1158 // Write 0x01 to RF_R22 to enable baseband loopback mode
1159 RT30xxReadRFRegister(pAd, RF_R22, &value);
1160 value |= 0x01;
1161 RT30xxWriteRFRegister(pAd, RF_R22, value);
1162
1163 // Write 0x00 to BBP_R24 to set power & frequency of passband test tone
1164 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0);
1165
1166 do
1167 {
1168 // Write 0x90 to BBP_R25 to transmit test tone
1169 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, 0x90);
1170
1171 RTMPusecDelay(1000);
1172 // Read BBP_R55[6:0] for received power, set R55x = BBP_R55[6:0]
1173 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R55, &value);
1174 R55x = value & 0xFF;
1175
1176 } while ((ReTry++ < 100) && (R55x == 0));
1177
1178 // Write 0x06 to BBP_R24 to set power & frequency of stopband test tone
1179 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0x06);
1180
1181 while(TRUE)
1182 {
1183 // Write 0x90 to BBP_R25 to transmit test tone
1184 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, 0x90);
1185
1186 //We need to wait for calibration
1187 RTMPusecDelay(1000);
1188 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R55, &value);
1189 value &= 0xFF;
1190 if ((R55x - value) < FilterTarget)
1191 {
1192 RF_R24_Value ++;
1193 }
1194 else if ((R55x - value) == FilterTarget)
1195 {
1196 RF_R24_Value ++;
1197 count ++;
1198 }
1199 else
1200 {
1201 break;
1202 }
1203
1204 // prevent infinite loop cause driver hang.
1205 if (loopcnt++ > 100)
1206 {
1207 DBGPRINT(RT_DEBUG_ERROR, ("RTMPFilterCalibration - can't find a valid value, loopcnt=%d stop calibrating", loopcnt));
1208 break;
1209 }
1210
1211 // Write RF_R24 to program filter
1212 RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
1213 }
1214
1215 if (count > 0)
1216 {
1217 RF_R24_Value = RF_R24_Value - ((count) ? (1) : (0));
1218 }
1219
1220 // Store for future usage
1221 if (loopcnt < 100)
1222 {
1223 if (loop++ == 0)
1224 {
1225 //BandWidth = 20 MHz
1226 pAd->Mlme.CaliBW20RfR24 = (UCHAR)RF_R24_Value;
1227 }
1228 else
1229 {
1230 //BandWidth = 40 MHz
1231 pAd->Mlme.CaliBW40RfR24 = (UCHAR)RF_R24_Value;
1232 break;
1233 }
1234 }
1235 else
1236 break;
1237
1238 RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
1239
1240 // reset count
1241 count = 0;
1242 } while(TRUE);
1243
1244 //
1245 // Set back to initial state
1246 //
1247 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0);
1248
1249 RT30xxReadRFRegister(pAd, RF_R22, &value);
1250 value &= ~(0x01);
1251 RT30xxWriteRFRegister(pAd, RF_R22, value);
1252
1253 // set BBP back to BW20
1254 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
1255 BBPValue&= (~0x18);
1256 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);
1257
1258 DBGPRINT(RT_DEBUG_TRACE, ("RTMPFilterCalibration - CaliBW20RfR24=0x%x, CaliBW40RfR24=0x%x\n", pAd->Mlme.CaliBW20RfR24, pAd->Mlme.CaliBW40RfR24));
1259 }
1260
1261 VOID NICInitRT30xxRFRegisters(IN PRTMP_ADAPTER pAd)
1262 {
1263 INT i;
1264 // Driver must read EEPROM to get RfIcType before initial RF registers
1265 // Initialize RF register to default value
1266 if (IS_RT3070(pAd)
1267 #ifdef RT30xx
1268 || IS_RT3071(pAd)
1269 #else
1270 && (pAd->RfIcType == RFIC_3020 || pAd->RfIcType == RFIC_2020)
1271 #endif
1272 )
1273 {
1274 // Init RF calibration
1275 // Driver should toggle RF R30 bit7 before init RF registers
1276 UINT32 RfReg = 0;
1277 #ifdef RT30xx
1278 UINT32 data;
1279 #endif
1280 RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg);
1281 RfReg |= 0x80;
1282 RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
1283 RTMPusecDelay(1000);
1284 RfReg &= 0x7F;
1285 RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg);
1286
1287 // Initialize RF register to default value
1288 for (i = 0; i < NUM_RF_REG_PARMS; i++)
1289 {
1290 RT30xxWriteRFRegister(pAd, RT30xx_RFRegTable[i].Register, RT30xx_RFRegTable[i].Value);
1291 }
1292
1293 #ifdef RT30xx
1294 if (IS_RT3070(pAd))
1295 {
1296 // Update MAC 0x05D4 from 01xxxxxx to 0Dxxxxxx (voltage 1.2V to 1.35V) for RT3070 to improve yield rate
1297 RTUSBReadMACRegister(pAd, LDO_CFG0, &data);
1298 data = ((data & 0xF0FFFFFF) | 0x0D000000);
1299 RTUSBWriteMACRegister(pAd, LDO_CFG0, data);
1300 }
1301 else if (IS_RT3071(pAd))
1302 {
1303 // Driver should set RF R6 bit6 on before init RF registers
1304 RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RfReg);
1305 RfReg |= 0x40;
1306 RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RfReg);
1307
1308 // init R31
1309 RT30xxWriteRFRegister(pAd, RF_R31, 0x14);
1310
1311 // RT3071 version E has fixed this issue
1312 if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211))
1313 {
1314 // patch tx EVM issue temporarily
1315 RTUSBReadMACRegister(pAd, LDO_CFG0, &data);
1316 data = ((data & 0xE0FFFFFF) | 0x0D000000);
1317 RTUSBWriteMACRegister(pAd, LDO_CFG0, data);
1318 }
1319 else
1320 {
1321 RTMP_IO_READ32(pAd, LDO_CFG0, &data);
1322 data = ((data & 0xE0FFFFFF) | 0x01000000);
1323 RTMP_IO_WRITE32(pAd, LDO_CFG0, data);
1324 }
1325
1326 // patch LNA_PE_G1 failed issue
1327 RTUSBReadMACRegister(pAd, GPIO_SWITCH, &data);
1328 data &= ~(0x20);
1329 RTUSBWriteMACRegister(pAd, GPIO_SWITCH, data);
1330 }
1331 #endif
1332 //For RF filter Calibration
1333 RTMPFilterCalibration(pAd);
1334 #ifdef RT30xx
1335 // Initialize RF R27 register, set RF R27 must be behind RTMPFilterCalibration()
1336 if ((pAd->MACVersion & 0xffff) < 0x0211)
1337 RT30xxWriteRFRegister(pAd, RF_R27, 0x3);
1338
1339 // set led open drain enable
1340 RTUSBReadMACRegister(pAd, OPT_14, &data);
1341 data |= 0x01;
1342 RTUSBWriteMACRegister(pAd, OPT_14, data);
1343
1344 if (IS_RT3071(pAd))
1345 {
1346 // add by johnli, RF power sequence setup, load RF normal operation-mode setup
1347 RT30xxLoadRFNormalModeSetup(pAd);
1348 }
1349 #endif
1350 }
1351 }
1352 #endif // RT2870 //
1353
1354
1355 /*
1356 ========================================================================
1357
1358 Routine Description:
1359 Read initial parameters from EEPROM
1360
1361 Arguments:
1362 Adapter Pointer to our adapter
1363
1364 Return Value:
1365 None
1366
1367 IRQL = PASSIVE_LEVEL
1368
1369 Note:
1370
1371 ========================================================================
1372 */
1373 VOID NICReadEEPROMParameters(
1374 IN PRTMP_ADAPTER pAd,
1375 IN PUCHAR mac_addr)
1376 {
1377 UINT32 data = 0;
1378 USHORT i, value, value2;
1379 UCHAR TmpPhy;
1380 EEPROM_TX_PWR_STRUC Power;
1381 EEPROM_VERSION_STRUC Version;
1382 EEPROM_ANTENNA_STRUC Antenna;
1383 EEPROM_NIC_CONFIG2_STRUC NicConfig2;
1384
1385 DBGPRINT(RT_DEBUG_TRACE, ("--> NICReadEEPROMParameters\n"));
1386
1387 // Init EEPROM Address Number, before access EEPROM; if 93c46, EEPROMAddressNum=6, else if 93c66, EEPROMAddressNum=8
1388 RTMP_IO_READ32(pAd, E2PROM_CSR, &data);
1389 DBGPRINT(RT_DEBUG_TRACE, ("--> E2PROM_CSR = 0x%x\n", data));
1390
1391 if((data & 0x30) == 0)
1392 pAd->EEPROMAddressNum = 6; // 93C46
1393 else if((data & 0x30) == 0x10)
1394 pAd->EEPROMAddressNum = 8; // 93C66
1395 else
1396 pAd->EEPROMAddressNum = 8; // 93C86
1397 DBGPRINT(RT_DEBUG_TRACE, ("--> EEPROMAddressNum = %d\n", pAd->EEPROMAddressNum ));
1398
1399 // RT2860 MAC no longer auto load MAC address from E2PROM. Driver has to intialize
1400 // MAC address registers according to E2PROM setting
1401 if (mac_addr == NULL ||
1402 strlen(mac_addr) != 17 ||
1403 mac_addr[2] != ':' || mac_addr[5] != ':' || mac_addr[8] != ':' ||
1404 mac_addr[11] != ':' || mac_addr[14] != ':')
1405 {
1406 USHORT Addr01,Addr23,Addr45 ;
1407
1408 RT28xx_EEPROM_READ16(pAd, 0x04, Addr01);
1409 RT28xx_EEPROM_READ16(pAd, 0x06, Addr23);
1410 RT28xx_EEPROM_READ16(pAd, 0x08, Addr45);
1411
1412 pAd->PermanentAddress[0] = (UCHAR)(Addr01 & 0xff);
1413 pAd->PermanentAddress[1] = (UCHAR)(Addr01 >> 8);
1414 pAd->PermanentAddress[2] = (UCHAR)(Addr23 & 0xff);
1415 pAd->PermanentAddress[3] = (UCHAR)(Addr23 >> 8);
1416 pAd->PermanentAddress[4] = (UCHAR)(Addr45 & 0xff);
1417 pAd->PermanentAddress[5] = (UCHAR)(Addr45 >> 8);
1418
1419 DBGPRINT(RT_DEBUG_TRACE, ("Initialize MAC Address from E2PROM \n"));
1420 }
1421 else
1422 {
1423 INT j;
1424 PUCHAR macptr;
1425
1426 macptr = mac_addr;
1427
1428 for (j=0; j<MAC_ADDR_LEN; j++)
1429 {
1430 AtoH(macptr, &pAd->PermanentAddress[j], 1);
1431 macptr=macptr+3;
1432 }
1433
1434 DBGPRINT(RT_DEBUG_TRACE, ("Initialize MAC Address from module parameter \n"));
1435 }
1436
1437
1438 {
1439 //more conveninet to test mbssid, so ap's bssid &0xf1
1440 if (pAd->PermanentAddress[0] == 0xff)
1441 pAd->PermanentAddress[0] = RandomByte(pAd)&0xf8;
1442
1443 //if (pAd->PermanentAddress[5] == 0xff)
1444 // pAd->PermanentAddress[5] = RandomByte(pAd)&0xf8;
1445
1446 DBGPRINT_RAW(RT_DEBUG_TRACE,("E2PROM MAC: =%02x:%02x:%02x:%02x:%02x:%02x\n",
1447 pAd->PermanentAddress[0], pAd->PermanentAddress[1],
1448 pAd->PermanentAddress[2], pAd->PermanentAddress[3],
1449 pAd->PermanentAddress[4], pAd->PermanentAddress[5]));
1450 if (pAd->bLocalAdminMAC == FALSE)
1451 {
1452 MAC_DW0_STRUC csr2;
1453 MAC_DW1_STRUC csr3;
1454 COPY_MAC_ADDR(pAd->CurrentAddress, pAd->PermanentAddress);
1455 csr2.field.Byte0 = pAd->CurrentAddress[0];
1456 csr2.field.Byte1 = pAd->CurrentAddress[1];
1457 csr2.field.Byte2 = pAd->CurrentAddress[2];
1458 csr2.field.Byte3 = pAd->CurrentAddress[3];
1459 RTMP_IO_WRITE32(pAd, MAC_ADDR_DW0, csr2.word);
1460 csr3.word = 0;
1461 csr3.field.Byte4 = pAd->CurrentAddress[4];
1462 csr3.field.Byte5 = pAd->CurrentAddress[5];
1463 csr3.field.U2MeMask = 0xff;
1464 RTMP_IO_WRITE32(pAd, MAC_ADDR_DW1, csr3.word);
1465 DBGPRINT_RAW(RT_DEBUG_TRACE,("E2PROM MAC: =%02x:%02x:%02x:%02x:%02x:%02x\n",
1466 pAd->PermanentAddress[0], pAd->PermanentAddress[1],
1467 pAd->PermanentAddress[2], pAd->PermanentAddress[3],
1468 pAd->PermanentAddress[4], pAd->PermanentAddress[5]));
1469 }
1470 }
1471
1472 // if not return early. cause fail at emulation.
1473 // Init the channel number for TX channel power
1474 RTMPReadChannelPwr(pAd);
1475
1476 // if E2PROM version mismatch with driver's expectation, then skip
1477 // all subsequent E2RPOM retieval and set a system error bit to notify GUI
1478 RT28xx_EEPROM_READ16(pAd, EEPROM_VERSION_OFFSET, Version.word);
1479 pAd->EepromVersion = Version.field.Version + Version.field.FaeReleaseNumber * 256;
1480 DBGPRINT(RT_DEBUG_TRACE, ("E2PROM: Version = %d, FAE release #%d\n", Version.field.Version, Version.field.FaeReleaseNumber));
1481
1482 if (Version.field.Version > VALID_EEPROM_VERSION)
1483 {
1484 DBGPRINT_ERR(("E2PROM: WRONG VERSION 0x%x, should be %d\n",Version.field.Version, VALID_EEPROM_VERSION));
1485 /*pAd->SystemErrorBitmap |= 0x00000001;
1486
1487 // hard-code default value when no proper E2PROM installed
1488 pAd->bAutoTxAgcA = FALSE;
1489 pAd->bAutoTxAgcG = FALSE;
1490
1491 // Default the channel power
1492 for (i = 0; i < MAX_NUM_OF_CHANNELS; i++)
1493 pAd->TxPower[i].Power = DEFAULT_RF_TX_POWER;
1494
1495 // Default the channel power
1496 for (i = 0; i < MAX_NUM_OF_11JCHANNELS; i++)
1497 pAd->TxPower11J[i].Power = DEFAULT_RF_TX_POWER;
1498
1499 for(i = 0; i < NUM_EEPROM_BBP_PARMS; i++)
1500 pAd->EEPROMDefaultValue[i] = 0xffff;
1501 return; */
1502 }
1503
1504 // Read BBP default value from EEPROM and store to array(EEPROMDefaultValue) in pAd
1505 RT28xx_EEPROM_READ16(pAd, EEPROM_NIC1_OFFSET, value);
1506 pAd->EEPROMDefaultValue[0] = value;
1507
1508 RT28xx_EEPROM_READ16(pAd, EEPROM_NIC2_OFFSET, value);
1509 pAd->EEPROMDefaultValue[1] = value;
1510
1511 RT28xx_EEPROM_READ16(pAd, 0x38, value); // Country Region
1512 pAd->EEPROMDefaultValue[2] = value;
1513
1514 for(i = 0; i < 8; i++)
1515 {
1516 RT28xx_EEPROM_READ16(pAd, EEPROM_BBP_BASE_OFFSET + i*2, value);
1517 pAd->EEPROMDefaultValue[i+3] = value;
1518 }
1519
1520 // We have to parse NIC configuration 0 at here.
1521 // If TSSI did not have preloaded value, it should reset the TxAutoAgc to false
1522 // Therefore, we have to read TxAutoAgc control beforehand.
1523 // Read Tx AGC control bit
1524 Antenna.word = pAd->EEPROMDefaultValue[0];
1525 if (Antenna.word == 0xFFFF)
1526 {
1527 if(IS_RT3090(pAd))
1528 {
1529 Antenna.word = 0;
1530 Antenna.field.RfIcType = RFIC_3020;
1531 Antenna.field.TxPath = 1;
1532 Antenna.field.RxPath = 1;
1533 }
1534 else
1535 {
1536 Antenna.word = 0;
1537 Antenna.field.RfIcType = RFIC_2820;
1538 Antenna.field.TxPath = 1;
1539 Antenna.field.RxPath = 2;
1540 DBGPRINT(RT_DEBUG_WARN, ("E2PROM error, hard code as 0x%04x\n", Antenna.word));
1541 }
1542 }
1543
1544 // Choose the desired Tx&Rx stream.
1545 if ((pAd->CommonCfg.TxStream == 0) || (pAd->CommonCfg.TxStream > Antenna.field.TxPath))
1546 pAd->CommonCfg.TxStream = Antenna.field.TxPath;
1547
1548 if ((pAd->CommonCfg.RxStream == 0) || (pAd->CommonCfg.RxStream > Antenna.field.RxPath))
1549 {
1550 pAd->CommonCfg.RxStream = Antenna.field.RxPath;
1551
1552 if ((pAd->MACVersion < RALINK_2883_VERSION) &&
1553 (pAd->CommonCfg.RxStream > 2))
1554 {
1555 // only 2 Rx streams for RT2860 series
1556 pAd->CommonCfg.RxStream = 2;
1557 }
1558 }
1559
1560 // 3*3
1561 // read value from EEPROM and set them to CSR174 ~ 177 in chain0 ~ chain2
1562 // yet implement
1563 for(i=0; i<3; i++)
1564 {
1565 }
1566
1567 NicConfig2.word = pAd->EEPROMDefaultValue[1];
1568
1569 {
1570 #ifndef RT30xx
1571 NicConfig2.word = 0;
1572 #endif
1573 if ((NicConfig2.word & 0x00ff) == 0xff)
1574 {
1575 NicConfig2.word &= 0xff00;
1576 }
1577
1578 if ((NicConfig2.word >> 8) == 0xff)
1579 {
1580 NicConfig2.word &= 0x00ff;
1581 }
1582 }
1583
1584 if (NicConfig2.field.DynamicTxAgcControl == 1)
1585 pAd->bAutoTxAgcA = pAd->bAutoTxAgcG = TRUE;
1586 else
1587 pAd->bAutoTxAgcA = pAd->bAutoTxAgcG = FALSE;
1588
1589 DBGPRINT_RAW(RT_DEBUG_TRACE, ("NICReadEEPROMParameters: RxPath = %d, TxPath = %d\n", Antenna.field.RxPath, Antenna.field.TxPath));
1590
1591 // Save the antenna for future use
1592 pAd->Antenna.word = Antenna.word;
1593
1594 //
1595 // Reset PhyMode if we don't support 802.11a
1596 // Only RFIC_2850 & RFIC_2750 support 802.11a
1597 //
1598 if ((Antenna.field.RfIcType != RFIC_2850) && (Antenna.field.RfIcType != RFIC_2750))
1599 {
1600 if ((pAd->CommonCfg.PhyMode == PHY_11ABG_MIXED) ||
1601 (pAd->CommonCfg.PhyMode == PHY_11A))
1602 pAd->CommonCfg.PhyMode = PHY_11BG_MIXED;
1603 else if ((pAd->CommonCfg.PhyMode == PHY_11ABGN_MIXED) ||
1604 (pAd->CommonCfg.PhyMode == PHY_11AN_MIXED) ||
1605 (pAd->CommonCfg.PhyMode == PHY_11AGN_MIXED) ||
1606 (pAd->CommonCfg.PhyMode == PHY_11N_5G))
1607 pAd->CommonCfg.PhyMode = PHY_11BGN_MIXED;
1608 }
1609
1610 // Read TSSI reference and TSSI boundary for temperature compensation. This is ugly
1611 // 0. 11b/g
1612 {
1613 /* these are tempature reference value (0x00 ~ 0xFE)
1614 ex: 0x00 0x15 0x25 0x45 0x88 0xA0 0xB5 0xD0 0xF0
1615 TssiPlusBoundaryG [4] [3] [2] [1] [0] (smaller) +
1616 TssiMinusBoundaryG[0] [1] [2] [3] [4] (larger) */
1617 RT28xx_EEPROM_READ16(pAd, 0x6E, Power.word);
1618 pAd->TssiMinusBoundaryG[4] = Power.field.Byte0;
1619 pAd->TssiMinusBoundaryG[3] = Power.field.Byte1;
1620 RT28xx_EEPROM_READ16(pAd, 0x70, Power.word);
1621 pAd->TssiMinusBoundaryG[2] = Power.field.Byte0;
1622 pAd->TssiMinusBoundaryG[1] = Power.field.Byte1;
1623 RT28xx_EEPROM_READ16(pAd, 0x72, Power.word);
1624 pAd->TssiRefG = Power.field.Byte0; /* reference value [0] */
1625 pAd->TssiPlusBoundaryG[1] = Power.field.Byte1;
1626 RT28xx_EEPROM_READ16(pAd, 0x74, Power.word);
1627 pAd->TssiPlusBoundaryG[2] = Power.field.Byte0;
1628 pAd->TssiPlusBoundaryG[3] = Power.field.Byte1;
1629 RT28xx_EEPROM_READ16(pAd, 0x76, Power.word);
1630 pAd->TssiPlusBoundaryG[4] = Power.field.Byte0;
1631 pAd->TxAgcStepG = Power.field.Byte1;
1632 pAd->TxAgcCompensateG = 0;
1633 pAd->TssiMinusBoundaryG[0] = pAd->TssiRefG;
1634 pAd->TssiPlusBoundaryG[0] = pAd->TssiRefG;
1635
1636 // Disable TxAgc if the based value is not right
1637 if (pAd->TssiRefG == 0xff)
1638 pAd->bAutoTxAgcG = FALSE;
1639
1640 DBGPRINT(RT_DEBUG_TRACE,("E2PROM: G Tssi[-4 .. +4] = %d %d %d %d - %d -%d %d %d %d, step=%d, tuning=%d\n",
1641 pAd->TssiMinusBoundaryG[4], pAd->TssiMinusBoundaryG[3], pAd->TssiMinusBoundaryG[2], pAd->TssiMinusBoundaryG[1],
1642 pAd->TssiRefG,
1643 pAd->TssiPlusBoundaryG[1], pAd->TssiPlusBoundaryG[2], pAd->TssiPlusBoundaryG[3], pAd->TssiPlusBoundaryG[4],
1644 pAd->TxAgcStepG, pAd->bAutoTxAgcG));
1645 }
1646 // 1. 11a
1647 {
1648 RT28xx_EEPROM_READ16(pAd, 0xD4, Power.word);
1649 pAd->TssiMinusBoundaryA[4] = Power.field.Byte0;
1650 pAd->TssiMinusBoundaryA[3] = Power.field.Byte1;
1651 RT28xx_EEPROM_READ16(pAd, 0xD6, Power.word);
1652 pAd->TssiMinusBoundaryA[2] = Power.field.Byte0;
1653 pAd->TssiMinusBoundaryA[1] = Power.field.Byte1;
1654 RT28xx_EEPROM_READ16(pAd, 0xD8, Power.word);
1655 pAd->TssiRefA = Power.field.Byte0;
1656 pAd->TssiPlusBoundaryA[1] = Power.field.Byte1;
1657 RT28xx_EEPROM_READ16(pAd, 0xDA, Power.word);
1658 pAd->TssiPlusBoundaryA[2] = Power.field.Byte0;
1659 pAd->TssiPlusBoundaryA[3] = Power.field.Byte1;
1660 RT28xx_EEPROM_READ16(pAd, 0xDC, Power.word);
1661 pAd->TssiPlusBoundaryA[4] = Power.field.Byte0;
1662 pAd->TxAgcStepA = Power.field.Byte1;
1663 pAd->TxAgcCompensateA = 0;
1664 pAd->TssiMinusBoundaryA[0] = pAd->TssiRefA;
1665 pAd->TssiPlusBoundaryA[0] = pAd->TssiRefA;
1666
1667 // Disable TxAgc if the based value is not right
1668 if (pAd->TssiRefA == 0xff)
1669 pAd->bAutoTxAgcA = FALSE;
1670
1671 DBGPRINT(RT_DEBUG_TRACE,("E2PROM: A Tssi[-4 .. +4] = %d %d %d %d - %d -%d %d %d %d, step=%d, tuning=%d\n",
1672 pAd->TssiMinusBoundaryA[4], pAd->TssiMinusBoundaryA[3], pAd->TssiMinusBoundaryA[2], pAd->TssiMinusBoundaryA[1],
1673 pAd->TssiRefA,
1674 pAd->TssiPlusBoundaryA[1], pAd->TssiPlusBoundaryA[2], pAd->TssiPlusBoundaryA[3], pAd->TssiPlusBoundaryA[4],
1675 pAd->TxAgcStepA, pAd->bAutoTxAgcA));
1676 }
1677 pAd->BbpRssiToDbmDelta = 0x0;
1678
1679 // Read frequency offset setting for RF
1680 RT28xx_EEPROM_READ16(pAd, EEPROM_FREQ_OFFSET, value);
1681 if ((value & 0x00FF) != 0x00FF)
1682 pAd->RfFreqOffset = (ULONG) (value & 0x00FF);
1683 else
1684 pAd->RfFreqOffset = 0;
1685 DBGPRINT(RT_DEBUG_TRACE, ("E2PROM: RF FreqOffset=0x%lx \n", pAd->RfFreqOffset));
1686
1687 //CountryRegion byte offset (38h)
1688 value = pAd->EEPROMDefaultValue[2] >> 8; // 2.4G band
1689 value2 = pAd->EEPROMDefaultValue[2] & 0x00FF; // 5G band
1690
1691 if ((value <= REGION_MAXIMUM_BG_BAND) && (value2 <= REGION_MAXIMUM_A_BAND))
1692 {
1693 pAd->CommonCfg.CountryRegion = ((UCHAR) value) | 0x80;
1694 pAd->CommonCfg.CountryRegionForABand = ((UCHAR) value2) | 0x80;
1695 TmpPhy = pAd->CommonCfg.PhyMode;
1696 pAd->CommonCfg.PhyMode = 0xff;
1697 RTMPSetPhyMode(pAd, TmpPhy);
1698 SetCommonHT(pAd);
1699 }
1700
1701 //
1702 // Get RSSI Offset on EEPROM 0x9Ah & 0x9Ch.
1703 // The valid value are (-10 ~ 10)
1704 //
1705 RT28xx_EEPROM_READ16(pAd, EEPROM_RSSI_BG_OFFSET, value);
1706 pAd->BGRssiOffset0 = value & 0x00ff;
1707 pAd->BGRssiOffset1 = (value >> 8);
1708 RT28xx_EEPROM_READ16(pAd, EEPROM_RSSI_BG_OFFSET+2, value);
1709 pAd->BGRssiOffset2 = value & 0x00ff;
1710 pAd->ALNAGain1 = (value >> 8);
1711 RT28xx_EEPROM_READ16(pAd, EEPROM_LNA_OFFSET, value);
1712 pAd->BLNAGain = value & 0x00ff;
1713 pAd->ALNAGain0 = (value >> 8);
1714
1715 // Validate 11b/g RSSI_0 offset.
1716 if ((pAd->BGRssiOffset0 < -10) || (pAd->BGRssiOffset0 > 10))
1717 pAd->BGRssiOffset0 = 0;
1718
1719 // Validate 11b/g RSSI_1 offset.
1720 if ((pAd->BGRssiOffset1 < -10) || (pAd->BGRssiOffset1 > 10))
1721 pAd->BGRssiOffset1 = 0;
1722
1723 // Validate 11b/g RSSI_2 offset.
1724 if ((pAd->BGRssiOffset2 < -10) || (pAd->BGRssiOffset2 > 10))
1725 pAd->BGRssiOffset2 = 0;
1726
1727 RT28xx_EEPROM_READ16(pAd, EEPROM_RSSI_A_OFFSET, value);
1728 pAd->ARssiOffset0 = value & 0x00ff;
1729 pAd->ARssiOffset1 = (value >> 8);
1730 RT28xx_EEPROM_READ16(pAd, (EEPROM_RSSI_A_OFFSET+2), value);
1731 pAd->ARssiOffset2 = value & 0x00ff;
1732 pAd->ALNAGain2 = (value >> 8);
1733
1734 if (((UCHAR)pAd->ALNAGain1 == 0xFF) || (pAd->ALNAGain1 == 0x00))
1735 pAd->ALNAGain1 = pAd->ALNAGain0;
1736 if (((UCHAR)pAd->ALNAGain2 == 0xFF) || (pAd->ALNAGain2 == 0x00))
1737 pAd->ALNAGain2 = pAd->ALNAGain0;
1738
1739 // Validate 11a RSSI_0 offset.
1740 if ((pAd->ARssiOffset0 < -10) || (pAd->ARssiOffset0 > 10))
1741 pAd->ARssiOffset0 = 0;
1742
1743 // Validate 11a RSSI_1 offset.
1744 if ((pAd->ARssiOffset1 < -10) || (pAd->ARssiOffset1 > 10))
1745 pAd->ARssiOffset1 = 0;
1746
1747 //Validate 11a RSSI_2 offset.
1748 if ((pAd->ARssiOffset2 < -10) || (pAd->ARssiOffset2 > 10))
1749 pAd->ARssiOffset2 = 0;
1750
1751 //
1752 // Get LED Setting.
1753 //
1754 RT28xx_EEPROM_READ16(pAd, 0x3a, value);
1755 pAd->LedCntl.word = (value&0xff00) >> 8;
1756 RT28xx_EEPROM_READ16(pAd, EEPROM_LED1_OFFSET, value);
1757 pAd->Led1 = value;
1758 RT28xx_EEPROM_READ16(pAd, EEPROM_LED2_OFFSET, value);
1759 pAd->Led2 = value;
1760 RT28xx_EEPROM_READ16(pAd, EEPROM_LED3_OFFSET, value);
1761 pAd->Led3 = value;
1762
1763 RTMPReadTxPwrPerRate(pAd);
1764
1765 DBGPRINT(RT_DEBUG_TRACE, ("<-- NICReadEEPROMParameters\n"));
1766 }
1767
1768 /*
1769 ========================================================================
1770
1771 Routine Description:
1772 Set default value from EEPROM
1773
1774 Arguments:
1775 Adapter Pointer to our adapter
1776
1777 Return Value:
1778 None
1779
1780 IRQL = PASSIVE_LEVEL
1781
1782 Note:
1783
1784 ========================================================================
1785 */
1786 VOID NICInitAsicFromEEPROM(
1787 IN PRTMP_ADAPTER pAd)
1788 {
1789 UINT32 data = 0;
1790 UCHAR BBPR1 = 0;
1791 USHORT i;
1792 EEPROM_ANTENNA_STRUC Antenna;
1793 EEPROM_NIC_CONFIG2_STRUC NicConfig2;
1794 UCHAR BBPR3 = 0;
1795
1796 DBGPRINT(RT_DEBUG_TRACE, ("--> NICInitAsicFromEEPROM\n"));
1797 for(i = 3; i < NUM_EEPROM_BBP_PARMS; i++)
1798 {
1799 UCHAR BbpRegIdx, BbpValue;
1800
1801 if ((pAd->EEPROMDefaultValue[i] != 0xFFFF) && (pAd->EEPROMDefaultValue[i] != 0))
1802 {
1803 BbpRegIdx = (UCHAR)(pAd->EEPROMDefaultValue[i] >> 8);
1804 BbpValue = (UCHAR)(pAd->EEPROMDefaultValue[i] & 0xff);
1805 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BbpRegIdx, BbpValue);
1806 }
1807 }
1808
1809 #ifndef RT30xx
1810 Antenna.word = pAd->Antenna.word;
1811 #endif
1812 #ifdef RT30xx
1813 Antenna.word = pAd->EEPROMDefaultValue[0];
1814 if (Antenna.word == 0xFFFF)
1815 {
1816 DBGPRINT(RT_DEBUG_ERROR, ("E2PROM error, hard code as 0x%04x\n", Antenna.word));
1817 BUG_ON(Antenna.word == 0xFFFF);
1818 }
1819 #endif
1820 pAd->Mlme.RealRxPath = (UCHAR) Antenna.field.RxPath;
1821 pAd->RfIcType = (UCHAR) Antenna.field.RfIcType;
1822
1823 #ifdef RT30xx
1824 DBGPRINT(RT_DEBUG_WARN, ("pAd->RfIcType = %d, RealRxPath=%d, TxPath = %d\n", pAd->RfIcType, pAd->Mlme.RealRxPath,Antenna.field.TxPath));
1825
1826 // Save the antenna for future use
1827 pAd->Antenna.word = Antenna.word;
1828 #endif
1829 NicConfig2.word = pAd->EEPROMDefaultValue[1];
1830
1831 #ifdef RT30xx
1832 {
1833 if ((NicConfig2.word & 0x00ff) == 0xff)
1834 {
1835 NicConfig2.word &= 0xff00;
1836 }
1837
1838 if ((NicConfig2.word >> 8) == 0xff)
1839 {
1840 NicConfig2.word &= 0x00ff;
1841 }
1842 }
1843 #endif
1844 // Save the antenna for future use
1845 pAd->NicConfig2.word = NicConfig2.word;
1846
1847 #ifdef RT30xx
1848 // set default antenna as main
1849 if (pAd->RfIcType == RFIC_3020)
1850 AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
1851 #endif
1852 //
1853 // Send LED Setting to MCU.
1854 //
1855 if (pAd->LedCntl.word == 0xFF)
1856 {
1857 pAd->LedCntl.word = 0x01;
1858 pAd->Led1 = 0x5555;
1859 pAd->Led2 = 0x2221;
1860 #ifdef RT2860
1861 pAd->Led3 = 0xA9F8;
1862 #endif
1863
1864 #ifdef RT2870
1865 pAd->Led3 = 0x5627;
1866 #endif // RT2870 //
1867 }
1868
1869 AsicSendCommandToMcu(pAd, 0x52, 0xff, (UCHAR)pAd->Led1, (UCHAR)(pAd->Led1 >> 8));
1870 AsicSendCommandToMcu(pAd, 0x53, 0xff, (UCHAR)pAd->Led2, (UCHAR)(pAd->Led2 >> 8));
1871 AsicSendCommandToMcu(pAd, 0x54, 0xff, (UCHAR)pAd->Led3, (UCHAR)(pAd->Led3 >> 8));
1872 pAd->LedIndicatorStregth = 0xFF;
1873 RTMPSetSignalLED(pAd, -100); // Force signal strength Led to be turned off, before link up
1874
1875 {
1876 // Read Hardware controlled Radio state enable bit
1877 if (NicConfig2.field.HardwareRadioControl == 1)
1878 {
1879 pAd->StaCfg.bHardwareRadio = TRUE;
1880
1881 // Read GPIO pin2 as Hardware controlled radio state
1882 RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &data);
1883 if ((data & 0x04) == 0)
1884 {
1885 pAd->StaCfg.bHwRadio = FALSE;
1886 pAd->StaCfg.bRadio = FALSE;
1887 RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF);
1888 }
1889 }
1890 else
1891 pAd->StaCfg.bHardwareRadio = FALSE;
1892
1893 if (pAd->StaCfg.bRadio == FALSE)
1894 {
1895 RTMPSetLED(pAd, LED_RADIO_OFF);
1896 }
1897 else
1898 {
1899 RTMPSetLED(pAd, LED_RADIO_ON);
1900 #ifdef RT2860
1901 AsicSendCommandToMcu(pAd, 0x30, 0xff, 0xff, 0x02);
1902 AsicSendCommandToMcu(pAd, 0x31, PowerWakeCID, 0x00, 0x00);
1903 // 2-1. wait command ok.
1904 AsicCheckCommanOk(pAd, PowerWakeCID);
1905 #endif
1906 }
1907 }
1908
1909 // Turn off patching for cardbus controller
1910 if (NicConfig2.field.CardbusAcceleration == 1)
1911 {
1912 }
1913
1914 if (NicConfig2.field.DynamicTxAgcControl == 1)
1915 pAd->bAutoTxAgcA = pAd->bAutoTxAgcG = TRUE;
1916 else
1917 pAd->bAutoTxAgcA = pAd->bAutoTxAgcG = FALSE;
1918
1919 /* BBP has been programmed so reset to UNKNOWN_BAND */
1920 pAd->CommonCfg.BandState = UNKNOWN_BAND;
1921
1922 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BBPR3);
1923 BBPR3 &= (~0x18);
1924 if(pAd->Antenna.field.RxPath == 3)
1925 {
1926 BBPR3 |= (0x10);
1927 }
1928 else if(pAd->Antenna.field.RxPath == 2)
1929 {
1930 BBPR3 |= (0x8);
1931 }
1932 else if(pAd->Antenna.field.RxPath == 1)
1933 {
1934 BBPR3 |= (0x0);
1935 }
1936 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BBPR3);
1937
1938 {
1939 // Handle the difference when 1T
1940 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BBPR1);
1941 if(pAd->Antenna.field.TxPath == 1)
1942 {
1943 BBPR1 &= (~0x18);
1944 }
1945 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BBPR1);
1946
1947 DBGPRINT(RT_DEBUG_TRACE, ("Use Hw Radio Control Pin=%d; if used Pin=%d;\n", pAd->CommonCfg.bHardwareRadio, pAd->CommonCfg.bHardwareRadio));
1948 }
1949
1950 DBGPRINT(RT_DEBUG_TRACE, ("TxPath = %d, RxPath = %d, RFIC=%d, Polar+LED mode=%x\n", pAd->Antenna.field.TxPath, pAd->Antenna.field.RxPath, pAd->RfIcType, pAd->LedCntl.word));
1951 DBGPRINT(RT_DEBUG_TRACE, ("<-- NICInitAsicFromEEPROM\n"));
1952 }
1953
1954 /*
1955 ========================================================================
1956
1957 Routine Description:
1958 Initialize NIC hardware
1959
1960 Arguments:
1961 Adapter Pointer to our adapter
1962
1963 Return Value:
1964 None
1965
1966 IRQL = PASSIVE_LEVEL
1967
1968 Note:
1969
1970 ========================================================================
1971 */
1972 NDIS_STATUS NICInitializeAdapter(
1973 IN PRTMP_ADAPTER pAd,
1974 IN BOOLEAN bHardReset)
1975 {
1976 NDIS_STATUS Status = NDIS_STATUS_SUCCESS;
1977 WPDMA_GLO_CFG_STRUC GloCfg;
1978 #ifdef RT2860
1979 UINT32 Value;
1980 DELAY_INT_CFG_STRUC IntCfg;
1981 #endif
1982 ULONG i =0, j=0;
1983 AC_TXOP_CSR0_STRUC csr0;
1984
1985 DBGPRINT(RT_DEBUG_TRACE, ("--> NICInitializeAdapter\n"));
1986
1987 // 3. Set DMA global configuration except TX_DMA_EN and RX_DMA_EN bits:
1988 retry:
1989 i = 0;
1990 do
1991 {
1992 RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word);
1993 if ((GloCfg.field.TxDMABusy == 0) && (GloCfg.field.RxDMABusy == 0))
1994 break;
1995
1996 RTMPusecDelay(1000);
1997 i++;
1998 }while ( i<100);
1999 DBGPRINT(RT_DEBUG_TRACE, ("<== DMA offset 0x208 = 0x%x\n", GloCfg.word));
2000 GloCfg.word &= 0xff0;
2001 GloCfg.field.EnTXWriteBackDDONE =1;
2002 RTMP_IO_WRITE32(pAd, WPDMA_GLO_CFG, GloCfg.word);
2003
2004 // Record HW Beacon offset
2005 pAd->BeaconOffset[0] = HW_BEACON_BASE0;
2006 pAd->BeaconOffset[1] = HW_BEACON_BASE1;
2007 pAd->BeaconOffset[2] = HW_BEACON_BASE2;
2008 pAd->BeaconOffset[3] = HW_BEACON_BASE3;
2009 pAd->BeaconOffset[4] = HW_BEACON_BASE4;
2010 pAd->BeaconOffset[5] = HW_BEACON_BASE5;
2011 pAd->BeaconOffset[6] = HW_BEACON_BASE6;
2012 pAd->BeaconOffset[7] = HW_BEACON_BASE7;
2013
2014 //
2015 // write all shared Ring's base address into ASIC
2016 //
2017
2018 // asic simulation sequence put this ahead before loading firmware.
2019 // pbf hardware reset
2020 #ifdef RT2860
2021 RTMP_IO_WRITE32(pAd, WPDMA_RST_IDX, 0x1003f); // 0x10000 for reset rx, 0x3f resets all 6 tx rings.
2022 RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, 0xe1f);
2023 RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, 0xe00);
2024 #endif
2025
2026 // Initialze ASIC for TX & Rx operation
2027 if (NICInitializeAsic(pAd , bHardReset) != NDIS_STATUS_SUCCESS)
2028 {
2029 if (j++ == 0)
2030 {
2031 NICLoadFirmware(pAd);
2032 goto retry;
2033 }
2034 return NDIS_STATUS_FAILURE;
2035 }
2036
2037
2038 #ifdef RT2860
2039 // Write AC_BK base address register
2040 Value = RTMP_GetPhysicalAddressLow(pAd->TxRing[QID_AC_BK].Cell[0].AllocPa);
2041 RTMP_IO_WRITE32(pAd, TX_BASE_PTR1, Value);
2042 DBGPRINT(RT_DEBUG_TRACE, ("--> TX_BASE_PTR1 : 0x%x\n", Value));
2043
2044 // Write AC_BE base address register
2045 Value = RTMP_GetPhysicalAddressLow(pAd->TxRing[QID_AC_BE].Cell[0].AllocPa);
2046 RTMP_IO_WRITE32(pAd, TX_BASE_PTR0, Value);
2047 DBGPRINT(RT_DEBUG_TRACE, ("--> TX_BASE_PTR0 : 0x%x\n", Value));
2048
2049 // Write AC_VI base address register
2050 Value = RTMP_GetPhysicalAddressLow(pAd->TxRing[QID_AC_VI].Cell[0].AllocPa);
2051 RTMP_IO_WRITE32(pAd, TX_BASE_PTR2, Value);
2052 DBGPRINT(RT_DEBUG_TRACE, ("--> TX_BASE_PTR2 : 0x%x\n", Value));
2053
2054 // Write AC_VO base address register
2055 Value = RTMP_GetPhysicalAddressLow(pAd->TxRing[QID_AC_VO].Cell[0].AllocPa);
2056 RTMP_IO_WRITE32(pAd, TX_BASE_PTR3, Value);
2057 DBGPRINT(RT_DEBUG_TRACE, ("--> TX_BASE_PTR3 : 0x%x\n", Value));
2058
2059 // Write HCCA base address register
2060 Value = RTMP_GetPhysicalAddressLow(pAd->TxRing[QID_HCCA].Cell[0].AllocPa);
2061 RTMP_IO_WRITE32(pAd, TX_BASE_PTR4, Value);
2062 DBGPRINT(RT_DEBUG_TRACE, ("--> TX_BASE_PTR4 : 0x%x\n", Value));
2063
2064 // Write MGMT_BASE_CSR register
2065 Value = RTMP_GetPhysicalAddressLow(pAd->MgmtRing.Cell[0].AllocPa);
2066 RTMP_IO_WRITE32(pAd, TX_BASE_PTR5, Value);
2067 DBGPRINT(RT_DEBUG_TRACE, ("--> TX_BASE_PTR5 : 0x%x\n", Value));
2068
2069 // Write RX_BASE_CSR register
2070 Value = RTMP_GetPhysicalAddressLow(pAd->RxRing.Cell[0].AllocPa);
2071 RTMP_IO_WRITE32(pAd, RX_BASE_PTR, Value);
2072 DBGPRINT(RT_DEBUG_TRACE, ("--> RX_BASE_PTR : 0x%x\n", Value));
2073
2074 // Init RX Ring index pointer
2075 pAd->RxRing.RxSwReadIdx = 0;
2076 pAd->RxRing.RxCpuIdx = RX_RING_SIZE-1;
2077 RTMP_IO_WRITE32(pAd, RX_CRX_IDX, pAd->RxRing.RxCpuIdx);
2078
2079 // Init TX rings index pointer
2080 {
2081 for (i=0; i<NUM_OF_TX_RING; i++)
2082 {
2083 pAd->TxRing[i].TxSwFreeIdx = 0;
2084 pAd->TxRing[i].TxCpuIdx = 0;
2085 RTMP_IO_WRITE32(pAd, (TX_CTX_IDX0 + i * 0x10) , pAd->TxRing[i].TxCpuIdx);
2086 }
2087 }
2088
2089 // init MGMT ring index pointer
2090 pAd->MgmtRing.TxSwFreeIdx = 0;
2091 pAd->MgmtRing.TxCpuIdx = 0;
2092 RTMP_IO_WRITE32(pAd, TX_MGMTCTX_IDX, pAd->MgmtRing.TxCpuIdx);
2093
2094 //
2095 // set each Ring's SIZE into ASIC. Descriptor Size is fixed by design.
2096 //
2097
2098 // Write TX_RING_CSR0 register
2099 Value = TX_RING_SIZE;
2100 RTMP_IO_WRITE32(pAd, TX_MAX_CNT0, Value);
2101 RTMP_IO_WRITE32(pAd, TX_MAX_CNT1, Value);
2102 RTMP_IO_WRITE32(pAd, TX_MAX_CNT2, Value);
2103 RTMP_IO_WRITE32(pAd, TX_MAX_CNT3, Value);
2104 RTMP_IO_WRITE32(pAd, TX_MAX_CNT4, Value);
2105 Value = MGMT_RING_SIZE;
2106 RTMP_IO_WRITE32(pAd, TX_MGMTMAX_CNT, Value);
2107
2108 // Write RX_RING_CSR register
2109 Value = RX_RING_SIZE;
2110 RTMP_IO_WRITE32(pAd, RX_MAX_CNT, Value);
2111 #endif /* RT2860 */
2112
2113
2114 // WMM parameter
2115 csr0.word = 0;
2116 RTMP_IO_WRITE32(pAd, WMM_TXOP0_CFG, csr0.word);
2117 if (pAd->CommonCfg.PhyMode == PHY_11B)
2118 {
2119 csr0.field.Ac0Txop = 192; // AC_VI: 192*32us ~= 6ms
2120 csr0.field.Ac1Txop = 96; // AC_VO: 96*32us ~= 3ms
2121 }
2122 else
2123 {
2124 csr0.field.Ac0Txop = 96; // AC_VI: 96*32us ~= 3ms
2125 csr0.field.Ac1Txop = 48; // AC_VO: 48*32us ~= 1.5ms
2126 }
2127 RTMP_IO_WRITE32(pAd, WMM_TXOP1_CFG, csr0.word);
2128
2129
2130 #ifdef RT2860
2131 // 3. Set DMA global configuration except TX_DMA_EN and RX_DMA_EN bits:
2132 i = 0;
2133 do
2134 {
2135 RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word);
2136 if ((GloCfg.field.TxDMABusy == 0) && (GloCfg.field.RxDMABusy == 0))
2137 break;
2138
2139 RTMPusecDelay(1000);
2140 i++;
2141 }while ( i < 100);
2142
2143 GloCfg.word &= 0xff0;
2144 GloCfg.field.EnTXWriteBackDDONE =1;
2145 RTMP_IO_WRITE32(pAd, WPDMA_GLO_CFG, GloCfg.word);
2146
2147 IntCfg.word = 0;
2148 RTMP_IO_WRITE32(pAd, DELAY_INT_CFG, IntCfg.word);
2149 #endif
2150
2151
2152 // reset action
2153 // Load firmware
2154 // Status = NICLoadFirmware(pAd);
2155
2156 DBGPRINT(RT_DEBUG_TRACE, ("<-- NICInitializeAdapter\n"));
2157 return Status;
2158 }
2159
2160 /*
2161 ========================================================================
2162
2163 Routine Description:
2164 Initialize ASIC
2165
2166 Arguments:
2167 Adapter Pointer to our adapter
2168
2169 Return Value:
2170 None
2171
2172 IRQL = PASSIVE_LEVEL
2173
2174 Note:
2175
2176 ========================================================================
2177 */
2178 NDIS_STATUS NICInitializeAsic(
2179 IN PRTMP_ADAPTER pAd,
2180 IN BOOLEAN bHardReset)
2181 {
2182 ULONG Index = 0;
2183 UCHAR R0 = 0xff;
2184 UINT32 MacCsr12 = 0, Counter = 0;
2185 #ifdef RT2870
2186 UINT32 MacCsr0 = 0;
2187 NTSTATUS Status;
2188 UCHAR Value = 0xff;
2189 UINT32 eFuseCtrl;
2190 #endif
2191 USHORT KeyIdx;
2192 INT i,apidx;
2193
2194 DBGPRINT(RT_DEBUG_TRACE, ("--> NICInitializeAsic\n"));
2195
2196 #ifdef RT2860
2197 if (bHardReset == TRUE)
2198 {
2199 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x3);
2200 }
2201 else
2202 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x1);
2203 #endif
2204 #ifdef RT2870
2205 //
2206 // Make sure MAC gets ready after NICLoadFirmware().
2207 //
2208 Index = 0;
2209
2210 //To avoid hang-on issue when interface up in kernel 2.4,
2211 //we use a local variable "MacCsr0" instead of using "pAd->MACVersion" directly.
2212 do
2213 {
2214 RTMP_IO_READ32(pAd, MAC_CSR0, &MacCsr0);
2215
2216 if ((MacCsr0 != 0x00) && (MacCsr0 != 0xFFFFFFFF))
2217 break;
2218
2219 RTMPusecDelay(10);
2220 } while (Index++ < 100);
2221
2222 pAd->MACVersion = MacCsr0;
2223 DBGPRINT(RT_DEBUG_TRACE, ("MAC_CSR0 [ Ver:Rev=0x%08x]\n", pAd->MACVersion));
2224 // turn on bit13 (set to zero) after rt2860D. This is to solve high-current issue.
2225 RTMP_IO_READ32(pAd, PBF_SYS_CTRL, &MacCsr12);
2226 MacCsr12 &= (~0x2000);
2227 RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, MacCsr12);
2228
2229 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x3);
2230 RTMP_IO_WRITE32(pAd, USB_DMA_CFG, 0x0);
2231 Status = RTUSBVenderReset(pAd);
2232 #endif
2233
2234 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x0);
2235
2236 // Initialize MAC register to default value
2237 #ifdef RT2860
2238 for (Index = 0; Index < NUM_MAC_REG_PARMS; Index++)
2239 {
2240 RTMP_IO_WRITE32(pAd, MACRegTable[Index].Register, MACRegTable[Index].Value);
2241 }
2242 #endif
2243 #ifdef RT2870
2244 for(Index=0; Index<NUM_MAC_REG_PARMS; Index++)
2245 {
2246 #ifdef RT3070
2247 if ((MACRegTable[Index].Register == TX_SW_CFG0) && (IS_RT3070(pAd) || IS_RT3071(pAd)))
2248 {
2249 MACRegTable[Index].Value = 0x00000400;
2250 }
2251 #endif // RT3070 //
2252 RTMP_IO_WRITE32(pAd, (USHORT)MACRegTable[Index].Register, MACRegTable[Index].Value);
2253 }
2254
2255 #ifndef RT30xx
2256 if(IS_RT3070(pAd))
2257 {
2258 // According to Frank Hsu (from Gary Tsao)
2259 RTMP_IO_WRITE32(pAd, (USHORT)TX_SW_CFG0, 0x00000400);
2260
2261 // Initialize RT3070 serial MAC registers which is different from RT2870 serial
2262 RTUSBWriteMACRegister(pAd, TX_SW_CFG1, 0);
2263 RTUSBWriteMACRegister(pAd, TX_SW_CFG2, 0);
2264 }
2265 #endif
2266 #endif // RT2870 //
2267
2268
2269 {
2270 for (Index = 0; Index < NUM_STA_MAC_REG_PARMS; Index++)
2271 {
2272 #ifdef RT2860
2273 RTMP_IO_WRITE32(pAd, STAMACRegTable[Index].Register, STAMACRegTable[Index].Value);
2274 #endif
2275 #ifdef RT2870
2276 RTMP_IO_WRITE32(pAd, (USHORT)STAMACRegTable[Index].Register, STAMACRegTable[Index].Value);
2277 #endif
2278 }
2279 }
2280
2281 // Initialize RT3070 serial MAc registers which is different from RT2870 serial
2282 if (IS_RT3090(pAd))
2283 {
2284 RTMP_IO_WRITE32(pAd, TX_SW_CFG1, 0);
2285
2286 // RT3071 version E has fixed this issue
2287 if ((pAd->MACVersion & 0xffff) < 0x0211)
2288 {
2289 if (pAd->NicConfig2.field.DACTestBit == 1)
2290 {
2291 RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x1F); // To fix throughput drop drastically
2292 }
2293 else
2294 {
2295 RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x0F); // To fix throughput drop drastically
2296 }
2297 }
2298 else
2299 {
2300 RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x0);
2301 }
2302 }
2303 #ifdef RT30xx
2304 else if (IS_RT3070(pAd))
2305 {
2306 RTMP_IO_WRITE32(pAd, TX_SW_CFG1, 0);
2307 RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x1F); // To fix throughput drop drastically
2308 }
2309 #endif // RT30xx //
2310
2311 //
2312 // Before program BBP, we need to wait BBP/RF get wake up.
2313 //
2314 Index = 0;
2315 do
2316 {
2317 RTMP_IO_READ32(pAd, MAC_STATUS_CFG, &MacCsr12);
2318
2319 if ((MacCsr12 & 0x03) == 0) // if BB.RF is stable
2320 break;
2321
2322 DBGPRINT(RT_DEBUG_TRACE, ("Check MAC_STATUS_CFG = Busy = %x\n", MacCsr12));
2323 RTMPusecDelay(1000);
2324 } while (Index++ < 100);
2325
2326 // The commands to firmware should be after these commands, these commands will init firmware
2327 // PCI and USB are not the same because PCI driver needs to wait for PCI bus ready
2328 RTMP_IO_WRITE32(pAd, H2M_BBP_AGENT, 0); // initialize BBP R/W access agent
2329 RTMP_IO_WRITE32(pAd, H2M_MAILBOX_CSR, 0);
2330 RTMPusecDelay(1000);
2331
2332 // Read BBP register, make sure BBP is up and running before write new data
2333 Index = 0;
2334 do
2335 {
2336 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R0, &R0);
2337 DBGPRINT(RT_DEBUG_TRACE, ("BBP version = %x\n", R0));
2338 } while ((++Index < 20) && ((R0 == 0xff) || (R0 == 0x00)));
2339 //ASSERT(Index < 20); //this will cause BSOD on Check-build driver
2340
2341 if ((R0 == 0xff) || (R0 == 0x00))
2342 return NDIS_STATUS_FAILURE;
2343
2344 // Initialize BBP register to default value
2345 for (Index = 0; Index < NUM_BBP_REG_PARMS; Index++)
2346 {
2347 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBPRegTable[Index].Register, BBPRegTable[Index].Value);
2348 }
2349
2350 #ifndef RT30xx
2351 // for rt2860E and after, init BBP_R84 with 0x19. This is for extension channel overlapping IOT.
2352 if ((pAd->MACVersion&0xffff) != 0x0101)
2353 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R84, 0x19);
2354
2355 #ifdef RT2870
2356 //write RT3070 BBP wchich different with 2870 after write RT2870 BBP
2357 if (IS_RT3070(pAd))
2358 {
2359 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0a);
2360 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R84, 0x99);
2361 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R105, 0x05);
2362 }
2363 #endif // RT2870 //
2364 #endif
2365 #ifdef RT30xx
2366 // for rt2860E and after, init BBP_R84 with 0x19. This is for extension channel overlapping IOT.
2367 // RT3090 should not program BBP R84 to 0x19, otherwise TX will block.
2368 if (((pAd->MACVersion&0xffff) != 0x0101) && (!IS_RT30xx(pAd)))
2369 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R84, 0x19);
2370
2371 // add by johnli, RF power sequence setup
2372 if (IS_RT30xx(pAd))
2373 { //update for RT3070/71/72/90/91/92.
2374 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R79, 0x13);
2375 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R80, 0x05);
2376 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R81, 0x33);
2377 }
2378
2379 if (IS_RT3090(pAd))
2380 {
2381 UCHAR bbpreg=0;
2382
2383 // enable DC filter
2384 if ((pAd->MACVersion & 0xffff) >= 0x0211)
2385 {
2386 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R103, 0xc0);
2387 }
2388
2389 // improve power consumption
2390 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R138, &bbpreg);
2391 if (pAd->Antenna.field.TxPath == 1)
2392 {
2393 // turn off tx DAC_1
2394 bbpreg = (bbpreg | 0x20);
2395 }
2396
2397 if (pAd->Antenna.field.RxPath == 1)
2398 {
2399 // turn off tx ADC_1
2400 bbpreg &= (~0x2);
2401 }
2402 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R138, bbpreg);
2403
2404 // improve power consumption in RT3071 Ver.E
2405 if ((pAd->MACVersion & 0xffff) >= 0x0211)
2406 {
2407 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R31, &bbpreg);
2408 bbpreg &= (~0x3);
2409 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R31, bbpreg);
2410 }
2411 }
2412 #endif
2413 if (pAd->MACVersion == 0x28600100)
2414 {
2415 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x16);
2416 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x12);
2417 }
2418
2419 if (pAd->MACVersion >= RALINK_2880E_VERSION && pAd->MACVersion < RALINK_3070_VERSION) // 3*3
2420 {
2421 // enlarge MAX_LEN_CFG
2422 UINT32 csr;
2423 RTMP_IO_READ32(pAd, MAX_LEN_CFG, &csr);
2424 csr &= 0xFFF;
2425 csr |= 0x2000;
2426 RTMP_IO_WRITE32(pAd, MAX_LEN_CFG, csr);
2427 }
2428
2429 #ifdef RT2870
2430 {
2431 UCHAR MAC_Value[]={0xff,0xff,0xff,0xff,0xff,0xff,0xff,0,0};
2432
2433 //Initialize WCID table
2434 Value = 0xff;
2435 for(Index =0 ;Index < 254;Index++)
2436 {
2437 RTUSBMultiWrite(pAd, (USHORT)(MAC_WCID_BASE + Index * 8), MAC_Value, 8);
2438 }
2439 }
2440 #endif // RT2870 //
2441
2442 // Add radio off control
2443 {
2444 if (pAd->StaCfg.bRadio == FALSE)
2445 {
2446 // RTMP_IO_WRITE32(pAd, PWR_PIN_CFG, 0x00001818);
2447 RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF);
2448 DBGPRINT(RT_DEBUG_TRACE, ("Set Radio Off\n"));
2449 }
2450 }
2451
2452 // Clear raw counters
2453 RTMP_IO_READ32(pAd, RX_STA_CNT0, &Counter);
2454 RTMP_IO_READ32(pAd, RX_STA_CNT1, &Counter);
2455 RTMP_IO_READ32(pAd, RX_STA_CNT2, &Counter);
2456 RTMP_IO_READ32(pAd, TX_STA_CNT0, &Counter);
2457 RTMP_IO_READ32(pAd, TX_STA_CNT1, &Counter);
2458 RTMP_IO_READ32(pAd, TX_STA_CNT2, &Counter);
2459
2460 // ASIC will keep garbage value after boot
2461 // Clear all seared key table when initial
2462 // This routine can be ignored in radio-ON/OFF operation.
2463 if (bHardReset)
2464 {
2465 for (KeyIdx = 0; KeyIdx < 4; KeyIdx++)
2466 {
2467 RTMP_IO_WRITE32(pAd, SHARED_KEY_MODE_BASE + 4*KeyIdx, 0);
2468 }
2469
2470 // Clear all pairwise key table when initial
2471 for (KeyIdx = 0; KeyIdx < 256; KeyIdx++)
2472 {
2473 RTMP_IO_WRITE32(pAd, MAC_WCID_ATTRIBUTE_BASE + (KeyIdx * HW_WCID_ATTRI_SIZE), 1);
2474 }
2475 }
2476
2477
2478 // It isn't necessary to clear this space when not hard reset.
2479 if (bHardReset == TRUE)
2480 {
2481 // clear all on-chip BEACON frame space
2482 for (apidx = 0; apidx < HW_BEACON_MAX_COUNT; apidx++)
2483 {
2484 for (i = 0; i < HW_BEACON_OFFSET>>2; i+=4)
2485 RTMP_IO_WRITE32(pAd, pAd->BeaconOffset[apidx] + i, 0x00);
2486 }
2487 }
2488 #ifdef RT2870
2489 AsicDisableSync(pAd);
2490 // Clear raw counters
2491 RTMP_IO_READ32(pAd, RX_STA_CNT0, &Counter);
2492 RTMP_IO_READ32(pAd, RX_STA_CNT1, &Counter);
2493 RTMP_IO_READ32(pAd, RX_STA_CNT2, &Counter);
2494 RTMP_IO_READ32(pAd, TX_STA_CNT0, &Counter);
2495 RTMP_IO_READ32(pAd, TX_STA_CNT1, &Counter);
2496 RTMP_IO_READ32(pAd, TX_STA_CNT2, &Counter);
2497 // Default PCI clock cycle per ms is different as default setting, which is based on PCI.
2498 RTMP_IO_READ32(pAd, USB_CYC_CFG, &Counter);
2499 Counter&=0xffffff00;
2500 Counter|=0x000001e;
2501 RTMP_IO_WRITE32(pAd, USB_CYC_CFG, Counter);
2502
2503 pAd->bUseEfuse=FALSE;
2504 RTMP_IO_READ32(pAd, EFUSE_CTRL, &eFuseCtrl);
2505 pAd->bUseEfuse = ( (eFuseCtrl & 0x80000000) == 0x80000000) ? 1 : 0;
2506 if(pAd->bUseEfuse)
2507 {
2508 DBGPRINT(RT_DEBUG_TRACE, ("NVM is Efuse\n"));
2509 }
2510 else
2511 {
2512 DBGPRINT(RT_DEBUG_TRACE, ("NVM is EEPROM\n"));
2513 }
2514 #endif
2515
2516 {
2517 // for rt2860E and after, init TXOP_CTRL_CFG with 0x583f. This is for extension channel overlapping IOT.
2518 if ((pAd->MACVersion&0xffff) != 0x0101)
2519 RTMP_IO_WRITE32(pAd, TXOP_CTRL_CFG, 0x583f);
2520 }
2521
2522 DBGPRINT(RT_DEBUG_TRACE, ("<-- NICInitializeAsic\n"));
2523 return NDIS_STATUS_SUCCESS;
2524 }
2525
2526
2527 #ifdef RT2860
2528 VOID NICRestoreBBPValue(
2529 IN PRTMP_ADAPTER pAd)
2530 {
2531 UCHAR index;
2532 UCHAR Value = 0;
2533 ULONG Data;
2534
2535 DBGPRINT(RT_DEBUG_TRACE, ("---> NICRestoreBBPValue !!!!!!!!!!!!!!!!!!!!!!! \n"));
2536 // Initialize BBP register to default value (rtmp_init.c)
2537 for (index = 0; index < NUM_BBP_REG_PARMS; index++)
2538 {
2539 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBPRegTable[index].Register, BBPRegTable[index].Value);
2540 }
2541 // copy from (rtmp_init.c)
2542 if (pAd->MACVersion == 0x28600100)
2543 {
2544 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x16);
2545 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x12);
2546 }
2547
2548 // copy from (connect.c LinkUp function)
2549 if (INFRA_ON(pAd))
2550 {
2551 // Change to AP channel
2552 if ((pAd->CommonCfg.CentralChannel > pAd->CommonCfg.Channel) && (pAd->MlmeAux.HtCapability.HtCapInfo.ChannelWidth == BW_40))
2553 {
2554 // Must using 40MHz.
2555 pAd->CommonCfg.BBPCurrentBW = BW_40;
2556 AsicSwitchChannel(pAd, pAd->CommonCfg.CentralChannel, FALSE);
2557 AsicLockChannel(pAd, pAd->CommonCfg.CentralChannel);
2558
2559 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &Value);
2560 Value &= (~0x18);
2561 Value |= 0x10;
2562 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, Value);
2563
2564 // RX : control channel at lower
2565 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &Value);
2566 Value &= (~0x20);
2567 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, Value);
2568 // Record BBPR3 setting, But don't keep R Antenna # information.
2569 pAd->StaCfg.BBPR3 = Value;
2570
2571 RTMP_IO_READ32(pAd, TX_BAND_CFG, &Data);
2572 Data &= 0xfffffffe;
2573 RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Data);
2574
2575 if (pAd->MACVersion == 0x28600100)
2576 {
2577 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x1A);
2578 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A);
2579 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x16);
2580 DBGPRINT(RT_DEBUG_TRACE, ("!!!rt2860C !!! \n" ));
2581 }
2582
2583 DBGPRINT(RT_DEBUG_TRACE, ("!!!40MHz Lower LINK UP !!! Control Channel at Below. Central = %d \n", pAd->CommonCfg.CentralChannel ));
2584 }
2585 else if ((pAd->CommonCfg.CentralChannel < pAd->CommonCfg.Channel) && (pAd->MlmeAux.HtCapability.HtCapInfo.ChannelWidth == BW_40))
2586 {
2587 // Must using 40MHz.
2588 pAd->CommonCfg.BBPCurrentBW = BW_40;
2589 AsicSwitchChannel(pAd, pAd->CommonCfg.CentralChannel, FALSE);
2590 AsicLockChannel(pAd, pAd->CommonCfg.CentralChannel);
2591
2592 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &Value);
2593 Value &= (~0x18);
2594 Value |= 0x10;
2595 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, Value);
2596
2597 RTMP_IO_READ32(pAd, TX_BAND_CFG, &Data);
2598 Data |= 0x1;
2599 RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Data);
2600
2601 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &Value);
2602 Value |= (0x20);
2603 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, Value);
2604 // Record BBPR3 setting, But don't keep R Antenna # information.
2605 pAd->StaCfg.BBPR3 = Value;
2606
2607 if (pAd->MACVersion == 0x28600100)
2608 {
2609 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x1A);
2610 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A);
2611 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x16);
2612 DBGPRINT(RT_DEBUG_TRACE, ("!!!rt2860C !!! \n" ));
2613 }
2614
2615 DBGPRINT(RT_DEBUG_TRACE, ("!!!40MHz Upper LINK UP !!! Control Channel at UpperCentral = %d \n", pAd->CommonCfg.CentralChannel ));
2616 }
2617 else
2618 {
2619 pAd->CommonCfg.BBPCurrentBW = BW_20;
2620 AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, FALSE);
2621 AsicLockChannel(pAd, pAd->CommonCfg.Channel);
2622
2623 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &Value);
2624 Value &= (~0x18);
2625 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, Value);
2626
2627 RTMP_IO_READ32(pAd, TX_BAND_CFG, &Data);
2628 Data &= 0xfffffffe;
2629 RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Data);
2630
2631 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &Value);
2632 Value &= (~0x20);
2633 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, Value);
2634 // Record BBPR3 setting, But don't keep R Antenna # information.
2635 pAd->StaCfg.BBPR3 = Value;
2636
2637 if (pAd->MACVersion == 0x28600100)
2638 {
2639 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x16);
2640 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x08);
2641 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x11);
2642 DBGPRINT(RT_DEBUG_TRACE, ("!!!rt2860C !!! \n" ));
2643 }
2644
2645 DBGPRINT(RT_DEBUG_TRACE, ("!!!20MHz LINK UP !!! \n" ));
2646 }
2647 }
2648
2649 DBGPRINT(RT_DEBUG_TRACE, ("<--- NICRestoreBBPValue !!!!!!!!!!!!!!!!!!!!!!! \n"));
2650 }
2651 #endif /* RT2860 */
2652
2653 /*
2654 ========================================================================
2655
2656 Routine Description:
2657 Reset NIC Asics
2658
2659 Arguments:
2660 Adapter Pointer to our adapter
2661
2662 Return Value:
2663 None
2664
2665 IRQL = PASSIVE_LEVEL
2666
2667 Note:
2668 Reset NIC to initial state AS IS system boot up time.
2669
2670 ========================================================================
2671 */
2672 VOID NICIssueReset(
2673 IN PRTMP_ADAPTER pAd)
2674 {
2675 UINT32 Value = 0;
2676 DBGPRINT(RT_DEBUG_TRACE, ("--> NICIssueReset\n"));
2677
2678 // Disable Rx, register value supposed will remain after reset
2679 RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
2680 Value &= (0xfffffff3);
2681 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
2682
2683 // Issue reset and clear from reset state
2684 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x03); // 2004-09-17 change from 0x01
2685 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x00);
2686
2687 DBGPRINT(RT_DEBUG_TRACE, ("<-- NICIssueReset\n"));
2688 }
2689
2690 /*
2691 ========================================================================
2692
2693 Routine Description:
2694 Check ASIC registers and find any reason the system might hang
2695
2696 Arguments:
2697 Adapter Pointer to our adapter
2698
2699 Return Value:
2700 None
2701
2702 IRQL = DISPATCH_LEVEL
2703
2704 ========================================================================
2705 */
2706 BOOLEAN NICCheckForHang(
2707 IN PRTMP_ADAPTER pAd)
2708 {
2709 return (FALSE);
2710 }
2711
2712 VOID NICUpdateFifoStaCounters(
2713 IN PRTMP_ADAPTER pAd)
2714 {
2715 TX_STA_FIFO_STRUC StaFifo;
2716 MAC_TABLE_ENTRY *pEntry;
2717 UCHAR i = 0;
2718 UCHAR pid = 0, wcid = 0;
2719 CHAR reTry;
2720 UCHAR succMCS;
2721
2722 do
2723 {
2724 RTMP_IO_READ32(pAd, TX_STA_FIFO, &StaFifo.word);
2725
2726 if (StaFifo.field.bValid == 0)
2727 break;
2728
2729 wcid = (UCHAR)StaFifo.field.wcid;
2730
2731
2732 /* ignore NoACK and MGMT frame use 0xFF as WCID */
2733 if ((StaFifo.field.TxAckRequired == 0) || (wcid >= MAX_LEN_OF_MAC_TABLE))
2734 {
2735 i++;
2736 continue;
2737 }
2738
2739 /* PID store Tx MCS Rate */
2740 pid = (UCHAR)StaFifo.field.PidType;
2741
2742 pEntry = &pAd->MacTab.Content[wcid];
2743
2744 pEntry->DebugFIFOCount++;
2745
2746 if (StaFifo.field.TxBF) // 3*3
2747 pEntry->TxBFCount++;
2748
2749 #ifdef UAPSD_AP_SUPPORT
2750 UAPSD_SP_AUE_Handle(pAd, pEntry, StaFifo.field.TxSuccess);
2751 #endif // UAPSD_AP_SUPPORT //
2752
2753 if (!StaFifo.field.TxSuccess)
2754 {
2755 pEntry->FIFOCount++;
2756 pEntry->OneSecTxFailCount++;
2757
2758 if (pEntry->FIFOCount >= 1)
2759 {
2760 DBGPRINT(RT_DEBUG_TRACE, ("#"));
2761 pEntry->NoBADataCountDown = 64;
2762
2763 if(pEntry->PsMode == PWR_ACTIVE)
2764 {
2765 int tid;
2766 for (tid=0; tid<NUM_OF_TID; tid++)
2767 {
2768 BAOriSessionTearDown(pAd, pEntry->Aid, tid, FALSE, FALSE);
2769 }
2770
2771 // Update the continuous transmission counter except PS mode
2772 pEntry->ContinueTxFailCnt++;
2773 }
2774 else
2775 {
2776 // Clear the FIFOCount when sta in Power Save mode. Basically we assume
2777 // this tx error happened due to sta just go to sleep.
2778 pEntry->FIFOCount = 0;
2779 pEntry->ContinueTxFailCnt = 0;
2780 }
2781 }
2782 }
2783 else
2784 {
2785 if ((pEntry->PsMode != PWR_SAVE) && (pEntry->NoBADataCountDown > 0))
2786 {
2787 pEntry->NoBADataCountDown--;
2788 if (pEntry->NoBADataCountDown==0)
2789 {
2790 DBGPRINT(RT_DEBUG_TRACE, ("@\n"));
2791 }
2792 }
2793
2794 pEntry->FIFOCount = 0;
2795 pEntry->OneSecTxNoRetryOkCount++;
2796 // update NoDataIdleCount when sucessful send packet to STA.
2797 pEntry->NoDataIdleCount = 0;
2798 pEntry->ContinueTxFailCnt = 0;
2799 }
2800
2801 succMCS = StaFifo.field.SuccessRate & 0x7F;
2802
2803 reTry = pid - succMCS;
2804
2805 if (StaFifo.field.TxSuccess)
2806 {
2807 pEntry->TXMCSExpected[pid]++;
2808 if (pid == succMCS)
2809 {
2810 pEntry->TXMCSSuccessful[pid]++;
2811 }
2812 else
2813 {
2814 pEntry->TXMCSAutoFallBack[pid][succMCS]++;
2815 }
2816 }
2817 else
2818 {
2819 pEntry->TXMCSFailed[pid]++;
2820 }
2821
2822 if (reTry > 0)
2823 {
2824 if ((pid >= 12) && succMCS <=7)
2825 {
2826 reTry -= 4;
2827 }
2828 pEntry->OneSecTxRetryOkCount += reTry;
2829 }
2830
2831 i++;
2832 // ASIC store 16 stack
2833 } while ( i < (2*TX_RING_SIZE) );
2834
2835 }
2836
2837 /*
2838 ========================================================================
2839
2840 Routine Description:
2841 Read statistical counters from hardware registers and record them
2842 in software variables for later on query
2843
2844 Arguments:
2845 pAd Pointer to our adapter
2846
2847 Return Value:
2848 None
2849
2850 IRQL = DISPATCH_LEVEL
2851
2852 ========================================================================
2853 */
2854 VOID NICUpdateRawCounters(
2855 IN PRTMP_ADAPTER pAd)
2856 {
2857 UINT32 OldValue;
2858 RX_STA_CNT0_STRUC RxStaCnt0;
2859 RX_STA_CNT1_STRUC RxStaCnt1;
2860 RX_STA_CNT2_STRUC RxStaCnt2;
2861 TX_STA_CNT0_STRUC TxStaCnt0;
2862 TX_STA_CNT1_STRUC StaTx1;
2863 TX_STA_CNT2_STRUC StaTx2;
2864 TX_AGG_CNT_STRUC TxAggCnt;
2865 TX_AGG_CNT0_STRUC TxAggCnt0;
2866 TX_AGG_CNT1_STRUC TxAggCnt1;
2867 TX_AGG_CNT2_STRUC TxAggCnt2;
2868 TX_AGG_CNT3_STRUC TxAggCnt3;
2869 TX_AGG_CNT4_STRUC TxAggCnt4;
2870 TX_AGG_CNT5_STRUC TxAggCnt5;
2871 TX_AGG_CNT6_STRUC TxAggCnt6;
2872 TX_AGG_CNT7_STRUC TxAggCnt7;
2873
2874 RTMP_IO_READ32(pAd, RX_STA_CNT0, &RxStaCnt0.word);
2875 RTMP_IO_READ32(pAd, RX_STA_CNT2, &RxStaCnt2.word);
2876
2877 {
2878 RTMP_IO_READ32(pAd, RX_STA_CNT1, &RxStaCnt1.word);
2879 // Update RX PLCP error counter
2880 pAd->PrivateInfo.PhyRxErrCnt += RxStaCnt1.field.PlcpErr;
2881 // Update False CCA counter
2882 pAd->RalinkCounters.OneSecFalseCCACnt += RxStaCnt1.field.FalseCca;
2883 }
2884
2885 // Update FCS counters
2886 OldValue= pAd->WlanCounters.FCSErrorCount.u.LowPart;
2887 pAd->WlanCounters.FCSErrorCount.u.LowPart += (RxStaCnt0.field.CrcErr); // >> 7);
2888 if (pAd->WlanCounters.FCSErrorCount.u.LowPart < OldValue)
2889 pAd->WlanCounters.FCSErrorCount.u.HighPart++;
2890
2891 // Add FCS error count to private counters
2892 pAd->RalinkCounters.OneSecRxFcsErrCnt += RxStaCnt0.field.CrcErr;
2893 OldValue = pAd->RalinkCounters.RealFcsErrCount.u.LowPart;
2894 pAd->RalinkCounters.RealFcsErrCount.u.LowPart += RxStaCnt0.field.CrcErr;
2895 if (pAd->RalinkCounters.RealFcsErrCount.u.LowPart < OldValue)
2896 pAd->RalinkCounters.RealFcsErrCount.u.HighPart++;
2897
2898 // Update Duplicate Rcv check
2899 pAd->RalinkCounters.DuplicateRcv += RxStaCnt2.field.RxDupliCount;
2900 pAd->WlanCounters.FrameDuplicateCount.u.LowPart += RxStaCnt2.field.RxDupliCount;
2901 // Update RX Overflow counter
2902 pAd->Counters8023.RxNoBuffer += (RxStaCnt2.field.RxFifoOverflowCount);
2903
2904 #ifdef RT2870
2905 if (pAd->RalinkCounters.RxCount != pAd->watchDogRxCnt)
2906 {
2907 pAd->watchDogRxCnt = pAd->RalinkCounters.RxCount;
2908 pAd->watchDogRxOverFlowCnt = 0;
2909 }
2910 else
2911 {
2912 if (RxStaCnt2.field.RxFifoOverflowCount)
2913 pAd->watchDogRxOverFlowCnt++;
2914 else
2915 pAd->watchDogRxOverFlowCnt = 0;
2916 }
2917 #endif // RT2870 //
2918
2919
2920 if (!pAd->bUpdateBcnCntDone)
2921 {
2922 // Update BEACON sent count
2923 RTMP_IO_READ32(pAd, TX_STA_CNT0, &TxStaCnt0.word);
2924 RTMP_IO_READ32(pAd, TX_STA_CNT1, &StaTx1.word);
2925 RTMP_IO_READ32(pAd, TX_STA_CNT2, &StaTx2.word);
2926 pAd->RalinkCounters.OneSecBeaconSentCnt += TxStaCnt0.field.TxBeaconCount;
2927 pAd->RalinkCounters.OneSecTxRetryOkCount += StaTx1.field.TxRetransmit;
2928 pAd->RalinkCounters.OneSecTxNoRetryOkCount += StaTx1.field.TxSuccess;
2929 pAd->RalinkCounters.OneSecTxFailCount += TxStaCnt0.field.TxFailCount;
2930 pAd->WlanCounters.TransmittedFragmentCount.u.LowPart += StaTx1.field.TxSuccess;
2931 pAd->WlanCounters.RetryCount.u.LowPart += StaTx1.field.TxRetransmit;
2932 pAd->WlanCounters.FailedCount.u.LowPart += TxStaCnt0.field.TxFailCount;
2933 }
2934
2935 {
2936 RTMP_IO_READ32(pAd, TX_AGG_CNT, &TxAggCnt.word);
2937 RTMP_IO_READ32(pAd, TX_AGG_CNT0, &TxAggCnt0.word);
2938 RTMP_IO_READ32(pAd, TX_AGG_CNT1, &TxAggCnt1.word);
2939 RTMP_IO_READ32(pAd, TX_AGG_CNT2, &TxAggCnt2.word);
2940 RTMP_IO_READ32(pAd, TX_AGG_CNT3, &TxAggCnt3.word);
2941 RTMP_IO_READ32(pAd, TX_AGG_CNT4, &TxAggCnt4.word);
2942 RTMP_IO_READ32(pAd, TX_AGG_CNT5, &TxAggCnt5.word);
2943 RTMP_IO_READ32(pAd, TX_AGG_CNT6, &TxAggCnt6.word);
2944 RTMP_IO_READ32(pAd, TX_AGG_CNT7, &TxAggCnt7.word);
2945 pAd->RalinkCounters.TxAggCount += TxAggCnt.field.AggTxCount;
2946 pAd->RalinkCounters.TxNonAggCount += TxAggCnt.field.NonAggTxCount;
2947 pAd->RalinkCounters.TxAgg1MPDUCount += TxAggCnt0.field.AggSize1Count;
2948 pAd->RalinkCounters.TxAgg2MPDUCount += TxAggCnt0.field.AggSize2Count;
2949
2950 pAd->RalinkCounters.TxAgg3MPDUCount += TxAggCnt1.field.AggSize3Count;
2951 pAd->RalinkCounters.TxAgg4MPDUCount += TxAggCnt1.field.AggSize4Count;
2952 pAd->RalinkCounters.TxAgg5MPDUCount += TxAggCnt2.field.AggSize5Count;
2953 pAd->RalinkCounters.TxAgg6MPDUCount += TxAggCnt2.field.AggSize6Count;
2954
2955 pAd->RalinkCounters.TxAgg7MPDUCount += TxAggCnt3.field.AggSize7Count;
2956 pAd->RalinkCounters.TxAgg8MPDUCount += TxAggCnt3.field.AggSize8Count;
2957 pAd->RalinkCounters.TxAgg9MPDUCount += TxAggCnt4.field.AggSize9Count;
2958 pAd->RalinkCounters.TxAgg10MPDUCount += TxAggCnt4.field.AggSize10Count;
2959
2960 pAd->RalinkCounters.TxAgg11MPDUCount += TxAggCnt5.field.AggSize11Count;
2961 pAd->RalinkCounters.TxAgg12MPDUCount += TxAggCnt5.field.AggSize12Count;
2962 pAd->RalinkCounters.TxAgg13MPDUCount += TxAggCnt6.field.AggSize13Count;
2963 pAd->RalinkCounters.TxAgg14MPDUCount += TxAggCnt6.field.AggSize14Count;
2964
2965 pAd->RalinkCounters.TxAgg15MPDUCount += TxAggCnt7.field.AggSize15Count;
2966 pAd->RalinkCounters.TxAgg16MPDUCount += TxAggCnt7.field.AggSize16Count;
2967
2968 // Calculate the transmitted A-MPDU count
2969 pAd->RalinkCounters.TransmittedAMPDUCount.u.LowPart += TxAggCnt0.field.AggSize1Count;
2970 pAd->RalinkCounters.TransmittedAMPDUCount.u.LowPart += (TxAggCnt0.field.AggSize2Count / 2);
2971
2972 pAd->RalinkCounters.TransmittedAMPDUCount.u.LowPart += (TxAggCnt1.field.AggSize3Count / 3);
2973 pAd->RalinkCounters.TransmittedAMPDUCount.u.LowPart += (TxAggCnt1.field.AggSize4Count / 4);
2974
2975 pAd->RalinkCounters.TransmittedAMPDUCount.u.LowPart += (TxAggCnt2.field.AggSize5Count / 5);
2976 pAd->RalinkCounters.TransmittedAMPDUCount.u.LowPart += (TxAggCnt2.field.AggSize6Count / 6);
2977
2978 pAd->RalinkCounters.TransmittedAMPDUCount.u.LowPart += (TxAggCnt3.field.AggSize7Count / 7);
2979 pAd->RalinkCounters.TransmittedAMPDUCount.u.LowPart += (TxAggCnt3.field.AggSize8Count / 8);
2980
2981 pAd->RalinkCounters.TransmittedAMPDUCount.u.LowPart += (TxAggCnt4.field.AggSize9Count / 9);
2982 pAd->RalinkCounters.TransmittedAMPDUCount.u.LowPart += (TxAggCnt4.field.AggSize10Count / 10);
2983
2984 pAd->RalinkCounters.TransmittedAMPDUCount.u.LowPart += (TxAggCnt5.field.AggSize11Count / 11);
2985 pAd->RalinkCounters.TransmittedAMPDUCount.u.LowPart += (TxAggCnt5.field.AggSize12Count / 12);
2986
2987 pAd->RalinkCounters.TransmittedAMPDUCount.u.LowPart += (TxAggCnt6.field.AggSize13Count / 13);
2988 pAd->RalinkCounters.TransmittedAMPDUCount.u.LowPart += (TxAggCnt6.field.AggSize14Count / 14);
2989
2990 pAd->RalinkCounters.TransmittedAMPDUCount.u.LowPart += (TxAggCnt7.field.AggSize15Count / 15);
2991 pAd->RalinkCounters.TransmittedAMPDUCount.u.LowPart += (TxAggCnt7.field.AggSize16Count / 16);
2992 }
2993
2994
2995
2996 }
2997
2998
2999 /*
3000 ========================================================================
3001
3002 Routine Description:
3003 Reset NIC from error
3004
3005 Arguments:
3006 Adapter Pointer to our adapter
3007
3008 Return Value:
3009 None
3010
3011 IRQL = PASSIVE_LEVEL
3012
3013 Note:
3014 Reset NIC from error state
3015
3016 ========================================================================
3017 */
3018 VOID NICResetFromError(
3019 IN PRTMP_ADAPTER pAd)
3020 {
3021 // Reset BBP (according to alex, reset ASIC will force reset BBP
3022 // Therefore, skip the reset BBP
3023 // RTMP_IO_WRITE32(pAd, MAC_CSR1, 0x2);
3024
3025 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x1);
3026 // Remove ASIC from reset state
3027 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x0);
3028
3029 NICInitializeAdapter(pAd, FALSE);
3030 NICInitAsicFromEEPROM(pAd);
3031
3032 // Switch to current channel, since during reset process, the connection should remains on.
3033 AsicSwitchChannel(pAd, pAd->CommonCfg.CentralChannel, FALSE);
3034 AsicLockChannel(pAd, pAd->CommonCfg.CentralChannel);
3035 }
3036
3037 /*
3038 ========================================================================
3039
3040 Routine Description:
3041 erase 8051 firmware image in MAC ASIC
3042
3043 Arguments:
3044 Adapter Pointer to our adapter
3045
3046 IRQL = PASSIVE_LEVEL
3047
3048 ========================================================================
3049 */
3050 VOID NICEraseFirmware(
3051 IN PRTMP_ADAPTER pAd)
3052 {
3053 ULONG i;
3054
3055 for(i=0; i<MAX_FIRMWARE_IMAGE_SIZE; i+=4)
3056 RTMP_IO_WRITE32(pAd, FIRMWARE_IMAGE_BASE + i, 0);
3057
3058 }/* End of NICEraseFirmware */
3059
3060 /*
3061 ========================================================================
3062
3063 Routine Description:
3064 Load 8051 firmware RT2561.BIN file into MAC ASIC
3065
3066 Arguments:
3067 Adapter Pointer to our adapter
3068
3069 Return Value:
3070 NDIS_STATUS_SUCCESS firmware image load ok
3071 NDIS_STATUS_FAILURE image not found
3072
3073 IRQL = PASSIVE_LEVEL
3074
3075 ========================================================================
3076 */
3077 NDIS_STATUS NICLoadFirmware(
3078 IN PRTMP_ADAPTER pAd)
3079 {
3080 NDIS_STATUS Status = NDIS_STATUS_SUCCESS;
3081 PUCHAR pFirmwareImage;
3082 ULONG FileLength, Index;
3083 //ULONG firm;
3084 UINT32 MacReg = 0;
3085 #ifdef RT2870
3086 UINT32 Version = (pAd->MACVersion >> 16);
3087 #endif // RT2870 //
3088
3089 pFirmwareImage = FirmwareImage;
3090 FileLength = sizeof(FirmwareImage);
3091 #ifdef RT2870
3092 // New 8k byte firmware size for RT3071/RT3072
3093 //printk("Usb Chip\n");
3094 if (FIRMWAREIMAGE_LENGTH == FIRMWAREIMAGE_MAX_LENGTH)
3095 //The firmware image consists of two parts. One is the origianl and the other is the new.
3096 //Use Second Part
3097 {
3098 if ((Version != 0x2860) && (Version != 0x2872) && (Version != 0x3070))
3099 { // Use Firmware V2.
3100 //printk("KH:Use New Version,part2\n");
3101 pFirmwareImage = (PUCHAR)&FirmwareImage[FIRMWAREIMAGEV1_LENGTH];
3102 FileLength = FIRMWAREIMAGEV2_LENGTH;
3103 }
3104 else
3105 {
3106 //printk("KH:Use New Version,part1\n");
3107 pFirmwareImage = FirmwareImage;
3108 FileLength = FIRMWAREIMAGEV1_LENGTH;
3109 }
3110 }
3111 else
3112 {
3113 DBGPRINT(RT_DEBUG_ERROR, ("KH: bin file should be 8KB.\n"));
3114 Status = NDIS_STATUS_FAILURE;
3115 }
3116
3117 #endif // RT2870 //
3118
3119 RT28XX_WRITE_FIRMWARE(pAd, pFirmwareImage, FileLength);
3120
3121 /* check if MCU is ready */
3122 Index = 0;
3123 do
3124 {
3125 RTMP_IO_READ32(pAd, PBF_SYS_CTRL, &MacReg);
3126
3127 if (MacReg & 0x80)
3128 break;
3129
3130 RTMPusecDelay(1000);
3131 } while (Index++ < 1000);
3132
3133 if (Index > 1000)
3134 {
3135 Status = NDIS_STATUS_FAILURE;
3136 DBGPRINT(RT_DEBUG_ERROR, ("NICLoadFirmware: MCU is not ready\n\n\n"));
3137 } /* End of if */
3138
3139 DBGPRINT(RT_DEBUG_TRACE,
3140 ("<=== %s (status=%d)\n", __func__, Status));
3141 return Status;
3142 } /* End of NICLoadFirmware */
3143
3144
3145 /*
3146 ========================================================================
3147
3148 Routine Description:
3149 Load Tx rate switching parameters
3150
3151 Arguments:
3152 Adapter Pointer to our adapter
3153
3154 Return Value:
3155 NDIS_STATUS_SUCCESS firmware image load ok
3156 NDIS_STATUS_FAILURE image not found
3157
3158 IRQL = PASSIVE_LEVEL
3159
3160 Rate Table Format:
3161 1. (B0: Valid Item number) (B1:Initial item from zero)
3162 2. Item Number(Dec) Mode(Hex) Current MCS(Dec) TrainUp(Dec) TrainDown(Dec)
3163
3164 ========================================================================
3165 */
3166 NDIS_STATUS NICLoadRateSwitchingParams(
3167 IN PRTMP_ADAPTER pAd)
3168 {
3169 return NDIS_STATUS_SUCCESS;
3170 }
3171
3172 /*
3173 ========================================================================
3174
3175 Routine Description:
3176 if pSrc1 all zero with length Length, return 0.
3177 If not all zero, return 1
3178
3179 Arguments:
3180 pSrc1
3181
3182 Return Value:
3183 1: not all zero
3184 0: all zero
3185
3186 IRQL = DISPATCH_LEVEL
3187
3188 Note:
3189
3190 ========================================================================
3191 */
3192 ULONG RTMPNotAllZero(
3193 IN PVOID pSrc1,
3194 IN ULONG Length)
3195 {
3196 PUCHAR pMem1;
3197 ULONG Index = 0;
3198
3199 pMem1 = (PUCHAR) pSrc1;
3200
3201 for (Index = 0; Index < Length; Index++)
3202 {
3203 if (pMem1[Index] != 0x0)
3204 {
3205 break;
3206 }
3207 }
3208
3209 if (Index == Length)
3210 {
3211 return (0);
3212 }
3213 else
3214 {
3215 return (1);
3216 }
3217 }
3218
3219 /*
3220 ========================================================================
3221
3222 Routine Description:
3223 Compare two memory block
3224
3225 Arguments:
3226 pSrc1 Pointer to first memory address
3227 pSrc2 Pointer to second memory address
3228
3229 Return Value:
3230 0: memory is equal
3231 1: pSrc1 memory is larger
3232 2: pSrc2 memory is larger
3233
3234 IRQL = DISPATCH_LEVEL
3235
3236 Note:
3237
3238 ========================================================================
3239 */
3240 ULONG RTMPCompareMemory(
3241 IN PVOID pSrc1,
3242 IN PVOID pSrc2,
3243 IN ULONG Length)
3244 {
3245 PUCHAR pMem1;
3246 PUCHAR pMem2;
3247 ULONG Index = 0;
3248
3249 pMem1 = (PUCHAR) pSrc1;
3250 pMem2 = (PUCHAR) pSrc2;
3251
3252 for (Index = 0; Index < Length; Index++)
3253 {
3254 if (pMem1[Index] > pMem2[Index])
3255 return (1);
3256 else if (pMem1[Index] < pMem2[Index])
3257 return (2);
3258 }
3259
3260 // Equal
3261 return (0);
3262 }
3263
3264 /*
3265 ========================================================================
3266
3267 Routine Description:
3268 Zero out memory block
3269
3270 Arguments:
3271 pSrc1 Pointer to memory address
3272 Length Size
3273
3274 Return Value:
3275 None
3276
3277 IRQL = PASSIVE_LEVEL
3278 IRQL = DISPATCH_LEVEL
3279
3280 Note:
3281
3282 ========================================================================
3283 */
3284 VOID RTMPZeroMemory(
3285 IN PVOID pSrc,
3286 IN ULONG Length)
3287 {
3288 PUCHAR pMem;
3289 ULONG Index = 0;
3290
3291 pMem = (PUCHAR) pSrc;
3292
3293 for (Index = 0; Index < Length; Index++)
3294 {
3295 pMem[Index] = 0x00;
3296 }
3297 }
3298
3299 VOID RTMPFillMemory(
3300 IN PVOID pSrc,
3301 IN ULONG Length,
3302 IN UCHAR Fill)
3303 {
3304 PUCHAR pMem;
3305 ULONG Index = 0;
3306
3307 pMem = (PUCHAR) pSrc;
3308
3309 for (Index = 0; Index < Length; Index++)
3310 {
3311 pMem[Index] = Fill;
3312 }
3313 }
3314
3315 /*
3316 ========================================================================
3317
3318 Routine Description:
3319 Copy data from memory block 1 to memory block 2
3320
3321 Arguments:
3322 pDest Pointer to destination memory address
3323 pSrc Pointer to source memory address
3324 Length Copy size
3325
3326 Return Value:
3327 None
3328
3329 IRQL = PASSIVE_LEVEL
3330 IRQL = DISPATCH_LEVEL
3331
3332 Note:
3333
3334 ========================================================================
3335 */
3336 VOID RTMPMoveMemory(
3337 OUT PVOID pDest,
3338 IN PVOID pSrc,
3339 IN ULONG Length)
3340 {
3341 PUCHAR pMem1;
3342 PUCHAR pMem2;
3343 UINT Index;
3344
3345 ASSERT((Length==0) || (pDest && pSrc));
3346
3347 pMem1 = (PUCHAR) pDest;
3348 pMem2 = (PUCHAR) pSrc;
3349
3350 for (Index = 0; Index < Length; Index++)
3351 {
3352 pMem1[Index] = pMem2[Index];
3353 }
3354 }
3355
3356 /*
3357 ========================================================================
3358
3359 Routine Description:
3360 Initialize port configuration structure
3361
3362 Arguments:
3363 Adapter Pointer to our adapter
3364
3365 Return Value:
3366 None
3367
3368 IRQL = PASSIVE_LEVEL
3369
3370 Note:
3371
3372 ========================================================================
3373 */
3374 VOID UserCfgInit(
3375 IN PRTMP_ADAPTER pAd)
3376 {
3377 UINT key_index, bss_index;
3378
3379 DBGPRINT(RT_DEBUG_TRACE, ("--> UserCfgInit\n"));
3380
3381 //
3382 // part I. intialize common configuration
3383 //
3384 #ifdef RT2870
3385 pAd->BulkOutReq = 0;
3386
3387 pAd->BulkOutComplete = 0;
3388 pAd->BulkOutCompleteOther = 0;
3389 pAd->BulkOutCompleteCancel = 0;
3390 pAd->BulkInReq = 0;
3391 pAd->BulkInComplete = 0;
3392 pAd->BulkInCompleteFail = 0;
3393
3394 //pAd->QuickTimerP = 100;
3395 //pAd->TurnAggrBulkInCount = 0;
3396 pAd->bUsbTxBulkAggre = 0;
3397
3398 // init as unsed value to ensure driver will set to MCU once.
3399 pAd->LedIndicatorStregth = 0xFF;
3400
3401 pAd->CommonCfg.MaxPktOneTxBulk = 2;
3402 pAd->CommonCfg.TxBulkFactor = 1;
3403 pAd->CommonCfg.RxBulkFactor =1;
3404
3405 pAd->CommonCfg.TxPower = 100; //mW
3406
3407 NdisZeroMemory(&pAd->CommonCfg.IOTestParm, sizeof(pAd->CommonCfg.IOTestParm));
3408 #endif // RT2870 //
3409
3410 for(key_index=0; key_index<SHARE_KEY_NUM; key_index++)
3411 {
3412 for(bss_index = 0; bss_index < MAX_MBSSID_NUM; bss_index++)
3413 {
3414 pAd->SharedKey[bss_index][key_index].KeyLen = 0;
3415 pAd->SharedKey[bss_index][key_index].CipherAlg = CIPHER_NONE;
3416 }
3417 }
3418
3419 #ifdef RT2870
3420 pAd->EepromAccess = FALSE;
3421 #endif
3422 pAd->Antenna.word = 0;
3423 pAd->CommonCfg.BBPCurrentBW = BW_20;
3424
3425 pAd->LedCntl.word = 0;
3426 #ifdef RT2860
3427 pAd->LedIndicatorStregth = 0;
3428 pAd->RLnkCtrlOffset = 0;
3429 pAd->HostLnkCtrlOffset = 0;
3430 pAd->CheckDmaBusyCount = 0;
3431 #endif
3432
3433 pAd->bAutoTxAgcA = FALSE; // Default is OFF
3434 pAd->bAutoTxAgcG = FALSE; // Default is OFF
3435 pAd->RfIcType = RFIC_2820;
3436
3437 // Init timer for reset complete event
3438 pAd->CommonCfg.CentralChannel = 1;
3439 pAd->bForcePrintTX = FALSE;
3440 pAd->bForcePrintRX = FALSE;
3441 pAd->bStaFifoTest = FALSE;
3442 pAd->bProtectionTest = FALSE;
3443 pAd->bHCCATest = FALSE;
3444 pAd->bGenOneHCCA = FALSE;
3445 pAd->CommonCfg.Dsifs = 10; // in units of usec
3446 pAd->CommonCfg.TxPower = 100; //mW
3447 pAd->CommonCfg.TxPowerPercentage = 0xffffffff; // AUTO
3448 pAd->CommonCfg.TxPowerDefault = 0xffffffff; // AUTO
3449 pAd->CommonCfg.TxPreamble = Rt802_11PreambleAuto; // use Long preamble on TX by defaut
3450 pAd->CommonCfg.bUseZeroToDisableFragment = FALSE;
3451 pAd->CommonCfg.RtsThreshold = 2347;
3452 pAd->CommonCfg.FragmentThreshold = 2346;
3453 pAd->CommonCfg.UseBGProtection = 0; // 0: AUTO
3454 pAd->CommonCfg.bEnableTxBurst = TRUE; //0;
3455 pAd->CommonCfg.PhyMode = 0xff; // unknown
3456 pAd->CommonCfg.BandState = UNKNOWN_BAND;
3457 pAd->CommonCfg.RadarDetect.CSPeriod = 10;
3458 pAd->CommonCfg.RadarDetect.CSCount = 0;
3459 pAd->CommonCfg.RadarDetect.RDMode = RD_NORMAL_MODE;
3460 pAd->CommonCfg.RadarDetect.ChMovingTime = 65;
3461 pAd->CommonCfg.RadarDetect.LongPulseRadarTh = 3;
3462 pAd->CommonCfg.bAPSDCapable = FALSE;
3463 pAd->CommonCfg.bNeedSendTriggerFrame = FALSE;
3464 pAd->CommonCfg.TriggerTimerCount = 0;
3465 pAd->CommonCfg.bAPSDForcePowerSave = FALSE;
3466 pAd->CommonCfg.bCountryFlag = FALSE;
3467 pAd->CommonCfg.TxStream = 0;
3468 pAd->CommonCfg.RxStream = 0;
3469
3470 NdisZeroMemory(&pAd->BeaconTxWI, sizeof(pAd->BeaconTxWI));
3471
3472 NdisZeroMemory(&pAd->CommonCfg.HtCapability, sizeof(pAd->CommonCfg.HtCapability));
3473 pAd->HTCEnable = FALSE;
3474 pAd->bBroadComHT = FALSE;
3475 pAd->CommonCfg.bRdg = FALSE;
3476
3477 NdisZeroMemory(&pAd->CommonCfg.AddHTInfo, sizeof(pAd->CommonCfg.AddHTInfo));
3478 pAd->CommonCfg.BACapability.field.MMPSmode = MMPS_ENABLE;
3479 pAd->CommonCfg.BACapability.field.MpduDensity = 0;
3480 pAd->CommonCfg.BACapability.field.Policy = IMMED_BA;
3481 pAd->CommonCfg.BACapability.field.RxBAWinLimit = 64; //32;
3482 pAd->CommonCfg.BACapability.field.TxBAWinLimit = 64; //32;
3483 DBGPRINT(RT_DEBUG_TRACE, ("--> UserCfgInit. BACapability = 0x%x\n", pAd->CommonCfg.BACapability.word));
3484
3485 pAd->CommonCfg.BACapability.field.AutoBA = FALSE;
3486 BATableInit(pAd, &pAd->BATable);
3487
3488 pAd->CommonCfg.bExtChannelSwitchAnnouncement = 1;
3489 pAd->CommonCfg.bHTProtect = 1;
3490 pAd->CommonCfg.bMIMOPSEnable = TRUE;
3491 pAd->CommonCfg.bBADecline = FALSE;
3492 pAd->CommonCfg.bDisableReordering = FALSE;
3493
3494 pAd->CommonCfg.TxBASize = 7;
3495
3496 pAd->CommonCfg.REGBACapability.word = pAd->CommonCfg.BACapability.word;
3497
3498 //pAd->CommonCfg.HTPhyMode.field.BW = BW_20;
3499 //pAd->CommonCfg.HTPhyMode.field.MCS = MCS_AUTO;
3500 //pAd->CommonCfg.HTPhyMode.field.ShortGI = GI_800;
3501 //pAd->CommonCfg.HTPhyMode.field.STBC = STBC_NONE;
3502 pAd->CommonCfg.TxRate = RATE_6;
3503
3504 pAd->CommonCfg.MlmeTransmit.field.MCS = MCS_RATE_6;
3505 pAd->CommonCfg.MlmeTransmit.field.BW = BW_20;
3506 pAd->CommonCfg.MlmeTransmit.field.MODE = MODE_OFDM;
3507
3508 pAd->CommonCfg.BeaconPeriod = 100; // in mSec
3509
3510 //
3511 // part II. intialize STA specific configuration
3512 //
3513 {
3514 RX_FILTER_SET_FLAG(pAd, fRX_FILTER_ACCEPT_DIRECT);
3515 RX_FILTER_CLEAR_FLAG(pAd, fRX_FILTER_ACCEPT_MULTICAST);
3516 RX_FILTER_SET_FLAG(pAd, fRX_FILTER_ACCEPT_BROADCAST);
3517 RX_FILTER_SET_FLAG(pAd, fRX_FILTER_ACCEPT_ALL_MULTICAST);
3518
3519 pAd->StaCfg.Psm = PWR_ACTIVE;
3520
3521 pAd->StaCfg.OrigWepStatus = Ndis802_11EncryptionDisabled;
3522 pAd->StaCfg.PairCipher = Ndis802_11EncryptionDisabled;
3523 pAd->StaCfg.GroupCipher = Ndis802_11EncryptionDisabled;
3524 pAd->StaCfg.bMixCipher = FALSE;
3525 pAd->StaCfg.DefaultKeyId = 0;
3526
3527 // 802.1x port control
3528 pAd->StaCfg.PrivacyFilter = Ndis802_11PrivFilter8021xWEP;
3529 pAd->StaCfg.PortSecured = WPA_802_1X_PORT_NOT_SECURED;
3530 pAd->StaCfg.LastMicErrorTime = 0;
3531 pAd->StaCfg.MicErrCnt = 0;
3532 pAd->StaCfg.bBlockAssoc = FALSE;
3533 pAd->StaCfg.WpaState = SS_NOTUSE;
3534
3535 pAd->CommonCfg.NdisRadioStateOff = FALSE; // New to support microsoft disable radio with OID command
3536
3537 pAd->StaCfg.RssiTrigger = 0;
3538 NdisZeroMemory(&pAd->StaCfg.RssiSample, sizeof(RSSI_SAMPLE));
3539 pAd->StaCfg.RssiTriggerMode = RSSI_TRIGGERED_UPON_BELOW_THRESHOLD;
3540 pAd->StaCfg.AtimWin = 0;
3541 pAd->StaCfg.DefaultListenCount = 3;//default listen count;
3542 pAd->StaCfg.BssType = BSS_INFRA; // BSS_INFRA or BSS_ADHOC or BSS_MONITOR
3543 pAd->StaCfg.bScanReqIsFromWebUI = FALSE;
3544 OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_DOZE);
3545 OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_WAKEUP_NOW);
3546
3547 pAd->StaCfg.bAutoTxRateSwitch = TRUE;
3548 pAd->StaCfg.DesiredTransmitSetting.field.MCS = MCS_AUTO;
3549 }
3550
3551 // global variables mXXXX used in MAC protocol state machines
3552 OPSTATUS_SET_FLAG(pAd, fOP_STATUS_RECEIVE_DTIM);
3553 OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_ADHOC_ON);
3554 OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_INFRA_ON);
3555
3556 // PHY specification
3557 pAd->CommonCfg.PhyMode = PHY_11BG_MIXED; // default PHY mode
3558 OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_SHORT_PREAMBLE_INUSED); // CCK use LONG preamble
3559
3560 {
3561 // user desired power mode
3562 pAd->StaCfg.WindowsPowerMode = Ndis802_11PowerModeCAM;
3563 pAd->StaCfg.WindowsBatteryPowerMode = Ndis802_11PowerModeCAM;
3564 pAd->StaCfg.bWindowsACCAMEnable = FALSE;
3565
3566 RTMPInitTimer(pAd, &pAd->StaCfg.StaQuickResponeForRateUpTimer, GET_TIMER_FUNCTION(StaQuickResponeForRateUpExec), pAd, FALSE);
3567 pAd->StaCfg.StaQuickResponeForRateUpTimerRunning = FALSE;
3568
3569 // Patch for Ndtest
3570 pAd->StaCfg.ScanCnt = 0;
3571
3572 // CCX 2.0 control flag init
3573 pAd->StaCfg.CCXEnable = FALSE;
3574 pAd->StaCfg.CCXReqType = MSRN_TYPE_UNUSED;
3575 pAd->StaCfg.CCXQosECWMin = 4;
3576 pAd->StaCfg.CCXQosECWMax = 10;
3577
3578 pAd->StaCfg.bHwRadio = TRUE; // Default Hardware Radio status is On
3579 pAd->StaCfg.bSwRadio = TRUE; // Default Software Radio status is On
3580 pAd->StaCfg.bRadio = TRUE; // bHwRadio && bSwRadio
3581 pAd->StaCfg.bHardwareRadio = FALSE; // Default is OFF
3582 pAd->StaCfg.bShowHiddenSSID = FALSE; // Default no show
3583
3584 // Nitro mode control
3585 pAd->StaCfg.bAutoReconnect = TRUE;
3586
3587 // Save the init time as last scan time, the system should do scan after 2 seconds.
3588 // This patch is for driver wake up from standby mode, system will do scan right away.
3589 pAd->StaCfg.LastScanTime = 0;
3590 NdisZeroMemory(pAd->nickname, IW_ESSID_MAX_SIZE+1);
3591 sprintf(pAd->nickname, "%s", STA_NIC_DEVICE_NAME);
3592 RTMPInitTimer(pAd, &pAd->StaCfg.WpaDisassocAndBlockAssocTimer, GET_TIMER_FUNCTION(WpaDisassocApAndBlockAssoc), pAd, FALSE);
3593 pAd->StaCfg.IEEE8021X = FALSE;
3594 pAd->StaCfg.IEEE8021x_required_keys = FALSE;
3595 pAd->StaCfg.WpaSupplicantUP = WPA_SUPPLICANT_DISABLE;
3596 pAd->StaCfg.WpaSupplicantUP = WPA_SUPPLICANT_ENABLE;
3597 }
3598
3599 // Default for extra information is not valid
3600 pAd->ExtraInfo = EXTRA_INFO_CLEAR;
3601
3602 // Default Config change flag
3603 pAd->bConfigChanged = FALSE;
3604
3605 //
3606 // part III. AP configurations
3607 //
3608
3609
3610 //
3611 // part IV. others
3612 //
3613 // dynamic BBP R66:sensibity tuning to overcome background noise
3614 pAd->BbpTuning.bEnable = TRUE;
3615 pAd->BbpTuning.FalseCcaLowerThreshold = 100;
3616 pAd->BbpTuning.FalseCcaUpperThreshold = 512;
3617 pAd->BbpTuning.R66Delta = 4;
3618 pAd->Mlme.bEnableAutoAntennaCheck = TRUE;
3619
3620 //
3621 // Also initial R66CurrentValue, RTUSBResumeMsduTransmission might use this value.
3622 // if not initial this value, the default value will be 0.
3623 //
3624 pAd->BbpTuning.R66CurrentValue = 0x38;
3625
3626 pAd->Bbp94 = BBPR94_DEFAULT;
3627 pAd->BbpForCCK = FALSE;
3628
3629 // initialize MAC table and allocate spin lock
3630 NdisZeroMemory(&pAd->MacTab, sizeof(MAC_TABLE));
3631 InitializeQueueHeader(&pAd->MacTab.McastPsQueue);
3632 NdisAllocateSpinLock(&pAd->MacTabLock);
3633
3634 pAd->CommonCfg.bWiFiTest = FALSE;
3635 #ifdef RT2860
3636 pAd->bPCIclkOff = FALSE;
3637
3638 RTMP_SET_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP);
3639 #endif
3640 DBGPRINT(RT_DEBUG_TRACE, ("<-- UserCfgInit\n"));
3641 }
3642
3643 // IRQL = PASSIVE_LEVEL
3644 UCHAR BtoH(char ch)
3645 {
3646 if (ch >= '0' && ch <= '9') return (ch - '0'); // Handle numerals
3647 if (ch >= 'A' && ch <= 'F') return (ch - 'A' + 0xA); // Handle capitol hex digits
3648 if (ch >= 'a' && ch <= 'f') return (ch - 'a' + 0xA); // Handle small hex digits
3649 return(255);
3650 }
3651
3652 //
3653 // FUNCTION: AtoH(char *, UCHAR *, int)
3654 //
3655 // PURPOSE: Converts ascii string to network order hex
3656 //
3657 // PARAMETERS:
3658 // src - pointer to input ascii string
3659 // dest - pointer to output hex
3660 // destlen - size of dest
3661 //
3662 // COMMENTS:
3663 //
3664 // 2 ascii bytes make a hex byte so must put 1st ascii byte of pair
3665 // into upper nibble and 2nd ascii byte of pair into lower nibble.
3666 //
3667 // IRQL = PASSIVE_LEVEL
3668
3669 void AtoH(char * src, UCHAR * dest, int destlen)
3670 {
3671 char * srcptr;
3672 PUCHAR destTemp;
3673
3674 srcptr = src;
3675 destTemp = (PUCHAR) dest;
3676
3677 while(destlen--)
3678 {
3679 *destTemp = BtoH(*srcptr++) << 4; // Put 1st ascii byte in upper nibble.
3680 *destTemp += BtoH(*srcptr++); // Add 2nd ascii byte to above.
3681 destTemp++;
3682 }
3683 }
3684
3685 VOID RTMPPatchMacBbpBug(
3686 IN PRTMP_ADAPTER pAd)
3687 {
3688 ULONG Index;
3689
3690 // Initialize BBP register to default value
3691 for (Index = 0; Index < NUM_BBP_REG_PARMS; Index++)
3692 {
3693 RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBPRegTable[Index].Register, (UCHAR)BBPRegTable[Index].Value);
3694 }
3695
3696 // Initialize RF register to default value
3697 AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, FALSE);
3698 AsicLockChannel(pAd, pAd->CommonCfg.Channel);
3699
3700 // Re-init BBP register from EEPROM value
3701 NICInitAsicFromEEPROM(pAd);
3702 }
3703
3704 /*
3705 ========================================================================
3706
3707 Routine Description:
3708 Init timer objects
3709
3710 Arguments:
3711 pAd Pointer to our adapter
3712 pTimer Timer structure
3713 pTimerFunc Function to execute when timer expired
3714 Repeat Ture for period timer
3715
3716 Return Value:
3717 None
3718
3719 Note:
3720
3721 ========================================================================
3722 */
3723 VOID RTMPInitTimer(
3724 IN PRTMP_ADAPTER pAd,
3725 IN PRALINK_TIMER_STRUCT pTimer,
3726 IN PVOID pTimerFunc,
3727 IN PVOID pData,
3728 IN BOOLEAN Repeat)
3729 {
3730 //
3731 // Set Valid to TRUE for later used.
3732 // It will crash if we cancel a timer or set a timer
3733 // that we haven't initialize before.
3734 //
3735 pTimer->Valid = TRUE;
3736
3737 pTimer->PeriodicType = Repeat;
3738 pTimer->State = FALSE;
3739 pTimer->cookie = (ULONG) pData;
3740
3741 #ifdef RT2870
3742 pTimer->pAd = pAd;
3743 #endif // RT2870 //
3744
3745 RTMP_OS_Init_Timer(pAd, &pTimer->TimerObj, pTimerFunc, (PVOID) pTimer);
3746 }
3747
3748 /*
3749 ========================================================================
3750
3751 Routine Description:
3752 Init timer objects
3753
3754 Arguments:
3755 pTimer Timer structure
3756 Value Timer value in milliseconds
3757
3758 Return Value:
3759 None
3760
3761 Note:
3762 To use this routine, must call RTMPInitTimer before.
3763
3764 ========================================================================
3765 */
3766 VOID RTMPSetTimer(
3767 IN PRALINK_TIMER_STRUCT pTimer,
3768 IN ULONG Value)
3769 {
3770 if (pTimer->Valid)
3771 {
3772 pTimer->TimerValue = Value;
3773 pTimer->State = FALSE;
3774 if (pTimer->PeriodicType == TRUE)
3775 {
3776 pTimer->Repeat = TRUE;
3777 RTMP_SetPeriodicTimer(&pTimer->TimerObj, Value);
3778 }
3779 else
3780 {
3781 pTimer->Repeat = FALSE;
3782 RTMP_OS_Add_Timer(&pTimer->TimerObj, Value);
3783 }
3784 }
3785 else
3786 {
3787 DBGPRINT_ERR(("RTMPSetTimer failed, Timer hasn't been initialize!\n"));
3788 }
3789 }
3790
3791
3792 /*
3793 ========================================================================
3794
3795 Routine Description:
3796 Init timer objects
3797
3798 Arguments:
3799 pTimer Timer structure
3800 Value Timer value in milliseconds
3801
3802 Return Value:
3803 None
3804
3805 Note:
3806 To use this routine, must call RTMPInitTimer before.
3807
3808 ========================================================================
3809 */
3810 VOID RTMPModTimer(
3811 IN PRALINK_TIMER_STRUCT pTimer,
3812 IN ULONG Value)
3813 {
3814 BOOLEAN Cancel;
3815
3816 if (pTimer->Valid)
3817 {
3818 pTimer->TimerValue = Value;
3819 pTimer->State = FALSE;
3820 if (pTimer->PeriodicType == TRUE)
3821 {
3822 RTMPCancelTimer(pTimer, &Cancel);
3823 RTMPSetTimer(pTimer, Value);
3824 }
3825 else
3826 {
3827 RTMP_OS_Mod_Timer(&pTimer->TimerObj, Value);
3828 }
3829 }
3830 else
3831 {
3832 DBGPRINT_ERR(("RTMPModTimer failed, Timer hasn't been initialize!\n"));
3833 }
3834 }
3835
3836 /*
3837 ========================================================================
3838
3839 Routine Description:
3840 Cancel timer objects
3841
3842 Arguments:
3843 Adapter Pointer to our adapter
3844
3845 Return Value:
3846 None
3847
3848 IRQL = PASSIVE_LEVEL
3849 IRQL = DISPATCH_LEVEL
3850
3851 Note:
3852 1.) To use this routine, must call RTMPInitTimer before.
3853 2.) Reset NIC to initial state AS IS system boot up time.
3854
3855 ========================================================================
3856 */
3857 VOID RTMPCancelTimer(
3858 IN PRALINK_TIMER_STRUCT pTimer,
3859 OUT BOOLEAN *pCancelled)
3860 {
3861 if (pTimer->Valid)
3862 {
3863 if (pTimer->State == FALSE)
3864 pTimer->Repeat = FALSE;
3865 RTMP_OS_Del_Timer(&pTimer->TimerObj, pCancelled);
3866
3867 if (*pCancelled == TRUE)
3868 pTimer->State = TRUE;
3869
3870 #ifdef RT2870
3871 // We need to go-through the TimerQ to findout this timer handler and remove it if
3872 // it's still waiting for execution.
3873
3874 RT2870_TimerQ_Remove(pTimer->pAd, pTimer);
3875 #endif // RT2870 //
3876 }
3877 else
3878 {
3879 //
3880 // NdisMCancelTimer just canced the timer and not mean release the timer.
3881 // And don't set the "Valid" to False. So that we can use this timer again.
3882 //
3883 DBGPRINT_ERR(("RTMPCancelTimer failed, Timer hasn't been initialize!\n"));
3884 }
3885 }
3886
3887 /*
3888 ========================================================================
3889
3890 Routine Description:
3891 Set LED Status
3892
3893 Arguments:
3894 pAd Pointer to our adapter
3895 Status LED Status
3896
3897 Return Value:
3898 None
3899
3900 IRQL = PASSIVE_LEVEL
3901 IRQL = DISPATCH_LEVEL
3902
3903 Note:
3904
3905 ========================================================================
3906 */
3907 VOID RTMPSetLED(
3908 IN PRTMP_ADAPTER pAd,
3909 IN UCHAR Status)
3910 {
3911 //ULONG data;
3912 UCHAR HighByte = 0;
3913 UCHAR LowByte;
3914
3915 LowByte = pAd->LedCntl.field.LedMode&0x7f;
3916 switch (Status)
3917 {
3918 case LED_LINK_DOWN:
3919 HighByte = 0x20;
3920 AsicSendCommandToMcu(pAd, 0x50, 0xff, LowByte, HighByte);
3921 pAd->LedIndicatorStregth = 0;
3922 break;
3923 case LED_LINK_UP:
3924 if (pAd->CommonCfg.Channel > 14)
3925 HighByte = 0xa0;
3926 else
3927 HighByte = 0x60;
3928 AsicSendCommandToMcu(pAd, 0x50, 0xff, LowByte, HighByte);
3929 break;
3930 case LED_RADIO_ON:
3931 HighByte = 0x20;
3932 AsicSendCommandToMcu(pAd, 0x50, 0xff, LowByte, HighByte);
3933 break;
3934 case LED_HALT:
3935 LowByte = 0; // Driver sets MAC register and MAC controls LED
3936 case LED_RADIO_OFF:
3937 HighByte = 0;
3938 AsicSendCommandToMcu(pAd, 0x50, 0xff, LowByte, HighByte);
3939 break;
3940 case LED_WPS:
3941 HighByte = 0x10;
3942 AsicSendCommandToMcu(pAd, 0x50, 0xff, LowByte, HighByte);
3943 break;
3944 case LED_ON_SITE_SURVEY:
3945 HighByte = 0x08;
3946 AsicSendCommandToMcu(pAd, 0x50, 0xff, LowByte, HighByte);
3947 break;
3948 case LED_POWER_UP:
3949 HighByte = 0x04;
3950 AsicSendCommandToMcu(pAd, 0x50, 0xff, LowByte, HighByte);
3951 break;
3952 default:
3953 DBGPRINT(RT_DEBUG_WARN, ("RTMPSetLED::Unknown Status %d\n", Status));
3954 break;
3955 }
3956
3957 //
3958 // Keep LED status for LED SiteSurvey mode.
3959 // After SiteSurvey, we will set the LED mode to previous status.
3960 //
3961 if ((Status != LED_ON_SITE_SURVEY) && (Status != LED_POWER_UP))
3962 pAd->LedStatus = Status;
3963
3964 DBGPRINT(RT_DEBUG_TRACE, ("RTMPSetLED::Mode=%d,HighByte=0x%02x,LowByte=0x%02x\n", pAd->LedCntl.field.LedMode, HighByte, LowByte));
3965 }
3966
3967 /*
3968 ========================================================================
3969
3970 Routine Description:
3971 Set LED Signal Stregth
3972
3973 Arguments:
3974 pAd Pointer to our adapter
3975 Dbm Signal Stregth
3976
3977 Return Value:
3978 None
3979
3980 IRQL = PASSIVE_LEVEL
3981
3982 Note:
3983 Can be run on any IRQL level.
3984
3985 According to Microsoft Zero Config Wireless Signal Stregth definition as belows.
3986 <= -90 No Signal
3987 <= -81 Very Low
3988 <= -71 Low
3989 <= -67 Good
3990 <= -57 Very Good
3991 > -57 Excellent
3992 ========================================================================
3993 */
3994 VOID RTMPSetSignalLED(
3995 IN PRTMP_ADAPTER pAd,
3996 IN NDIS_802_11_RSSI Dbm)
3997 {
3998 UCHAR nLed = 0;
3999
4000 //
4001 // if not Signal Stregth, then do nothing.
4002 //
4003 if (pAd->LedCntl.field.LedMode != LED_MODE_SIGNAL_STREGTH)
4004 {
4005 return;
4006 }
4007
4008 if (Dbm <= -90)
4009 nLed = 0;
4010 else if (Dbm <= -81)
4011 nLed = 1;
4012 else if (Dbm <= -71)
4013 nLed = 3;
4014 else if (Dbm <= -67)
4015 nLed = 7;
4016 else if (Dbm <= -57)
4017 nLed = 15;
4018 else
4019 nLed = 31;
4020
4021 //
4022 // Update Signal Stregth to firmware if changed.
4023 //
4024 if (pAd->LedIndicatorStregth != nLed)
4025 {
4026 AsicSendCommandToMcu(pAd, 0x51, 0xff, nLed, pAd->LedCntl.field.Polarity);
4027 pAd->LedIndicatorStregth = nLed;
4028 }
4029 }
4030
4031 /*
4032 ========================================================================
4033
4034 Routine Description:
4035 Enable RX
4036
4037 Arguments:
4038 pAd Pointer to our adapter
4039
4040 Return Value:
4041 None
4042
4043 IRQL <= DISPATCH_LEVEL
4044
4045 Note:
4046 Before Enable RX, make sure you have enabled Interrupt.
4047 ========================================================================
4048 */
4049 VOID RTMPEnableRxTx(
4050 IN PRTMP_ADAPTER pAd)
4051 {
4052 DBGPRINT(RT_DEBUG_TRACE, ("==> RTMPEnableRxTx\n"));
4053
4054 // Enable Rx DMA.
4055 RT28XXDMAEnable(pAd);
4056
4057 // enable RX of MAC block
4058 if (pAd->OpMode == OPMODE_AP)
4059 {
4060 UINT32 rx_filter_flag = APNORMAL;
4061
4062
4063 RTMP_IO_WRITE32(pAd, RX_FILTR_CFG, rx_filter_flag); // enable RX of DMA block
4064 }
4065 else
4066 {
4067 RTMP_IO_WRITE32(pAd, RX_FILTR_CFG, STANORMAL); // Staion not drop control frame will fail WiFi Certification.
4068 }
4069
4070 RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0xc);
4071 DBGPRINT(RT_DEBUG_TRACE, ("<== RTMPEnableRxTx\n"));
4072 }
4073
4074
Support for the Chinese Samsung S3C2440 based development boards