arch/arm/mach-omap1/clock.h

   1 /*
   2  *  linux/arch/arm/mach-omap1/clock.h
   3  *
   4  *  Copyright (C) 2004 - 2005 Nokia corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H
  14 #define __ARCH_ARM_MACH_OMAP1_CLOCK_H
  15
  16 static int omap1_clk_enable_generic(struct clk * clk);
  17 static void omap1_clk_disable_generic(struct clk * clk);
  18 static void omap1_ckctl_recalc(struct clk * clk);
  19 static void omap1_watchdog_recalc(struct clk * clk);
  20 static void omap1_ckctl_recalc_dsp_domain(struct clk * clk);
  21 static int omap1_clk_enable_dsp_domain(struct clk * clk);
  22 static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate);
  23 static void omap1_clk_disable_dsp_domain(struct clk * clk);
  24 static int omap1_set_uart_rate(struct clk * clk, unsigned long rate);
  25 static void omap1_uart_recalc(struct clk * clk);
  26 static int omap1_clk_enable_uart_functional(struct clk * clk);
  27 static void omap1_clk_disable_uart_functional(struct clk * clk);
  28 static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate);
  29 static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate);
  30 static void omap1_init_ext_clk(struct clk * clk);
  31 static int omap1_select_table_rate(struct clk * clk, unsigned long rate);
  32 static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate);
  33 static int omap1_clk_enable(struct clk *clk);
  34 static void omap1_clk_disable(struct clk *clk);
  35
  36 struct mpu_rate {
  37         unsigned long           rate;
  38         unsigned long           xtal;
  39         unsigned long           pll_rate;
  40         __u16                   ckctl_val;
  41         __u16                   dpllctl_val;
  42 };
  43
  44 struct uart_clk {
  45         struct clk      clk;
  46         unsigned long   sysc_addr;
  47 };
  48
  49 /* Provide a method for preventing idling some ARM IDLECT clocks */
  50 struct arm_idlect1_clk {
  51         struct clk      clk;
  52         unsigned long   no_idle_count;
  53         __u8            idlect_shift;
  54 };
  55
  56 /* ARM_CKCTL bit shifts */
  57 #define CKCTL_PERDIV_OFFSET     0
  58 #define CKCTL_LCDDIV_OFFSET     2
  59 #define CKCTL_ARMDIV_OFFSET     4
  60 #define CKCTL_DSPDIV_OFFSET     6
  61 #define CKCTL_TCDIV_OFFSET      8
  62 #define CKCTL_DSPMMUDIV_OFFSET  10
  63 /*#define ARM_TIMXO             12*/
  64 #define EN_DSPCK                13
  65 /*#define ARM_INTHCK_SEL        14*/ /* Divide-by-2 for mpu inth_ck */
  66 /* DSP_CKCTL bit shifts */
  67 #define CKCTL_DSPPERDIV_OFFSET  0
  68
  69 /* ARM_IDLECT2 bit shifts */
  70 #define EN_WDTCK        0
  71 #define EN_XORPCK       1
  72 #define EN_PERCK        2
  73 #define EN_LCDCK        3
  74 #define EN_LBCK         4 /* Not on 1610/1710 */
  75 /*#define EN_HSABCK     5*/
  76 #define EN_APICK        6
  77 #define EN_TIMCK        7
  78 #define DMACK_REQ       8
  79 #define EN_GPIOCK       9 /* Not on 1610/1710 */
  80 /*#define EN_LBFREECK   10*/
  81 #define EN_CKOUT_ARM    11
  82
  83 /* ARM_IDLECT3 bit shifts */
  84 #define EN_OCPI_CK      0
  85 #define EN_TC1_CK       2
  86 #define EN_TC2_CK       4
  87
  88 /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */
  89 #define EN_DSPTIMCK     5
  90
  91 /* Various register defines for clock controls scattered around OMAP chip */
  92 #define SDW_MCLK_INV_BIT        2       /* In ULPD_CLKC_CTRL */
  93 #define USB_MCLK_EN_BIT         4       /* In ULPD_CLKC_CTRL */
  94 #define USB_HOST_HHC_UHOST_EN   9       /* In MOD_CONF_CTRL_0 */
  95 #define SWD_ULPD_PLL_CLK_REQ    1       /* In SWD_CLK_DIV_CTRL_SEL */
  96 #define COM_ULPD_PLL_CLK_REQ    1       /* In COM_CLK_DIV_CTRL_SEL */
  97 #define SWD_CLK_DIV_CTRL_SEL    0xfffe0874
  98 #define COM_CLK_DIV_CTRL_SEL    0xfffe0878
  99 #define SOFT_REQ_REG            0xfffe0834
 100 #define SOFT_REQ_REG2           0xfffe0880
 101
 102 /*-------------------------------------------------------------------------
 103  * Omap1 MPU rate table
 104  *-------------------------------------------------------------------------*/
 105 static struct mpu_rate rate_table[] = {
 106         /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
 107          * NOTE: Comment order here is different from bits in CKCTL value:
 108          * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
 109          */
 110 #if defined(CONFIG_OMAP_ARM_216MHZ)
 111         { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
 112 #endif
 113 #if defined(CONFIG_OMAP_ARM_195MHZ)
 114         { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
 115 #endif
 116 #if defined(CONFIG_OMAP_ARM_192MHZ)
 117         { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
 118         { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
 119         {  96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
 120         {  48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
 121         {  24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
 122 #endif
 123 #if defined(CONFIG_OMAP_ARM_182MHZ)
 124         { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
 125 #endif
 126 #if defined(CONFIG_OMAP_ARM_168MHZ)
 127         { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
 128 #endif
 129 #if defined(CONFIG_OMAP_ARM_150MHZ)
 130         { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
 131 #endif
 132 #if defined(CONFIG_OMAP_ARM_120MHZ)
 133         { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
 134 #endif
 135 #if defined(CONFIG_OMAP_ARM_96MHZ)
 136         {  96000000, 12000000,  96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
 137 #endif
 138 #if defined(CONFIG_OMAP_ARM_60MHZ)
 139         {  60000000, 12000000,  60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
 140 #endif
 141 #if defined(CONFIG_OMAP_ARM_30MHZ)
 142         {  30000000, 12000000,  60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
 143 #endif
 144         { 0, 0, 0, 0, 0 },
 145 };
 146
 147 /*-------------------------------------------------------------------------
 148  * Omap1 clocks
 149  *-------------------------------------------------------------------------*/
 150
 151 static struct clk ck_ref = {
 152         .name           = "ck_ref",
 153         .rate           = 12000000,
 154         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 155                           CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
 156         .enable         = &omap1_clk_enable_generic,
 157         .disable        = &omap1_clk_disable_generic,
 158 };
 159
 160 static struct clk ck_dpll1 = {
 161         .name           = "ck_dpll1",
 162         .parent         = &ck_ref,
 163         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 164                           CLOCK_IN_OMAP310 | RATE_PROPAGATES | ALWAYS_ENABLED,
 165         .enable         = &omap1_clk_enable_generic,
 166         .disable        = &omap1_clk_disable_generic,
 167 };
 168
 169 static struct arm_idlect1_clk ck_dpll1out = {
 170         .clk = {
 171                 .name           = "ck_dpll1out",
 172                 .parent         = &ck_dpll1,
 173                 .flags          = CLOCK_IN_OMAP16XX | CLOCK_IDLE_CONTROL,
 174                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 175                 .enable_bit     = EN_CKOUT_ARM,
 176                 .recalc         = &followparent_recalc,
 177                 .enable         = &omap1_clk_enable_generic,
 178                 .disable        = &omap1_clk_disable_generic,
 179         },
 180         .idlect_shift   = 12,
 181 };
 182
 183 static struct clk arm_ck = {
 184         .name           = "arm_ck",
 185         .parent         = &ck_dpll1,
 186         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 187                           CLOCK_IN_OMAP310 | RATE_CKCTL | RATE_PROPAGATES |
 188                           ALWAYS_ENABLED,
 189         .rate_offset    = CKCTL_ARMDIV_OFFSET,
 190         .recalc         = &omap1_ckctl_recalc,
 191         .enable         = &omap1_clk_enable_generic,
 192         .disable        = &omap1_clk_disable_generic,
 193 };
 194
 195 static struct arm_idlect1_clk armper_ck = {
 196         .clk = {
 197                 .name           = "armper_ck",
 198                 .parent         = &ck_dpll1,
 199                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 200                                   CLOCK_IN_OMAP310 | RATE_CKCTL |
 201                                   CLOCK_IDLE_CONTROL,
 202                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 203                 .enable_bit     = EN_PERCK,
 204                 .rate_offset    = CKCTL_PERDIV_OFFSET,
 205                 .recalc         = &omap1_ckctl_recalc,
 206                 .enable         = &omap1_clk_enable_generic,
 207                 .disable        = &omap1_clk_disable_generic,
 208         },
 209         .idlect_shift   = 2,
 210 };
 211
 212 static struct clk arm_gpio_ck = {
 213         .name           = "arm_gpio_ck",
 214         .parent         = &ck_dpll1,
 215         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
 216         .enable_reg     = (void __iomem *)ARM_IDLECT2,
 217         .enable_bit     = EN_GPIOCK,
 218         .recalc         = &followparent_recalc,
 219         .enable         = &omap1_clk_enable_generic,
 220         .disable        = &omap1_clk_disable_generic,
 221 };
 222
 223 static struct arm_idlect1_clk armxor_ck = {
 224         .clk = {
 225                 .name           = "armxor_ck",
 226                 .parent         = &ck_ref,
 227                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 228                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 229                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 230                 .enable_bit     = EN_XORPCK,
 231                 .recalc         = &followparent_recalc,
 232                 .enable         = &omap1_clk_enable_generic,
 233                 .disable        = &omap1_clk_disable_generic,
 234         },
 235         .idlect_shift   = 1,
 236 };
 237
 238 static struct arm_idlect1_clk armtim_ck = {
 239         .clk = {
 240                 .name           = "armtim_ck",
 241                 .parent         = &ck_ref,
 242                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 243                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 244                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 245                 .enable_bit     = EN_TIMCK,
 246                 .recalc         = &followparent_recalc,
 247                 .enable         = &omap1_clk_enable_generic,
 248                 .disable        = &omap1_clk_disable_generic,
 249         },
 250         .idlect_shift   = 9,
 251 };
 252
 253 static struct arm_idlect1_clk armwdt_ck = {
 254         .clk = {
 255                 .name           = "armwdt_ck",
 256                 .parent         = &ck_ref,
 257                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 258                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 259                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 260                 .enable_bit     = EN_WDTCK,
 261                 .recalc         = &omap1_watchdog_recalc,
 262                 .enable         = &omap1_clk_enable_generic,
 263                 .disable        = &omap1_clk_disable_generic,
 264         },
 265         .idlect_shift   = 0,
 266 };
 267
 268 static struct clk arminth_ck16xx = {
 269         .name           = "arminth_ck",
 270         .parent         = &arm_ck,
 271         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 272         .recalc         = &followparent_recalc,
 273         /* Note: On 16xx the frequency can be divided by 2 by programming
 274          * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
 275          *
 276          * 1510 version is in TC clocks.
 277          */
 278         .enable         = &omap1_clk_enable_generic,
 279         .disable        = &omap1_clk_disable_generic,
 280 };
 281
 282 static struct clk dsp_ck = {
 283         .name           = "dsp_ck",
 284         .parent         = &ck_dpll1,
 285         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 286                           RATE_CKCTL,
 287         .enable_reg     = (void __iomem *)ARM_CKCTL,
 288         .enable_bit     = EN_DSPCK,
 289         .rate_offset    = CKCTL_DSPDIV_OFFSET,
 290         .recalc         = &omap1_ckctl_recalc,
 291         .enable         = &omap1_clk_enable_generic,
 292         .disable        = &omap1_clk_disable_generic,
 293 };
 294
 295 static struct clk dspmmu_ck = {
 296         .name           = "dspmmu_ck",
 297         .parent         = &ck_dpll1,
 298         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 299                           RATE_CKCTL | ALWAYS_ENABLED,
 300         .rate_offset    = CKCTL_DSPMMUDIV_OFFSET,
 301         .recalc         = &omap1_ckctl_recalc,
 302         .enable         = &omap1_clk_enable_generic,
 303         .disable        = &omap1_clk_disable_generic,
 304 };
 305
 306 static struct clk dspper_ck = {
 307         .name           = "dspper_ck",
 308         .parent         = &ck_dpll1,
 309         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 310                           RATE_CKCTL | VIRTUAL_IO_ADDRESS,
 311         .enable_reg     = (void __iomem *)DSP_IDLECT2,
 312         .enable_bit     = EN_PERCK,
 313         .rate_offset    = CKCTL_PERDIV_OFFSET,
 314         .recalc         = &omap1_ckctl_recalc_dsp_domain,
 315         .set_rate       = &omap1_clk_set_rate_dsp_domain,
 316         .enable         = &omap1_clk_enable_dsp_domain,
 317         .disable        = &omap1_clk_disable_dsp_domain,
 318 };
 319
 320 static struct clk dspxor_ck = {
 321         .name           = "dspxor_ck",
 322         .parent         = &ck_ref,
 323         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 324                           VIRTUAL_IO_ADDRESS,
 325         .enable_reg     = (void __iomem *)DSP_IDLECT2,
 326         .enable_bit     = EN_XORPCK,
 327         .recalc         = &followparent_recalc,
 328         .enable         = &omap1_clk_enable_dsp_domain,
 329         .disable        = &omap1_clk_disable_dsp_domain,
 330 };
 331
 332 static struct clk dsptim_ck = {
 333         .name           = "dsptim_ck",
 334         .parent         = &ck_ref,
 335         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 336                           VIRTUAL_IO_ADDRESS,
 337         .enable_reg     = (void __iomem *)DSP_IDLECT2,
 338         .enable_bit     = EN_DSPTIMCK,
 339         .recalc         = &followparent_recalc,
 340         .enable         = &omap1_clk_enable_dsp_domain,
 341         .disable        = &omap1_clk_disable_dsp_domain,
 342 };
 343
 344 /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
 345 static struct arm_idlect1_clk tc_ck = {
 346         .clk = {
 347                 .name           = "tc_ck",
 348                 .parent         = &ck_dpll1,
 349                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 350                                   CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
 351                                   RATE_CKCTL | RATE_PROPAGATES |
 352                                   ALWAYS_ENABLED | CLOCK_IDLE_CONTROL,
 353                 .rate_offset    = CKCTL_TCDIV_OFFSET,
 354                 .recalc         = &omap1_ckctl_recalc,
 355                 .enable         = &omap1_clk_enable_generic,
 356                 .disable        = &omap1_clk_disable_generic,
 357         },
 358         .idlect_shift   = 6,
 359 };
 360
 361 static struct clk arminth_ck1510 = {
 362         .name           = "arminth_ck",
 363         .parent         = &tc_ck.clk,
 364         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 365                           ALWAYS_ENABLED,
 366         .recalc         = &followparent_recalc,
 367         /* Note: On 1510 the frequency follows TC_CK
 368          *
 369          * 16xx version is in MPU clocks.
 370          */
 371         .enable         = &omap1_clk_enable_generic,
 372         .disable        = &omap1_clk_disable_generic,
 373 };
 374
 375 static struct clk tipb_ck = {
 376         /* No-idle controlled by "tc_ck" */
 377         .name           = "tipb_ck",
 378         .parent         = &tc_ck.clk,
 379         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 380                           ALWAYS_ENABLED,
 381         .recalc         = &followparent_recalc,
 382         .enable         = &omap1_clk_enable_generic,
 383         .disable        = &omap1_clk_disable_generic,
 384 };
 385
 386 static struct clk l3_ocpi_ck = {
 387         /* No-idle controlled by "tc_ck" */
 388         .name           = "l3_ocpi_ck",
 389         .parent         = &tc_ck.clk,
 390         .flags          = CLOCK_IN_OMAP16XX,
 391         .enable_reg     = (void __iomem *)ARM_IDLECT3,
 392         .enable_bit     = EN_OCPI_CK,
 393         .recalc         = &followparent_recalc,
 394         .enable         = &omap1_clk_enable_generic,
 395         .disable        = &omap1_clk_disable_generic,
 396 };
 397
 398 static struct clk tc1_ck = {
 399         .name           = "tc1_ck",
 400         .parent         = &tc_ck.clk,
 401         .flags          = CLOCK_IN_OMAP16XX,
 402         .enable_reg     = (void __iomem *)ARM_IDLECT3,
 403         .enable_bit     = EN_TC1_CK,
 404         .recalc         = &followparent_recalc,
 405         .enable         = &omap1_clk_enable_generic,
 406         .disable        = &omap1_clk_disable_generic,
 407 };
 408
 409 static struct clk tc2_ck = {
 410         .name           = "tc2_ck",
 411         .parent         = &tc_ck.clk,
 412         .flags          = CLOCK_IN_OMAP16XX,
 413         .enable_reg     = (void __iomem *)ARM_IDLECT3,
 414         .enable_bit     = EN_TC2_CK,
 415         .recalc         = &followparent_recalc,
 416         .enable         = &omap1_clk_enable_generic,
 417         .disable        = &omap1_clk_disable_generic,
 418 };
 419
 420 static struct clk dma_ck = {
 421         /* No-idle controlled by "tc_ck" */
 422         .name           = "dma_ck",
 423         .parent         = &tc_ck.clk,
 424         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 425                           CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
 426         .recalc         = &followparent_recalc,
 427         .enable         = &omap1_clk_enable_generic,
 428         .disable        = &omap1_clk_disable_generic,
 429 };
 430
 431 static struct clk dma_lcdfree_ck = {
 432         .name           = "dma_lcdfree_ck",
 433         .parent         = &tc_ck.clk,
 434         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 435         .recalc         = &followparent_recalc,
 436         .enable         = &omap1_clk_enable_generic,
 437         .disable        = &omap1_clk_disable_generic,
 438 };
 439
 440 static struct arm_idlect1_clk api_ck = {
 441         .clk = {
 442                 .name           = "api_ck",
 443                 .parent         = &tc_ck.clk,
 444                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 445                                   CLOCK_IN_OMAP310 | CLOCK_IDLE_CONTROL,
 446                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 447                 .enable_bit     = EN_APICK,
 448                 .recalc         = &followparent_recalc,
 449                 .enable         = &omap1_clk_enable_generic,
 450                 .disable        = &omap1_clk_disable_generic,
 451         },
 452         .idlect_shift   = 8,
 453 };
 454
 455 static struct arm_idlect1_clk lb_ck = {
 456         .clk = {
 457                 .name           = "lb_ck",
 458                 .parent         = &tc_ck.clk,
 459                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 460                                   CLOCK_IDLE_CONTROL,
 461                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 462                 .enable_bit     = EN_LBCK,
 463                 .recalc         = &followparent_recalc,
 464                 .enable         = &omap1_clk_enable_generic,
 465                 .disable        = &omap1_clk_disable_generic,
 466         },
 467         .idlect_shift   = 4,
 468 };
 469
 470 static struct clk rhea1_ck = {
 471         .name           = "rhea1_ck",
 472         .parent         = &tc_ck.clk,
 473         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 474         .recalc         = &followparent_recalc,
 475         .enable         = &omap1_clk_enable_generic,
 476         .disable        = &omap1_clk_disable_generic,
 477 };
 478
 479 static struct clk rhea2_ck = {
 480         .name           = "rhea2_ck",
 481         .parent         = &tc_ck.clk,
 482         .flags          = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
 483         .recalc         = &followparent_recalc,
 484         .enable         = &omap1_clk_enable_generic,
 485         .disable        = &omap1_clk_disable_generic,
 486 };
 487
 488 static struct clk lcd_ck_16xx = {
 489         .name           = "lcd_ck",
 490         .parent         = &ck_dpll1,
 491         .flags          = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730 | RATE_CKCTL,
 492         .enable_reg     = (void __iomem *)ARM_IDLECT2,
 493         .enable_bit     = EN_LCDCK,
 494         .rate_offset    = CKCTL_LCDDIV_OFFSET,
 495         .recalc         = &omap1_ckctl_recalc,
 496         .enable         = &omap1_clk_enable_generic,
 497         .disable        = &omap1_clk_disable_generic,
 498 };
 499
 500 static struct arm_idlect1_clk lcd_ck_1510 = {
 501         .clk = {
 502                 .name           = "lcd_ck",
 503                 .parent         = &ck_dpll1,
 504                 .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 505                                   RATE_CKCTL | CLOCK_IDLE_CONTROL,
 506                 .enable_reg     = (void __iomem *)ARM_IDLECT2,
 507                 .enable_bit     = EN_LCDCK,
 508                 .rate_offset    = CKCTL_LCDDIV_OFFSET,
 509                 .recalc         = &omap1_ckctl_recalc,
 510                 .enable         = &omap1_clk_enable_generic,
 511                 .disable        = &omap1_clk_disable_generic,
 512         },
 513         .idlect_shift   = 3,
 514 };
 515
 516 static struct clk uart1_1510 = {
 517         .name           = "uart1_ck",
 518         /* Direct from ULPD, no real parent */
 519         .parent         = &armper_ck.clk,
 520         .rate           = 12000000,
 521         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 522                           ENABLE_REG_32BIT | ALWAYS_ENABLED |
 523                           CLOCK_NO_IDLE_PARENT,
 524         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 525         .enable_bit     = 29,   /* Chooses between 12MHz and 48MHz */
 526         .set_rate       = &omap1_set_uart_rate,
 527         .recalc         = &omap1_uart_recalc,
 528         .enable         = &omap1_clk_enable_generic,
 529         .disable        = &omap1_clk_disable_generic,
 530 };
 531
 532 static struct uart_clk uart1_16xx = {
 533         .clk    = {
 534                 .name           = "uart1_ck",
 535                 /* Direct from ULPD, no real parent */
 536                 .parent         = &armper_ck.clk,
 537                 .rate           = 48000000,
 538                 .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED |
 539                                   ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 540                 .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 541                 .enable_bit     = 29,
 542                 .enable         = &omap1_clk_enable_uart_functional,
 543                 .disable        = &omap1_clk_disable_uart_functional,
 544         },
 545         .sysc_addr      = 0xfffb0054,
 546 };
 547
 548 static struct clk uart2_ck = {
 549         .name           = "uart2_ck",
 550         /* Direct from ULPD, no real parent */
 551         .parent         = &armper_ck.clk,
 552         .rate           = 12000000,
 553         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 554                           CLOCK_IN_OMAP310 | ENABLE_REG_32BIT |
 555                           ALWAYS_ENABLED | CLOCK_NO_IDLE_PARENT,
 556         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 557         .enable_bit     = 30,   /* Chooses between 12MHz and 48MHz */
 558         .set_rate       = &omap1_set_uart_rate,
 559         .recalc         = &omap1_uart_recalc,
 560         .enable         = &omap1_clk_enable_generic,
 561         .disable        = &omap1_clk_disable_generic,
 562 };
 563
 564 static struct clk uart3_1510 = {
 565         .name           = "uart3_ck",
 566         /* Direct from ULPD, no real parent */
 567         .parent         = &armper_ck.clk,
 568         .rate           = 12000000,
 569         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 570                           ENABLE_REG_32BIT | ALWAYS_ENABLED |
 571                           CLOCK_NO_IDLE_PARENT,
 572         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 573         .enable_bit     = 31,   /* Chooses between 12MHz and 48MHz */
 574         .set_rate       = &omap1_set_uart_rate,
 575         .recalc         = &omap1_uart_recalc,
 576         .enable         = &omap1_clk_enable_generic,
 577         .disable        = &omap1_clk_disable_generic,
 578 };
 579
 580 static struct uart_clk uart3_16xx = {
 581         .clk    = {
 582                 .name           = "uart3_ck",
 583                 /* Direct from ULPD, no real parent */
 584                 .parent         = &armper_ck.clk,
 585                 .rate           = 48000000,
 586                 .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED |
 587                                   ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 588                 .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 589                 .enable_bit     = 31,
 590                 .enable         = &omap1_clk_enable_uart_functional,
 591                 .disable        = &omap1_clk_disable_uart_functional,
 592         },
 593         .sysc_addr      = 0xfffb9854,
 594 };
 595
 596 static struct clk usb_clko = {  /* 6 MHz output on W4_USB_CLKO */
 597         .name           = "usb_clko",
 598         /* Direct from ULPD, no parent */
 599         .rate           = 6000000,
 600         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 601                           CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT,
 602         .enable_reg     = (void __iomem *)ULPD_CLOCK_CTRL,
 603         .enable_bit     = USB_MCLK_EN_BIT,
 604         .enable         = &omap1_clk_enable_generic,
 605         .disable        = &omap1_clk_disable_generic,
 606 };
 607
 608 static struct clk usb_hhc_ck1510 = {
 609         .name           = "usb_hhc_ck",
 610         /* Direct from ULPD, no parent */
 611         .rate           = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
 612         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 |
 613                           RATE_FIXED | ENABLE_REG_32BIT,
 614         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 615         .enable_bit     = USB_HOST_HHC_UHOST_EN,
 616         .enable         = &omap1_clk_enable_generic,
 617         .disable        = &omap1_clk_disable_generic,
 618 };
 619
 620 static struct clk usb_hhc_ck16xx = {
 621         .name           = "usb_hhc_ck",
 622         /* Direct from ULPD, no parent */
 623         .rate           = 48000000,
 624         /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
 625         .flags          = CLOCK_IN_OMAP16XX |
 626                           RATE_FIXED | ENABLE_REG_32BIT,
 627         .enable_reg     = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */,
 628         .enable_bit     = 8 /* UHOST_EN */,
 629         .enable         = &omap1_clk_enable_generic,
 630         .disable        = &omap1_clk_disable_generic,
 631 };
 632
 633 static struct clk usb_dc_ck = {
 634         .name           = "usb_dc_ck",
 635         /* Direct from ULPD, no parent */
 636         .rate           = 48000000,
 637         .flags          = CLOCK_IN_OMAP16XX | RATE_FIXED,
 638         .enable_reg     = (void __iomem *)SOFT_REQ_REG,
 639         .enable_bit     = 4,
 640         .enable         = &omap1_clk_enable_generic,
 641         .disable        = &omap1_clk_disable_generic,
 642 };
 643
 644 static struct clk mclk_1510 = {
 645         .name           = "mclk",
 646         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 647         .rate           = 12000000,
 648         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
 649         .enable_reg     = (void __iomem *)SOFT_REQ_REG,
 650         .enable_bit     = 6,
 651         .enable         = &omap1_clk_enable_generic,
 652         .disable        = &omap1_clk_disable_generic,
 653 };
 654
 655 static struct clk mclk_16xx = {
 656         .name           = "mclk",
 657         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 658         .flags          = CLOCK_IN_OMAP16XX,
 659         .enable_reg     = (void __iomem *)COM_CLK_DIV_CTRL_SEL,
 660         .enable_bit     = COM_ULPD_PLL_CLK_REQ,
 661         .set_rate       = &omap1_set_ext_clk_rate,
 662         .round_rate     = &omap1_round_ext_clk_rate,
 663         .init           = &omap1_init_ext_clk,
 664         .enable         = &omap1_clk_enable_generic,
 665         .disable        = &omap1_clk_disable_generic,
 666 };
 667
 668 static struct clk bclk_1510 = {
 669         .name           = "bclk",
 670         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 671         .rate           = 12000000,
 672         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | RATE_FIXED,
 673         .enable         = &omap1_clk_enable_generic,
 674         .disable        = &omap1_clk_disable_generic,
 675 };
 676
 677 static struct clk bclk_16xx = {
 678         .name           = "bclk",
 679         /* Direct from ULPD, no parent. May be enabled by ext hardware. */
 680         .flags          = CLOCK_IN_OMAP16XX,
 681         .enable_reg     = (void __iomem *)SWD_CLK_DIV_CTRL_SEL,
 682         .enable_bit     = SWD_ULPD_PLL_CLK_REQ,
 683         .set_rate       = &omap1_set_ext_clk_rate,
 684         .round_rate     = &omap1_round_ext_clk_rate,
 685         .init           = &omap1_init_ext_clk,
 686         .enable         = &omap1_clk_enable_generic,
 687         .disable        = &omap1_clk_disable_generic,
 688 };
 689
 690 static struct clk mmc1_ck = {
 691         .name           = "mmc_ck",
 692         .id             = 1,
 693         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 694         .parent         = &armper_ck.clk,
 695         .rate           = 48000000,
 696         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 697                           CLOCK_IN_OMAP310 | RATE_FIXED | ENABLE_REG_32BIT |
 698                           CLOCK_NO_IDLE_PARENT,
 699         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 700         .enable_bit     = 23,
 701         .enable         = &omap1_clk_enable_generic,
 702         .disable        = &omap1_clk_disable_generic,
 703 };
 704
 705 static struct clk mmc2_ck = {
 706         .name           = "mmc_ck",
 707         .id             = 2,
 708         /* Functional clock is direct from ULPD, interface clock is ARMPER */
 709         .parent         = &armper_ck.clk,
 710         .rate           = 48000000,
 711         .flags          = CLOCK_IN_OMAP16XX |
 712                           RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
 713         .enable_reg     = (void __iomem *)MOD_CONF_CTRL_0,
 714         .enable_bit     = 20,
 715         .enable         = &omap1_clk_enable_generic,
 716         .disable        = &omap1_clk_disable_generic,
 717 };
 718
 719 static struct clk virtual_ck_mpu = {
 720         .name           = "mpu",
 721         .flags          = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 722                           CLOCK_IN_OMAP310 | VIRTUAL_CLOCK | ALWAYS_ENABLED,
 723         .parent         = &arm_ck, /* Is smarter alias for */
 724         .recalc         = &followparent_recalc,
 725         .set_rate       = &omap1_select_table_rate,
 726         .round_rate     = &omap1_round_to_table_rate,
 727         .enable         = &omap1_clk_enable_generic,
 728         .disable        = &omap1_clk_disable_generic,
 729 };
 730
 731 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
 732 remains active during MPU idle whenever this is enabled */
 733 static struct clk i2c_fck = {
 734         .name           = "i2c_fck",
 735         .id             = 1,
 736         .flags          = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
 737                           VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT |
 738                           ALWAYS_ENABLED,
 739         .parent         = &armxor_ck.clk,
 740         .recalc         = &followparent_recalc,
 741         .enable         = &omap1_clk_enable_generic,
 742         .disable        = &omap1_clk_disable_generic,
 743 };
 744
 745 static struct clk i2c_ick = {
 746         .name           = "i2c_ick",
 747         .id             = 1,
 748         .flags          = CLOCK_IN_OMAP16XX |
 749                           VIRTUAL_CLOCK | CLOCK_NO_IDLE_PARENT |
 750                           ALWAYS_ENABLED,
 751         .parent         = &armper_ck.clk,
 752         .recalc         = &followparent_recalc,
 753         .enable         = &omap1_clk_enable_generic,
 754         .disable        = &omap1_clk_disable_generic,
 755 };
 756
 757 static struct clk * onchip_clks[] = {
 758         /* non-ULPD clocks */
 759         &ck_ref,
 760         &ck_dpll1,
 761         /* CK_GEN1 clocks */
 762         &ck_dpll1out.clk,
 763         &arm_ck,
 764         &armper_ck.clk,
 765         &arm_gpio_ck,
 766         &armxor_ck.clk,
 767         &armtim_ck.clk,
 768         &armwdt_ck.clk,
 769         &arminth_ck1510,  &arminth_ck16xx,
 770         /* CK_GEN2 clocks */
 771         &dsp_ck,
 772         &dspmmu_ck,
 773         &dspper_ck,
 774         &dspxor_ck,
 775         &dsptim_ck,
 776         /* CK_GEN3 clocks */
 777         &tc_ck.clk,
 778         &tipb_ck,
 779         &l3_ocpi_ck,
 780         &tc1_ck,
 781         &tc2_ck,
 782         &dma_ck,
 783         &dma_lcdfree_ck,
 784         &api_ck.clk,
 785         &lb_ck.clk,
 786         &rhea1_ck,
 787         &rhea2_ck,
 788         &lcd_ck_16xx,
 789         &lcd_ck_1510.clk,
 790         /* ULPD clocks */
 791         &uart1_1510,
 792         &uart1_16xx.clk,
 793         &uart2_ck,
 794         &uart3_1510,
 795         &uart3_16xx.clk,
 796         &usb_clko,
 797         &usb_hhc_ck1510, &usb_hhc_ck16xx,
 798         &usb_dc_ck,
 799         &mclk_1510,  &mclk_16xx,
 800         &bclk_1510,  &bclk_16xx,
 801         &mmc1_ck,
 802         &mmc2_ck,
 803         /* Virtual clocks */
 804         &virtual_ck_mpu,
 805         &i2c_fck,
 806         &i2c_ick,
 807 };
 808
 809 #endif