2 * linux/arch/arm/mach-omap2/memory.c
4 * Memory timing related functions for OMAP24XX
6 * Copyright (C) 2005 Texas Instruments Inc.
7 * Richard Woodruff <r-woodruff2@ti.com>
9 * Copyright (C) 2005 Nokia Corporation
10 * Tony Lindgren <tony@atomide.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
26 #include <mach/common.h>
27 #include <mach/clock.h>
28 #include <mach/sram.h>
35 void __iomem
*omap2_sdrc_base
;
36 void __iomem
*omap2_sms_base
;
38 static struct memory_timings mem_timings
;
39 static u32 curr_perf_level
= CORE_CLK_SRC_DPLL_X2
;
41 u32
omap2_memory_get_slow_dll_ctrl(void)
43 return mem_timings
.slow_dll_ctrl
;
46 u32
omap2_memory_get_fast_dll_ctrl(void)
48 return mem_timings
.fast_dll_ctrl
;
51 u32
omap2_memory_get_type(void)
53 return mem_timings
.m_type
;
57 * Check the DLL lock state, and return tue if running in unlock mode.
58 * This is needed to compensate for the shifted DLL value in unlock mode.
60 u32
omap2_dll_force_needed(void)
62 /* dlla and dllb are a set */
63 u32 dll_state
= sdrc_read_reg(SDRC_DLLA_CTRL
);
65 if ((dll_state
& (1 << 2)) == (1 << 2))
72 * 'level' is the value to store to CM_CLKSEL2_PLL.CORE_CLK_SRC.
73 * Practical values are CORE_CLK_SRC_DPLL (for CORE_CLK = DPLL_CLK) or
74 * CORE_CLK_SRC_DPLL_X2 (for CORE_CLK = * DPLL_CLK * 2)
76 u32
omap2_reprogram_sdrc(u32 level
, u32 force
)
79 u32 prev
= curr_perf_level
;
82 if ((curr_perf_level
== level
) && !force
)
85 if (level
== CORE_CLK_SRC_DPLL
) {
86 dll_ctrl
= omap2_memory_get_slow_dll_ctrl();
87 } else if (level
== CORE_CLK_SRC_DPLL_X2
) {
88 dll_ctrl
= omap2_memory_get_fast_dll_ctrl();
93 m_type
= omap2_memory_get_type();
95 local_irq_save(flags
);
96 __raw_writel(0xffff, OMAP24XX_PRCM_VOLTSETUP
);
97 omap2_sram_reprogram_sdrc(level
, dll_ctrl
, m_type
);
98 curr_perf_level
= level
;
99 local_irq_restore(flags
);
104 #if !defined(CONFIG_ARCH_OMAP2)
105 void omap2_sram_ddr_init(u32
*slow_dll_ctrl
, u32 fast_dll_ctrl
,
106 u32 base_cs
, u32 force_unlock
)
109 void omap2_sram_reprogram_sdrc(u32 perf_level
, u32 dll_val
,
115 void omap2_init_memory_params(u32 force_lock_to_unlock_mode
)
117 unsigned long dll_cnt
;
120 mem_timings
.m_type
= !((sdrc_read_reg(SDRC_MR_0
) & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
122 /* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
123 * In the case of 2422, its ok to use CS1 instead of CS0.
125 if (cpu_is_omap2422())
126 mem_timings
.base_cs
= 1;
128 mem_timings
.base_cs
= 0;
130 if (mem_timings
.m_type
!= M_DDR
)
133 /* With DDR we need to determine the low frequency DLL value */
134 if (((mem_timings
.fast_dll_ctrl
& (1 << 2)) == M_LOCK_CTRL
))
135 mem_timings
.dll_mode
= M_UNLOCK
;
137 mem_timings
.dll_mode
= M_LOCK
;
139 if (mem_timings
.base_cs
== 0) {
140 fast_dll
= sdrc_read_reg(SDRC_DLLA_CTRL
);
141 dll_cnt
= sdrc_read_reg(SDRC_DLLA_STATUS
) & 0xff00;
143 fast_dll
= sdrc_read_reg(SDRC_DLLB_CTRL
);
144 dll_cnt
= sdrc_read_reg(SDRC_DLLB_STATUS
) & 0xff00;
146 if (force_lock_to_unlock_mode
) {
148 fast_dll
|= dll_cnt
; /* Current lock mode */
150 /* set fast timings with DLL filter disabled */
151 mem_timings
.fast_dll_ctrl
= (fast_dll
| (3 << 8));
153 /* No disruptions, DDR will be offline & C-ABI not followed */
154 omap2_sram_ddr_init(&mem_timings
.slow_dll_ctrl
,
155 mem_timings
.fast_dll_ctrl
,
157 force_lock_to_unlock_mode
);
158 mem_timings
.slow_dll_ctrl
&= 0xff00; /* Keep lock value */
160 /* Turn status into unlock ctrl */
161 mem_timings
.slow_dll_ctrl
|=
162 ((mem_timings
.fast_dll_ctrl
& 0xF) | (1 << 2));
164 /* 90 degree phase for anything below 133Mhz + disable DLL filter */
165 mem_timings
.slow_dll_ctrl
|= ((1 << 1) | (3 << 8));
168 void __init
omap2_set_globals_memory(struct omap_globals
*omap2_globals
)
170 omap2_sdrc_base
= omap2_globals
->sdrc
;
171 omap2_sms_base
= omap2_globals
->sms
;
174 /* turn on smart idle modes for SDRAM scheduler and controller */
175 void __init
omap2_init_memory(void)
179 if (!cpu_is_omap2420())
182 l
= sms_read_reg(SMS_SYSCONFIG
);
185 sms_write_reg(l
, SMS_SYSCONFIG
);
187 l
= sdrc_read_reg(SDRC_SYSCONFIG
);
190 sdrc_write_reg(l
, SDRC_SYSCONFIG
);