2 * linux/arch/arm/plat-omap/mcbsp.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Multichannel mode not supported.
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/device.h>
18 #include <linux/platform_device.h>
19 #include <linux/wait.h>
20 #include <linux/completion.h>
21 #include <linux/interrupt.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/delay.h>
28 #include <mach/mcbsp.h>
30 struct omap_mcbsp
**mcbsp_ptr
;
33 void omap_mcbsp_write(void __iomem
*io_base
, u16 reg
, u32 val
)
35 if (cpu_class_is_omap1() || cpu_is_omap2420())
36 __raw_writew((u16
)val
, io_base
+ reg
);
38 __raw_writel(val
, io_base
+ reg
);
41 int omap_mcbsp_read(void __iomem
*io_base
, u16 reg
)
43 if (cpu_class_is_omap1() || cpu_is_omap2420())
44 return __raw_readw(io_base
+ reg
);
46 return __raw_readl(io_base
+ reg
);
49 #define OMAP_MCBSP_READ(base, reg) \
50 omap_mcbsp_read(base, OMAP_MCBSP_REG_##reg)
51 #define OMAP_MCBSP_WRITE(base, reg, val) \
52 omap_mcbsp_write(base, OMAP_MCBSP_REG_##reg, val)
54 #define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
55 #define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
57 static void omap_mcbsp_dump_reg(u8 id
)
59 struct omap_mcbsp
*mcbsp
= id_to_mcbsp_ptr(id
);
61 dev_dbg(mcbsp
->dev
, "**** McBSP%d regs ****\n", mcbsp
->id
);
62 dev_dbg(mcbsp
->dev
, "DRR2: 0x%04x\n",
63 OMAP_MCBSP_READ(mcbsp
->io_base
, DRR2
));
64 dev_dbg(mcbsp
->dev
, "DRR1: 0x%04x\n",
65 OMAP_MCBSP_READ(mcbsp
->io_base
, DRR1
));
66 dev_dbg(mcbsp
->dev
, "DXR2: 0x%04x\n",
67 OMAP_MCBSP_READ(mcbsp
->io_base
, DXR2
));
68 dev_dbg(mcbsp
->dev
, "DXR1: 0x%04x\n",
69 OMAP_MCBSP_READ(mcbsp
->io_base
, DXR1
));
70 dev_dbg(mcbsp
->dev
, "SPCR2: 0x%04x\n",
71 OMAP_MCBSP_READ(mcbsp
->io_base
, SPCR2
));
72 dev_dbg(mcbsp
->dev
, "SPCR1: 0x%04x\n",
73 OMAP_MCBSP_READ(mcbsp
->io_base
, SPCR1
));
74 dev_dbg(mcbsp
->dev
, "RCR2: 0x%04x\n",
75 OMAP_MCBSP_READ(mcbsp
->io_base
, RCR2
));
76 dev_dbg(mcbsp
->dev
, "RCR1: 0x%04x\n",
77 OMAP_MCBSP_READ(mcbsp
->io_base
, RCR1
));
78 dev_dbg(mcbsp
->dev
, "XCR2: 0x%04x\n",
79 OMAP_MCBSP_READ(mcbsp
->io_base
, XCR2
));
80 dev_dbg(mcbsp
->dev
, "XCR1: 0x%04x\n",
81 OMAP_MCBSP_READ(mcbsp
->io_base
, XCR1
));
82 dev_dbg(mcbsp
->dev
, "SRGR2: 0x%04x\n",
83 OMAP_MCBSP_READ(mcbsp
->io_base
, SRGR2
));
84 dev_dbg(mcbsp
->dev
, "SRGR1: 0x%04x\n",
85 OMAP_MCBSP_READ(mcbsp
->io_base
, SRGR1
));
86 dev_dbg(mcbsp
->dev
, "PCR0: 0x%04x\n",
87 OMAP_MCBSP_READ(mcbsp
->io_base
, PCR0
));
88 dev_dbg(mcbsp
->dev
, "***********************\n");
91 static irqreturn_t
omap_mcbsp_tx_irq_handler(int irq
, void *dev_id
)
93 struct omap_mcbsp
*mcbsp_tx
= dev_id
;
95 dev_dbg(mcbsp_tx
->dev
, "TX IRQ callback : 0x%x\n",
96 OMAP_MCBSP_READ(mcbsp_tx
->io_base
, SPCR2
));
98 complete(&mcbsp_tx
->tx_irq_completion
);
103 static irqreturn_t
omap_mcbsp_rx_irq_handler(int irq
, void *dev_id
)
105 struct omap_mcbsp
*mcbsp_rx
= dev_id
;
107 dev_dbg(mcbsp_rx
->dev
, "RX IRQ callback : 0x%x\n",
108 OMAP_MCBSP_READ(mcbsp_rx
->io_base
, SPCR2
));
110 complete(&mcbsp_rx
->rx_irq_completion
);
115 static void omap_mcbsp_tx_dma_callback(int lch
, u16 ch_status
, void *data
)
117 struct omap_mcbsp
*mcbsp_dma_tx
= data
;
119 dev_dbg(mcbsp_dma_tx
->dev
, "TX DMA callback : 0x%x\n",
120 OMAP_MCBSP_READ(mcbsp_dma_tx
->io_base
, SPCR2
));
122 /* We can free the channels */
123 omap_free_dma(mcbsp_dma_tx
->dma_tx_lch
);
124 mcbsp_dma_tx
->dma_tx_lch
= -1;
126 complete(&mcbsp_dma_tx
->tx_dma_completion
);
129 static void omap_mcbsp_rx_dma_callback(int lch
, u16 ch_status
, void *data
)
131 struct omap_mcbsp
*mcbsp_dma_rx
= data
;
133 dev_dbg(mcbsp_dma_rx
->dev
, "RX DMA callback : 0x%x\n",
134 OMAP_MCBSP_READ(mcbsp_dma_rx
->io_base
, SPCR2
));
136 /* We can free the channels */
137 omap_free_dma(mcbsp_dma_rx
->dma_rx_lch
);
138 mcbsp_dma_rx
->dma_rx_lch
= -1;
140 complete(&mcbsp_dma_rx
->rx_dma_completion
);
144 * omap_mcbsp_config simply write a config to the
146 * You either call this function or set the McBSP registers
147 * by yourself before calling omap_mcbsp_start().
149 void omap_mcbsp_config(unsigned int id
, const struct omap_mcbsp_reg_cfg
*config
)
151 struct omap_mcbsp
*mcbsp
;
152 void __iomem
*io_base
;
154 if (!omap_mcbsp_check_valid_id(id
)) {
155 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
158 mcbsp
= id_to_mcbsp_ptr(id
);
160 io_base
= mcbsp
->io_base
;
161 dev_dbg(mcbsp
->dev
, "Configuring McBSP%d phys_base: 0x%08lx\n",
162 mcbsp
->id
, mcbsp
->phys_base
);
164 /* We write the given config */
165 OMAP_MCBSP_WRITE(io_base
, SPCR2
, config
->spcr2
);
166 OMAP_MCBSP_WRITE(io_base
, SPCR1
, config
->spcr1
);
167 OMAP_MCBSP_WRITE(io_base
, RCR2
, config
->rcr2
);
168 OMAP_MCBSP_WRITE(io_base
, RCR1
, config
->rcr1
);
169 OMAP_MCBSP_WRITE(io_base
, XCR2
, config
->xcr2
);
170 OMAP_MCBSP_WRITE(io_base
, XCR1
, config
->xcr1
);
171 OMAP_MCBSP_WRITE(io_base
, SRGR2
, config
->srgr2
);
172 OMAP_MCBSP_WRITE(io_base
, SRGR1
, config
->srgr1
);
173 OMAP_MCBSP_WRITE(io_base
, MCR2
, config
->mcr2
);
174 OMAP_MCBSP_WRITE(io_base
, MCR1
, config
->mcr1
);
175 OMAP_MCBSP_WRITE(io_base
, PCR0
, config
->pcr0
);
176 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
177 OMAP_MCBSP_WRITE(io_base
, XCCR
, config
->xccr
);
178 OMAP_MCBSP_WRITE(io_base
, RCCR
, config
->rccr
);
181 EXPORT_SYMBOL(omap_mcbsp_config
);
184 * We can choose between IRQ based or polled IO.
185 * This needs to be called before omap_mcbsp_request().
187 int omap_mcbsp_set_io_type(unsigned int id
, omap_mcbsp_io_type_t io_type
)
189 struct omap_mcbsp
*mcbsp
;
191 if (!omap_mcbsp_check_valid_id(id
)) {
192 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
195 mcbsp
= id_to_mcbsp_ptr(id
);
197 spin_lock(&mcbsp
->lock
);
200 dev_err(mcbsp
->dev
, "McBSP%d is currently in use\n",
202 spin_unlock(&mcbsp
->lock
);
206 mcbsp
->io_type
= io_type
;
208 spin_unlock(&mcbsp
->lock
);
212 EXPORT_SYMBOL(omap_mcbsp_set_io_type
);
214 int omap_mcbsp_request(unsigned int id
)
216 struct omap_mcbsp
*mcbsp
;
220 if (!omap_mcbsp_check_valid_id(id
)) {
221 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
224 mcbsp
= id_to_mcbsp_ptr(id
);
226 if (mcbsp
->pdata
&& mcbsp
->pdata
->ops
&& mcbsp
->pdata
->ops
->request
)
227 mcbsp
->pdata
->ops
->request(id
);
229 for (i
= 0; i
< mcbsp
->num_clks
; i
++)
230 clk_enable(mcbsp
->clks
[i
]);
232 spin_lock(&mcbsp
->lock
);
234 dev_err(mcbsp
->dev
, "McBSP%d is currently in use\n",
236 spin_unlock(&mcbsp
->lock
);
241 spin_unlock(&mcbsp
->lock
);
244 * Make sure that transmitter, receiver and sample-rate generator are
245 * not running before activating IRQs.
247 OMAP_MCBSP_WRITE(mcbsp
->io_base
, SPCR1
, 0);
248 OMAP_MCBSP_WRITE(mcbsp
->io_base
, SPCR2
, 0);
250 if (mcbsp
->io_type
== OMAP_MCBSP_IRQ_IO
) {
251 /* We need to get IRQs here */
252 init_completion(&mcbsp
->tx_irq_completion
);
253 err
= request_irq(mcbsp
->tx_irq
, omap_mcbsp_tx_irq_handler
,
254 0, "McBSP", (void *)mcbsp
);
256 dev_err(mcbsp
->dev
, "Unable to request TX IRQ %d "
257 "for McBSP%d\n", mcbsp
->tx_irq
,
262 init_completion(&mcbsp
->rx_irq_completion
);
263 err
= request_irq(mcbsp
->rx_irq
, omap_mcbsp_rx_irq_handler
,
264 0, "McBSP", (void *)mcbsp
);
266 dev_err(mcbsp
->dev
, "Unable to request RX IRQ %d "
267 "for McBSP%d\n", mcbsp
->rx_irq
,
269 free_irq(mcbsp
->tx_irq
, (void *)mcbsp
);
276 EXPORT_SYMBOL(omap_mcbsp_request
);
278 void omap_mcbsp_free(unsigned int id
)
280 struct omap_mcbsp
*mcbsp
;
283 if (!omap_mcbsp_check_valid_id(id
)) {
284 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
287 mcbsp
= id_to_mcbsp_ptr(id
);
289 if (mcbsp
->pdata
&& mcbsp
->pdata
->ops
&& mcbsp
->pdata
->ops
->free
)
290 mcbsp
->pdata
->ops
->free(id
);
292 for (i
= mcbsp
->num_clks
- 1; i
>= 0; i
--)
293 clk_disable(mcbsp
->clks
[i
]);
295 spin_lock(&mcbsp
->lock
);
297 dev_err(mcbsp
->dev
, "McBSP%d was not reserved\n",
299 spin_unlock(&mcbsp
->lock
);
304 spin_unlock(&mcbsp
->lock
);
306 if (mcbsp
->io_type
== OMAP_MCBSP_IRQ_IO
) {
308 free_irq(mcbsp
->rx_irq
, (void *)mcbsp
);
309 free_irq(mcbsp
->tx_irq
, (void *)mcbsp
);
312 EXPORT_SYMBOL(omap_mcbsp_free
);
315 * Here we start the McBSP, by enabling the sample
316 * generator, both transmitter and receivers,
317 * and the frame sync.
319 void omap_mcbsp_start(unsigned int id
)
321 struct omap_mcbsp
*mcbsp
;
322 void __iomem
*io_base
;
325 if (!omap_mcbsp_check_valid_id(id
)) {
326 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
329 mcbsp
= id_to_mcbsp_ptr(id
);
330 io_base
= mcbsp
->io_base
;
332 mcbsp
->rx_word_length
= (OMAP_MCBSP_READ(io_base
, RCR1
) >> 5) & 0x7;
333 mcbsp
->tx_word_length
= (OMAP_MCBSP_READ(io_base
, XCR1
) >> 5) & 0x7;
335 /* Start the sample generator */
336 w
= OMAP_MCBSP_READ(io_base
, SPCR2
);
337 OMAP_MCBSP_WRITE(io_base
, SPCR2
, w
| (1 << 6));
339 /* Enable transmitter and receiver */
340 w
= OMAP_MCBSP_READ(io_base
, SPCR2
);
341 OMAP_MCBSP_WRITE(io_base
, SPCR2
, w
| 1);
343 w
= OMAP_MCBSP_READ(io_base
, SPCR1
);
344 OMAP_MCBSP_WRITE(io_base
, SPCR1
, w
| 1);
348 /* Start frame sync */
349 w
= OMAP_MCBSP_READ(io_base
, SPCR2
);
350 OMAP_MCBSP_WRITE(io_base
, SPCR2
, w
| (1 << 7));
352 /* Dump McBSP Regs */
353 omap_mcbsp_dump_reg(id
);
355 EXPORT_SYMBOL(omap_mcbsp_start
);
357 void omap_mcbsp_stop(unsigned int id
)
359 struct omap_mcbsp
*mcbsp
;
360 void __iomem
*io_base
;
363 if (!omap_mcbsp_check_valid_id(id
)) {
364 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
368 mcbsp
= id_to_mcbsp_ptr(id
);
369 io_base
= mcbsp
->io_base
;
371 /* Reset transmitter */
372 w
= OMAP_MCBSP_READ(io_base
, SPCR2
);
373 OMAP_MCBSP_WRITE(io_base
, SPCR2
, w
& ~(1));
376 w
= OMAP_MCBSP_READ(io_base
, SPCR1
);
377 OMAP_MCBSP_WRITE(io_base
, SPCR1
, w
& ~(1));
379 /* Reset the sample rate generator */
380 w
= OMAP_MCBSP_READ(io_base
, SPCR2
);
381 OMAP_MCBSP_WRITE(io_base
, SPCR2
, w
& ~(1 << 6));
383 EXPORT_SYMBOL(omap_mcbsp_stop
);
385 /* polled mcbsp i/o operations */
386 int omap_mcbsp_pollwrite(unsigned int id
, u16 buf
)
388 struct omap_mcbsp
*mcbsp
;
391 if (!omap_mcbsp_check_valid_id(id
)) {
392 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
396 mcbsp
= id_to_mcbsp_ptr(id
);
397 base
= mcbsp
->io_base
;
399 writew(buf
, base
+ OMAP_MCBSP_REG_DXR1
);
400 /* if frame sync error - clear the error */
401 if (readw(base
+ OMAP_MCBSP_REG_SPCR2
) & XSYNC_ERR
) {
403 writew(readw(base
+ OMAP_MCBSP_REG_SPCR2
) & (~XSYNC_ERR
),
404 base
+ OMAP_MCBSP_REG_SPCR2
);
408 /* wait for transmit confirmation */
410 while (!(readw(base
+ OMAP_MCBSP_REG_SPCR2
) & XRDY
)) {
411 if (attemps
++ > 1000) {
412 writew(readw(base
+ OMAP_MCBSP_REG_SPCR2
) &
414 base
+ OMAP_MCBSP_REG_SPCR2
);
416 writew(readw(base
+ OMAP_MCBSP_REG_SPCR2
) |
418 base
+ OMAP_MCBSP_REG_SPCR2
);
420 dev_err(mcbsp
->dev
, "Could not write to"
421 " McBSP%d Register\n", mcbsp
->id
);
429 EXPORT_SYMBOL(omap_mcbsp_pollwrite
);
431 int omap_mcbsp_pollread(unsigned int id
, u16
*buf
)
433 struct omap_mcbsp
*mcbsp
;
436 if (!omap_mcbsp_check_valid_id(id
)) {
437 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
440 mcbsp
= id_to_mcbsp_ptr(id
);
442 base
= mcbsp
->io_base
;
443 /* if frame sync error - clear the error */
444 if (readw(base
+ OMAP_MCBSP_REG_SPCR1
) & RSYNC_ERR
) {
446 writew(readw(base
+ OMAP_MCBSP_REG_SPCR1
) & (~RSYNC_ERR
),
447 base
+ OMAP_MCBSP_REG_SPCR1
);
451 /* wait for recieve confirmation */
453 while (!(readw(base
+ OMAP_MCBSP_REG_SPCR1
) & RRDY
)) {
454 if (attemps
++ > 1000) {
455 writew(readw(base
+ OMAP_MCBSP_REG_SPCR1
) &
457 base
+ OMAP_MCBSP_REG_SPCR1
);
459 writew(readw(base
+ OMAP_MCBSP_REG_SPCR1
) |
461 base
+ OMAP_MCBSP_REG_SPCR1
);
463 dev_err(mcbsp
->dev
, "Could not read from"
464 " McBSP%d Register\n", mcbsp
->id
);
469 *buf
= readw(base
+ OMAP_MCBSP_REG_DRR1
);
473 EXPORT_SYMBOL(omap_mcbsp_pollread
);
476 * IRQ based word transmission.
478 void omap_mcbsp_xmit_word(unsigned int id
, u32 word
)
480 struct omap_mcbsp
*mcbsp
;
481 void __iomem
*io_base
;
482 omap_mcbsp_word_length word_length
;
484 if (!omap_mcbsp_check_valid_id(id
)) {
485 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
489 mcbsp
= id_to_mcbsp_ptr(id
);
490 io_base
= mcbsp
->io_base
;
491 word_length
= mcbsp
->tx_word_length
;
493 wait_for_completion(&mcbsp
->tx_irq_completion
);
495 if (word_length
> OMAP_MCBSP_WORD_16
)
496 OMAP_MCBSP_WRITE(io_base
, DXR2
, word
>> 16);
497 OMAP_MCBSP_WRITE(io_base
, DXR1
, word
& 0xffff);
499 EXPORT_SYMBOL(omap_mcbsp_xmit_word
);
501 u32
omap_mcbsp_recv_word(unsigned int id
)
503 struct omap_mcbsp
*mcbsp
;
504 void __iomem
*io_base
;
505 u16 word_lsb
, word_msb
= 0;
506 omap_mcbsp_word_length word_length
;
508 if (!omap_mcbsp_check_valid_id(id
)) {
509 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
512 mcbsp
= id_to_mcbsp_ptr(id
);
514 word_length
= mcbsp
->rx_word_length
;
515 io_base
= mcbsp
->io_base
;
517 wait_for_completion(&mcbsp
->rx_irq_completion
);
519 if (word_length
> OMAP_MCBSP_WORD_16
)
520 word_msb
= OMAP_MCBSP_READ(io_base
, DRR2
);
521 word_lsb
= OMAP_MCBSP_READ(io_base
, DRR1
);
523 return (word_lsb
| (word_msb
<< 16));
525 EXPORT_SYMBOL(omap_mcbsp_recv_word
);
527 int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id
, u32 word
)
529 struct omap_mcbsp
*mcbsp
;
530 void __iomem
*io_base
;
531 omap_mcbsp_word_length tx_word_length
;
532 omap_mcbsp_word_length rx_word_length
;
533 u16 spcr2
, spcr1
, attempts
= 0, word_lsb
, word_msb
= 0;
535 if (!omap_mcbsp_check_valid_id(id
)) {
536 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
539 mcbsp
= id_to_mcbsp_ptr(id
);
540 io_base
= mcbsp
->io_base
;
541 tx_word_length
= mcbsp
->tx_word_length
;
542 rx_word_length
= mcbsp
->rx_word_length
;
544 if (tx_word_length
!= rx_word_length
)
547 /* First we wait for the transmitter to be ready */
548 spcr2
= OMAP_MCBSP_READ(io_base
, SPCR2
);
549 while (!(spcr2
& XRDY
)) {
550 spcr2
= OMAP_MCBSP_READ(io_base
, SPCR2
);
551 if (attempts
++ > 1000) {
552 /* We must reset the transmitter */
553 OMAP_MCBSP_WRITE(io_base
, SPCR2
, spcr2
& (~XRST
));
555 OMAP_MCBSP_WRITE(io_base
, SPCR2
, spcr2
| XRST
);
557 dev_err(mcbsp
->dev
, "McBSP%d transmitter not "
558 "ready\n", mcbsp
->id
);
563 /* Now we can push the data */
564 if (tx_word_length
> OMAP_MCBSP_WORD_16
)
565 OMAP_MCBSP_WRITE(io_base
, DXR2
, word
>> 16);
566 OMAP_MCBSP_WRITE(io_base
, DXR1
, word
& 0xffff);
568 /* We wait for the receiver to be ready */
569 spcr1
= OMAP_MCBSP_READ(io_base
, SPCR1
);
570 while (!(spcr1
& RRDY
)) {
571 spcr1
= OMAP_MCBSP_READ(io_base
, SPCR1
);
572 if (attempts
++ > 1000) {
573 /* We must reset the receiver */
574 OMAP_MCBSP_WRITE(io_base
, SPCR1
, spcr1
& (~RRST
));
576 OMAP_MCBSP_WRITE(io_base
, SPCR1
, spcr1
| RRST
);
578 dev_err(mcbsp
->dev
, "McBSP%d receiver not "
579 "ready\n", mcbsp
->id
);
584 /* Receiver is ready, let's read the dummy data */
585 if (rx_word_length
> OMAP_MCBSP_WORD_16
)
586 word_msb
= OMAP_MCBSP_READ(io_base
, DRR2
);
587 word_lsb
= OMAP_MCBSP_READ(io_base
, DRR1
);
591 EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll
);
593 int omap_mcbsp_spi_master_recv_word_poll(unsigned int id
, u32
*word
)
595 struct omap_mcbsp
*mcbsp
;
597 void __iomem
*io_base
;
598 omap_mcbsp_word_length tx_word_length
;
599 omap_mcbsp_word_length rx_word_length
;
600 u16 spcr2
, spcr1
, attempts
= 0, word_lsb
, word_msb
= 0;
602 if (!omap_mcbsp_check_valid_id(id
)) {
603 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
607 mcbsp
= id_to_mcbsp_ptr(id
);
608 io_base
= mcbsp
->io_base
;
610 tx_word_length
= mcbsp
->tx_word_length
;
611 rx_word_length
= mcbsp
->rx_word_length
;
613 if (tx_word_length
!= rx_word_length
)
616 /* First we wait for the transmitter to be ready */
617 spcr2
= OMAP_MCBSP_READ(io_base
, SPCR2
);
618 while (!(spcr2
& XRDY
)) {
619 spcr2
= OMAP_MCBSP_READ(io_base
, SPCR2
);
620 if (attempts
++ > 1000) {
621 /* We must reset the transmitter */
622 OMAP_MCBSP_WRITE(io_base
, SPCR2
, spcr2
& (~XRST
));
624 OMAP_MCBSP_WRITE(io_base
, SPCR2
, spcr2
| XRST
);
626 dev_err(mcbsp
->dev
, "McBSP%d transmitter not "
627 "ready\n", mcbsp
->id
);
632 /* We first need to enable the bus clock */
633 if (tx_word_length
> OMAP_MCBSP_WORD_16
)
634 OMAP_MCBSP_WRITE(io_base
, DXR2
, clock_word
>> 16);
635 OMAP_MCBSP_WRITE(io_base
, DXR1
, clock_word
& 0xffff);
637 /* We wait for the receiver to be ready */
638 spcr1
= OMAP_MCBSP_READ(io_base
, SPCR1
);
639 while (!(spcr1
& RRDY
)) {
640 spcr1
= OMAP_MCBSP_READ(io_base
, SPCR1
);
641 if (attempts
++ > 1000) {
642 /* We must reset the receiver */
643 OMAP_MCBSP_WRITE(io_base
, SPCR1
, spcr1
& (~RRST
));
645 OMAP_MCBSP_WRITE(io_base
, SPCR1
, spcr1
| RRST
);
647 dev_err(mcbsp
->dev
, "McBSP%d receiver not "
648 "ready\n", mcbsp
->id
);
653 /* Receiver is ready, there is something for us */
654 if (rx_word_length
> OMAP_MCBSP_WORD_16
)
655 word_msb
= OMAP_MCBSP_READ(io_base
, DRR2
);
656 word_lsb
= OMAP_MCBSP_READ(io_base
, DRR1
);
658 word
[0] = (word_lsb
| (word_msb
<< 16));
662 EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll
);
665 * Simple DMA based buffer rx/tx routines.
666 * Nothing fancy, just a single buffer tx/rx through DMA.
667 * The DMA resources are released once the transfer is done.
668 * For anything fancier, you should use your own customized DMA
669 * routines and callbacks.
671 int omap_mcbsp_xmit_buffer(unsigned int id
, dma_addr_t buffer
,
674 struct omap_mcbsp
*mcbsp
;
680 if (!omap_mcbsp_check_valid_id(id
)) {
681 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
684 mcbsp
= id_to_mcbsp_ptr(id
);
686 if (omap_request_dma(mcbsp
->dma_tx_sync
, "McBSP TX",
687 omap_mcbsp_tx_dma_callback
,
690 dev_err(mcbsp
->dev
, " Unable to request DMA channel for "
691 "McBSP%d TX. Trying IRQ based TX\n",
695 mcbsp
->dma_tx_lch
= dma_tx_ch
;
697 dev_err(mcbsp
->dev
, "McBSP%d TX DMA on channel %d\n", mcbsp
->id
,
700 init_completion(&mcbsp
->tx_dma_completion
);
702 if (cpu_class_is_omap1()) {
703 src_port
= OMAP_DMA_PORT_TIPB
;
704 dest_port
= OMAP_DMA_PORT_EMIFF
;
706 if (cpu_class_is_omap2())
707 sync_dev
= mcbsp
->dma_tx_sync
;
709 omap_set_dma_transfer_params(mcbsp
->dma_tx_lch
,
710 OMAP_DMA_DATA_TYPE_S16
,
712 OMAP_DMA_SYNC_ELEMENT
,
715 omap_set_dma_dest_params(mcbsp
->dma_tx_lch
,
717 OMAP_DMA_AMODE_CONSTANT
,
718 mcbsp
->phys_base
+ OMAP_MCBSP_REG_DXR1
,
721 omap_set_dma_src_params(mcbsp
->dma_tx_lch
,
723 OMAP_DMA_AMODE_POST_INC
,
727 omap_start_dma(mcbsp
->dma_tx_lch
);
728 wait_for_completion(&mcbsp
->tx_dma_completion
);
732 EXPORT_SYMBOL(omap_mcbsp_xmit_buffer
);
734 int omap_mcbsp_recv_buffer(unsigned int id
, dma_addr_t buffer
,
737 struct omap_mcbsp
*mcbsp
;
743 if (!omap_mcbsp_check_valid_id(id
)) {
744 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
747 mcbsp
= id_to_mcbsp_ptr(id
);
749 if (omap_request_dma(mcbsp
->dma_rx_sync
, "McBSP RX",
750 omap_mcbsp_rx_dma_callback
,
753 dev_err(mcbsp
->dev
, "Unable to request DMA channel for "
754 "McBSP%d RX. Trying IRQ based RX\n",
758 mcbsp
->dma_rx_lch
= dma_rx_ch
;
760 dev_err(mcbsp
->dev
, "McBSP%d RX DMA on channel %d\n", mcbsp
->id
,
763 init_completion(&mcbsp
->rx_dma_completion
);
765 if (cpu_class_is_omap1()) {
766 src_port
= OMAP_DMA_PORT_TIPB
;
767 dest_port
= OMAP_DMA_PORT_EMIFF
;
769 if (cpu_class_is_omap2())
770 sync_dev
= mcbsp
->dma_rx_sync
;
772 omap_set_dma_transfer_params(mcbsp
->dma_rx_lch
,
773 OMAP_DMA_DATA_TYPE_S16
,
775 OMAP_DMA_SYNC_ELEMENT
,
778 omap_set_dma_src_params(mcbsp
->dma_rx_lch
,
780 OMAP_DMA_AMODE_CONSTANT
,
781 mcbsp
->phys_base
+ OMAP_MCBSP_REG_DRR1
,
784 omap_set_dma_dest_params(mcbsp
->dma_rx_lch
,
786 OMAP_DMA_AMODE_POST_INC
,
790 omap_start_dma(mcbsp
->dma_rx_lch
);
791 wait_for_completion(&mcbsp
->rx_dma_completion
);
795 EXPORT_SYMBOL(omap_mcbsp_recv_buffer
);
799 * Since SPI setup is much simpler than the generic McBSP one,
800 * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
801 * Once this is done, you can call omap_mcbsp_start().
803 void omap_mcbsp_set_spi_mode(unsigned int id
,
804 const struct omap_mcbsp_spi_cfg
*spi_cfg
)
806 struct omap_mcbsp
*mcbsp
;
807 struct omap_mcbsp_reg_cfg mcbsp_cfg
;
809 if (!omap_mcbsp_check_valid_id(id
)) {
810 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
813 mcbsp
= id_to_mcbsp_ptr(id
);
815 memset(&mcbsp_cfg
, 0, sizeof(struct omap_mcbsp_reg_cfg
));
817 /* SPI has only one frame */
818 mcbsp_cfg
.rcr1
|= (RWDLEN1(spi_cfg
->word_length
) | RFRLEN1(0));
819 mcbsp_cfg
.xcr1
|= (XWDLEN1(spi_cfg
->word_length
) | XFRLEN1(0));
821 /* Clock stop mode */
822 if (spi_cfg
->clk_stp_mode
== OMAP_MCBSP_CLK_STP_MODE_NO_DELAY
)
823 mcbsp_cfg
.spcr1
|= (1 << 12);
825 mcbsp_cfg
.spcr1
|= (3 << 11);
827 /* Set clock parities */
828 if (spi_cfg
->rx_clock_polarity
== OMAP_MCBSP_CLK_RISING
)
829 mcbsp_cfg
.pcr0
|= CLKRP
;
831 mcbsp_cfg
.pcr0
&= ~CLKRP
;
833 if (spi_cfg
->tx_clock_polarity
== OMAP_MCBSP_CLK_RISING
)
834 mcbsp_cfg
.pcr0
&= ~CLKXP
;
836 mcbsp_cfg
.pcr0
|= CLKXP
;
838 /* Set SCLKME to 0 and CLKSM to 1 */
839 mcbsp_cfg
.pcr0
&= ~SCLKME
;
840 mcbsp_cfg
.srgr2
|= CLKSM
;
843 if (spi_cfg
->fsx_polarity
== OMAP_MCBSP_FS_ACTIVE_HIGH
)
844 mcbsp_cfg
.pcr0
&= ~FSXP
;
846 mcbsp_cfg
.pcr0
|= FSXP
;
848 if (spi_cfg
->spi_mode
== OMAP_MCBSP_SPI_MASTER
) {
849 mcbsp_cfg
.pcr0
|= CLKXM
;
850 mcbsp_cfg
.srgr1
|= CLKGDV(spi_cfg
->clk_div
- 1);
851 mcbsp_cfg
.pcr0
|= FSXM
;
852 mcbsp_cfg
.srgr2
&= ~FSGM
;
853 mcbsp_cfg
.xcr2
|= XDATDLY(1);
854 mcbsp_cfg
.rcr2
|= RDATDLY(1);
856 mcbsp_cfg
.pcr0
&= ~CLKXM
;
857 mcbsp_cfg
.srgr1
|= CLKGDV(1);
858 mcbsp_cfg
.pcr0
&= ~FSXM
;
859 mcbsp_cfg
.xcr2
&= ~XDATDLY(3);
860 mcbsp_cfg
.rcr2
&= ~RDATDLY(3);
863 mcbsp_cfg
.xcr2
&= ~XPHASE
;
864 mcbsp_cfg
.rcr2
&= ~RPHASE
;
866 omap_mcbsp_config(id
, &mcbsp_cfg
);
868 EXPORT_SYMBOL(omap_mcbsp_set_spi_mode
);
871 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
872 * 730 has only 2 McBSP, and both of them are MPU peripherals.
874 static int __devinit
omap_mcbsp_probe(struct platform_device
*pdev
)
876 struct omap_mcbsp_platform_data
*pdata
= pdev
->dev
.platform_data
;
877 struct omap_mcbsp
*mcbsp
;
878 int id
= pdev
->id
- 1;
883 dev_err(&pdev
->dev
, "McBSP device initialized without"
889 dev_dbg(&pdev
->dev
, "Initializing OMAP McBSP (%d).\n", pdev
->id
);
891 if (id
>= omap_mcbsp_count
) {
892 dev_err(&pdev
->dev
, "Invalid McBSP device id (%d)\n", id
);
897 mcbsp
= kzalloc(sizeof(struct omap_mcbsp
), GFP_KERNEL
);
902 mcbsp_ptr
[id
] = mcbsp
;
904 spin_lock_init(&mcbsp
->lock
);
907 mcbsp
->dma_tx_lch
= -1;
908 mcbsp
->dma_rx_lch
= -1;
910 mcbsp
->phys_base
= pdata
->phys_base
;
911 mcbsp
->io_base
= ioremap(pdata
->phys_base
, SZ_4K
);
912 if (!mcbsp
->io_base
) {
917 /* Default I/O is IRQ based */
918 mcbsp
->io_type
= OMAP_MCBSP_IRQ_IO
;
919 mcbsp
->tx_irq
= pdata
->tx_irq
;
920 mcbsp
->rx_irq
= pdata
->rx_irq
;
921 mcbsp
->dma_rx_sync
= pdata
->dma_rx_sync
;
922 mcbsp
->dma_tx_sync
= pdata
->dma_tx_sync
;
924 if (pdata
->num_clks
) {
925 mcbsp
->num_clks
= pdata
->num_clks
;
926 mcbsp
->clks
= kzalloc(mcbsp
->num_clks
* sizeof(struct clk
*),
932 for (i
= 0; i
< mcbsp
->num_clks
; i
++) {
933 mcbsp
->clks
[i
] = clk_get(&pdev
->dev
, pdata
->clk_names
[i
]);
934 if (IS_ERR(mcbsp
->clks
[i
])) {
936 "Invalid %s configuration for McBSP%d.\n",
937 pdata
->clk_names
[i
], mcbsp
->id
);
938 ret
= PTR_ERR(mcbsp
->clks
[i
]);
945 mcbsp
->pdata
= pdata
;
946 mcbsp
->dev
= &pdev
->dev
;
947 platform_set_drvdata(pdev
, mcbsp
);
952 clk_put(mcbsp
->clks
[i
]);
954 iounmap(mcbsp
->io_base
);
961 static int __devexit
omap_mcbsp_remove(struct platform_device
*pdev
)
963 struct omap_mcbsp
*mcbsp
= platform_get_drvdata(pdev
);
966 platform_set_drvdata(pdev
, NULL
);
969 if (mcbsp
->pdata
&& mcbsp
->pdata
->ops
&&
970 mcbsp
->pdata
->ops
->free
)
971 mcbsp
->pdata
->ops
->free(mcbsp
->id
);
973 for (i
= mcbsp
->num_clks
- 1; i
>= 0; i
--) {
974 clk_disable(mcbsp
->clks
[i
]);
975 clk_put(mcbsp
->clks
[i
]);
978 iounmap(mcbsp
->io_base
);
980 if (mcbsp
->num_clks
) {
992 static struct platform_driver omap_mcbsp_driver
= {
993 .probe
= omap_mcbsp_probe
,
994 .remove
= __devexit_p(omap_mcbsp_remove
),
996 .name
= "omap-mcbsp",
1000 int __init
omap_mcbsp_init(void)
1002 /* Register the McBSP driver */
1003 return platform_driver_register(&omap_mcbsp_driver
);