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[POWERPC] Sky Cpu and Nexus: check for create_proc_entry ret code
[linux-2.6/mini2440.git] / drivers / pci / probe.c
blob171ca712e523b0453c44f1657fff8d0564de9ad1
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include "pci.h"
13
14 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
15 #define CARDBUS_RESERVE_BUSNR 3
16 #define PCI_CFG_SPACE_SIZE 256
17 #define PCI_CFG_SPACE_EXP_SIZE 4096
18
19 /* Ugh. Need to stop exporting this to modules. */
20 LIST_HEAD(pci_root_buses);
21 EXPORT_SYMBOL(pci_root_buses);
22
23 LIST_HEAD(pci_devices);
24
25 /*
26 * Some device drivers need know if pci is initiated.
27 * Basically, we think pci is not initiated when there
28 * is no device in list of pci_devices.
29 */
30 int no_pci_devices(void)
31 {
32 return list_empty(&pci_devices);
33 }
34
35 EXPORT_SYMBOL(no_pci_devices);
36
37 #ifdef HAVE_PCI_LEGACY
38 /**
39 * pci_create_legacy_files - create legacy I/O port and memory files
40 * @b: bus to create files under
41 *
42 * Some platforms allow access to legacy I/O port and ISA memory space on
43 * a per-bus basis. This routine creates the files and ties them into
44 * their associated read, write and mmap files from pci-sysfs.c
45 */
46 static void pci_create_legacy_files(struct pci_bus *b)
47 {
48 b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2,
49 GFP_ATOMIC);
50 if (b->legacy_io) {
51 b->legacy_io->attr.name = "legacy_io";
52 b->legacy_io->size = 0xffff;
53 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
54 b->legacy_io->read = pci_read_legacy_io;
55 b->legacy_io->write = pci_write_legacy_io;
56 class_device_create_bin_file(&b->class_dev, b->legacy_io);
57
58 /* Allocated above after the legacy_io struct */
59 b->legacy_mem = b->legacy_io + 1;
60 b->legacy_mem->attr.name = "legacy_mem";
61 b->legacy_mem->size = 1024*1024;
62 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
63 b->legacy_mem->mmap = pci_mmap_legacy_mem;
64 class_device_create_bin_file(&b->class_dev, b->legacy_mem);
65 }
66 }
67
68 void pci_remove_legacy_files(struct pci_bus *b)
69 {
70 if (b->legacy_io) {
71 class_device_remove_bin_file(&b->class_dev, b->legacy_io);
72 class_device_remove_bin_file(&b->class_dev, b->legacy_mem);
73 kfree(b->legacy_io); /* both are allocated here */
74 }
75 }
76 #else /* !HAVE_PCI_LEGACY */
77 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
78 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
79 #endif /* HAVE_PCI_LEGACY */
80
81 /*
82 * PCI Bus Class Devices
83 */
84 static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev,
85 char *buf)
86 {
87 int ret;
88 cpumask_t cpumask;
89
90 cpumask = pcibus_to_cpumask(to_pci_bus(class_dev));
91 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
92 if (ret < PAGE_SIZE)
93 buf[ret++] = '\n';
94 return ret;
95 }
96 CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
97
98 /*
99 * PCI Bus Class
100 */
101 static void release_pcibus_dev(struct class_device *class_dev)
102 {
103 struct pci_bus *pci_bus = to_pci_bus(class_dev);
104
105 if (pci_bus->bridge)
106 put_device(pci_bus->bridge);
107 kfree(pci_bus);
108 }
109
110 static struct class pcibus_class = {
111 .name = "pci_bus",
112 .release = &release_pcibus_dev,
113 };
114
115 static int __init pcibus_class_init(void)
116 {
117 return class_register(&pcibus_class);
118 }
119 postcore_initcall(pcibus_class_init);
120
121 /*
122 * Translate the low bits of the PCI base
123 * to the resource type
124 */
125 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
126 {
127 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
128 return IORESOURCE_IO;
129
130 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
131 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
132
133 return IORESOURCE_MEM;
134 }
135
136 /*
137 * Find the extent of a PCI decode..
138 */
139 static u32 pci_size(u32 base, u32 maxbase, u32 mask)
140 {
141 u32 size = mask & maxbase; /* Find the significant bits */
142 if (!size)
143 return 0;
144
145 /* Get the lowest of them to find the decode size, and
146 from that the extent. */
147 size = (size & ~(size-1)) - 1;
148
149 /* base == maxbase can be valid only if the BAR has
150 already been programmed with all 1s. */
151 if (base == maxbase && ((base | size) & mask) != mask)
152 return 0;
153
154 return size;
155 }
156
157 static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
158 {
159 u64 size = mask & maxbase; /* Find the significant bits */
160 if (!size)
161 return 0;
162
163 /* Get the lowest of them to find the decode size, and
164 from that the extent. */
165 size = (size & ~(size-1)) - 1;
166
167 /* base == maxbase can be valid only if the BAR has
168 already been programmed with all 1s. */
169 if (base == maxbase && ((base | size) & mask) != mask)
170 return 0;
171
172 return size;
173 }
174
175 static inline int is_64bit_memory(u32 mask)
176 {
177 if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
178 (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
179 return 1;
180 return 0;
181 }
182
183 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
184 {
185 unsigned int pos, reg, next;
186 u32 l, sz;
187 struct resource *res;
188
189 for(pos=0; pos<howmany; pos = next) {
190 u64 l64;
191 u64 sz64;
192 u32 raw_sz;
193
194 next = pos+1;
195 res = &dev->resource[pos];
196 res->name = pci_name(dev);
197 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
198 pci_read_config_dword(dev, reg, &l);
199 pci_write_config_dword(dev, reg, ~0);
200 pci_read_config_dword(dev, reg, &sz);
201 pci_write_config_dword(dev, reg, l);
202 if (!sz || sz == 0xffffffff)
203 continue;
204 if (l == 0xffffffff)
205 l = 0;
206 raw_sz = sz;
207 if ((l & PCI_BASE_ADDRESS_SPACE) ==
208 PCI_BASE_ADDRESS_SPACE_MEMORY) {
209 sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
210 /*
211 * For 64bit prefetchable memory sz could be 0, if the
212 * real size is bigger than 4G, so we need to check
213 * szhi for that.
214 */
215 if (!is_64bit_memory(l) && !sz)
216 continue;
217 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
218 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
219 } else {
220 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
221 if (!sz)
222 continue;
223 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
224 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
225 }
226 res->end = res->start + (unsigned long) sz;
227 res->flags |= pci_calc_resource_flags(l);
228 if (is_64bit_memory(l)) {
229 u32 szhi, lhi;
230
231 pci_read_config_dword(dev, reg+4, &lhi);
232 pci_write_config_dword(dev, reg+4, ~0);
233 pci_read_config_dword(dev, reg+4, &szhi);
234 pci_write_config_dword(dev, reg+4, lhi);
235 sz64 = ((u64)szhi << 32) | raw_sz;
236 l64 = ((u64)lhi << 32) | l;
237 sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
238 next++;
239 #if BITS_PER_LONG == 64
240 if (!sz64) {
241 res->start = 0;
242 res->end = 0;
243 res->flags = 0;
244 continue;
245 }
246 res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
247 res->end = res->start + sz64;
248 #else
249 if (sz64 > 0x100000000ULL) {
250 printk(KERN_ERR "PCI: Unable to handle 64-bit "
251 "BAR for device %s\n", pci_name(dev));
252 res->start = 0;
253 res->flags = 0;
254 } else if (lhi) {
255 /* 64-bit wide address, treat as disabled */
256 pci_write_config_dword(dev, reg,
257 l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
258 pci_write_config_dword(dev, reg+4, 0);
259 res->start = 0;
260 res->end = sz;
261 }
262 #endif
263 }
264 }
265 if (rom) {
266 dev->rom_base_reg = rom;
267 res = &dev->resource[PCI_ROM_RESOURCE];
268 res->name = pci_name(dev);
269 pci_read_config_dword(dev, rom, &l);
270 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
271 pci_read_config_dword(dev, rom, &sz);
272 pci_write_config_dword(dev, rom, l);
273 if (l == 0xffffffff)
274 l = 0;
275 if (sz && sz != 0xffffffff) {
276 sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
277 if (sz) {
278 res->flags = (l & IORESOURCE_ROM_ENABLE) |
279 IORESOURCE_MEM | IORESOURCE_PREFETCH |
280 IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
281 res->start = l & PCI_ROM_ADDRESS_MASK;
282 res->end = res->start + (unsigned long) sz;
283 }
284 }
285 }
286 }
287
288 void pci_read_bridge_bases(struct pci_bus *child)
289 {
290 struct pci_dev *dev = child->self;
291 u8 io_base_lo, io_limit_lo;
292 u16 mem_base_lo, mem_limit_lo;
293 unsigned long base, limit;
294 struct resource *res;
295 int i;
296
297 if (!dev) /* It's a host bus, nothing to read */
298 return;
299
300 if (dev->transparent) {
301 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
302 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
303 child->resource[i] = child->parent->resource[i - 3];
304 }
305
306 for(i=0; i<3; i++)
307 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
308
309 res = child->resource[0];
310 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
311 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
312 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
313 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
314
315 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
316 u16 io_base_hi, io_limit_hi;
317 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
318 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
319 base |= (io_base_hi << 16);
320 limit |= (io_limit_hi << 16);
321 }
322
323 if (base <= limit) {
324 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
325 if (!res->start)
326 res->start = base;
327 if (!res->end)
328 res->end = limit + 0xfff;
329 }
330
331 res = child->resource[1];
332 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
333 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
334 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
335 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
336 if (base <= limit) {
337 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
338 res->start = base;
339 res->end = limit + 0xfffff;
340 }
341
342 res = child->resource[2];
343 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
344 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
345 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
346 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
347
348 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
349 u32 mem_base_hi, mem_limit_hi;
350 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
351 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
352
353 /*
354 * Some bridges set the base > limit by default, and some
355 * (broken) BIOSes do not initialize them. If we find
356 * this, just assume they are not being used.
357 */
358 if (mem_base_hi <= mem_limit_hi) {
359 #if BITS_PER_LONG == 64
360 base |= ((long) mem_base_hi) << 32;
361 limit |= ((long) mem_limit_hi) << 32;
362 #else
363 if (mem_base_hi || mem_limit_hi) {
364 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
365 return;
366 }
367 #endif
368 }
369 }
370 if (base <= limit) {
371 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
372 res->start = base;
373 res->end = limit + 0xfffff;
374 }
375 }
376
377 static struct pci_bus * pci_alloc_bus(void)
378 {
379 struct pci_bus *b;
380
381 b = kzalloc(sizeof(*b), GFP_KERNEL);
382 if (b) {
383 INIT_LIST_HEAD(&b->node);
384 INIT_LIST_HEAD(&b->children);
385 INIT_LIST_HEAD(&b->devices);
386 }
387 return b;
388 }
389
390 static struct pci_bus * __devinit
391 pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
392 {
393 struct pci_bus *child;
394 int i;
395 int retval;
396
397 /*
398 * Allocate a new bus, and inherit stuff from the parent..
399 */
400 child = pci_alloc_bus();
401 if (!child)
402 return NULL;
403
404 child->self = bridge;
405 child->parent = parent;
406 child->ops = parent->ops;
407 child->sysdata = parent->sysdata;
408 child->bus_flags = parent->bus_flags;
409 child->bridge = get_device(&bridge->dev);
410
411 child->class_dev.class = &pcibus_class;
412 sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr);
413 retval = class_device_register(&child->class_dev);
414 if (retval)
415 goto error_register;
416 retval = class_device_create_file(&child->class_dev,
417 &class_device_attr_cpuaffinity);
418 if (retval)
419 goto error_file_create;
420
421 /*
422 * Set up the primary, secondary and subordinate
423 * bus numbers.
424 */
425 child->number = child->secondary = busnr;
426 child->primary = parent->secondary;
427 child->subordinate = 0xff;
428
429 /* Set up default resource pointers and names.. */
430 for (i = 0; i < 4; i++) {
431 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
432 child->resource[i]->name = child->name;
433 }
434 bridge->subordinate = child;
435
436 return child;
437
438 error_file_create:
439 class_device_unregister(&child->class_dev);
440 error_register:
441 kfree(child);
442 return NULL;
443 }
444
445 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
446 {
447 struct pci_bus *child;
448
449 child = pci_alloc_child_bus(parent, dev, busnr);
450 if (child) {
451 down_write(&pci_bus_sem);
452 list_add_tail(&child->node, &parent->children);
453 up_write(&pci_bus_sem);
454 }
455 return child;
456 }
457
458 static void pci_enable_crs(struct pci_dev *dev)
459 {
460 u16 cap, rpctl;
461 int rpcap = pci_find_capability(dev, PCI_CAP_ID_EXP);
462 if (!rpcap)
463 return;
464
465 pci_read_config_word(dev, rpcap + PCI_CAP_FLAGS, &cap);
466 if (((cap & PCI_EXP_FLAGS_TYPE) >> 4) != PCI_EXP_TYPE_ROOT_PORT)
467 return;
468
469 pci_read_config_word(dev, rpcap + PCI_EXP_RTCTL, &rpctl);
470 rpctl |= PCI_EXP_RTCTL_CRSSVE;
471 pci_write_config_word(dev, rpcap + PCI_EXP_RTCTL, rpctl);
472 }
473
474 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
475 {
476 struct pci_bus *parent = child->parent;
477
478 /* Attempts to fix that up are really dangerous unless
479 we're going to re-assign all bus numbers. */
480 if (!pcibios_assign_all_busses())
481 return;
482
483 while (parent->parent && parent->subordinate < max) {
484 parent->subordinate = max;
485 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
486 parent = parent->parent;
487 }
488 }
489
490 unsigned int pci_scan_child_bus(struct pci_bus *bus);
491
492 /*
493 * If it's a bridge, configure it and scan the bus behind it.
494 * For CardBus bridges, we don't scan behind as the devices will
495 * be handled by the bridge driver itself.
496 *
497 * We need to process bridges in two passes -- first we scan those
498 * already configured by the BIOS and after we are done with all of
499 * them, we proceed to assigning numbers to the remaining buses in
500 * order to avoid overlaps between old and new bus numbers.
501 */
502 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
503 {
504 struct pci_bus *child;
505 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
506 u32 buses, i, j = 0;
507 u16 bctl;
508
509 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
510
511 pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
512 pci_name(dev), buses & 0xffffff, pass);
513
514 /* Disable MasterAbortMode during probing to avoid reporting
515 of bus errors (in some architectures) */
516 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
517 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
518 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
519
520 pci_enable_crs(dev);
521
522 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
523 unsigned int cmax, busnr;
524 /*
525 * Bus already configured by firmware, process it in the first
526 * pass and just note the configuration.
527 */
528 if (pass)
529 goto out;
530 busnr = (buses >> 8) & 0xFF;
531
532 /*
533 * If we already got to this bus through a different bridge,
534 * ignore it. This can happen with the i450NX chipset.
535 */
536 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
537 printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
538 pci_domain_nr(bus), busnr);
539 goto out;
540 }
541
542 child = pci_add_new_bus(bus, dev, busnr);
543 if (!child)
544 goto out;
545 child->primary = buses & 0xFF;
546 child->subordinate = (buses >> 16) & 0xFF;
547 child->bridge_ctl = bctl;
548
549 cmax = pci_scan_child_bus(child);
550 if (cmax > max)
551 max = cmax;
552 if (child->subordinate > max)
553 max = child->subordinate;
554 } else {
555 /*
556 * We need to assign a number to this bus which we always
557 * do in the second pass.
558 */
559 if (!pass) {
560 if (pcibios_assign_all_busses())
561 /* Temporarily disable forwarding of the
562 configuration cycles on all bridges in
563 this bus segment to avoid possible
564 conflicts in the second pass between two
565 bridges programmed with overlapping
566 bus ranges. */
567 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
568 buses & ~0xffffff);
569 goto out;
570 }
571
572 /* Clear errors */
573 pci_write_config_word(dev, PCI_STATUS, 0xffff);
574
575 /* Prevent assigning a bus number that already exists.
576 * This can happen when a bridge is hot-plugged */
577 if (pci_find_bus(pci_domain_nr(bus), max+1))
578 goto out;
579 child = pci_add_new_bus(bus, dev, ++max);
580 buses = (buses & 0xff000000)
581 | ((unsigned int)(child->primary) << 0)
582 | ((unsigned int)(child->secondary) << 8)
583 | ((unsigned int)(child->subordinate) << 16);
584
585 /*
586 * yenta.c forces a secondary latency timer of 176.
587 * Copy that behaviour here.
588 */
589 if (is_cardbus) {
590 buses &= ~0xff000000;
591 buses |= CARDBUS_LATENCY_TIMER << 24;
592 }
593
594 /*
595 * We need to blast all three values with a single write.
596 */
597 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
598
599 if (!is_cardbus) {
600 child->bridge_ctl = bctl | PCI_BRIDGE_CTL_NO_ISA;
601 /*
602 * Adjust subordinate busnr in parent buses.
603 * We do this before scanning for children because
604 * some devices may not be detected if the bios
605 * was lazy.
606 */
607 pci_fixup_parent_subordinate_busnr(child, max);
608 /* Now we can scan all subordinate buses... */
609 max = pci_scan_child_bus(child);
610 /*
611 * now fix it up again since we have found
612 * the real value of max.
613 */
614 pci_fixup_parent_subordinate_busnr(child, max);
615 } else {
616 /*
617 * For CardBus bridges, we leave 4 bus numbers
618 * as cards with a PCI-to-PCI bridge can be
619 * inserted later.
620 */
621 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
622 struct pci_bus *parent = bus;
623 if (pci_find_bus(pci_domain_nr(bus),
624 max+i+1))
625 break;
626 while (parent->parent) {
627 if ((!pcibios_assign_all_busses()) &&
628 (parent->subordinate > max) &&
629 (parent->subordinate <= max+i)) {
630 j = 1;
631 }
632 parent = parent->parent;
633 }
634 if (j) {
635 /*
636 * Often, there are two cardbus bridges
637 * -- try to leave one valid bus number
638 * for each one.
639 */
640 i /= 2;
641 break;
642 }
643 }
644 max += i;
645 pci_fixup_parent_subordinate_busnr(child, max);
646 }
647 /*
648 * Set the subordinate bus number to its real value.
649 */
650 child->subordinate = max;
651 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
652 }
653
654 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
655
656 /* Has only triggered on CardBus, fixup is in yenta_socket */
657 while (bus->parent) {
658 if ((child->subordinate > bus->subordinate) ||
659 (child->number > bus->subordinate) ||
660 (child->number < bus->number) ||
661 (child->subordinate < bus->number)) {
662 pr_debug("PCI: Bus #%02x (-#%02x) is %s"
663 "hidden behind%s bridge #%02x (-#%02x)\n",
664 child->number, child->subordinate,
665 (bus->number > child->subordinate &&
666 bus->subordinate < child->number) ?
667 "wholly " : " partially",
668 bus->self->transparent ? " transparent" : " ",
669 bus->number, bus->subordinate);
670 }
671 bus = bus->parent;
672 }
673
674 out:
675 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
676
677 return max;
678 }
679
680 /*
681 * Read interrupt line and base address registers.
682 * The architecture-dependent code can tweak these, of course.
683 */
684 static void pci_read_irq(struct pci_dev *dev)
685 {
686 unsigned char irq;
687
688 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
689 dev->pin = irq;
690 if (irq)
691 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
692 dev->irq = irq;
693 }
694
695 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
696
697 /**
698 * pci_setup_device - fill in class and map information of a device
699 * @dev: the device structure to fill
700 *
701 * Initialize the device structure with information about the device's
702 * vendor,class,memory and IO-space addresses,IRQ lines etc.
703 * Called at initialisation of the PCI subsystem and by CardBus services.
704 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
705 * or CardBus).
706 */
707 static int pci_setup_device(struct pci_dev * dev)
708 {
709 u32 class;
710
711 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
712 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
713
714 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
715 dev->revision = class & 0xff;
716 class >>= 8; /* upper 3 bytes */
717 dev->class = class;
718 class >>= 8;
719
720 pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
721 dev->vendor, dev->device, class, dev->hdr_type);
722
723 /* "Unknown power state" */
724 dev->current_state = PCI_UNKNOWN;
725
726 /* Early fixups, before probing the BARs */
727 pci_fixup_device(pci_fixup_early, dev);
728 class = dev->class >> 8;
729
730 switch (dev->hdr_type) { /* header type */
731 case PCI_HEADER_TYPE_NORMAL: /* standard header */
732 if (class == PCI_CLASS_BRIDGE_PCI)
733 goto bad;
734 pci_read_irq(dev);
735 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
736 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
737 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
738
739 /*
740 * Do the ugly legacy mode stuff here rather than broken chip
741 * quirk code. Legacy mode ATA controllers have fixed
742 * addresses. These are not always echoed in BAR0-3, and
743 * BAR0-3 in a few cases contain junk!
744 */
745 if (class == PCI_CLASS_STORAGE_IDE) {
746 u8 progif;
747 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
748 if ((progif & 1) == 0) {
749 dev->resource[0].start = 0x1F0;
750 dev->resource[0].end = 0x1F7;
751 dev->resource[0].flags = LEGACY_IO_RESOURCE;
752 dev->resource[1].start = 0x3F6;
753 dev->resource[1].end = 0x3F6;
754 dev->resource[1].flags = LEGACY_IO_RESOURCE;
755 }
756 if ((progif & 4) == 0) {
757 dev->resource[2].start = 0x170;
758 dev->resource[2].end = 0x177;
759 dev->resource[2].flags = LEGACY_IO_RESOURCE;
760 dev->resource[3].start = 0x376;
761 dev->resource[3].end = 0x376;
762 dev->resource[3].flags = LEGACY_IO_RESOURCE;
763 }
764 }
765 break;
766
767 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
768 if (class != PCI_CLASS_BRIDGE_PCI)
769 goto bad;
770 /* The PCI-to-PCI bridge spec requires that subtractive
771 decoding (i.e. transparent) bridge must have programming
772 interface code of 0x01. */
773 pci_read_irq(dev);
774 dev->transparent = ((dev->class & 0xff) == 1);
775 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
776 break;
777
778 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
779 if (class != PCI_CLASS_BRIDGE_CARDBUS)
780 goto bad;
781 pci_read_irq(dev);
782 pci_read_bases(dev, 1, 0);
783 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
784 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
785 break;
786
787 default: /* unknown header */
788 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
789 pci_name(dev), dev->hdr_type);
790 return -1;
791
792 bad:
793 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
794 pci_name(dev), class, dev->hdr_type);
795 dev->class = PCI_CLASS_NOT_DEFINED;
796 }
797
798 /* We found a fine healthy device, go go go... */
799 return 0;
800 }
801
802 /**
803 * pci_release_dev - free a pci device structure when all users of it are finished.
804 * @dev: device that's been disconnected
805 *
806 * Will be called only by the device core when all users of this pci device are
807 * done.
808 */
809 static void pci_release_dev(struct device *dev)
810 {
811 struct pci_dev *pci_dev;
812
813 pci_dev = to_pci_dev(dev);
814 kfree(pci_dev);
815 }
816
817 /**
818 * pci_cfg_space_size - get the configuration space size of the PCI device.
819 * @dev: PCI device
820 *
821 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
822 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
823 * access it. Maybe we don't have a way to generate extended config space
824 * accesses, or the device is behind a reverse Express bridge. So we try
825 * reading the dword at 0x100 which must either be 0 or a valid extended
826 * capability header.
827 */
828 int pci_cfg_space_size(struct pci_dev *dev)
829 {
830 int pos;
831 u32 status;
832
833 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
834 if (!pos) {
835 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
836 if (!pos)
837 goto fail;
838
839 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
840 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
841 goto fail;
842 }
843
844 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
845 goto fail;
846 if (status == 0xffffffff)
847 goto fail;
848
849 return PCI_CFG_SPACE_EXP_SIZE;
850
851 fail:
852 return PCI_CFG_SPACE_SIZE;
853 }
854
855 static void pci_release_bus_bridge_dev(struct device *dev)
856 {
857 kfree(dev);
858 }
859
860 struct pci_dev *alloc_pci_dev(void)
861 {
862 struct pci_dev *dev;
863
864 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
865 if (!dev)
866 return NULL;
867
868 INIT_LIST_HEAD(&dev->global_list);
869 INIT_LIST_HEAD(&dev->bus_list);
870
871 pci_msi_init_pci_dev(dev);
872
873 return dev;
874 }
875 EXPORT_SYMBOL(alloc_pci_dev);
876
877 /*
878 * Read the config data for a PCI device, sanity-check it
879 * and fill in the dev structure...
880 */
881 static struct pci_dev * __devinit
882 pci_scan_device(struct pci_bus *bus, int devfn)
883 {
884 struct pci_dev *dev;
885 u32 l;
886 u8 hdr_type;
887 int delay = 1;
888
889 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
890 return NULL;
891
892 /* some broken boards return 0 or ~0 if a slot is empty: */
893 if (l == 0xffffffff || l == 0x00000000 ||
894 l == 0x0000ffff || l == 0xffff0000)
895 return NULL;
896
897 /* Configuration request Retry Status */
898 while (l == 0xffff0001) {
899 msleep(delay);
900 delay *= 2;
901 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
902 return NULL;
903 /* Card hasn't responded in 60 seconds? Must be stuck. */
904 if (delay > 60 * 1000) {
905 printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
906 "responding\n", pci_domain_nr(bus),
907 bus->number, PCI_SLOT(devfn),
908 PCI_FUNC(devfn));
909 return NULL;
910 }
911 }
912
913 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
914 return NULL;
915
916 dev = alloc_pci_dev();
917 if (!dev)
918 return NULL;
919
920 dev->bus = bus;
921 dev->sysdata = bus->sysdata;
922 dev->dev.parent = bus->bridge;
923 dev->dev.bus = &pci_bus_type;
924 dev->devfn = devfn;
925 dev->hdr_type = hdr_type & 0x7f;
926 dev->multifunction = !!(hdr_type & 0x80);
927 dev->vendor = l & 0xffff;
928 dev->device = (l >> 16) & 0xffff;
929 dev->cfg_size = pci_cfg_space_size(dev);
930 dev->error_state = pci_channel_io_normal;
931
932 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
933 set this higher, assuming the system even supports it. */
934 dev->dma_mask = 0xffffffff;
935 if (pci_setup_device(dev) < 0) {
936 kfree(dev);
937 return NULL;
938 }
939
940 return dev;
941 }
942
943 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
944 {
945 device_initialize(&dev->dev);
946 dev->dev.release = pci_release_dev;
947 pci_dev_get(dev);
948
949 set_dev_node(&dev->dev, pcibus_to_node(bus));
950 dev->dev.dma_mask = &dev->dma_mask;
951 dev->dev.coherent_dma_mask = 0xffffffffull;
952
953 /* Fix up broken headers */
954 pci_fixup_device(pci_fixup_header, dev);
955
956 /*
957 * Add the device to our list of discovered devices
958 * and the bus list for fixup functions, etc.
959 */
960 INIT_LIST_HEAD(&dev->global_list);
961 down_write(&pci_bus_sem);
962 list_add_tail(&dev->bus_list, &bus->devices);
963 up_write(&pci_bus_sem);
964 }
965
966 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
967 {
968 struct pci_dev *dev;
969
970 dev = pci_scan_device(bus, devfn);
971 if (!dev)
972 return NULL;
973
974 pci_device_add(dev, bus);
975
976 return dev;
977 }
978
979 /**
980 * pci_scan_slot - scan a PCI slot on a bus for devices.
981 * @bus: PCI bus to scan
982 * @devfn: slot number to scan (must have zero function.)
983 *
984 * Scan a PCI slot on the specified PCI bus for devices, adding
985 * discovered devices to the @bus->devices list. New devices
986 * will have an empty dev->global_list head.
987 */
988 int pci_scan_slot(struct pci_bus *bus, int devfn)
989 {
990 int func, nr = 0;
991 int scan_all_fns;
992
993 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
994
995 for (func = 0; func < 8; func++, devfn++) {
996 struct pci_dev *dev;
997
998 dev = pci_scan_single_device(bus, devfn);
999 if (dev) {
1000 nr++;
1001
1002 /*
1003 * If this is a single function device,
1004 * don't scan past the first function.
1005 */
1006 if (!dev->multifunction) {
1007 if (func > 0) {
1008 dev->multifunction = 1;
1009 } else {
1010 break;
1011 }
1012 }
1013 } else {
1014 if (func == 0 && !scan_all_fns)
1015 break;
1016 }
1017 }
1018 return nr;
1019 }
1020
1021 unsigned int pci_scan_child_bus(struct pci_bus *bus)
1022 {
1023 unsigned int devfn, pass, max = bus->secondary;
1024 struct pci_dev *dev;
1025
1026 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1027
1028 /* Go find them, Rover! */
1029 for (devfn = 0; devfn < 0x100; devfn += 8)
1030 pci_scan_slot(bus, devfn);
1031
1032 /*
1033 * After performing arch-dependent fixup of the bus, look behind
1034 * all PCI-to-PCI bridges on this bus.
1035 */
1036 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1037 pcibios_fixup_bus(bus);
1038 for (pass=0; pass < 2; pass++)
1039 list_for_each_entry(dev, &bus->devices, bus_list) {
1040 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1041 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1042 max = pci_scan_bridge(bus, dev, max, pass);
1043 }
1044
1045 /*
1046 * We've scanned the bus and so we know all about what's on
1047 * the other side of any bridges that may be on this bus plus
1048 * any devices.
1049 *
1050 * Return how far we've got finding sub-buses.
1051 */
1052 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1053 pci_domain_nr(bus), bus->number, max);
1054 return max;
1055 }
1056
1057 unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
1058 {
1059 unsigned int max;
1060
1061 max = pci_scan_child_bus(bus);
1062
1063 /*
1064 * Make the discovered devices available.
1065 */
1066 pci_bus_add_devices(bus);
1067
1068 return max;
1069 }
1070
1071 struct pci_bus * pci_create_bus(struct device *parent,
1072 int bus, struct pci_ops *ops, void *sysdata)
1073 {
1074 int error;
1075 struct pci_bus *b;
1076 struct device *dev;
1077
1078 b = pci_alloc_bus();
1079 if (!b)
1080 return NULL;
1081
1082 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
1083 if (!dev){
1084 kfree(b);
1085 return NULL;
1086 }
1087
1088 b->sysdata = sysdata;
1089 b->ops = ops;
1090
1091 if (pci_find_bus(pci_domain_nr(b), bus)) {
1092 /* If we already got to this bus through a different bridge, ignore it */
1093 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1094 goto err_out;
1095 }
1096
1097 down_write(&pci_bus_sem);
1098 list_add_tail(&b->node, &pci_root_buses);
1099 up_write(&pci_bus_sem);
1100
1101 memset(dev, 0, sizeof(*dev));
1102 dev->parent = parent;
1103 dev->release = pci_release_bus_bridge_dev;
1104 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
1105 error = device_register(dev);
1106 if (error)
1107 goto dev_reg_err;
1108 b->bridge = get_device(dev);
1109
1110 b->class_dev.class = &pcibus_class;
1111 sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus);
1112 error = class_device_register(&b->class_dev);
1113 if (error)
1114 goto class_dev_reg_err;
1115 error = class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity);
1116 if (error)
1117 goto class_dev_create_file_err;
1118
1119 /* Create legacy_io and legacy_mem files for this bus */
1120 pci_create_legacy_files(b);
1121
1122 error = sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge");
1123 if (error)
1124 goto sys_create_link_err;
1125
1126 b->number = b->secondary = bus;
1127 b->resource[0] = &ioport_resource;
1128 b->resource[1] = &iomem_resource;
1129
1130 return b;
1131
1132 sys_create_link_err:
1133 class_device_remove_file(&b->class_dev, &class_device_attr_cpuaffinity);
1134 class_dev_create_file_err:
1135 class_device_unregister(&b->class_dev);
1136 class_dev_reg_err:
1137 device_unregister(dev);
1138 dev_reg_err:
1139 down_write(&pci_bus_sem);
1140 list_del(&b->node);
1141 up_write(&pci_bus_sem);
1142 err_out:
1143 kfree(dev);
1144 kfree(b);
1145 return NULL;
1146 }
1147 EXPORT_SYMBOL_GPL(pci_create_bus);
1148
1149 struct pci_bus *pci_scan_bus_parented(struct device *parent,
1150 int bus, struct pci_ops *ops, void *sysdata)
1151 {
1152 struct pci_bus *b;
1153
1154 b = pci_create_bus(parent, bus, ops, sysdata);
1155 if (b)
1156 b->subordinate = pci_scan_child_bus(b);
1157 return b;
1158 }
1159 EXPORT_SYMBOL(pci_scan_bus_parented);
1160
1161 #ifdef CONFIG_HOTPLUG
1162 EXPORT_SYMBOL(pci_add_new_bus);
1163 EXPORT_SYMBOL(pci_do_scan_bus);
1164 EXPORT_SYMBOL(pci_scan_slot);
1165 EXPORT_SYMBOL(pci_scan_bridge);
1166 EXPORT_SYMBOL(pci_scan_single_device);
1167 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1168 #endif
1169
1170 static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev *b)
1171 {
1172 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1173 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1174
1175 if (a->bus->number < b->bus->number) return -1;
1176 else if (a->bus->number > b->bus->number) return 1;
1177
1178 if (a->devfn < b->devfn) return -1;
1179 else if (a->devfn > b->devfn) return 1;
1180
1181 return 0;
1182 }
1183
1184 /*
1185 * Yes, this forcably breaks the klist abstraction temporarily. It
1186 * just wants to sort the klist, not change reference counts and
1187 * take/drop locks rapidly in the process. It does all this while
1188 * holding the lock for the list, so objects can't otherwise be
1189 * added/removed while we're swizzling.
1190 */
1191 static void __init pci_insertion_sort_klist(struct pci_dev *a, struct list_head *list)
1192 {
1193 struct list_head *pos;
1194 struct klist_node *n;
1195 struct device *dev;
1196 struct pci_dev *b;
1197
1198 list_for_each(pos, list) {
1199 n = container_of(pos, struct klist_node, n_node);
1200 dev = container_of(n, struct device, knode_bus);
1201 b = to_pci_dev(dev);
1202 if (pci_sort_bf_cmp(a, b) <= 0) {
1203 list_move_tail(&a->dev.knode_bus.n_node, &b->dev.knode_bus.n_node);
1204 return;
1205 }
1206 }
1207 list_move_tail(&a->dev.knode_bus.n_node, list);
1208 }
1209
1210 static void __init pci_sort_breadthfirst_klist(void)
1211 {
1212 LIST_HEAD(sorted_devices);
1213 struct list_head *pos, *tmp;
1214 struct klist_node *n;
1215 struct device *dev;
1216 struct pci_dev *pdev;
1217
1218 spin_lock(&pci_bus_type.klist_devices.k_lock);
1219 list_for_each_safe(pos, tmp, &pci_bus_type.klist_devices.k_list) {
1220 n = container_of(pos, struct klist_node, n_node);
1221 dev = container_of(n, struct device, knode_bus);
1222 pdev = to_pci_dev(dev);
1223 pci_insertion_sort_klist(pdev, &sorted_devices);
1224 }
1225 list_splice(&sorted_devices, &pci_bus_type.klist_devices.k_list);
1226 spin_unlock(&pci_bus_type.klist_devices.k_lock);
1227 }
1228
1229 static void __init pci_insertion_sort_devices(struct pci_dev *a, struct list_head *list)
1230 {
1231 struct pci_dev *b;
1232
1233 list_for_each_entry(b, list, global_list) {
1234 if (pci_sort_bf_cmp(a, b) <= 0) {
1235 list_move_tail(&a->global_list, &b->global_list);
1236 return;
1237 }
1238 }
1239 list_move_tail(&a->global_list, list);
1240 }
1241
1242 static void __init pci_sort_breadthfirst_devices(void)
1243 {
1244 LIST_HEAD(sorted_devices);
1245 struct pci_dev *dev, *tmp;
1246
1247 down_write(&pci_bus_sem);
1248 list_for_each_entry_safe(dev, tmp, &pci_devices, global_list) {
1249 pci_insertion_sort_devices(dev, &sorted_devices);
1250 }
1251 list_splice(&sorted_devices, &pci_devices);
1252 up_write(&pci_bus_sem);
1253 }
1254
1255 void __init pci_sort_breadthfirst(void)
1256 {
1257 pci_sort_breadthfirst_devices();
1258 pci_sort_breadthfirst_klist();
1259 }
1260
Support for the Chinese Samsung S3C2440 based development boards