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fbdev: fix integer as NULL pointer warning
[linux-2.6/mini2440.git] / drivers / video / aty / radeon_base.c
blob400e9264e4564877cc481d8e57c7a83f69ba6a63
1 /*
2 * drivers/video/aty/radeon_base.c
3 *
4 * framebuffer driver for ATI Radeon chipset video boards
5 *
6 * Copyright 2003 Ben. Herrenschmidt <benh@kernel.crashing.org>
7 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
8 *
9 * i2c bits from Luca Tettamanti <kronos@kronoz.cjb.net>
10 *
11 * Special thanks to ATI DevRel team for their hardware donations.
12 *
13 * ...Insert GPL boilerplate here...
14 *
15 * Significant portions of this driver apdated from XFree86 Radeon
16 * driver which has the following copyright notice:
17 *
18 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
19 * VA Linux Systems Inc., Fremont, California.
20 *
21 * All Rights Reserved.
22 *
23 * Permission is hereby granted, free of charge, to any person obtaining
24 * a copy of this software and associated documentation files (the
25 * "Software"), to deal in the Software without restriction, including
26 * without limitation on the rights to use, copy, modify, merge,
27 * publish, distribute, sublicense, and/or sell copies of the Software,
28 * and to permit persons to whom the Software is furnished to do so,
29 * subject to the following conditions:
30 *
31 * The above copyright notice and this permission notice (including the
32 * next paragraph) shall be included in all copies or substantial
33 * portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR
39 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
41 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
42 * DEALINGS IN THE SOFTWARE.
43 *
44 * XFree86 driver authors:
45 *
46 * Kevin E. Martin <martin@xfree86.org>
47 * Rickard E. Faith <faith@valinux.com>
48 * Alan Hourihane <alanh@fairlite.demon.co.uk>
49 *
50 */
51
52
53 #define RADEON_VERSION "0.2.0"
54
55 #include "radeonfb.h"
56
57 #include <linux/module.h>
58 #include <linux/moduleparam.h>
59 #include <linux/kernel.h>
60 #include <linux/errno.h>
61 #include <linux/string.h>
62 #include <linux/ctype.h>
63 #include <linux/mm.h>
64 #include <linux/slab.h>
65 #include <linux/delay.h>
66 #include <linux/time.h>
67 #include <linux/fb.h>
68 #include <linux/ioport.h>
69 #include <linux/init.h>
70 #include <linux/pci.h>
71 #include <linux/vmalloc.h>
72 #include <linux/device.h>
73
74 #include <asm/io.h>
75 #include <linux/uaccess.h>
76
77 #ifdef CONFIG_PPC_OF
78
79 #include <asm/pci-bridge.h>
80 #include "../macmodes.h"
81
82 #ifdef CONFIG_BOOTX_TEXT
83 #include <asm/btext.h>
84 #endif
85
86 #endif /* CONFIG_PPC_OF */
87
88 #ifdef CONFIG_MTRR
89 #include <asm/mtrr.h>
90 #endif
91
92 #include <video/radeon.h>
93 #include <linux/radeonfb.h>
94
95 #include "../edid.h" // MOVE THAT TO include/video
96 #include "ati_ids.h"
97
98 #define MAX_MAPPED_VRAM (2048*2048*4)
99 #define MIN_MAPPED_VRAM (1024*768*1)
100
101 #define CHIP_DEF(id, family, flags) \
102 { PCI_VENDOR_ID_ATI, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (flags) | (CHIP_FAMILY_##family) }
103
104 static struct pci_device_id radeonfb_pci_table[] = {
105 /* Radeon Xpress 200m */
106 CHIP_DEF(PCI_CHIP_RS480_5955, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
107 CHIP_DEF(PCI_CHIP_RS482_5975, RS480, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
108 /* Mobility M6 */
109 CHIP_DEF(PCI_CHIP_RADEON_LY, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
110 CHIP_DEF(PCI_CHIP_RADEON_LZ, RV100, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
111 /* Radeon VE/7000 */
112 CHIP_DEF(PCI_CHIP_RV100_QY, RV100, CHIP_HAS_CRTC2),
113 CHIP_DEF(PCI_CHIP_RV100_QZ, RV100, CHIP_HAS_CRTC2),
114 CHIP_DEF(PCI_CHIP_RN50, RV100, CHIP_HAS_CRTC2),
115 /* Radeon IGP320M (U1) */
116 CHIP_DEF(PCI_CHIP_RS100_4336, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
117 /* Radeon IGP320 (A3) */
118 CHIP_DEF(PCI_CHIP_RS100_4136, RS100, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
119 /* IGP330M/340M/350M (U2) */
120 CHIP_DEF(PCI_CHIP_RS200_4337, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
121 /* IGP330/340/350 (A4) */
122 CHIP_DEF(PCI_CHIP_RS200_4137, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
123 /* Mobility 7000 IGP */
124 CHIP_DEF(PCI_CHIP_RS250_4437, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
125 /* 7000 IGP (A4+) */
126 CHIP_DEF(PCI_CHIP_RS250_4237, RS200, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
127 /* 8500 AIW */
128 CHIP_DEF(PCI_CHIP_R200_BB, R200, CHIP_HAS_CRTC2),
129 CHIP_DEF(PCI_CHIP_R200_BC, R200, CHIP_HAS_CRTC2),
130 /* 8700/8800 */
131 CHIP_DEF(PCI_CHIP_R200_QH, R200, CHIP_HAS_CRTC2),
132 /* 8500 */
133 CHIP_DEF(PCI_CHIP_R200_QL, R200, CHIP_HAS_CRTC2),
134 /* 9100 */
135 CHIP_DEF(PCI_CHIP_R200_QM, R200, CHIP_HAS_CRTC2),
136 /* Mobility M7 */
137 CHIP_DEF(PCI_CHIP_RADEON_LW, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
138 CHIP_DEF(PCI_CHIP_RADEON_LX, RV200, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
139 /* 7500 */
140 CHIP_DEF(PCI_CHIP_RV200_QW, RV200, CHIP_HAS_CRTC2),
141 CHIP_DEF(PCI_CHIP_RV200_QX, RV200, CHIP_HAS_CRTC2),
142 /* Mobility M9 */
143 CHIP_DEF(PCI_CHIP_RV250_Ld, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
144 CHIP_DEF(PCI_CHIP_RV250_Le, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
145 CHIP_DEF(PCI_CHIP_RV250_Lf, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
146 CHIP_DEF(PCI_CHIP_RV250_Lg, RV250, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
147 /* 9000/Pro */
148 CHIP_DEF(PCI_CHIP_RV250_If, RV250, CHIP_HAS_CRTC2),
149 CHIP_DEF(PCI_CHIP_RV250_Ig, RV250, CHIP_HAS_CRTC2),
150
151 CHIP_DEF(PCI_CHIP_RC410_5A62, RC410, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
152 /* Mobility 9100 IGP (U3) */
153 CHIP_DEF(PCI_CHIP_RS300_5835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
154 CHIP_DEF(PCI_CHIP_RS350_7835, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP | CHIP_IS_MOBILITY),
155 /* 9100 IGP (A5) */
156 CHIP_DEF(PCI_CHIP_RS300_5834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
157 CHIP_DEF(PCI_CHIP_RS350_7834, RS300, CHIP_HAS_CRTC2 | CHIP_IS_IGP),
158 /* Mobility 9200 (M9+) */
159 CHIP_DEF(PCI_CHIP_RV280_5C61, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
160 CHIP_DEF(PCI_CHIP_RV280_5C63, RV280, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
161 /* 9200 */
162 CHIP_DEF(PCI_CHIP_RV280_5960, RV280, CHIP_HAS_CRTC2),
163 CHIP_DEF(PCI_CHIP_RV280_5961, RV280, CHIP_HAS_CRTC2),
164 CHIP_DEF(PCI_CHIP_RV280_5962, RV280, CHIP_HAS_CRTC2),
165 CHIP_DEF(PCI_CHIP_RV280_5964, RV280, CHIP_HAS_CRTC2),
166 /* 9500 */
167 CHIP_DEF(PCI_CHIP_R300_AD, R300, CHIP_HAS_CRTC2),
168 CHIP_DEF(PCI_CHIP_R300_AE, R300, CHIP_HAS_CRTC2),
169 /* 9600TX / FireGL Z1 */
170 CHIP_DEF(PCI_CHIP_R300_AF, R300, CHIP_HAS_CRTC2),
171 CHIP_DEF(PCI_CHIP_R300_AG, R300, CHIP_HAS_CRTC2),
172 /* 9700/9500/Pro/FireGL X1 */
173 CHIP_DEF(PCI_CHIP_R300_ND, R300, CHIP_HAS_CRTC2),
174 CHIP_DEF(PCI_CHIP_R300_NE, R300, CHIP_HAS_CRTC2),
175 CHIP_DEF(PCI_CHIP_R300_NF, R300, CHIP_HAS_CRTC2),
176 CHIP_DEF(PCI_CHIP_R300_NG, R300, CHIP_HAS_CRTC2),
177 /* Mobility M10/M11 */
178 CHIP_DEF(PCI_CHIP_RV350_NP, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
179 CHIP_DEF(PCI_CHIP_RV350_NQ, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
180 CHIP_DEF(PCI_CHIP_RV350_NR, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
181 CHIP_DEF(PCI_CHIP_RV350_NS, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
182 CHIP_DEF(PCI_CHIP_RV350_NT, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
183 CHIP_DEF(PCI_CHIP_RV350_NV, RV350, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
184 /* 9600/FireGL T2 */
185 CHIP_DEF(PCI_CHIP_RV350_AP, RV350, CHIP_HAS_CRTC2),
186 CHIP_DEF(PCI_CHIP_RV350_AQ, RV350, CHIP_HAS_CRTC2),
187 CHIP_DEF(PCI_CHIP_RV360_AR, RV350, CHIP_HAS_CRTC2),
188 CHIP_DEF(PCI_CHIP_RV350_AS, RV350, CHIP_HAS_CRTC2),
189 CHIP_DEF(PCI_CHIP_RV350_AT, RV350, CHIP_HAS_CRTC2),
190 CHIP_DEF(PCI_CHIP_RV350_AV, RV350, CHIP_HAS_CRTC2),
191 /* 9800/Pro/FileGL X2 */
192 CHIP_DEF(PCI_CHIP_R350_AH, R350, CHIP_HAS_CRTC2),
193 CHIP_DEF(PCI_CHIP_R350_AI, R350, CHIP_HAS_CRTC2),
194 CHIP_DEF(PCI_CHIP_R350_AJ, R350, CHIP_HAS_CRTC2),
195 CHIP_DEF(PCI_CHIP_R350_AK, R350, CHIP_HAS_CRTC2),
196 CHIP_DEF(PCI_CHIP_R350_NH, R350, CHIP_HAS_CRTC2),
197 CHIP_DEF(PCI_CHIP_R350_NI, R350, CHIP_HAS_CRTC2),
198 CHIP_DEF(PCI_CHIP_R360_NJ, R350, CHIP_HAS_CRTC2),
199 CHIP_DEF(PCI_CHIP_R350_NK, R350, CHIP_HAS_CRTC2),
200 /* Newer stuff */
201 CHIP_DEF(PCI_CHIP_RV380_3E50, RV380, CHIP_HAS_CRTC2),
202 CHIP_DEF(PCI_CHIP_RV380_3E54, RV380, CHIP_HAS_CRTC2),
203 CHIP_DEF(PCI_CHIP_RV380_3150, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
204 CHIP_DEF(PCI_CHIP_RV380_3154, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
205 CHIP_DEF(PCI_CHIP_RV370_5B60, RV380, CHIP_HAS_CRTC2),
206 CHIP_DEF(PCI_CHIP_RV370_5B62, RV380, CHIP_HAS_CRTC2),
207 CHIP_DEF(PCI_CHIP_RV370_5B63, RV380, CHIP_HAS_CRTC2),
208 CHIP_DEF(PCI_CHIP_RV370_5B64, RV380, CHIP_HAS_CRTC2),
209 CHIP_DEF(PCI_CHIP_RV370_5B65, RV380, CHIP_HAS_CRTC2),
210 CHIP_DEF(PCI_CHIP_RV370_5460, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
211 CHIP_DEF(PCI_CHIP_RV370_5464, RV380, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
212 CHIP_DEF(PCI_CHIP_R420_JH, R420, CHIP_HAS_CRTC2),
213 CHIP_DEF(PCI_CHIP_R420_JI, R420, CHIP_HAS_CRTC2),
214 CHIP_DEF(PCI_CHIP_R420_JJ, R420, CHIP_HAS_CRTC2),
215 CHIP_DEF(PCI_CHIP_R420_JK, R420, CHIP_HAS_CRTC2),
216 CHIP_DEF(PCI_CHIP_R420_JL, R420, CHIP_HAS_CRTC2),
217 CHIP_DEF(PCI_CHIP_R420_JM, R420, CHIP_HAS_CRTC2),
218 CHIP_DEF(PCI_CHIP_R420_JN, R420, CHIP_HAS_CRTC2 | CHIP_IS_MOBILITY),
219 CHIP_DEF(PCI_CHIP_R420_JP, R420, CHIP_HAS_CRTC2),
220 CHIP_DEF(PCI_CHIP_R423_UH, R420, CHIP_HAS_CRTC2),
221 CHIP_DEF(PCI_CHIP_R423_UI, R420, CHIP_HAS_CRTC2),
222 CHIP_DEF(PCI_CHIP_R423_UJ, R420, CHIP_HAS_CRTC2),
223 CHIP_DEF(PCI_CHIP_R423_UK, R420, CHIP_HAS_CRTC2),
224 CHIP_DEF(PCI_CHIP_R423_UQ, R420, CHIP_HAS_CRTC2),
225 CHIP_DEF(PCI_CHIP_R423_UR, R420, CHIP_HAS_CRTC2),
226 CHIP_DEF(PCI_CHIP_R423_UT, R420, CHIP_HAS_CRTC2),
227 CHIP_DEF(PCI_CHIP_R423_5D57, R420, CHIP_HAS_CRTC2),
228 /* Original Radeon/7200 */
229 CHIP_DEF(PCI_CHIP_RADEON_QD, RADEON, 0),
230 CHIP_DEF(PCI_CHIP_RADEON_QE, RADEON, 0),
231 CHIP_DEF(PCI_CHIP_RADEON_QF, RADEON, 0),
232 CHIP_DEF(PCI_CHIP_RADEON_QG, RADEON, 0),
233 { 0, }
234 };
235 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
236
237
238 typedef struct {
239 u16 reg;
240 u32 val;
241 } reg_val;
242
243
244 /* these common regs are cleared before mode setting so they do not
245 * interfere with anything
246 */
247 static reg_val common_regs[] = {
248 { OVR_CLR, 0 },
249 { OVR_WID_LEFT_RIGHT, 0 },
250 { OVR_WID_TOP_BOTTOM, 0 },
251 { OV0_SCALE_CNTL, 0 },
252 { SUBPIC_CNTL, 0 },
253 { VIPH_CONTROL, 0 },
254 { I2C_CNTL_1, 0 },
255 { GEN_INT_CNTL, 0 },
256 { CAP0_TRIG_CNTL, 0 },
257 { CAP1_TRIG_CNTL, 0 },
258 };
259
260 /*
261 * globals
262 */
263
264 static char *mode_option;
265 static char *monitor_layout;
266 static int noaccel = 0;
267 static int default_dynclk = -2;
268 static int nomodeset = 0;
269 static int ignore_edid = 0;
270 static int mirror = 0;
271 static int panel_yres = 0;
272 static int force_dfp = 0;
273 static int force_measure_pll = 0;
274 #ifdef CONFIG_MTRR
275 static int nomtrr = 0;
276 #endif
277 static int force_sleep;
278 static int ignore_devlist;
279 #ifdef CONFIG_PMAC_BACKLIGHT
280 static int backlight = 1;
281 #else
282 static int backlight = 0;
283 #endif
284
285 /*
286 * prototypes
287 */
288
289 static void radeon_unmap_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
290 {
291 if (!rinfo->bios_seg)
292 return;
293 pci_unmap_rom(dev, rinfo->bios_seg);
294 }
295
296 static int __devinit radeon_map_ROM(struct radeonfb_info *rinfo, struct pci_dev *dev)
297 {
298 void __iomem *rom;
299 u16 dptr;
300 u8 rom_type;
301 size_t rom_size;
302
303 /* If this is a primary card, there is a shadow copy of the
304 * ROM somewhere in the first meg. We will just ignore the copy
305 * and use the ROM directly.
306 */
307
308 /* Fix from ATI for problem with Radeon hardware not leaving ROM enabled */
309 unsigned int temp;
310 temp = INREG(MPP_TB_CONFIG);
311 temp &= 0x00ffffffu;
312 temp |= 0x04 << 24;
313 OUTREG(MPP_TB_CONFIG, temp);
314 temp = INREG(MPP_TB_CONFIG);
315
316 rom = pci_map_rom(dev, &rom_size);
317 if (!rom) {
318 printk(KERN_ERR "radeonfb (%s): ROM failed to map\n",
319 pci_name(rinfo->pdev));
320 return -ENOMEM;
321 }
322
323 rinfo->bios_seg = rom;
324
325 /* Very simple test to make sure it appeared */
326 if (BIOS_IN16(0) != 0xaa55) {
327 printk(KERN_DEBUG "radeonfb (%s): Invalid ROM signature %x "
328 "should be 0xaa55\n",
329 pci_name(rinfo->pdev), BIOS_IN16(0));
330 goto failed;
331 }
332 /* Look for the PCI data to check the ROM type */
333 dptr = BIOS_IN16(0x18);
334
335 /* Check the PCI data signature. If it's wrong, we still assume a normal x86 ROM
336 * for now, until I've verified this works everywhere. The goal here is more
337 * to phase out Open Firmware images.
338 *
339 * Currently, we only look at the first PCI data, we could iteratre and deal with
340 * them all, and we should use fb_bios_start relative to start of image and not
341 * relative start of ROM, but so far, I never found a dual-image ATI card
342 *
343 * typedef struct {
344 * u32 signature; + 0x00
345 * u16 vendor; + 0x04
346 * u16 device; + 0x06
347 * u16 reserved_1; + 0x08
348 * u16 dlen; + 0x0a
349 * u8 drevision; + 0x0c
350 * u8 class_hi; + 0x0d
351 * u16 class_lo; + 0x0e
352 * u16 ilen; + 0x10
353 * u16 irevision; + 0x12
354 * u8 type; + 0x14
355 * u8 indicator; + 0x15
356 * u16 reserved_2; + 0x16
357 * } pci_data_t;
358 */
359 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
360 printk(KERN_WARNING "radeonfb (%s): PCI DATA signature in ROM"
361 "incorrect: %08x\n", pci_name(rinfo->pdev), BIOS_IN32(dptr));
362 goto anyway;
363 }
364 rom_type = BIOS_IN8(dptr + 0x14);
365 switch(rom_type) {
366 case 0:
367 printk(KERN_INFO "radeonfb: Found Intel x86 BIOS ROM Image\n");
368 break;
369 case 1:
370 printk(KERN_INFO "radeonfb: Found Open Firmware ROM Image\n");
371 goto failed;
372 case 2:
373 printk(KERN_INFO "radeonfb: Found HP PA-RISC ROM Image\n");
374 goto failed;
375 default:
376 printk(KERN_INFO "radeonfb: Found unknown type %d ROM Image\n", rom_type);
377 goto failed;
378 }
379 anyway:
380 /* Locate the flat panel infos, do some sanity checking !!! */
381 rinfo->fp_bios_start = BIOS_IN16(0x48);
382 return 0;
383
384 failed:
385 rinfo->bios_seg = NULL;
386 radeon_unmap_ROM(rinfo, dev);
387 return -ENXIO;
388 }
389
390 #ifdef CONFIG_X86
391 static int __devinit radeon_find_mem_vbios(struct radeonfb_info *rinfo)
392 {
393 /* I simplified this code as we used to miss the signatures in
394 * a lot of case. It's now closer to XFree, we just don't check
395 * for signatures at all... Something better will have to be done
396 * if we end up having conflicts
397 */
398 u32 segstart;
399 void __iomem *rom_base = NULL;
400
401 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
402 rom_base = ioremap(segstart, 0x10000);
403 if (rom_base == NULL)
404 return -ENOMEM;
405 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
406 break;
407 iounmap(rom_base);
408 rom_base = NULL;
409 }
410 if (rom_base == NULL)
411 return -ENXIO;
412
413 /* Locate the flat panel infos, do some sanity checking !!! */
414 rinfo->bios_seg = rom_base;
415 rinfo->fp_bios_start = BIOS_IN16(0x48);
416
417 return 0;
418 }
419 #endif
420
421 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
422 /*
423 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
424 * tree. Hopefully, ATI OF driver is kind enough to fill these
425 */
426 static int __devinit radeon_read_xtal_OF (struct radeonfb_info *rinfo)
427 {
428 struct device_node *dp = rinfo->of_node;
429 const u32 *val;
430
431 if (dp == NULL)
432 return -ENODEV;
433 val = of_get_property(dp, "ATY,RefCLK", NULL);
434 if (!val || !*val) {
435 printk(KERN_WARNING "radeonfb: No ATY,RefCLK property !\n");
436 return -EINVAL;
437 }
438
439 rinfo->pll.ref_clk = (*val) / 10;
440
441 val = of_get_property(dp, "ATY,SCLK", NULL);
442 if (val && *val)
443 rinfo->pll.sclk = (*val) / 10;
444
445 val = of_get_property(dp, "ATY,MCLK", NULL);
446 if (val && *val)
447 rinfo->pll.mclk = (*val) / 10;
448
449 return 0;
450 }
451 #endif /* CONFIG_PPC_OF || CONFIG_SPARC */
452
453 /*
454 * Read PLL infos from chip registers
455 */
456 static int __devinit radeon_probe_pll_params(struct radeonfb_info *rinfo)
457 {
458 unsigned char ppll_div_sel;
459 unsigned Ns, Nm, M;
460 unsigned sclk, mclk, tmp, ref_div;
461 int hTotal, vTotal, num, denom, m, n;
462 unsigned long long hz, vclk;
463 long xtal;
464 struct timeval start_tv, stop_tv;
465 long total_secs, total_usecs;
466 int i;
467
468 /* Ugh, we cut interrupts, bad bad bad, but we want some precision
469 * here, so... --BenH
470 */
471
472 /* Flush PCI buffers ? */
473 tmp = INREG16(DEVICE_ID);
474
475 local_irq_disable();
476
477 for(i=0; i<1000000; i++)
478 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
479 break;
480
481 do_gettimeofday(&start_tv);
482
483 for(i=0; i<1000000; i++)
484 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) != 0)
485 break;
486
487 for(i=0; i<1000000; i++)
488 if (((INREG(CRTC_VLINE_CRNT_VLINE) >> 16) & 0x3ff) == 0)
489 break;
490
491 do_gettimeofday(&stop_tv);
492
493 local_irq_enable();
494
495 total_secs = stop_tv.tv_sec - start_tv.tv_sec;
496 if (total_secs > 10)
497 return -1;
498 total_usecs = stop_tv.tv_usec - start_tv.tv_usec;
499 total_usecs += total_secs * 1000000;
500 if (total_usecs < 0)
501 total_usecs = -total_usecs;
502 hz = 1000000/total_usecs;
503
504 hTotal = ((INREG(CRTC_H_TOTAL_DISP) & 0x1ff) + 1) * 8;
505 vTotal = ((INREG(CRTC_V_TOTAL_DISP) & 0x3ff) + 1);
506 vclk = (long long)hTotal * (long long)vTotal * hz;
507
508 switch((INPLL(PPLL_REF_DIV) & 0x30000) >> 16) {
509 case 0:
510 default:
511 num = 1;
512 denom = 1;
513 break;
514 case 1:
515 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 16) & 0xff);
516 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
517 num = 2*n;
518 denom = 2*m;
519 break;
520 case 2:
521 n = ((INPLL(M_SPLL_REF_FB_DIV) >> 8) & 0xff);
522 m = (INPLL(M_SPLL_REF_FB_DIV) & 0xff);
523 num = 2*n;
524 denom = 2*m;
525 break;
526 }
527
528 ppll_div_sel = INREG8(CLOCK_CNTL_INDEX + 1) & 0x3;
529 radeon_pll_errata_after_index(rinfo);
530
531 n = (INPLL(PPLL_DIV_0 + ppll_div_sel) & 0x7ff);
532 m = (INPLL(PPLL_REF_DIV) & 0x3ff);
533
534 num *= n;
535 denom *= m;
536
537 switch ((INPLL(PPLL_DIV_0 + ppll_div_sel) >> 16) & 0x7) {
538 case 1:
539 denom *= 2;
540 break;
541 case 2:
542 denom *= 4;
543 break;
544 case 3:
545 denom *= 8;
546 break;
547 case 4:
548 denom *= 3;
549 break;
550 case 6:
551 denom *= 6;
552 break;
553 case 7:
554 denom *= 12;
555 break;
556 }
557
558 vclk *= denom;
559 do_div(vclk, 1000 * num);
560 xtal = vclk;
561
562 if ((xtal > 26900) && (xtal < 27100))
563 xtal = 2700;
564 else if ((xtal > 14200) && (xtal < 14400))
565 xtal = 1432;
566 else if ((xtal > 29400) && (xtal < 29600))
567 xtal = 2950;
568 else {
569 printk(KERN_WARNING "xtal calculation failed: %ld\n", xtal);
570 return -1;
571 }
572
573 tmp = INPLL(M_SPLL_REF_FB_DIV);
574 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
575
576 Ns = (tmp & 0xff0000) >> 16;
577 Nm = (tmp & 0xff00) >> 8;
578 M = (tmp & 0xff);
579 sclk = round_div((2 * Ns * xtal), (2 * M));
580 mclk = round_div((2 * Nm * xtal), (2 * M));
581
582 /* we're done, hopefully these are sane values */
583 rinfo->pll.ref_clk = xtal;
584 rinfo->pll.ref_div = ref_div;
585 rinfo->pll.sclk = sclk;
586 rinfo->pll.mclk = mclk;
587
588 return 0;
589 }
590
591 /*
592 * Retrieve PLL infos by different means (BIOS, Open Firmware, register probing...)
593 */
594 static void __devinit radeon_get_pllinfo(struct radeonfb_info *rinfo)
595 {
596 /*
597 * In the case nothing works, these are defaults; they are mostly
598 * incomplete, however. It does provide ppll_max and _min values
599 * even for most other methods, however.
600 */
601 switch (rinfo->chipset) {
602 case PCI_DEVICE_ID_ATI_RADEON_QW:
603 case PCI_DEVICE_ID_ATI_RADEON_QX:
604 rinfo->pll.ppll_max = 35000;
605 rinfo->pll.ppll_min = 12000;
606 rinfo->pll.mclk = 23000;
607 rinfo->pll.sclk = 23000;
608 rinfo->pll.ref_clk = 2700;
609 break;
610 case PCI_DEVICE_ID_ATI_RADEON_QL:
611 case PCI_DEVICE_ID_ATI_RADEON_QN:
612 case PCI_DEVICE_ID_ATI_RADEON_QO:
613 case PCI_DEVICE_ID_ATI_RADEON_Ql:
614 case PCI_DEVICE_ID_ATI_RADEON_BB:
615 rinfo->pll.ppll_max = 35000;
616 rinfo->pll.ppll_min = 12000;
617 rinfo->pll.mclk = 27500;
618 rinfo->pll.sclk = 27500;
619 rinfo->pll.ref_clk = 2700;
620 break;
621 case PCI_DEVICE_ID_ATI_RADEON_Id:
622 case PCI_DEVICE_ID_ATI_RADEON_Ie:
623 case PCI_DEVICE_ID_ATI_RADEON_If:
624 case PCI_DEVICE_ID_ATI_RADEON_Ig:
625 rinfo->pll.ppll_max = 35000;
626 rinfo->pll.ppll_min = 12000;
627 rinfo->pll.mclk = 25000;
628 rinfo->pll.sclk = 25000;
629 rinfo->pll.ref_clk = 2700;
630 break;
631 case PCI_DEVICE_ID_ATI_RADEON_ND:
632 case PCI_DEVICE_ID_ATI_RADEON_NE:
633 case PCI_DEVICE_ID_ATI_RADEON_NF:
634 case PCI_DEVICE_ID_ATI_RADEON_NG:
635 rinfo->pll.ppll_max = 40000;
636 rinfo->pll.ppll_min = 20000;
637 rinfo->pll.mclk = 27000;
638 rinfo->pll.sclk = 27000;
639 rinfo->pll.ref_clk = 2700;
640 break;
641 case PCI_DEVICE_ID_ATI_RADEON_QD:
642 case PCI_DEVICE_ID_ATI_RADEON_QE:
643 case PCI_DEVICE_ID_ATI_RADEON_QF:
644 case PCI_DEVICE_ID_ATI_RADEON_QG:
645 default:
646 rinfo->pll.ppll_max = 35000;
647 rinfo->pll.ppll_min = 12000;
648 rinfo->pll.mclk = 16600;
649 rinfo->pll.sclk = 16600;
650 rinfo->pll.ref_clk = 2700;
651 break;
652 }
653 rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
654
655
656 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
657 /*
658 * Retrieve PLL infos from Open Firmware first
659 */
660 if (!force_measure_pll && radeon_read_xtal_OF(rinfo) == 0) {
661 printk(KERN_INFO "radeonfb: Retrieved PLL infos from Open Firmware\n");
662 goto found;
663 }
664 #endif /* CONFIG_PPC_OF || CONFIG_SPARC */
665
666 /*
667 * Check out if we have an X86 which gave us some PLL informations
668 * and if yes, retrieve them
669 */
670 if (!force_measure_pll && rinfo->bios_seg) {
671 u16 pll_info_block = BIOS_IN16(rinfo->fp_bios_start + 0x30);
672
673 rinfo->pll.sclk = BIOS_IN16(pll_info_block + 0x08);
674 rinfo->pll.mclk = BIOS_IN16(pll_info_block + 0x0a);
675 rinfo->pll.ref_clk = BIOS_IN16(pll_info_block + 0x0e);
676 rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10);
677 rinfo->pll.ppll_min = BIOS_IN32(pll_info_block + 0x12);
678 rinfo->pll.ppll_max = BIOS_IN32(pll_info_block + 0x16);
679
680 printk(KERN_INFO "radeonfb: Retrieved PLL infos from BIOS\n");
681 goto found;
682 }
683
684 /*
685 * We didn't get PLL parameters from either OF or BIOS, we try to
686 * probe them
687 */
688 if (radeon_probe_pll_params(rinfo) == 0) {
689 printk(KERN_INFO "radeonfb: Retrieved PLL infos from registers\n");
690 goto found;
691 }
692
693 /*
694 * Fall back to already-set defaults...
695 */
696 printk(KERN_INFO "radeonfb: Used default PLL infos\n");
697
698 found:
699 /*
700 * Some methods fail to retrieve SCLK and MCLK values, we apply default
701 * settings in this case (200Mhz). If that really happne often, we could
702 * fetch from registers instead...
703 */
704 if (rinfo->pll.mclk == 0)
705 rinfo->pll.mclk = 20000;
706 if (rinfo->pll.sclk == 0)
707 rinfo->pll.sclk = 20000;
708
709 printk("radeonfb: Reference=%d.%02d MHz (RefDiv=%d) Memory=%d.%02d Mhz, System=%d.%02d MHz\n",
710 rinfo->pll.ref_clk / 100, rinfo->pll.ref_clk % 100,
711 rinfo->pll.ref_div,
712 rinfo->pll.mclk / 100, rinfo->pll.mclk % 100,
713 rinfo->pll.sclk / 100, rinfo->pll.sclk % 100);
714 printk("radeonfb: PLL min %d max %d\n", rinfo->pll.ppll_min, rinfo->pll.ppll_max);
715 }
716
717 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
718 {
719 struct radeonfb_info *rinfo = info->par;
720 struct fb_var_screeninfo v;
721 int nom, den;
722 unsigned int pitch;
723
724 if (radeon_match_mode(rinfo, &v, var))
725 return -EINVAL;
726
727 switch (v.bits_per_pixel) {
728 case 0 ... 8:
729 v.bits_per_pixel = 8;
730 break;
731 case 9 ... 16:
732 v.bits_per_pixel = 16;
733 break;
734 case 17 ... 24:
735 #if 0 /* Doesn't seem to work */
736 v.bits_per_pixel = 24;
737 break;
738 #endif
739 return -EINVAL;
740 case 25 ... 32:
741 v.bits_per_pixel = 32;
742 break;
743 default:
744 return -EINVAL;
745 }
746
747 switch (var_to_depth(&v)) {
748 case 8:
749 nom = den = 1;
750 v.red.offset = v.green.offset = v.blue.offset = 0;
751 v.red.length = v.green.length = v.blue.length = 8;
752 v.transp.offset = v.transp.length = 0;
753 break;
754 case 15:
755 nom = 2;
756 den = 1;
757 v.red.offset = 10;
758 v.green.offset = 5;
759 v.blue.offset = 0;
760 v.red.length = v.green.length = v.blue.length = 5;
761 v.transp.offset = v.transp.length = 0;
762 break;
763 case 16:
764 nom = 2;
765 den = 1;
766 v.red.offset = 11;
767 v.green.offset = 5;
768 v.blue.offset = 0;
769 v.red.length = 5;
770 v.green.length = 6;
771 v.blue.length = 5;
772 v.transp.offset = v.transp.length = 0;
773 break;
774 case 24:
775 nom = 4;
776 den = 1;
777 v.red.offset = 16;
778 v.green.offset = 8;
779 v.blue.offset = 0;
780 v.red.length = v.blue.length = v.green.length = 8;
781 v.transp.offset = v.transp.length = 0;
782 break;
783 case 32:
784 nom = 4;
785 den = 1;
786 v.red.offset = 16;
787 v.green.offset = 8;
788 v.blue.offset = 0;
789 v.red.length = v.blue.length = v.green.length = 8;
790 v.transp.offset = 24;
791 v.transp.length = 8;
792 break;
793 default:
794 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
795 var->xres, var->yres, var->bits_per_pixel);
796 return -EINVAL;
797 }
798
799 if (v.yres_virtual < v.yres)
800 v.yres_virtual = v.yres;
801 if (v.xres_virtual < v.xres)
802 v.xres_virtual = v.xres;
803
804
805 /* XXX I'm adjusting xres_virtual to the pitch, that may help XFree
806 * with some panels, though I don't quite like this solution
807 */
808 if (rinfo->info->flags & FBINFO_HWACCEL_DISABLED) {
809 v.xres_virtual = v.xres_virtual & ~7ul;
810 } else {
811 pitch = ((v.xres_virtual * ((v.bits_per_pixel + 1) / 8) + 0x3f)
812 & ~(0x3f)) >> 6;
813 v.xres_virtual = (pitch << 6) / ((v.bits_per_pixel + 1) / 8);
814 }
815
816 if (((v.xres_virtual * v.yres_virtual * nom) / den) > rinfo->mapped_vram)
817 return -EINVAL;
818
819 if (v.xres_virtual < v.xres)
820 v.xres = v.xres_virtual;
821
822 if (v.xoffset < 0)
823 v.xoffset = 0;
824 if (v.yoffset < 0)
825 v.yoffset = 0;
826
827 if (v.xoffset > v.xres_virtual - v.xres)
828 v.xoffset = v.xres_virtual - v.xres - 1;
829
830 if (v.yoffset > v.yres_virtual - v.yres)
831 v.yoffset = v.yres_virtual - v.yres - 1;
832
833 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
834 v.transp.offset = v.transp.length =
835 v.transp.msb_right = 0;
836
837 memcpy(var, &v, sizeof(v));
838
839 return 0;
840 }
841
842
843 static int radeonfb_pan_display (struct fb_var_screeninfo *var,
844 struct fb_info *info)
845 {
846 struct radeonfb_info *rinfo = info->par;
847
848 if ((var->xoffset + var->xres > var->xres_virtual)
849 || (var->yoffset + var->yres > var->yres_virtual))
850 return -EINVAL;
851
852 if (rinfo->asleep)
853 return 0;
854
855 radeon_fifo_wait(2);
856 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
857 * var->bits_per_pixel / 8) & ~7);
858 return 0;
859 }
860
861
862 static int radeonfb_ioctl (struct fb_info *info, unsigned int cmd,
863 unsigned long arg)
864 {
865 struct radeonfb_info *rinfo = info->par;
866 unsigned int tmp;
867 u32 value = 0;
868 int rc;
869
870 switch (cmd) {
871 /*
872 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
873 * and do something better using 2nd CRTC instead of just hackish
874 * routing to second output
875 */
876 case FBIO_RADEON_SET_MIRROR:
877 if (!rinfo->is_mobility)
878 return -EINVAL;
879
880 rc = get_user(value, (__u32 __user *)arg);
881
882 if (rc)
883 return rc;
884
885 radeon_fifo_wait(2);
886 if (value & 0x01) {
887 tmp = INREG(LVDS_GEN_CNTL);
888
889 tmp |= (LVDS_ON | LVDS_BLON);
890 } else {
891 tmp = INREG(LVDS_GEN_CNTL);
892
893 tmp &= ~(LVDS_ON | LVDS_BLON);
894 }
895
896 OUTREG(LVDS_GEN_CNTL, tmp);
897
898 if (value & 0x02) {
899 tmp = INREG(CRTC_EXT_CNTL);
900 tmp |= CRTC_CRT_ON;
901
902 mirror = 1;
903 } else {
904 tmp = INREG(CRTC_EXT_CNTL);
905 tmp &= ~CRTC_CRT_ON;
906
907 mirror = 0;
908 }
909
910 OUTREG(CRTC_EXT_CNTL, tmp);
911
912 return 0;
913 case FBIO_RADEON_GET_MIRROR:
914 if (!rinfo->is_mobility)
915 return -EINVAL;
916
917 tmp = INREG(LVDS_GEN_CNTL);
918 if ((LVDS_ON | LVDS_BLON) & tmp)
919 value |= 0x01;
920
921 tmp = INREG(CRTC_EXT_CNTL);
922 if (CRTC_CRT_ON & tmp)
923 value |= 0x02;
924
925 return put_user(value, (__u32 __user *)arg);
926 default:
927 return -EINVAL;
928 }
929
930 return -EINVAL;
931 }
932
933
934 int radeon_screen_blank(struct radeonfb_info *rinfo, int blank, int mode_switch)
935 {
936 u32 val;
937 u32 tmp_pix_clks;
938 int unblank = 0;
939
940 if (rinfo->lock_blank)
941 return 0;
942
943 radeon_engine_idle();
944
945 val = INREG(CRTC_EXT_CNTL);
946 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
947 CRTC_VSYNC_DIS);
948 switch (blank) {
949 case FB_BLANK_VSYNC_SUSPEND:
950 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
951 break;
952 case FB_BLANK_HSYNC_SUSPEND:
953 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
954 break;
955 case FB_BLANK_POWERDOWN:
956 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
957 CRTC_HSYNC_DIS);
958 break;
959 case FB_BLANK_NORMAL:
960 val |= CRTC_DISPLAY_DIS;
961 break;
962 case FB_BLANK_UNBLANK:
963 default:
964 unblank = 1;
965 }
966 OUTREG(CRTC_EXT_CNTL, val);
967
968
969 switch (rinfo->mon1_type) {
970 case MT_DFP:
971 if (unblank)
972 OUTREGP(FP_GEN_CNTL, (FP_FPON | FP_TMDS_EN),
973 ~(FP_FPON | FP_TMDS_EN));
974 else {
975 if (mode_switch || blank == FB_BLANK_NORMAL)
976 break;
977 OUTREGP(FP_GEN_CNTL, 0, ~(FP_FPON | FP_TMDS_EN));
978 }
979 break;
980 case MT_LCD:
981 del_timer_sync(&rinfo->lvds_timer);
982 val = INREG(LVDS_GEN_CNTL);
983 if (unblank) {
984 u32 target_val = (val & ~LVDS_DISPLAY_DIS) | LVDS_BLON | LVDS_ON
985 | LVDS_EN | (rinfo->init_state.lvds_gen_cntl
986 & (LVDS_DIGON | LVDS_BL_MOD_EN));
987 if ((val ^ target_val) == LVDS_DISPLAY_DIS)
988 OUTREG(LVDS_GEN_CNTL, target_val);
989 else if ((val ^ target_val) != 0) {
990 OUTREG(LVDS_GEN_CNTL, target_val
991 & ~(LVDS_ON | LVDS_BL_MOD_EN));
992 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
993 rinfo->init_state.lvds_gen_cntl |=
994 target_val & LVDS_STATE_MASK;
995 if (mode_switch) {
996 radeon_msleep(rinfo->panel_info.pwr_delay);
997 OUTREG(LVDS_GEN_CNTL, target_val);
998 }
999 else {
1000 rinfo->pending_lvds_gen_cntl = target_val;
1001 mod_timer(&rinfo->lvds_timer,
1002 jiffies +
1003 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1004 }
1005 }
1006 } else {
1007 val |= LVDS_DISPLAY_DIS;
1008 OUTREG(LVDS_GEN_CNTL, val);
1009
1010 /* We don't do a full switch-off on a simple mode switch */
1011 if (mode_switch || blank == FB_BLANK_NORMAL)
1012 break;
1013
1014 /* Asic bug, when turning off LVDS_ON, we have to make sure
1015 * RADEON_PIXCLK_LVDS_ALWAYS_ON bit is off
1016 */
1017 tmp_pix_clks = INPLL(PIXCLKS_CNTL);
1018 if (rinfo->is_mobility || rinfo->is_IGP)
1019 OUTPLLP(PIXCLKS_CNTL, 0, ~PIXCLK_LVDS_ALWAYS_ONb);
1020 val &= ~(LVDS_BL_MOD_EN);
1021 OUTREG(LVDS_GEN_CNTL, val);
1022 udelay(100);
1023 val &= ~(LVDS_ON | LVDS_EN);
1024 OUTREG(LVDS_GEN_CNTL, val);
1025 val &= ~LVDS_DIGON;
1026 rinfo->pending_lvds_gen_cntl = val;
1027 mod_timer(&rinfo->lvds_timer,
1028 jiffies +
1029 msecs_to_jiffies(rinfo->panel_info.pwr_delay));
1030 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
1031 rinfo->init_state.lvds_gen_cntl |= val & LVDS_STATE_MASK;
1032 if (rinfo->is_mobility || rinfo->is_IGP)
1033 OUTPLL(PIXCLKS_CNTL, tmp_pix_clks);
1034 }
1035 break;
1036 case MT_CRT:
1037 // todo: powerdown DAC
1038 default:
1039 break;
1040 }
1041
1042 return 0;
1043 }
1044
1045 static int radeonfb_blank (int blank, struct fb_info *info)
1046 {
1047 struct radeonfb_info *rinfo = info->par;
1048
1049 if (rinfo->asleep)
1050 return 0;
1051
1052 return radeon_screen_blank(rinfo, blank, 0);
1053 }
1054
1055 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
1056 unsigned blue, unsigned transp,
1057 struct radeonfb_info *rinfo)
1058 {
1059 u32 pindex;
1060 unsigned int i;
1061
1062
1063 if (regno > 255)
1064 return -EINVAL;
1065
1066 red >>= 8;
1067 green >>= 8;
1068 blue >>= 8;
1069 rinfo->palette[regno].red = red;
1070 rinfo->palette[regno].green = green;
1071 rinfo->palette[regno].blue = blue;
1072
1073 /* default */
1074 pindex = regno;
1075
1076 if (!rinfo->asleep) {
1077 radeon_fifo_wait(9);
1078
1079 if (rinfo->bpp == 16) {
1080 pindex = regno * 8;
1081
1082 if (rinfo->depth == 16 && regno > 63)
1083 return -EINVAL;
1084 if (rinfo->depth == 15 && regno > 31)
1085 return -EINVAL;
1086
1087 /* For 565, the green component is mixed one order
1088 * below
1089 */
1090 if (rinfo->depth == 16) {
1091 OUTREG(PALETTE_INDEX, pindex>>1);
1092 OUTREG(PALETTE_DATA,
1093 (rinfo->palette[regno>>1].red << 16) |
1094 (green << 8) |
1095 (rinfo->palette[regno>>1].blue));
1096 green = rinfo->palette[regno<<1].green;
1097 }
1098 }
1099
1100 if (rinfo->depth != 16 || regno < 32) {
1101 OUTREG(PALETTE_INDEX, pindex);
1102 OUTREG(PALETTE_DATA, (red << 16) |
1103 (green << 8) | blue);
1104 }
1105 }
1106 if (regno < 16) {
1107 u32 *pal = rinfo->info->pseudo_palette;
1108 switch (rinfo->depth) {
1109 case 15:
1110 pal[regno] = (regno << 10) | (regno << 5) | regno;
1111 break;
1112 case 16:
1113 pal[regno] = (regno << 11) | (regno << 5) | regno;
1114 break;
1115 case 24:
1116 pal[regno] = (regno << 16) | (regno << 8) | regno;
1117 break;
1118 case 32:
1119 i = (regno << 8) | regno;
1120 pal[regno] = (i << 16) | i;
1121 break;
1122 }
1123 }
1124 return 0;
1125 }
1126
1127 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1128 unsigned blue, unsigned transp,
1129 struct fb_info *info)
1130 {
1131 struct radeonfb_info *rinfo = info->par;
1132 u32 dac_cntl2, vclk_cntl = 0;
1133 int rc;
1134
1135 if (!rinfo->asleep) {
1136 if (rinfo->is_mobility) {
1137 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1138 OUTPLL(VCLK_ECP_CNTL,
1139 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1140 }
1141
1142 /* Make sure we are on first palette */
1143 if (rinfo->has_CRTC2) {
1144 dac_cntl2 = INREG(DAC_CNTL2);
1145 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1146 OUTREG(DAC_CNTL2, dac_cntl2);
1147 }
1148 }
1149
1150 rc = radeon_setcolreg (regno, red, green, blue, transp, rinfo);
1151
1152 if (!rinfo->asleep && rinfo->is_mobility)
1153 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1154
1155 return rc;
1156 }
1157
1158 static int radeonfb_setcmap(struct fb_cmap *cmap, struct fb_info *info)
1159 {
1160 struct radeonfb_info *rinfo = info->par;
1161 u16 *red, *green, *blue, *transp;
1162 u32 dac_cntl2, vclk_cntl = 0;
1163 int i, start, rc = 0;
1164
1165 if (!rinfo->asleep) {
1166 if (rinfo->is_mobility) {
1167 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1168 OUTPLL(VCLK_ECP_CNTL,
1169 vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1170 }
1171
1172 /* Make sure we are on first palette */
1173 if (rinfo->has_CRTC2) {
1174 dac_cntl2 = INREG(DAC_CNTL2);
1175 dac_cntl2 &= ~DAC2_PALETTE_ACCESS_CNTL;
1176 OUTREG(DAC_CNTL2, dac_cntl2);
1177 }
1178 }
1179
1180 red = cmap->red;
1181 green = cmap->green;
1182 blue = cmap->blue;
1183 transp = cmap->transp;
1184 start = cmap->start;
1185
1186 for (i = 0; i < cmap->len; i++) {
1187 u_int hred, hgreen, hblue, htransp = 0xffff;
1188
1189 hred = *red++;
1190 hgreen = *green++;
1191 hblue = *blue++;
1192 if (transp)
1193 htransp = *transp++;
1194 rc = radeon_setcolreg (start++, hred, hgreen, hblue, htransp,
1195 rinfo);
1196 if (rc)
1197 break;
1198 }
1199
1200 if (!rinfo->asleep && rinfo->is_mobility)
1201 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1202
1203 return rc;
1204 }
1205
1206 static void radeon_save_state (struct radeonfb_info *rinfo,
1207 struct radeon_regs *save)
1208 {
1209 /* CRTC regs */
1210 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1211 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1212 save->crtc_more_cntl = INREG(CRTC_MORE_CNTL);
1213 save->dac_cntl = INREG(DAC_CNTL);
1214 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1215 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1216 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1217 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1218 save->crtc_pitch = INREG(CRTC_PITCH);
1219 save->surface_cntl = INREG(SURFACE_CNTL);
1220
1221 /* FP regs */
1222 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1223 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1224 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1225 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1226 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1227 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1228 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1229 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1230 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1231 save->tmds_crc = INREG(TMDS_CRC);
1232 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1233 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1234
1235 /* PLL regs */
1236 save->clk_cntl_index = INREG(CLOCK_CNTL_INDEX) & ~0x3f;
1237 radeon_pll_errata_after_index(rinfo);
1238 save->ppll_div_3 = INPLL(PPLL_DIV_3);
1239 save->ppll_ref_div = INPLL(PPLL_REF_DIV);
1240 }
1241
1242
1243 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode)
1244 {
1245 int i;
1246
1247 radeon_fifo_wait(20);
1248
1249 /* Workaround from XFree */
1250 if (rinfo->is_mobility) {
1251 /* A temporal workaround for the occational blanking on certain laptop
1252 * panels. This appears to related to the PLL divider registers
1253 * (fail to lock?). It occurs even when all dividers are the same
1254 * with their old settings. In this case we really don't need to
1255 * fiddle with PLL registers. By doing this we can avoid the blanking
1256 * problem with some panels.
1257 */
1258 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) &&
1259 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) &
1260 (PPLL_POST3_DIV_MASK | PPLL_FB3_DIV_MASK)))) {
1261 /* We still have to force a switch to selected PPLL div thanks to
1262 * an XFree86 driver bug which will switch it away in some cases
1263 * even when using UseFDev */
1264 OUTREGP(CLOCK_CNTL_INDEX,
1265 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1266 ~PPLL_DIV_SEL_MASK);
1267 radeon_pll_errata_after_index(rinfo);
1268 radeon_pll_errata_after_data(rinfo);
1269 return;
1270 }
1271 }
1272
1273 /* Swich VCKL clock input to CPUCLK so it stays fed while PPLL updates*/
1274 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_CPUCLK, ~VCLK_SRC_SEL_MASK);
1275
1276 /* Reset PPLL & enable atomic update */
1277 OUTPLLP(PPLL_CNTL,
1278 PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN,
1279 ~(PPLL_RESET | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1280
1281 /* Switch to selected PPLL divider */
1282 OUTREGP(CLOCK_CNTL_INDEX,
1283 mode->clk_cntl_index & PPLL_DIV_SEL_MASK,
1284 ~PPLL_DIV_SEL_MASK);
1285 radeon_pll_errata_after_index(rinfo);
1286 radeon_pll_errata_after_data(rinfo);
1287
1288 /* Set PPLL ref. div */
1289 if (rinfo->family == CHIP_FAMILY_R300 ||
1290 rinfo->family == CHIP_FAMILY_RS300 ||
1291 rinfo->family == CHIP_FAMILY_R350 ||
1292 rinfo->family == CHIP_FAMILY_RV350 ||
1293 rinfo->family == CHIP_FAMILY_RV380 ) {
1294 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
1295 /* When restoring console mode, use saved PPLL_REF_DIV
1296 * setting.
1297 */
1298 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0);
1299 } else {
1300 /* R300 uses ref_div_acc field as real ref divider */
1301 OUTPLLP(PPLL_REF_DIV,
1302 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
1303 ~R300_PPLL_REF_DIV_ACC_MASK);
1304 }
1305 } else
1306 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
1307
1308 /* Set PPLL divider 3 & post divider*/
1309 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
1310 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
1311
1312 /* Write update */
1313 while (INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R)
1314 ;
1315 OUTPLLP(PPLL_REF_DIV, PPLL_ATOMIC_UPDATE_W, ~PPLL_ATOMIC_UPDATE_W);
1316
1317 /* Wait read update complete */
1318 /* FIXME: Certain revisions of R300 can't recover here. Not sure of
1319 the cause yet, but this workaround will mask the problem for now.
1320 Other chips usually will pass at the very first test, so the
1321 workaround shouldn't have any effect on them. */
1322 for (i = 0; (i < 10000 && INPLL(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R); i++)
1323 ;
1324
1325 OUTPLL(HTOTAL_CNTL, 0);
1326
1327 /* Clear reset & atomic update */
1328 OUTPLLP(PPLL_CNTL, 0,
1329 ~(PPLL_RESET | PPLL_SLEEP | PPLL_ATOMIC_UPDATE_EN | PPLL_VGA_ATOMIC_UPDATE_EN));
1330
1331 /* We may want some locking ... oh well */
1332 radeon_msleep(5);
1333
1334 /* Switch back VCLK source to PPLL */
1335 OUTPLLP(VCLK_ECP_CNTL, VCLK_SRC_SEL_PPLLCLK, ~VCLK_SRC_SEL_MASK);
1336 }
1337
1338 /*
1339 * Timer function for delayed LVDS panel power up/down
1340 */
1341 static void radeon_lvds_timer_func(unsigned long data)
1342 {
1343 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
1344
1345 radeon_engine_idle();
1346
1347 OUTREG(LVDS_GEN_CNTL, rinfo->pending_lvds_gen_cntl);
1348 }
1349
1350 /*
1351 * Apply a video mode. This will apply the whole register set, including
1352 * the PLL registers, to the card
1353 */
1354 void radeon_write_mode (struct radeonfb_info *rinfo, struct radeon_regs *mode,
1355 int regs_only)
1356 {
1357 int i;
1358 int primary_mon = PRIMARY_MONITOR(rinfo);
1359
1360 if (nomodeset)
1361 return;
1362
1363 if (!regs_only)
1364 radeon_screen_blank(rinfo, FB_BLANK_NORMAL, 0);
1365
1366 radeon_fifo_wait(31);
1367 for (i=0; i<10; i++)
1368 OUTREG(common_regs[i].reg, common_regs[i].val);
1369
1370 /* Apply surface registers */
1371 for (i=0; i<8; i++) {
1372 OUTREG(SURFACE0_LOWER_BOUND + 0x10*i, mode->surf_lower_bound[i]);
1373 OUTREG(SURFACE0_UPPER_BOUND + 0x10*i, mode->surf_upper_bound[i]);
1374 OUTREG(SURFACE0_INFO + 0x10*i, mode->surf_info[i]);
1375 }
1376
1377 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
1378 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
1379 ~(CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS));
1380 OUTREG(CRTC_MORE_CNTL, mode->crtc_more_cntl);
1381 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
1382 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
1383 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
1384 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
1385 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
1386 OUTREG(CRTC_OFFSET, 0);
1387 OUTREG(CRTC_OFFSET_CNTL, 0);
1388 OUTREG(CRTC_PITCH, mode->crtc_pitch);
1389 OUTREG(SURFACE_CNTL, mode->surface_cntl);
1390
1391 radeon_write_pll_regs(rinfo, mode);
1392
1393 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1394 radeon_fifo_wait(10);
1395 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
1396 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
1397 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
1398 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
1399 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
1400 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
1401 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
1402 OUTREG(TMDS_CRC, mode->tmds_crc);
1403 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
1404 }
1405
1406 if (!regs_only)
1407 radeon_screen_blank(rinfo, FB_BLANK_UNBLANK, 0);
1408
1409 radeon_fifo_wait(2);
1410 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
1411
1412 return;
1413 }
1414
1415 /*
1416 * Calculate the PLL values for a given mode
1417 */
1418 static void radeon_calc_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *regs,
1419 unsigned long freq)
1420 {
1421 const struct {
1422 int divider;
1423 int bitvalue;
1424 } *post_div,
1425 post_divs[] = {
1426 { 1, 0 },
1427 { 2, 1 },
1428 { 4, 2 },
1429 { 8, 3 },
1430 { 3, 4 },
1431 { 16, 5 },
1432 { 6, 6 },
1433 { 12, 7 },
1434 { 0, 0 },
1435 };
1436 int fb_div, pll_output_freq = 0;
1437 int uses_dvo = 0;
1438
1439 /* Check if the DVO port is enabled and sourced from the primary CRTC. I'm
1440 * not sure which model starts having FP2_GEN_CNTL, I assume anything more
1441 * recent than an r(v)100...
1442 */
1443 #if 1
1444 /* XXX I had reports of flicker happening with the cinema display
1445 * on TMDS1 that seem to be fixed if I also forbit odd dividers in
1446 * this case. This could just be a bandwidth calculation issue, I
1447 * haven't implemented the bandwidth code yet, but in the meantime,
1448 * forcing uses_dvo to 1 fixes it and shouln't have bad side effects,
1449 * I haven't seen a case were were absolutely needed an odd PLL
1450 * divider. I'll find a better fix once I have more infos on the
1451 * real cause of the problem.
1452 */
1453 while (rinfo->has_CRTC2) {
1454 u32 fp2_gen_cntl = INREG(FP2_GEN_CNTL);
1455 u32 disp_output_cntl;
1456 int source;
1457
1458 /* FP2 path not enabled */
1459 if ((fp2_gen_cntl & FP2_ON) == 0)
1460 break;
1461 /* Not all chip revs have the same format for this register,
1462 * extract the source selection
1463 */
1464 if (rinfo->family == CHIP_FAMILY_R200 ||
1465 rinfo->family == CHIP_FAMILY_R300 ||
1466 rinfo->family == CHIP_FAMILY_R350 ||
1467 rinfo->family == CHIP_FAMILY_RV350) {
1468 source = (fp2_gen_cntl >> 10) & 0x3;
1469 /* sourced from transform unit, check for transform unit
1470 * own source
1471 */
1472 if (source == 3) {
1473 disp_output_cntl = INREG(DISP_OUTPUT_CNTL);
1474 source = (disp_output_cntl >> 12) & 0x3;
1475 }
1476 } else
1477 source = (fp2_gen_cntl >> 13) & 0x1;
1478 /* sourced from CRTC2 -> exit */
1479 if (source == 1)
1480 break;
1481
1482 /* so we end up on CRTC1, let's set uses_dvo to 1 now */
1483 uses_dvo = 1;
1484 break;
1485 }
1486 #else
1487 uses_dvo = 1;
1488 #endif
1489 if (freq > rinfo->pll.ppll_max)
1490 freq = rinfo->pll.ppll_max;
1491 if (freq*12 < rinfo->pll.ppll_min)
1492 freq = rinfo->pll.ppll_min / 12;
1493 pr_debug("freq = %lu, PLL min = %u, PLL max = %u\n",
1494 freq, rinfo->pll.ppll_min, rinfo->pll.ppll_max);
1495
1496 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1497 pll_output_freq = post_div->divider * freq;
1498 /* If we output to the DVO port (external TMDS), we don't allow an
1499 * odd PLL divider as those aren't supported on this path
1500 */
1501 if (uses_dvo && (post_div->divider & 1))
1502 continue;
1503 if (pll_output_freq >= rinfo->pll.ppll_min &&
1504 pll_output_freq <= rinfo->pll.ppll_max)
1505 break;
1506 }
1507
1508 /* If we fall through the bottom, try the "default value"
1509 given by the terminal post_div->bitvalue */
1510 if ( !post_div->divider ) {
1511 post_div = &post_divs[post_div->bitvalue];
1512 pll_output_freq = post_div->divider * freq;
1513 }
1514 pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1515 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1516 pll_output_freq);
1517
1518 /* If we fall through the bottom, try the "default value"
1519 given by the terminal post_div->bitvalue */
1520 if ( !post_div->divider ) {
1521 post_div = &post_divs[post_div->bitvalue];
1522 pll_output_freq = post_div->divider * freq;
1523 }
1524 pr_debug("ref_div = %d, ref_clk = %d, output_freq = %d\n",
1525 rinfo->pll.ref_div, rinfo->pll.ref_clk,
1526 pll_output_freq);
1527
1528 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq,
1529 rinfo->pll.ref_clk);
1530 regs->ppll_ref_div = rinfo->pll.ref_div;
1531 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16);
1532
1533 pr_debug("post div = 0x%x\n", post_div->bitvalue);
1534 pr_debug("fb_div = 0x%x\n", fb_div);
1535 pr_debug("ppll_div_3 = 0x%x\n", regs->ppll_div_3);
1536 }
1537
1538 static int radeonfb_set_par(struct fb_info *info)
1539 {
1540 struct radeonfb_info *rinfo = info->par;
1541 struct fb_var_screeninfo *mode = &info->var;
1542 struct radeon_regs *newmode;
1543 int hTotal, vTotal, hSyncStart, hSyncEnd,
1544 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1545 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1546 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1547 u32 sync, h_sync_pol, v_sync_pol, dotClock, pixClock;
1548 int i, freq;
1549 int format = 0;
1550 int nopllcalc = 0;
1551 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1552 int primary_mon = PRIMARY_MONITOR(rinfo);
1553 int depth = var_to_depth(mode);
1554 int use_rmx = 0;
1555
1556 newmode = kmalloc(sizeof(struct radeon_regs), GFP_KERNEL);
1557 if (!newmode)
1558 return -ENOMEM;
1559
1560 /* We always want engine to be idle on a mode switch, even
1561 * if we won't actually change the mode
1562 */
1563 radeon_engine_idle();
1564
1565 hSyncStart = mode->xres + mode->right_margin;
1566 hSyncEnd = hSyncStart + mode->hsync_len;
1567 hTotal = hSyncEnd + mode->left_margin;
1568
1569 vSyncStart = mode->yres + mode->lower_margin;
1570 vSyncEnd = vSyncStart + mode->vsync_len;
1571 vTotal = vSyncEnd + mode->upper_margin;
1572 pixClock = mode->pixclock;
1573
1574 sync = mode->sync;
1575 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1576 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1577
1578 if (primary_mon == MT_DFP || primary_mon == MT_LCD) {
1579 if (rinfo->panel_info.xres < mode->xres)
1580 mode->xres = rinfo->panel_info.xres;
1581 if (rinfo->panel_info.yres < mode->yres)
1582 mode->yres = rinfo->panel_info.yres;
1583
1584 hTotal = mode->xres + rinfo->panel_info.hblank;
1585 hSyncStart = mode->xres + rinfo->panel_info.hOver_plus;
1586 hSyncEnd = hSyncStart + rinfo->panel_info.hSync_width;
1587
1588 vTotal = mode->yres + rinfo->panel_info.vblank;
1589 vSyncStart = mode->yres + rinfo->panel_info.vOver_plus;
1590 vSyncEnd = vSyncStart + rinfo->panel_info.vSync_width;
1591
1592 h_sync_pol = !rinfo->panel_info.hAct_high;
1593 v_sync_pol = !rinfo->panel_info.vAct_high;
1594
1595 pixClock = 100000000 / rinfo->panel_info.clock;
1596
1597 if (rinfo->panel_info.use_bios_dividers) {
1598 nopllcalc = 1;
1599 newmode->ppll_div_3 = rinfo->panel_info.fbk_divider |
1600 (rinfo->panel_info.post_divider << 16);
1601 newmode->ppll_ref_div = rinfo->panel_info.ref_divider;
1602 }
1603 }
1604 dotClock = 1000000000 / pixClock;
1605 freq = dotClock / 10; /* x100 */
1606
1607 pr_debug("hStart = %d, hEnd = %d, hTotal = %d\n",
1608 hSyncStart, hSyncEnd, hTotal);
1609 pr_debug("vStart = %d, vEnd = %d, vTotal = %d\n",
1610 vSyncStart, vSyncEnd, vTotal);
1611
1612 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1613 vsync_wid = vSyncEnd - vSyncStart;
1614 if (hsync_wid == 0)
1615 hsync_wid = 1;
1616 else if (hsync_wid > 0x3f) /* max */
1617 hsync_wid = 0x3f;
1618
1619 if (vsync_wid == 0)
1620 vsync_wid = 1;
1621 else if (vsync_wid > 0x1f) /* max */
1622 vsync_wid = 0x1f;
1623
1624 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1625 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1626
1627 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1628
1629 format = radeon_get_dstbpp(depth);
1630 bytpp = mode->bits_per_pixel >> 3;
1631
1632 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1633 hsync_fudge = hsync_fudge_fp[format-1];
1634 else
1635 hsync_fudge = hsync_adj_tab[format-1];
1636
1637 hsync_start = hSyncStart - 8 + hsync_fudge;
1638
1639 newmode->crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1640 (format << 8);
1641
1642 /* Clear auto-center etc... */
1643 newmode->crtc_more_cntl = rinfo->init_state.crtc_more_cntl;
1644 newmode->crtc_more_cntl &= 0xfffffff0;
1645
1646 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1647 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1648 if (mirror)
1649 newmode->crtc_ext_cntl |= CRTC_CRT_ON;
1650
1651 newmode->crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1652 CRTC_INTERLACE_EN);
1653 } else {
1654 newmode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1655 CRTC_CRT_ON;
1656 }
1657
1658 newmode->dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1659 DAC_8BIT_EN;
1660
1661 newmode->crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1662 (((mode->xres / 8) - 1) << 16));
1663
1664 newmode->crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1665 (hsync_wid << 16) | (h_sync_pol << 23));
1666
1667 newmode->crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1668 ((mode->yres - 1) << 16);
1669
1670 newmode->crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1671 (vsync_wid << 16) | (v_sync_pol << 23));
1672
1673 if (!(info->flags & FBINFO_HWACCEL_DISABLED)) {
1674 /* We first calculate the engine pitch */
1675 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1676 & ~(0x3f)) >> 6;
1677
1678 /* Then, re-multiply it to get the CRTC pitch */
1679 newmode->crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1680 } else
1681 newmode->crtc_pitch = (mode->xres_virtual >> 3);
1682
1683 newmode->crtc_pitch |= (newmode->crtc_pitch << 16);
1684
1685 /*
1686 * It looks like recent chips have a problem with SURFACE_CNTL,
1687 * setting SURF_TRANSLATION_DIS completely disables the
1688 * swapper as well, so we leave it unset now.
1689 */
1690 newmode->surface_cntl = 0;
1691
1692 #if defined(__BIG_ENDIAN)
1693
1694 /* Setup swapping on both apertures, though we currently
1695 * only use aperture 0, enabling swapper on aperture 1
1696 * won't harm
1697 */
1698 switch (mode->bits_per_pixel) {
1699 case 16:
1700 newmode->surface_cntl |= NONSURF_AP0_SWP_16BPP;
1701 newmode->surface_cntl |= NONSURF_AP1_SWP_16BPP;
1702 break;
1703 case 24:
1704 case 32:
1705 newmode->surface_cntl |= NONSURF_AP0_SWP_32BPP;
1706 newmode->surface_cntl |= NONSURF_AP1_SWP_32BPP;
1707 break;
1708 }
1709 #endif
1710
1711 /* Clear surface registers */
1712 for (i=0; i<8; i++) {
1713 newmode->surf_lower_bound[i] = 0;
1714 newmode->surf_upper_bound[i] = 0x1f;
1715 newmode->surf_info[i] = 0;
1716 }
1717
1718 pr_debug("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1719 newmode->crtc_h_total_disp, newmode->crtc_h_sync_strt_wid);
1720 pr_debug("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1721 newmode->crtc_v_total_disp, newmode->crtc_v_sync_strt_wid);
1722
1723 rinfo->bpp = mode->bits_per_pixel;
1724 rinfo->depth = depth;
1725
1726 pr_debug("pixclock = %lu\n", (unsigned long)pixClock);
1727 pr_debug("freq = %lu\n", (unsigned long)freq);
1728
1729 /* We use PPLL_DIV_3 */
1730 newmode->clk_cntl_index = 0x300;
1731
1732 /* Calculate PPLL value if necessary */
1733 if (!nopllcalc)
1734 radeon_calc_pll_regs(rinfo, newmode, freq);
1735
1736 newmode->vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1737
1738 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1739 unsigned int hRatio, vRatio;
1740
1741 if (mode->xres > rinfo->panel_info.xres)
1742 mode->xres = rinfo->panel_info.xres;
1743 if (mode->yres > rinfo->panel_info.yres)
1744 mode->yres = rinfo->panel_info.yres;
1745
1746 newmode->fp_horz_stretch = (((rinfo->panel_info.xres / 8) - 1)
1747 << HORZ_PANEL_SHIFT);
1748 newmode->fp_vert_stretch = ((rinfo->panel_info.yres - 1)
1749 << VERT_PANEL_SHIFT);
1750
1751 if (mode->xres != rinfo->panel_info.xres) {
1752 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
1753 rinfo->panel_info.xres);
1754 newmode->fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
1755 (newmode->fp_horz_stretch &
1756 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
1757 HORZ_AUTO_RATIO_INC)));
1758 newmode->fp_horz_stretch |= (HORZ_STRETCH_BLEND |
1759 HORZ_STRETCH_ENABLE);
1760 use_rmx = 1;
1761 }
1762 newmode->fp_horz_stretch &= ~HORZ_AUTO_RATIO;
1763
1764 if (mode->yres != rinfo->panel_info.yres) {
1765 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
1766 rinfo->panel_info.yres);
1767 newmode->fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
1768 (newmode->fp_vert_stretch &
1769 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
1770 newmode->fp_vert_stretch |= (VERT_STRETCH_BLEND |
1771 VERT_STRETCH_ENABLE);
1772 use_rmx = 1;
1773 }
1774 newmode->fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
1775
1776 newmode->fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
1777 ~(FP_SEL_CRTC2 |
1778 FP_RMX_HVSYNC_CONTROL_EN |
1779 FP_DFP_SYNC_SEL |
1780 FP_CRT_SYNC_SEL |
1781 FP_CRTC_LOCK_8DOT |
1782 FP_USE_SHADOW_EN |
1783 FP_CRTC_USE_SHADOW_VEND |
1784 FP_CRT_SYNC_ALT));
1785
1786 newmode->fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
1787 FP_CRTC_DONT_SHADOW_HEND |
1788 FP_PANEL_FORMAT);
1789
1790 if (IS_R300_VARIANT(rinfo) ||
1791 (rinfo->family == CHIP_FAMILY_R200)) {
1792 newmode->fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
1793 if (use_rmx)
1794 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
1795 else
1796 newmode->fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
1797 } else
1798 newmode->fp_gen_cntl |= FP_SEL_CRTC1;
1799
1800 newmode->lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
1801 newmode->lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
1802 newmode->tmds_crc = rinfo->init_state.tmds_crc;
1803 newmode->tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
1804
1805 if (primary_mon == MT_LCD) {
1806 newmode->lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
1807 newmode->fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
1808 } else {
1809 /* DFP */
1810 newmode->fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
1811 newmode->tmds_transmitter_cntl &= ~(TMDS_PLLRST);
1812 /* TMDS_PLL_EN bit is reversed on RV (and mobility) chips */
1813 if (IS_R300_VARIANT(rinfo) ||
1814 (rinfo->family == CHIP_FAMILY_R200) || !rinfo->has_CRTC2)
1815 newmode->tmds_transmitter_cntl &= ~TMDS_PLL_EN;
1816 else
1817 newmode->tmds_transmitter_cntl |= TMDS_PLL_EN;
1818 newmode->crtc_ext_cntl &= ~CRTC_CRT_ON;
1819 }
1820
1821 newmode->fp_crtc_h_total_disp = (((rinfo->panel_info.hblank / 8) & 0x3ff) |
1822 (((mode->xres / 8) - 1) << 16));
1823 newmode->fp_crtc_v_total_disp = (rinfo->panel_info.vblank & 0xffff) |
1824 ((mode->yres - 1) << 16);
1825 newmode->fp_h_sync_strt_wid = ((rinfo->panel_info.hOver_plus & 0x1fff) |
1826 (hsync_wid << 16) | (h_sync_pol << 23));
1827 newmode->fp_v_sync_strt_wid = ((rinfo->panel_info.vOver_plus & 0xfff) |
1828 (vsync_wid << 16) | (v_sync_pol << 23));
1829 }
1830
1831 /* do it! */
1832 if (!rinfo->asleep) {
1833 memcpy(&rinfo->state, newmode, sizeof(*newmode));
1834 radeon_write_mode (rinfo, newmode, 0);
1835 /* (re)initialize the engine */
1836 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1837 radeonfb_engine_init (rinfo);
1838 }
1839 /* Update fix */
1840 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1841 info->fix.line_length = rinfo->pitch*64;
1842 else
1843 info->fix.line_length = mode->xres_virtual
1844 * ((mode->bits_per_pixel + 1) / 8);
1845 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR
1846 : FB_VISUAL_DIRECTCOLOR;
1847
1848 #ifdef CONFIG_BOOTX_TEXT
1849 /* Update debug text engine */
1850 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
1851 rinfo->depth, info->fix.line_length);
1852 #endif
1853
1854 kfree(newmode);
1855 return 0;
1856 }
1857
1858
1859 static struct fb_ops radeonfb_ops = {
1860 .owner = THIS_MODULE,
1861 .fb_check_var = radeonfb_check_var,
1862 .fb_set_par = radeonfb_set_par,
1863 .fb_setcolreg = radeonfb_setcolreg,
1864 .fb_setcmap = radeonfb_setcmap,
1865 .fb_pan_display = radeonfb_pan_display,
1866 .fb_blank = radeonfb_blank,
1867 .fb_ioctl = radeonfb_ioctl,
1868 .fb_sync = radeonfb_sync,
1869 .fb_fillrect = radeonfb_fillrect,
1870 .fb_copyarea = radeonfb_copyarea,
1871 .fb_imageblit = radeonfb_imageblit,
1872 };
1873
1874
1875 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1876 {
1877 struct fb_info *info = rinfo->info;
1878
1879 info->par = rinfo;
1880 info->pseudo_palette = rinfo->pseudo_palette;
1881 info->flags = FBINFO_DEFAULT
1882 | FBINFO_HWACCEL_COPYAREA
1883 | FBINFO_HWACCEL_FILLRECT
1884 | FBINFO_HWACCEL_XPAN
1885 | FBINFO_HWACCEL_YPAN;
1886 info->fbops = &radeonfb_ops;
1887 info->screen_base = rinfo->fb_base;
1888 info->screen_size = rinfo->mapped_vram;
1889 /* Fill fix common fields */
1890 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
1891 info->fix.smem_start = rinfo->fb_base_phys;
1892 info->fix.smem_len = rinfo->video_ram;
1893 info->fix.type = FB_TYPE_PACKED_PIXELS;
1894 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
1895 info->fix.xpanstep = 8;
1896 info->fix.ypanstep = 1;
1897 info->fix.ywrapstep = 0;
1898 info->fix.type_aux = 0;
1899 info->fix.mmio_start = rinfo->mmio_base_phys;
1900 info->fix.mmio_len = RADEON_REGSIZE;
1901 info->fix.accel = FB_ACCEL_ATI_RADEON;
1902
1903 fb_alloc_cmap(&info->cmap, 256, 0);
1904
1905 if (noaccel)
1906 info->flags |= FBINFO_HWACCEL_DISABLED;
1907
1908 return 0;
1909 }
1910
1911 /*
1912 * This reconfigure the card's internal memory map. In theory, we'd like
1913 * to setup the card's memory at the same address as it's PCI bus address,
1914 * and the AGP aperture right after that so that system RAM on 32 bits
1915 * machines at least, is directly accessible. However, doing so would
1916 * conflict with the current XFree drivers...
1917 * Ultimately, I hope XFree, GATOS and ATI binary drivers will all agree
1918 * on the proper way to set this up and duplicate this here. In the meantime,
1919 * I put the card's memory at 0 in card space and AGP at some random high
1920 * local (0xe0000000 for now) that will be changed by XFree/DRI anyway
1921 */
1922 #ifdef CONFIG_PPC_OF
1923 #undef SET_MC_FB_FROM_APERTURE
1924 static void fixup_memory_mappings(struct radeonfb_info *rinfo)
1925 {
1926 u32 save_crtc_gen_cntl, save_crtc2_gen_cntl = 0;
1927 u32 save_crtc_ext_cntl;
1928 u32 aper_base, aper_size;
1929 u32 agp_base;
1930
1931 /* First, we disable display to avoid interfering */
1932 if (rinfo->has_CRTC2) {
1933 save_crtc2_gen_cntl = INREG(CRTC2_GEN_CNTL);
1934 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl | CRTC2_DISP_REQ_EN_B);
1935 }
1936 save_crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1937 save_crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1938
1939 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl | CRTC_DISPLAY_DIS);
1940 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl | CRTC_DISP_REQ_EN_B);
1941 mdelay(100);
1942
1943 aper_base = INREG(CONFIG_APER_0_BASE);
1944 aper_size = INREG(CONFIG_APER_SIZE);
1945
1946 #ifdef SET_MC_FB_FROM_APERTURE
1947 /* Set framebuffer to be at the same address as set in PCI BAR */
1948 OUTREG(MC_FB_LOCATION,
1949 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16));
1950 rinfo->fb_local_base = aper_base;
1951 #else
1952 OUTREG(MC_FB_LOCATION, 0x7fff0000);
1953 rinfo->fb_local_base = 0;
1954 #endif
1955 agp_base = aper_base + aper_size;
1956 if (agp_base & 0xf0000000)
1957 agp_base = (aper_base | 0x0fffffff) + 1;
1958
1959 /* Set AGP to be just after the framebuffer on a 256Mb boundary. This
1960 * assumes the FB isn't mapped to 0xf0000000 or above, but this is
1961 * always the case on PPCs afaik.
1962 */
1963 #ifdef SET_MC_FB_FROM_APERTURE
1964 OUTREG(MC_AGP_LOCATION, 0xffff0000 | (agp_base >> 16));
1965 #else
1966 OUTREG(MC_AGP_LOCATION, 0xffffe000);
1967 #endif
1968
1969 /* Fixup the display base addresses & engine offsets while we
1970 * are at it as well
1971 */
1972 #ifdef SET_MC_FB_FROM_APERTURE
1973 OUTREG(DISPLAY_BASE_ADDR, aper_base);
1974 if (rinfo->has_CRTC2)
1975 OUTREG(CRTC2_DISPLAY_BASE_ADDR, aper_base);
1976 OUTREG(OV0_BASE_ADDR, aper_base);
1977 #else
1978 OUTREG(DISPLAY_BASE_ADDR, 0);
1979 if (rinfo->has_CRTC2)
1980 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0);
1981 OUTREG(OV0_BASE_ADDR, 0);
1982 #endif
1983 mdelay(100);
1984
1985 /* Restore display settings */
1986 OUTREG(CRTC_GEN_CNTL, save_crtc_gen_cntl);
1987 OUTREG(CRTC_EXT_CNTL, save_crtc_ext_cntl);
1988 if (rinfo->has_CRTC2)
1989 OUTREG(CRTC2_GEN_CNTL, save_crtc2_gen_cntl);
1990
1991 pr_debug("aper_base: %08x MC_FB_LOC to: %08x, MC_AGP_LOC to: %08x\n",
1992 aper_base,
1993 ((aper_base + aper_size - 1) & 0xffff0000) | (aper_base >> 16),
1994 0xffff0000 | (agp_base >> 16));
1995 }
1996 #endif /* CONFIG_PPC_OF */
1997
1998
1999 static void radeon_identify_vram(struct radeonfb_info *rinfo)
2000 {
2001 u32 tmp;
2002
2003 /* framebuffer size */
2004 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2005 (rinfo->family == CHIP_FAMILY_RS200) ||
2006 (rinfo->family == CHIP_FAMILY_RS300) ||
2007 (rinfo->family == CHIP_FAMILY_RC410) ||
2008 (rinfo->family == CHIP_FAMILY_RS480) ) {
2009 u32 tom = INREG(NB_TOM);
2010 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024);
2011
2012 radeon_fifo_wait(6);
2013 OUTREG(MC_FB_LOCATION, tom);
2014 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2015 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16);
2016 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16);
2017
2018 /* This is supposed to fix the crtc2 noise problem. */
2019 OUTREG(GRPH2_BUFFER_CNTL, INREG(GRPH2_BUFFER_CNTL) & ~0x7f0000);
2020
2021 if ((rinfo->family == CHIP_FAMILY_RS100) ||
2022 (rinfo->family == CHIP_FAMILY_RS200)) {
2023 /* This is to workaround the asic bug for RMX, some versions
2024 of BIOS dosen't have this register initialized correctly.
2025 */
2026 OUTREGP(CRTC_MORE_CNTL, CRTC_H_CUTOFF_ACTIVE_EN,
2027 ~CRTC_H_CUTOFF_ACTIVE_EN);
2028 }
2029 } else {
2030 tmp = INREG(CONFIG_MEMSIZE);
2031 }
2032
2033 /* mem size is bits [28:0], mask off the rest */
2034 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2035
2036 /*
2037 * Hack to get around some busted production M6's
2038 * reporting no ram
2039 */
2040 if (rinfo->video_ram == 0) {
2041 switch (rinfo->pdev->device) {
2042 case PCI_CHIP_RADEON_LY:
2043 case PCI_CHIP_RADEON_LZ:
2044 rinfo->video_ram = 8192 * 1024;
2045 break;
2046 default:
2047 break;
2048 }
2049 }
2050
2051
2052 /*
2053 * Now try to identify VRAM type
2054 */
2055 if (rinfo->is_IGP || (rinfo->family >= CHIP_FAMILY_R300) ||
2056 (INREG(MEM_SDRAM_MODE_REG) & (1<<30)))
2057 rinfo->vram_ddr = 1;
2058 else
2059 rinfo->vram_ddr = 0;
2060
2061 tmp = INREG(MEM_CNTL);
2062 if (IS_R300_VARIANT(rinfo)) {
2063 tmp &= R300_MEM_NUM_CHANNELS_MASK;
2064 switch (tmp) {
2065 case 0: rinfo->vram_width = 64; break;
2066 case 1: rinfo->vram_width = 128; break;
2067 case 2: rinfo->vram_width = 256; break;
2068 default: rinfo->vram_width = 128; break;
2069 }
2070 } else if ((rinfo->family == CHIP_FAMILY_RV100) ||
2071 (rinfo->family == CHIP_FAMILY_RS100) ||
2072 (rinfo->family == CHIP_FAMILY_RS200)){
2073 if (tmp & RV100_MEM_HALF_MODE)
2074 rinfo->vram_width = 32;
2075 else
2076 rinfo->vram_width = 64;
2077 } else {
2078 if (tmp & MEM_NUM_CHANNELS_MASK)
2079 rinfo->vram_width = 128;
2080 else
2081 rinfo->vram_width = 64;
2082 }
2083
2084 /* This may not be correct, as some cards can have half of channel disabled
2085 * ToDo: identify these cases
2086 */
2087
2088 pr_debug("radeonfb (%s): Found %ldk of %s %d bits wide videoram\n",
2089 pci_name(rinfo->pdev),
2090 rinfo->video_ram / 1024,
2091 rinfo->vram_ddr ? "DDR" : "SDRAM",
2092 rinfo->vram_width);
2093 }
2094
2095 /*
2096 * Sysfs
2097 */
2098
2099 static ssize_t radeon_show_one_edid(char *buf, loff_t off, size_t count, const u8 *edid)
2100 {
2101 if (off > EDID_LENGTH)
2102 return 0;
2103
2104 if (off + count > EDID_LENGTH)
2105 count = EDID_LENGTH - off;
2106
2107 memcpy(buf, edid + off, count);
2108
2109 return count;
2110 }
2111
2112
2113 static ssize_t radeon_show_edid1(struct kobject *kobj,
2114 struct bin_attribute *bin_attr,
2115 char *buf, loff_t off, size_t count)
2116 {
2117 struct device *dev = container_of(kobj, struct device, kobj);
2118 struct pci_dev *pdev = to_pci_dev(dev);
2119 struct fb_info *info = pci_get_drvdata(pdev);
2120 struct radeonfb_info *rinfo = info->par;
2121
2122 return radeon_show_one_edid(buf, off, count, rinfo->mon1_EDID);
2123 }
2124
2125
2126 static ssize_t radeon_show_edid2(struct kobject *kobj,
2127 struct bin_attribute *bin_attr,
2128 char *buf, loff_t off, size_t count)
2129 {
2130 struct device *dev = container_of(kobj, struct device, kobj);
2131 struct pci_dev *pdev = to_pci_dev(dev);
2132 struct fb_info *info = pci_get_drvdata(pdev);
2133 struct radeonfb_info *rinfo = info->par;
2134
2135 return radeon_show_one_edid(buf, off, count, rinfo->mon2_EDID);
2136 }
2137
2138 static struct bin_attribute edid1_attr = {
2139 .attr = {
2140 .name = "edid1",
2141 .mode = 0444,
2142 },
2143 .size = EDID_LENGTH,
2144 .read = radeon_show_edid1,
2145 };
2146
2147 static struct bin_attribute edid2_attr = {
2148 .attr = {
2149 .name = "edid2",
2150 .mode = 0444,
2151 },
2152 .size = EDID_LENGTH,
2153 .read = radeon_show_edid2,
2154 };
2155
2156
2157 static int __devinit radeonfb_pci_register (struct pci_dev *pdev,
2158 const struct pci_device_id *ent)
2159 {
2160 struct fb_info *info;
2161 struct radeonfb_info *rinfo;
2162 int ret;
2163 unsigned char c1, c2;
2164
2165 pr_debug("radeonfb_pci_register BEGIN\n");
2166
2167 /* Enable device in PCI config */
2168 ret = pci_enable_device(pdev);
2169 if (ret < 0) {
2170 printk(KERN_ERR "radeonfb (%s): Cannot enable PCI device\n",
2171 pci_name(pdev));
2172 goto err_out;
2173 }
2174
2175 info = framebuffer_alloc(sizeof(struct radeonfb_info), &pdev->dev);
2176 if (!info) {
2177 printk (KERN_ERR "radeonfb (%s): could not allocate memory\n",
2178 pci_name(pdev));
2179 ret = -ENOMEM;
2180 goto err_disable;
2181 }
2182 rinfo = info->par;
2183 rinfo->info = info;
2184 rinfo->pdev = pdev;
2185
2186 spin_lock_init(&rinfo->reg_lock);
2187 init_timer(&rinfo->lvds_timer);
2188 rinfo->lvds_timer.function = radeon_lvds_timer_func;
2189 rinfo->lvds_timer.data = (unsigned long)rinfo;
2190
2191 c1 = ent->device >> 8;
2192 c2 = ent->device & 0xff;
2193 if (isprint(c1) && isprint(c2))
2194 snprintf(rinfo->name, sizeof(rinfo->name),
2195 "ATI Radeon %x \"%c%c\"", ent->device & 0xffff, c1, c2);
2196 else
2197 snprintf(rinfo->name, sizeof(rinfo->name),
2198 "ATI Radeon %x", ent->device & 0xffff);
2199
2200 rinfo->family = ent->driver_data & CHIP_FAMILY_MASK;
2201 rinfo->chipset = pdev->device;
2202 rinfo->has_CRTC2 = (ent->driver_data & CHIP_HAS_CRTC2) != 0;
2203 rinfo->is_mobility = (ent->driver_data & CHIP_IS_MOBILITY) != 0;
2204 rinfo->is_IGP = (ent->driver_data & CHIP_IS_IGP) != 0;
2205
2206 /* Set base addrs */
2207 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2208 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2209
2210 /* request the mem regions */
2211 ret = pci_request_region(pdev, 0, "radeonfb framebuffer");
2212 if (ret < 0) {
2213 printk( KERN_ERR "radeonfb (%s): cannot request region 0.\n",
2214 pci_name(rinfo->pdev));
2215 goto err_release_fb;
2216 }
2217
2218 ret = pci_request_region(pdev, 2, "radeonfb mmio");
2219 if (ret < 0) {
2220 printk( KERN_ERR "radeonfb (%s): cannot request region 2.\n",
2221 pci_name(rinfo->pdev));
2222 goto err_release_pci0;
2223 }
2224
2225 /* map the regions */
2226 rinfo->mmio_base = ioremap(rinfo->mmio_base_phys, RADEON_REGSIZE);
2227 if (!rinfo->mmio_base) {
2228 printk(KERN_ERR "radeonfb (%s): cannot map MMIO\n",
2229 pci_name(rinfo->pdev));
2230 ret = -EIO;
2231 goto err_release_pci2;
2232 }
2233
2234 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16;
2235
2236 /*
2237 * Check for errata
2238 */
2239 rinfo->errata = 0;
2240 if (rinfo->family == CHIP_FAMILY_R300 &&
2241 (INREG(CONFIG_CNTL) & CFG_ATI_REV_ID_MASK)
2242 == CFG_ATI_REV_A11)
2243 rinfo->errata |= CHIP_ERRATA_R300_CG;
2244
2245 if (rinfo->family == CHIP_FAMILY_RV200 ||
2246 rinfo->family == CHIP_FAMILY_RS200)
2247 rinfo->errata |= CHIP_ERRATA_PLL_DUMMYREADS;
2248
2249 if (rinfo->family == CHIP_FAMILY_RV100 ||
2250 rinfo->family == CHIP_FAMILY_RS100 ||
2251 rinfo->family == CHIP_FAMILY_RS200)
2252 rinfo->errata |= CHIP_ERRATA_PLL_DELAY;
2253
2254 #if defined(CONFIG_PPC_OF) || defined(CONFIG_SPARC)
2255 /* On PPC, we obtain the OF device-node pointer to the firmware
2256 * data for this chip
2257 */
2258 rinfo->of_node = pci_device_to_OF_node(pdev);
2259 if (rinfo->of_node == NULL)
2260 printk(KERN_WARNING "radeonfb (%s): Cannot match card to OF node !\n",
2261 pci_name(rinfo->pdev));
2262
2263 #endif /* CONFIG_PPC_OF || CONFIG_SPARC */
2264 #ifdef CONFIG_PPC_OF
2265 /* On PPC, the firmware sets up a memory mapping that tends
2266 * to cause lockups when enabling the engine. We reconfigure
2267 * the card internal memory mappings properly
2268 */
2269 fixup_memory_mappings(rinfo);
2270 #endif /* CONFIG_PPC_OF */
2271
2272 /* Get VRAM size and type */
2273 radeon_identify_vram(rinfo);
2274
2275 rinfo->mapped_vram = min_t(unsigned long, MAX_MAPPED_VRAM, rinfo->video_ram);
2276
2277 do {
2278 rinfo->fb_base = ioremap (rinfo->fb_base_phys,
2279 rinfo->mapped_vram);
2280 } while (rinfo->fb_base == NULL &&
2281 ((rinfo->mapped_vram /= 2) >= MIN_MAPPED_VRAM));
2282
2283 if (rinfo->fb_base == NULL) {
2284 printk (KERN_ERR "radeonfb (%s): cannot map FB\n",
2285 pci_name(rinfo->pdev));
2286 ret = -EIO;
2287 goto err_unmap_rom;
2288 }
2289
2290 pr_debug("radeonfb (%s): mapped %ldk videoram\n", pci_name(rinfo->pdev),
2291 rinfo->mapped_vram/1024);
2292
2293 /*
2294 * Map the BIOS ROM if any and retrieve PLL parameters from
2295 * the BIOS. We skip that on mobility chips as the real panel
2296 * values we need aren't in the ROM but in the BIOS image in
2297 * memory. This is definitely not the best meacnism though,
2298 * we really need the arch code to tell us which is the "primary"
2299 * video adapter to use the memory image (or better, the arch
2300 * should provide us a copy of the BIOS image to shield us from
2301 * archs who would store that elsewhere and/or could initialize
2302 * more than one adapter during boot).
2303 */
2304 if (!rinfo->is_mobility)
2305 radeon_map_ROM(rinfo, pdev);
2306
2307 /*
2308 * On x86, the primary display on laptop may have it's BIOS
2309 * ROM elsewhere, try to locate it at the legacy memory hole.
2310 * We probably need to make sure this is the primary display,
2311 * but that is difficult without some arch support.
2312 */
2313 #ifdef CONFIG_X86
2314 if (rinfo->bios_seg == NULL)
2315 radeon_find_mem_vbios(rinfo);
2316 #endif
2317
2318 /* If both above failed, try the BIOS ROM again for mobility
2319 * chips
2320 */
2321 if (rinfo->bios_seg == NULL && rinfo->is_mobility)
2322 radeon_map_ROM(rinfo, pdev);
2323
2324 /* Get informations about the board's PLL */
2325 radeon_get_pllinfo(rinfo);
2326
2327 #ifdef CONFIG_FB_RADEON_I2C
2328 /* Register I2C bus */
2329 radeon_create_i2c_busses(rinfo);
2330 #endif
2331
2332 /* set all the vital stuff */
2333 radeon_set_fbinfo (rinfo);
2334
2335 /* Probe screen types */
2336 radeon_probe_screens(rinfo, monitor_layout, ignore_edid);
2337
2338 /* Build mode list, check out panel native model */
2339 radeon_check_modes(rinfo, mode_option);
2340
2341 /* Register some sysfs stuff (should be done better) */
2342 if (rinfo->mon1_EDID)
2343 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2344 if (rinfo->mon2_EDID)
2345 sysfs_create_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2346
2347 /* save current mode regs before we switch into the new one
2348 * so we can restore this upon __exit
2349 */
2350 radeon_save_state (rinfo, &rinfo->init_state);
2351 memcpy(&rinfo->state, &rinfo->init_state, sizeof(struct radeon_regs));
2352
2353 /* Setup Power Management capabilities */
2354 if (default_dynclk < -1) {
2355 /* -2 is special: means ON on mobility chips and do not
2356 * change on others
2357 */
2358 radeonfb_pm_init(rinfo, rinfo->is_mobility ? 1 : -1, ignore_devlist, force_sleep);
2359 } else
2360 radeonfb_pm_init(rinfo, default_dynclk, ignore_devlist, force_sleep);
2361
2362 pci_set_drvdata(pdev, info);
2363
2364 /* Register with fbdev layer */
2365 ret = register_framebuffer(info);
2366 if (ret < 0) {
2367 printk (KERN_ERR "radeonfb (%s): could not register framebuffer\n",
2368 pci_name(rinfo->pdev));
2369 goto err_unmap_fb;
2370 }
2371
2372 #ifdef CONFIG_MTRR
2373 rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
2374 rinfo->video_ram,
2375 MTRR_TYPE_WRCOMB, 1);
2376 #endif
2377
2378 if (backlight)
2379 radeonfb_bl_init(rinfo);
2380
2381 printk ("radeonfb (%s): %s\n", pci_name(rinfo->pdev), rinfo->name);
2382
2383 if (rinfo->bios_seg)
2384 radeon_unmap_ROM(rinfo, pdev);
2385 pr_debug("radeonfb_pci_register END\n");
2386
2387 return 0;
2388 err_unmap_fb:
2389 iounmap(rinfo->fb_base);
2390 err_unmap_rom:
2391 kfree(rinfo->mon1_EDID);
2392 kfree(rinfo->mon2_EDID);
2393 if (rinfo->mon1_modedb)
2394 fb_destroy_modedb(rinfo->mon1_modedb);
2395 fb_dealloc_cmap(&info->cmap);
2396 #ifdef CONFIG_FB_RADEON_I2C
2397 radeon_delete_i2c_busses(rinfo);
2398 #endif
2399 if (rinfo->bios_seg)
2400 radeon_unmap_ROM(rinfo, pdev);
2401 iounmap(rinfo->mmio_base);
2402 err_release_pci2:
2403 pci_release_region(pdev, 2);
2404 err_release_pci0:
2405 pci_release_region(pdev, 0);
2406 err_release_fb:
2407 framebuffer_release(info);
2408 err_disable:
2409 err_out:
2410 return ret;
2411 }
2412
2413
2414
2415 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
2416 {
2417 struct fb_info *info = pci_get_drvdata(pdev);
2418 struct radeonfb_info *rinfo = info->par;
2419
2420 if (!rinfo)
2421 return;
2422
2423 radeonfb_pm_exit(rinfo);
2424
2425 if (rinfo->mon1_EDID)
2426 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid1_attr);
2427 if (rinfo->mon2_EDID)
2428 sysfs_remove_bin_file(&rinfo->pdev->dev.kobj, &edid2_attr);
2429
2430 #if 0
2431 /* restore original state
2432 *
2433 * Doesn't quite work yet, I suspect if we come from a legacy
2434 * VGA mode (or worse, text mode), we need to do some VGA black
2435 * magic here that I know nothing about. --BenH
2436 */
2437 radeon_write_mode (rinfo, &rinfo->init_state, 1);
2438 #endif
2439
2440 del_timer_sync(&rinfo->lvds_timer);
2441
2442 #ifdef CONFIG_MTRR
2443 if (rinfo->mtrr_hdl >= 0)
2444 mtrr_del(rinfo->mtrr_hdl, 0, 0);
2445 #endif
2446
2447 unregister_framebuffer(info);
2448
2449 radeonfb_bl_exit(rinfo);
2450
2451 iounmap(rinfo->mmio_base);
2452 iounmap(rinfo->fb_base);
2453
2454 pci_release_region(pdev, 2);
2455 pci_release_region(pdev, 0);
2456
2457 kfree(rinfo->mon1_EDID);
2458 kfree(rinfo->mon2_EDID);
2459 if (rinfo->mon1_modedb)
2460 fb_destroy_modedb(rinfo->mon1_modedb);
2461 #ifdef CONFIG_FB_RADEON_I2C
2462 radeon_delete_i2c_busses(rinfo);
2463 #endif
2464 fb_dealloc_cmap(&info->cmap);
2465 framebuffer_release(info);
2466 }
2467
2468
2469 static struct pci_driver radeonfb_driver = {
2470 .name = "radeonfb",
2471 .id_table = radeonfb_pci_table,
2472 .probe = radeonfb_pci_register,
2473 .remove = __devexit_p(radeonfb_pci_unregister),
2474 #ifdef CONFIG_PM
2475 .suspend = radeonfb_pci_suspend,
2476 .resume = radeonfb_pci_resume,
2477 #endif /* CONFIG_PM */
2478 };
2479
2480 #ifndef MODULE
2481 static int __init radeonfb_setup (char *options)
2482 {
2483 char *this_opt;
2484
2485 if (!options || !*options)
2486 return 0;
2487
2488 while ((this_opt = strsep (&options, ",")) != NULL) {
2489 if (!*this_opt)
2490 continue;
2491
2492 if (!strncmp(this_opt, "noaccel", 7)) {
2493 noaccel = 1;
2494 } else if (!strncmp(this_opt, "mirror", 6)) {
2495 mirror = 1;
2496 } else if (!strncmp(this_opt, "force_dfp", 9)) {
2497 force_dfp = 1;
2498 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
2499 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
2500 } else if (!strncmp(this_opt, "backlight:", 10)) {
2501 backlight = simple_strtoul(this_opt+10, NULL, 0);
2502 #ifdef CONFIG_MTRR
2503 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2504 nomtrr = 1;
2505 #endif
2506 } else if (!strncmp(this_opt, "nomodeset", 9)) {
2507 nomodeset = 1;
2508 } else if (!strncmp(this_opt, "force_measure_pll", 17)) {
2509 force_measure_pll = 1;
2510 } else if (!strncmp(this_opt, "ignore_edid", 11)) {
2511 ignore_edid = 1;
2512 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2513 } else if (!strncmp(this_opt, "force_sleep", 11)) {
2514 force_sleep = 1;
2515 } else if (!strncmp(this_opt, "ignore_devlist", 14)) {
2516 ignore_devlist = 1;
2517 #endif
2518 } else
2519 mode_option = this_opt;
2520 }
2521 return 0;
2522 }
2523 #endif /* MODULE */
2524
2525 static int __init radeonfb_init (void)
2526 {
2527 #ifndef MODULE
2528 char *option = NULL;
2529
2530 if (fb_get_options("radeonfb", &option))
2531 return -ENODEV;
2532 radeonfb_setup(option);
2533 #endif
2534 return pci_register_driver (&radeonfb_driver);
2535 }
2536
2537
2538 static void __exit radeonfb_exit (void)
2539 {
2540 pci_unregister_driver (&radeonfb_driver);
2541 }
2542
2543 module_init(radeonfb_init);
2544 module_exit(radeonfb_exit);
2545
2546 MODULE_AUTHOR("Ani Joshi");
2547 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
2548 MODULE_LICENSE("GPL");
2549 module_param(noaccel, bool, 0);
2550 module_param(default_dynclk, int, 0);
2551 MODULE_PARM_DESC(default_dynclk, "int: -2=enable on mobility only,-1=do not change,0=off,1=on");
2552 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2553 module_param(nomodeset, bool, 0);
2554 MODULE_PARM_DESC(nomodeset, "bool: disable actual setting of video mode");
2555 module_param(mirror, bool, 0);
2556 MODULE_PARM_DESC(mirror, "bool: mirror the display to both monitors");
2557 module_param(force_dfp, bool, 0);
2558 MODULE_PARM_DESC(force_dfp, "bool: force display to dfp");
2559 module_param(ignore_edid, bool, 0);
2560 MODULE_PARM_DESC(ignore_edid, "bool: Ignore EDID data when doing DDC probe");
2561 module_param(monitor_layout, charp, 0);
2562 MODULE_PARM_DESC(monitor_layout, "Specify monitor mapping (like XFree86)");
2563 module_param(force_measure_pll, bool, 0);
2564 MODULE_PARM_DESC(force_measure_pll, "Force measurement of PLL (debug)");
2565 #ifdef CONFIG_MTRR
2566 module_param(nomtrr, bool, 0);
2567 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
2568 #endif
2569 module_param(panel_yres, int, 0);
2570 MODULE_PARM_DESC(panel_yres, "int: set panel yres");
2571 module_param(mode_option, charp, 0);
2572 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2573 #if defined(CONFIG_PM) && defined(CONFIG_X86)
2574 module_param(force_sleep, bool, 0);
2575 MODULE_PARM_DESC(force_sleep, "bool: force D2 sleep mode on all hardware");
2576 module_param(ignore_devlist, bool, 0);
2577 MODULE_PARM_DESC(ignore_devlist, "bool: ignore workarounds for bugs in specific laptops");
2578 #endif
Support for the Chinese Samsung S3C2440 based development boards