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x86, mce: use a call vector to call the 64bit mce handler
[linux-2.6/mini2440.git] / drivers / staging / meilhaus / me4600_ai.c
bloba3cfef09a4de2f1e9818e0f44944d441a739a104
1 /**
2 * @file me4600_ai.c
3 *
4 * @brief ME-4000 analog input subdevice instance.
5 * @note Copyright (C) 2007 Meilhaus Electronic GmbH (support@meilhaus.de)
6 * @author Guenter Gebhardt
7 * @author Krzysztof Gantzke (k.gantzke@meilhaus.de)
8 */
9
10 /*
11 * Copyright (C) 2007 Meilhaus Electronic GmbH (support@meilhaus.de)
12 *
13 * This file is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 */
27
28 #ifndef __KERNEL__
29 # define __KERNEL__
30 #endif
31
32 /*
33 * Includes
34 */
35 #include <linux/module.h>
36
37 #include <linux/slab.h>
38 #include <linux/spinlock.h>
39 #include <linux/io.h>
40 #include <linux/uaccess.h>
41 #include <linux/types.h>
42 #include <linux/interrupt.h>
43 #include <linux/delay.h>
44
45 #include "medefines.h"
46 #include "meinternal.h"
47 #include "meerror.h"
48 #include "medebug.h"
49 #include "meids.h"
50
51 #include "me4600_reg.h"
52 #include "me4600_ai_reg.h"
53 #include "me4600_ai.h"
54
55 /*
56 * Declarations (local)
57 */
58
59 static void me4600_ai_destructor(struct me_subdevice *subdevice);
60 static int me4600_ai_io_reset_subdevice(me_subdevice_t *subdevice,
61 struct file *filep, int flags);
62
63 static int me4600_ai_io_single_config(me_subdevice_t *subdevice,
64 struct file *filep,
65 int channel,
66 int single_config,
67 int ref,
68 int trig_chan,
69 int trig_type, int trig_edge, int flags);
70
71 static int me4600_ai_io_single_read(me_subdevice_t *subdevice,
72 struct file *filep,
73 int channel,
74 int *value, int time_out, int flags);
75
76 static int me4600_ai_io_stream_config(me_subdevice_t *subdevice,
77 struct file *filep,
78 meIOStreamConfig_t *config_list,
79 int count,
80 meIOStreamTrigger_t *trigger,
81 int fifo_irq_threshold, int flags);
82 static int me4600_ai_io_stream_read(me_subdevice_t *subdevice,
83 struct file *filep,
84 int read_mode,
85 int *values, int *count, int flags);
86 static int me4600_ai_io_stream_new_values(me_subdevice_t *subdevice,
87 struct file *filep,
88 int time_out, int *count, int flags);
89 static inline int me4600_ai_io_stream_read_get_value(me4600_ai_subdevice_t *
90 instance, int *values,
91 const int count,
92 const int flags);
93
94 static int me4600_ai_io_stream_start(me_subdevice_t *subdevice,
95 struct file *filep,
96 int start_mode, int time_out, int flags);
97 static int me4600_ai_io_stream_stop(me_subdevice_t *subdevice,
98 struct file *filep,
99 int stop_mode, int flags);
100 static int me4600_ai_io_stream_status(me_subdevice_t *subdevice,
101 struct file *filep,
102 int wait,
103 int *status, int *values, int flags);
104
105 static int me4600_ai_query_range_by_min_max(me_subdevice_t *subdevice,
106 int unit,
107 int *min,
108 int *max, int *maxdata, int *range);
109 static int me4600_ai_query_number_ranges(me_subdevice_t *subdevice,
110 int unit, int *count);
111 static int me4600_ai_query_range_info(me_subdevice_t *subdevice,
112 int range,
113 int *unit,
114 int *min, int *max, int *maxdata);
115 static int me4600_ai_query_timer(me_subdevice_t *subdevice,
116 int timer,
117 int *base_frequency,
118 long long *min_ticks, long long *max_ticks);
119 static int me4600_ai_query_number_channels(me_subdevice_t *subdevice,
120 int *number);
121 static int me4600_ai_query_subdevice_type(me_subdevice_t *subdevice,
122 int *type, int *subtype);
123 static int me4600_ai_query_subdevice_caps(me_subdevice_t *subdevice,
124 int *caps);
125 static int me4600_ai_query_subdevice_caps_args(struct me_subdevice *subdevice,
126 int cap, int *args, int count);
127
128 static irqreturn_t me4600_ai_isr(int irq, void *dev_id);
129
130 static int ai_mux_toggler(me4600_ai_subdevice_t *subdevice);
131
132 /** Immidiate stop.
133 * Reset all IRQ's sources. (block laches)
134 * Preserve FIFO
135 */
136 static int ai_stop_immediately(me4600_ai_subdevice_t *instance);
137
138 /** Immidiate stop.
139 * Reset all IRQ's sources. (block laches)
140 * Reset data FIFO
141 */
142 inline void ai_stop_isr(me4600_ai_subdevice_t *instance);
143
144 /** Interrupt logics.
145 * Read datas
146 * Reset latches
147 */
148 void ai_limited_isr(me4600_ai_subdevice_t *instance, const uint32_t irq_status,
149 const uint32_t ctrl_status);
150 void ai_infinite_isr(me4600_ai_subdevice_t *instance,
151 const uint32_t irq_status, const uint32_t ctrl_status);
152
153 /** Last chunck of datas. We must reschedule sample counter.
154 * Leaving SC_RELOAD doesn't do any harm, but in some bad case can make extra interrupts.
155 * When threshold is wrongly set some IRQ are lost.(!!!)
156 */
157 inline void ai_reschedule_SC(me4600_ai_subdevice_t *instance);
158
159 /** Read datas from FIFO and copy them to buffer */
160 static inline int ai_read_data(me4600_ai_subdevice_t *instance,
161 const int count);
162
163 /** Copy rest of data from fifo to circular buffer.*/
164 static inline int ai_read_data_pooling(me4600_ai_subdevice_t *instance);
165
166 /** Set ISM to next state for infinite data aqusation mode*/
167 inline void ai_infinite_ISM(me4600_ai_subdevice_t *instance);
168
169 /** Set ISM to next state for define amount of data aqusation mode*/
170 inline void ai_limited_ISM(me4600_ai_subdevice_t *instance,
171 uint32_t irq_status);
172
173 /** Set ISM to next stage for limited mode */
174 inline void ai_data_acquisition_logic(me4600_ai_subdevice_t *instance);
175
176 static void me4600_ai_work_control_task(struct work_struct *work);
177
178 /* Definitions
179 */
180
181 me4600_ai_subdevice_t *me4600_ai_constructor(uint32_t reg_base,
182 unsigned int channels,
183 unsigned int ranges,
184 int isolated,
185 int sh,
186 int irq,
187 spinlock_t *ctrl_reg_lock,
188 struct workqueue_struct *me4600_wq)
189 {
190 me4600_ai_subdevice_t *subdevice;
191 int err;
192 unsigned int i;
193
194 PDEBUG("executed. idx=0\n");
195
196 // Allocate memory for subdevice instance.
197 subdevice = kmalloc(sizeof(me4600_ai_subdevice_t), GFP_KERNEL);
198
199 if (!subdevice) {
200 PERROR("Cannot get memory for subdevice instance.\n");
201 return NULL;
202 }
203
204 memset(subdevice, 0, sizeof(me4600_ai_subdevice_t));
205
206 // Initialize subdevice base class.
207 err = me_subdevice_init(&subdevice->base);
208
209 if (err) {
210 PERROR("Cannot initialize subdevice base class instance.\n");
211 kfree(subdevice);
212 return NULL;
213 }
214 // Initialize spin locks.
215 spin_lock_init(&subdevice->subdevice_lock);
216
217 subdevice->ctrl_reg_lock = ctrl_reg_lock;
218
219 // Initialize circular buffer.
220 subdevice->circ_buf.mask = ME4600_AI_CIRC_BUF_COUNT - 1;
221
222 subdevice->circ_buf.buf =
223 (void *)__get_free_pages(GFP_KERNEL, ME4600_AI_CIRC_BUF_SIZE_ORDER);
224 PDEBUG("circ_buf = %p size=%ld\n", subdevice->circ_buf.buf,
225 ME4600_AI_CIRC_BUF_SIZE);
226
227 if (!subdevice->circ_buf.buf) {
228 PERROR("Cannot get circular buffer.\n");
229 me_subdevice_deinit((me_subdevice_t *) subdevice);
230 kfree(subdevice);
231 return NULL;
232 }
233
234 memset(subdevice->circ_buf.buf, 0, ME4600_AI_CIRC_BUF_SIZE);
235 subdevice->circ_buf.head = 0;
236 subdevice->circ_buf.tail = 0;
237 subdevice->status = ai_status_none;
238
239 // Initialize wait queue.
240 init_waitqueue_head(&subdevice->wait_queue);
241
242 // Save the number of channels.
243 subdevice->channels = channels;
244
245 /* Initialize the single config entries to reset values */
246 for (i = 0; i < channels; i++) {
247 subdevice->single_config[i].status = ME_SINGLE_CHANNEL_NOT_CONFIGURED; //not configured
248 }
249
250 // Save if isolated device.
251 subdevice->isolated = isolated;
252
253 // Save if sample and hold is available.
254 subdevice->sh = sh;
255
256 // Set stream config to not configured state.
257 subdevice->fifo_irq_threshold = 0;
258 subdevice->data_required = 0;
259 subdevice->chan_list_len = 0;
260
261 // Initialize registers addresses.
262 subdevice->ctrl_reg = reg_base + ME4600_AI_CTRL_REG;
263 subdevice->status_reg = reg_base + ME4600_AI_STATUS_REG;
264 subdevice->channel_list_reg = reg_base + ME4600_AI_CHANNEL_LIST_REG;
265 subdevice->data_reg = reg_base + ME4600_AI_DATA_REG;
266 subdevice->chan_timer_reg = reg_base + ME4600_AI_CHAN_TIMER_REG;
267 subdevice->chan_pre_timer_reg = reg_base + ME4600_AI_CHAN_PRE_TIMER_REG;
268 subdevice->scan_timer_low_reg = reg_base + ME4600_AI_SCAN_TIMER_LOW_REG;
269 subdevice->scan_timer_high_reg =
270 reg_base + ME4600_AI_SCAN_TIMER_HIGH_REG;
271 subdevice->scan_pre_timer_low_reg =
272 reg_base + ME4600_AI_SCAN_PRE_TIMER_LOW_REG;
273 subdevice->scan_pre_timer_high_reg =
274 reg_base + ME4600_AI_SCAN_PRE_TIMER_HIGH_REG;
275 subdevice->start_reg = reg_base + ME4600_AI_START_REG;
276 subdevice->irq_status_reg = reg_base + ME4600_IRQ_STATUS_REG;
277 subdevice->sample_counter_reg = reg_base + ME4600_AI_SAMPLE_COUNTER_REG;
278 #ifdef MEDEBUG_DEBUG_REG
279 subdevice->reg_base = reg_base;
280 #endif
281
282 // Initialize ranges.
283 subdevice->ranges_len = ranges;
284 subdevice->ranges[0].min = -10E6;
285 subdevice->ranges[0].max = 9999694;
286
287 subdevice->ranges[1].min = 0;
288 subdevice->ranges[1].max = 9999847;
289
290 subdevice->ranges[2].min = -25E5;
291 subdevice->ranges[2].max = 2499923;
292
293 subdevice->ranges[3].min = 0;
294 subdevice->ranges[3].max = 2499961;
295
296 // We have to switch the mux in order to get it work correctly.
297 ai_mux_toggler(subdevice);
298
299 // Register interrupt service routine.
300 subdevice->irq = irq;
301 if (request_irq(subdevice->irq, me4600_ai_isr,
302 #ifdef IRQF_DISABLED
303 IRQF_DISABLED | IRQF_SHARED,
304 #else
305 SA_INTERRUPT | SA_SHIRQ,
306 #endif
307 ME4600_NAME, subdevice)) {
308 PERROR("Cannot register interrupt service routine.\n");
309 me_subdevice_deinit((me_subdevice_t *) subdevice);
310 free_pages((unsigned long)subdevice->circ_buf.buf,
311 ME4600_AI_CIRC_BUF_SIZE_ORDER);
312 subdevice->circ_buf.buf = NULL;
313 kfree(subdevice);
314 return NULL;
315 }
316 PINFO("Registered irq=%d.\n", subdevice->irq);
317
318 // Override base class methods.
319 subdevice->base.me_subdevice_destructor = me4600_ai_destructor;
320 subdevice->base.me_subdevice_io_reset_subdevice =
321 me4600_ai_io_reset_subdevice;
322 subdevice->base.me_subdevice_io_single_config =
323 me4600_ai_io_single_config;
324 subdevice->base.me_subdevice_io_single_read = me4600_ai_io_single_read;
325 subdevice->base.me_subdevice_io_stream_config =
326 me4600_ai_io_stream_config;
327 subdevice->base.me_subdevice_io_stream_new_values =
328 me4600_ai_io_stream_new_values;
329 subdevice->base.me_subdevice_io_stream_read = me4600_ai_io_stream_read;
330 subdevice->base.me_subdevice_io_stream_start =
331 me4600_ai_io_stream_start;
332 subdevice->base.me_subdevice_io_stream_status =
333 me4600_ai_io_stream_status;
334 subdevice->base.me_subdevice_io_stream_stop = me4600_ai_io_stream_stop;
335 subdevice->base.me_subdevice_query_number_channels =
336 me4600_ai_query_number_channels;
337 subdevice->base.me_subdevice_query_subdevice_type =
338 me4600_ai_query_subdevice_type;
339 subdevice->base.me_subdevice_query_subdevice_caps =
340 me4600_ai_query_subdevice_caps;
341 subdevice->base.me_subdevice_query_subdevice_caps_args =
342 me4600_ai_query_subdevice_caps_args;
343 subdevice->base.me_subdevice_query_range_by_min_max =
344 me4600_ai_query_range_by_min_max;
345 subdevice->base.me_subdevice_query_number_ranges =
346 me4600_ai_query_number_ranges;
347 subdevice->base.me_subdevice_query_range_info =
348 me4600_ai_query_range_info;
349 subdevice->base.me_subdevice_query_timer = me4600_ai_query_timer;
350
351 // Prepare work queue.
352 subdevice->me4600_workqueue = me4600_wq;
353
354 /* workqueue API changed in kernel 2.6.20 */
355 INIT_DELAYED_WORK(&subdevice->ai_control_task,
356 me4600_ai_work_control_task);
357
358 return subdevice;
359 }
360
361 static void me4600_ai_destructor(struct me_subdevice *subdevice)
362 {
363 me4600_ai_subdevice_t *instance;
364
365 instance = (me4600_ai_subdevice_t *) subdevice;
366
367 PDEBUG("executed. idx=0\n");
368
369 instance->ai_control_task_flag = 0;
370 // Reset subdevice to asure clean exit.
371 me4600_ai_io_reset_subdevice(subdevice, NULL,
372 ME_IO_RESET_SUBDEVICE_NO_FLAGS);
373
374 // Remove any tasks from work queue. This is paranoic because it was done allready in reset().
375 if (!cancel_delayed_work(&instance->ai_control_task)) { //Wait 2 ticks to be sure that control task is removed from queue.
376 set_current_state(TASK_INTERRUPTIBLE);
377 schedule_timeout(2);
378 }
379
380 free_irq(instance->irq, instance);
381 free_pages((unsigned long)instance->circ_buf.buf,
382 ME4600_AI_CIRC_BUF_SIZE_ORDER);
383 me_subdevice_deinit(&instance->base);
384 kfree(instance);
385 }
386
387 static int me4600_ai_io_reset_subdevice(me_subdevice_t *subdevice,
388 struct file *filep, int flags)
389 {
390 me4600_ai_subdevice_t *instance;
391 int err = ME_ERRNO_SUCCESS;
392 volatile uint32_t ctrl;
393 unsigned long status;
394 const int timeout = HZ / 10; //100ms
395 int i;
396
397 PDEBUG("executed. idx=0\n");
398
399 if (flags) {
400 PERROR("Invalid flag specified.\n");
401 return ME_ERRNO_INVALID_FLAGS;
402 }
403
404 instance = (me4600_ai_subdevice_t *) subdevice;
405
406 ME_SUBDEVICE_ENTER;
407
408 instance->ai_control_task_flag = 0;
409 instance->status = ai_status_none;
410
411 for (i = 0; i <= timeout; i++) {
412 spin_lock_irqsave(instance->ctrl_reg_lock, status);
413 ctrl = inl(instance->ctrl_reg);
414 //Stop DMA
415 ctrl &= ~ME4600_AI_CTRL_RPCI_FIFO;
416 // Stop all actions. No conditions!
417 ctrl &= ~ME4600_AI_CTRL_BIT_STOP;
418 ctrl |= ME4600_AI_CTRL_BIT_IMMEDIATE_STOP;
419
420 outl(ctrl, instance->ctrl_reg);
421 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
422 instance->reg_base,
423 instance->ctrl_reg - instance->reg_base, ctrl);
424 spin_unlock_irqrestore(instance->ctrl_reg_lock, status);
425
426 if (!(inl(instance->status_reg) & ME4600_AI_STATUS_BIT_FSM))
427 break;
428
429 set_current_state(TASK_INTERRUPTIBLE);
430 schedule_timeout(1);
431 }
432
433 if (i > timeout) {
434 PERROR("FSM is still busy.\n");
435 ME_SUBDEVICE_EXIT;
436 return ME_ERRNO_INTERNAL;
437 }
438
439 spin_lock_irqsave(instance->ctrl_reg_lock, status);
440 ctrl = inl(instance->ctrl_reg);
441 // Clear all features. Dissable interrupts.
442 ctrl &= ~(ME4600_AI_CTRL_BIT_STOP
443 | ME4600_AI_CTRL_BIT_LE_IRQ
444 | ME4600_AI_CTRL_BIT_HF_IRQ | ME4600_AI_CTRL_BIT_SC_IRQ);
445 ctrl |= (ME4600_AI_CTRL_BIT_IMMEDIATE_STOP
446 | ME4600_AI_CTRL_BIT_LE_IRQ_RESET
447 | ME4600_AI_CTRL_BIT_HF_IRQ_RESET
448 | ME4600_AI_CTRL_BIT_SC_IRQ_RESET);
449
450 outl(ctrl, instance->ctrl_reg);
451 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
452 instance->ctrl_reg - instance->reg_base, ctrl);
453 spin_unlock_irqrestore(instance->ctrl_reg_lock, status);
454
455 outl(ME4600_AI_MIN_CHAN_TICKS - 1, instance->chan_timer_reg);
456 PDEBUG_REG("chan_timer_reg outl(0x%lX+0x%lX)=0x%llx\n",
457 instance->reg_base,
458 instance->chan_timer_reg - instance->reg_base,
459 ME4600_AI_MIN_CHAN_TICKS);
460 outl(ME4600_AI_MIN_ACQ_TICKS - 1, instance->chan_pre_timer_reg);
461 PDEBUG_REG("chan_pre_timer_reg outl(0x%lX+0x%lX)=0x%llx\n",
462 instance->reg_base,
463 instance->chan_pre_timer_reg - instance->reg_base,
464 ME4600_AI_MIN_ACQ_TICKS);
465 outl(0, instance->scan_timer_low_reg);
466 PDEBUG_REG("scan_timer_low_reg outl(0x%lX+0x%lX)=0x%x\n",
467 instance->reg_base,
468 instance->scan_timer_low_reg - instance->reg_base, 0);
469 outl(0, instance->scan_timer_high_reg);
470 PDEBUG_REG("scan_timer_high_reg outl(0x%lX+0x%lX)=0x%x\n",
471 instance->reg_base,
472 instance->scan_timer_high_reg - instance->reg_base, 0);
473 outl(0, instance->scan_pre_timer_low_reg);
474 PDEBUG_REG("scan_pre_timer_low_reg outl(0x%lX+0x%lX)=0x%x\n",
475 instance->reg_base,
476 instance->scan_pre_timer_low_reg - instance->reg_base, 0);
477 outl(0, instance->scan_pre_timer_high_reg);
478 PDEBUG_REG("scan_pre_timer_high_reg outl(0x%lX+0x%lX)=0x%x\n",
479 instance->reg_base,
480 instance->scan_pre_timer_high_reg - instance->reg_base, 0);
481 outl(0xEFFFFFFF, instance->sample_counter_reg);
482 PDEBUG_REG("sample_counter_reg outl(0x%lX+0x%lX)=0x%x\n",
483 instance->reg_base,
484 instance->sample_counter_reg - instance->reg_base,
485 0xEFFFFFFF);
486
487 instance->circ_buf.head = 0;
488 instance->circ_buf.tail = 0;
489
490 instance->fifo_irq_threshold = 0;
491 instance->data_required = 0;
492 instance->chan_list_len = 0;
493
494 // Initialize the single config entries to reset values.
495 for (i = 0; i < instance->channels; i++) {
496 instance->single_config[i].status =
497 ME_SINGLE_CHANNEL_NOT_CONFIGURED;
498 }
499 instance->status = ai_status_none;
500
501 //Signal reset if user is on wait.
502 wake_up_interruptible_all(&instance->wait_queue);
503
504 ME_SUBDEVICE_EXIT;
505
506 return err;
507 }
508
509 static int me4600_ai_io_single_config(me_subdevice_t *subdevice,
510 struct file *filep,
511 int channel,
512 int single_config,
513 int ref,
514 int trig_chan,
515 int trig_type, int trig_edge, int flags)
516 {
517 me4600_ai_subdevice_t *instance;
518 int err = ME_ERRNO_SUCCESS;
519 unsigned long cpu_flags;
520 int i;
521
522 instance = (me4600_ai_subdevice_t *) subdevice;
523
524 PDEBUG("executed. idx=0\n");
525
526 if (flags & ~ME_IO_SINGLE_CONFIG_CONTINUE) {
527 PERROR("Invalid flag specified.\n");
528 return ME_ERRNO_INVALID_FLAGS;
529 }
530
531 switch (trig_type) {
532 case ME_TRIG_TYPE_SW:
533 if (trig_edge != ME_TRIG_EDGE_NONE) {
534 PERROR
535 ("Invalid trigger edge. Software trigger has not edge.\n");
536 return ME_ERRNO_INVALID_TRIG_EDGE;
537 }
538 break;
539
540 case ME_TRIG_TYPE_EXT_ANALOG:
541 if (instance->channels <= 16) //Only versions with 32 channels have analog trigger (4670 and 4680)
542 {
543 PERROR("Invalid trigger type specified.\n");
544 return ME_ERRNO_INVALID_TRIG_TYPE;
545 }
546
547 case ME_TRIG_TYPE_EXT_DIGITAL:
548 if ((trig_edge != ME_TRIG_EDGE_ANY)
549 && (trig_edge != ME_TRIG_EDGE_RISING)
550 && (trig_edge != ME_TRIG_EDGE_FALLING)) {
551 PERROR("Invalid trigger edge specified.\n");
552 return ME_ERRNO_INVALID_TRIG_EDGE;
553 }
554 break;
555
556 default:
557 PERROR("Invalid trigger type specified.\n");
558 return ME_ERRNO_INVALID_TRIG_TYPE;
559 }
560
561 if (trig_chan != ME_TRIG_CHAN_DEFAULT) {
562 PERROR("Invalid trigger channel specified.\n");
563 return ME_ERRNO_INVALID_TRIG_CHAN;
564 }
565
566 if ((single_config < 0) || (single_config >= instance->ranges_len)) {
567 PERROR("Invalid single config specified.\n");
568 return ME_ERRNO_INVALID_SINGLE_CONFIG;
569 }
570
571 if ((ref != ME_REF_AI_GROUND) && (ref != ME_REF_AI_DIFFERENTIAL)) {
572 PERROR("Invalid analog reference specified.\n");
573 return ME_ERRNO_INVALID_REF;
574 }
575
576 if ((single_config % 2) && (ref != ME_REF_AI_GROUND)) {
577 PERROR("Invalid analog reference specified.\n");
578 return ME_ERRNO_INVALID_REF;
579 }
580
581 if ((ref == ME_REF_AI_DIFFERENTIAL)
582 && ((instance->channels == 16) || (channel >= 16))) {
583 PERROR("Invalid analog reference specified.\n");
584 return ME_ERRNO_INVALID_REF;
585 }
586
587 if (channel < 0) {
588 PERROR("Invalid channel number specified.\n");
589 return ME_ERRNO_INVALID_CHANNEL;
590 }
591
592 if (channel >= instance->channels) {
593 PERROR("Invalid channel number specified.\n");
594 return ME_ERRNO_INVALID_CHANNEL;
595 }
596
597 ME_SUBDEVICE_ENTER;
598
599 spin_lock_irqsave(&instance->subdevice_lock, cpu_flags);
600 //Prepare data entry.
601 // Common for all modes.
602 instance->single_config[channel].entry =
603 channel | ME4600_AI_LIST_LAST_ENTRY;
604
605 if (ref == ME_REF_AI_DIFFERENTIAL) { // ME_REF_AI_DIFFERENTIAL
606 instance->single_config[channel].entry |=
607 ME4600_AI_LIST_INPUT_DIFFERENTIAL;
608 }
609 /*
610 // ME4600_AI_LIST_INPUT_SINGLE_ENDED = 0x0000
611 // 'entry |= ME4600_AI_LIST_INPUT_SINGLE_ENDED' <== Do nothing. Removed.
612 else
613 {// ME_REF_AI_GROUND
614 instance->single_config[channel].entry |= ME4600_AI_LIST_INPUT_SINGLE_ENDED;
615 }
616 */
617 switch (single_config) {
618 case 0: //-10V..10V
619 /*
620 // ME4600_AI_LIST_RANGE_BIPOLAR_10 = 0x0000
621 // 'entry |= ME4600_AI_LIST_RANGE_BIPOLAR_10' <== Do nothing. Removed.
622 instance->single_config[channel].entry |= ME4600_AI_LIST_RANGE_BIPOLAR_10;
623 */ break;
624
625 case 1: //0V..10V
626 instance->single_config[channel].entry |=
627 ME4600_AI_LIST_RANGE_UNIPOLAR_10;
628 break;
629
630 case 2: //-2.5V..2.5V
631 instance->single_config[channel].entry |=
632 ME4600_AI_LIST_RANGE_BIPOLAR_2_5;
633 break;
634
635 case 3: //0V..2.5V
636 instance->single_config[channel].entry |=
637 ME4600_AI_LIST_RANGE_UNIPOLAR_2_5;
638 break;
639 }
640
641 // Prepare control register.
642 // Common for all modes.
643 instance->single_config[channel].ctrl =
644 ME4600_AI_CTRL_BIT_CHANNEL_FIFO | ME4600_AI_CTRL_BIT_DATA_FIFO;
645
646 switch (trig_type) {
647 case ME_TRIG_TYPE_SW:
648 // Nothing to set.
649 break;
650
651 case ME_TRIG_TYPE_EXT_ANALOG:
652 instance->single_config[channel].ctrl |=
653 ME4600_AI_CTRL_BIT_EX_TRIG_ANALOG;
654
655 case ME_TRIG_TYPE_EXT_DIGITAL:
656 instance->single_config[channel].ctrl |=
657 ME4600_AI_CTRL_BIT_EX_TRIG;
658 break;
659 }
660
661 switch (trig_edge) {
662 case ME_TRIG_EDGE_RISING:
663 // Nothing to set.
664 break;
665
666 case ME_TRIG_EDGE_ANY:
667 instance->single_config[channel].ctrl |=
668 ME4600_AI_CTRL_BIT_EX_TRIG_BOTH;
669
670 case ME_TRIG_EDGE_FALLING:
671 instance->single_config[channel].ctrl |=
672 ME4600_AI_CTRL_BIT_EX_TRIG_FALLING;
673 break;
674 }
675
676 // Enable this channel
677 instance->single_config[channel].status = ME_SINGLE_CHANNEL_CONFIGURED;
678
679 // Copy this settings to other outputs.
680 if (flags == ME_IO_SINGLE_CONFIG_CONTINUE) {
681 for (i = channel + 1; i < instance->channels; i++) {
682 instance->single_config[i].ctrl =
683 instance->single_config[channel].ctrl;
684 instance->single_config[i].entry =
685 instance->single_config[channel].entry;
686 instance->single_config[i].status =
687 ME_SINGLE_CHANNEL_CONFIGURED;
688 }
689 }
690
691 instance->status = ai_status_single_configured;
692 spin_unlock_irqrestore(&instance->subdevice_lock, cpu_flags);
693
694 ME_SUBDEVICE_EXIT;
695
696 return err;
697 }
698
699 static int me4600_ai_io_single_read(me_subdevice_t *subdevice,
700 struct file *filep,
701 int channel,
702 int *value, int time_out, int flags)
703 {
704 me4600_ai_subdevice_t *instance;
705 volatile uint32_t tmp;
706 volatile uint32_t val;
707 unsigned long cpu_flags;
708 int err = ME_ERRNO_SUCCESS;
709
710 unsigned long j;
711 unsigned long delay = 0;
712
713 PDEBUG("executed. idx=0\n");
714
715 instance = (me4600_ai_subdevice_t *) subdevice;
716
717 if (flags) {
718 PERROR("Invalid flag specified.\n");
719 return ME_ERRNO_INVALID_FLAGS;
720 }
721
722 if (instance->status != ai_status_single_configured) {
723 PERROR("Subdevice not configured to work in single mode!\n");
724 return ME_ERRNO_PREVIOUS_CONFIG;
725 }
726
727 if ((channel > instance->channels) || (channel < 0)) {
728 PERROR("Invalid channel specified.\n");
729 return ME_ERRNO_INVALID_CHANNEL;
730 }
731
732 if (time_out < 0) {
733 PERROR("Invalid timeout specified.\n");
734 return ME_ERRNO_INVALID_TIMEOUT;
735 }
736
737 if (instance->single_config[channel].status !=
738 ME_SINGLE_CHANNEL_CONFIGURED) {
739 PERROR("Channel is not configured to work in single mode!\n");
740 return ME_ERRNO_PREVIOUS_CONFIG;
741 }
742
743 if (inl(instance->status_reg) & ME4600_AI_STATUS_BIT_FSM) {
744 PERROR("Subdevice is busy.\n");
745 return ME_ERRNO_SUBDEVICE_BUSY;
746 }
747
748 ME_SUBDEVICE_ENTER;
749
750 // Cancel control task
751 PDEBUG("Cancel control task.\n");
752 instance->ai_control_task_flag = 0;
753 cancel_delayed_work(&instance->ai_control_task);
754
755 if (time_out) {
756 delay = (time_out * HZ) / 1000;
757
758 if (delay == 0)
759 delay = 1;
760 }
761
762 spin_lock_irqsave(&instance->subdevice_lock, cpu_flags);
763
764 // Mark that StreamConfig is removed.
765 instance->chan_list_len = 0;
766
767 spin_lock_irqsave(instance->ctrl_reg_lock, cpu_flags);
768 /// @note Imprtant: Preserve EXT IRQ settings.
769 tmp = inl(instance->ctrl_reg);
770 // Clear FIFOs and dissable interrupts
771 tmp &=
772 ~(ME4600_AI_CTRL_BIT_CHANNEL_FIFO | ME4600_AI_CTRL_BIT_DATA_FIFO);
773
774 tmp &=
775 ~(ME4600_AI_CTRL_BIT_SC_IRQ | ME4600_AI_CTRL_BIT_HF_IRQ |
776 ME4600_AI_CTRL_BIT_LE_IRQ);
777 tmp |=
778 ME4600_AI_CTRL_BIT_SC_IRQ_RESET | ME4600_AI_CTRL_BIT_HF_IRQ_RESET |
779 ME4600_AI_CTRL_BIT_LE_IRQ_RESET;
780
781 tmp |= ME4600_AI_CTRL_BIT_IMMEDIATE_STOP;
782 outl(tmp, instance->ctrl_reg);
783 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
784 instance->ctrl_reg - instance->reg_base, tmp);
785
786 outl(0, instance->scan_pre_timer_low_reg);
787 PDEBUG_REG("scan_pre_timer_low_reg outl(0x%lX+0x%lX)=0x%x\n",
788 instance->reg_base,
789 instance->scan_pre_timer_low_reg - instance->reg_base, 0);
790 outl(0, instance->scan_pre_timer_high_reg);
791 PDEBUG_REG("scan_pre_timer_high_reg outl(0x%lX+0x%lX)=0x%x\n",
792 instance->reg_base,
793 instance->scan_pre_timer_high_reg - instance->reg_base, 0);
794 outl(0, instance->scan_timer_low_reg);
795 PDEBUG_REG("scan_timer_low_reg outl(0x%lX+0x%lX)=0x%x\n",
796 instance->reg_base,
797 instance->scan_timer_low_reg - instance->reg_base, 0);
798 outl(0, instance->scan_timer_high_reg);
799 PDEBUG_REG("scan_timer_high_reg outl(0x%lX+0x%lX)=0x%x\n",
800 instance->reg_base,
801 instance->scan_timer_high_reg - instance->reg_base, 0);
802 outl(65, instance->chan_timer_reg);
803 PDEBUG_REG("chan_timer_reg outl(0x%lX+0x%lX)=0x%x\n",
804 instance->reg_base,
805 instance->chan_timer_reg - instance->reg_base, 65);
806 outl(65, instance->chan_pre_timer_reg);
807 PDEBUG_REG("chan_pre_timer_reg outl(0x%lX+0x%lX)=0x%x\n",
808 instance->reg_base,
809 instance->chan_pre_timer_reg - instance->reg_base, 65);
810
811 //Reactive FIFOs. Enable work.
812 tmp |= ME4600_AI_CTRL_BIT_CHANNEL_FIFO | ME4600_AI_CTRL_BIT_DATA_FIFO;
813 outl(tmp, instance->ctrl_reg);
814 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
815 instance->ctrl_reg - instance->reg_base, tmp);
816
817 outl(instance->single_config[channel].entry,
818 instance->channel_list_reg);
819 PDEBUG_REG("channel_list_reg outl(0x%lX+0x%lX)=0x%x\n",
820 instance->reg_base,
821 instance->channel_list_reg - instance->reg_base,
822 instance->single_config[channel].entry);
823
824 // Preserve EXT IRQ settings.
825 tmp &= (ME4600_AI_CTRL_BIT_EX_IRQ | ME4600_AI_CTRL_BIT_EX_IRQ_RESET);
826 outl(instance->single_config[channel].ctrl | tmp, instance->ctrl_reg);
827 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
828 instance->ctrl_reg - instance->reg_base,
829 instance->single_config[channel].ctrl | tmp);
830
831 spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
832
833 if (!(instance->single_config[channel].ctrl & ME4600_AI_CTRL_BIT_EX_TRIG)) { // Software start
834 inl(instance->start_reg);
835 PDEBUG_REG("start_reg inl(0x%lX+0x%lX)\n", instance->reg_base,
836 instance->start_reg - instance->reg_base);
837
838 delay = 2;
839 }
840
841 j = jiffies;
842
843 while (!(inl(instance->status_reg) & ME4600_AI_STATUS_BIT_EF_DATA)) {
844 if (delay && ((jiffies - j) >= delay)) {
845 if (!(instance->single_config[channel].ctrl & ME4600_AI_CTRL_BIT_EX_TRIG)) { // Software start.
846 PERROR("Value not available after wait.\n");
847 err = ME_ERRNO_INTERNAL;
848 } else { // External start.
849 PERROR("Timeout reached.\n");
850 err = ME_ERRNO_TIMEOUT;
851 }
852 break;
853 }
854 // Wait
855 set_current_state(TASK_INTERRUPTIBLE);
856 schedule_timeout(1);
857
858 if (signal_pending(current)) {
859 PERROR
860 ("Wait on external trigger interrupted by signal.\n");
861 err = ME_ERRNO_SIGNAL;
862 break;
863 }
864
865 if (instance->status != ai_status_single_configured) {
866 PERROR("Wait interrupted by reset.\n");
867 err = ME_ERRNO_CANCELLED;
868 break;
869 }
870 }
871
872 // Read value.
873 if (!err) {
874 val = inl(instance->data_reg) ^ 0x8000;
875 PDEBUG_REG("data_reg inl(0x%lX+0x%lX)=0x%x\n",
876 instance->reg_base,
877 instance->data_reg - instance->reg_base, val);
878 *value = val & ME4600_AI_MAX_DATA;
879 } else {
880 *value = 0xFFFFFFFF;
881 }
882
883 // Restore settings.
884 spin_lock_irqsave(instance->ctrl_reg_lock, cpu_flags);
885 tmp = inl(instance->ctrl_reg);
886 // Clear FIFOs and dissable interrupts.
887 tmp &=
888 ~(ME4600_AI_CTRL_BIT_CHANNEL_FIFO | ME4600_AI_CTRL_BIT_DATA_FIFO);
889 tmp |= ME4600_AI_CTRL_BIT_SC_IRQ | ME4600_AI_CTRL_BIT_HF_IRQ;
890 tmp |=
891 ME4600_AI_CTRL_BIT_SC_IRQ_RESET | ME4600_AI_CTRL_BIT_HF_IRQ_RESET |
892 ME4600_AI_CTRL_BIT_LE_IRQ_RESET | ME4600_AI_CTRL_BIT_IMMEDIATE_STOP;
893 outl(tmp, instance->ctrl_reg);
894 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
895 instance->ctrl_reg - instance->reg_base, tmp);
896 spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
897
898 spin_unlock_irqrestore(&instance->subdevice_lock, cpu_flags);
899
900 ME_SUBDEVICE_EXIT;
901
902 return err;
903 }
904
905 static int me4600_ai_io_stream_config(me_subdevice_t *subdevice,
906 struct file *filep,
907 meIOStreamConfig_t *config_list,
908 int count,
909 meIOStreamTrigger_t *trigger,
910 int fifo_irq_threshold, int flags)
911 {
912 me4600_ai_subdevice_t *instance;
913 int err = ME_ERRNO_SUCCESS;
914 int i; // internal multipurpose variable
915 unsigned long long data_required;
916
917 volatile uint32_t entry;
918 volatile uint32_t ctrl = ME4600_AI_CTRL_BIT_IMMEDIATE_STOP;
919 volatile uint32_t tmp; // use when current copy of register's value needed
920 unsigned long cpu_flags;
921
922 uint64_t acq_ticks;
923 uint64_t scan_ticks;
924 uint64_t conv_ticks;
925 unsigned int acq_start_ticks_low = trigger->iAcqStartTicksLow;
926 unsigned int acq_start_ticks_high = trigger->iAcqStartTicksHigh;
927 unsigned int scan_start_ticks_low = trigger->iScanStartTicksLow;
928 unsigned int scan_start_ticks_high = trigger->iScanStartTicksHigh;
929 unsigned int conv_start_ticks_low = trigger->iConvStartTicksLow;
930 unsigned int conv_start_ticks_high = trigger->iConvStartTicksHigh;
931
932 PDEBUG("executed. idx=0\n");
933
934 instance = (me4600_ai_subdevice_t *) subdevice;
935
936 if (flags) {
937 PERROR("Invalid flag specified.\n");
938 return ME_ERRNO_INVALID_FLAGS;
939 }
940
941 ME_SUBDEVICE_ENTER
942 // Convert ticks to 64 bit long values
943 acq_ticks =
944 (uint64_t) acq_start_ticks_low +
945 ((uint64_t) acq_start_ticks_high << 32);
946 scan_ticks =
947 (uint64_t) scan_start_ticks_low +
948 ((uint64_t) scan_start_ticks_high << 32);
949 conv_ticks =
950 (uint64_t) conv_start_ticks_low +
951 ((uint64_t) conv_start_ticks_high << 32);
952
953 // Check settings - begin
954 switch (trigger->iAcqStartTrigType) {
955 case ME_TRIG_TYPE_SW:
956 case ME_TRIG_TYPE_EXT_DIGITAL:
957 case ME_TRIG_TYPE_EXT_ANALOG:
958 break;
959
960 default:
961 PERROR("Invalid acquisition start trigger type specified.\n");
962 err = ME_ERRNO_INVALID_ACQ_START_TRIG_TYPE;
963 goto ERROR;
964 break;
965 }
966
967 if ((trigger->iAcqStartTrigType == ME_TRIG_TYPE_SW)
968 && (trigger->iAcqStartTrigEdge != ME_TRIG_EDGE_NONE)) {
969 PERROR("Invalid acquisition start trigger edge specified.\n");
970 err = ME_ERRNO_INVALID_ACQ_START_TRIG_EDGE;
971 goto ERROR;
972 }
973
974 if (trigger->iAcqStartTrigType != ME_TRIG_TYPE_SW) {
975 switch (trigger->iAcqStartTrigEdge) {
976 case ME_TRIG_EDGE_RISING:
977 case ME_TRIG_EDGE_FALLING:
978 case ME_TRIG_EDGE_ANY:
979 break;
980
981 default:
982 PERROR
983 ("Invalid acquisition start trigger edge specified.\n");
984 err = ME_ERRNO_INVALID_ACQ_START_TRIG_EDGE;
985 goto ERROR;
986 break;
987 }
988 }
989
990 if (trigger->iAcqStartTrigChan != ME_TRIG_CHAN_DEFAULT) {
991 PERROR
992 ("Invalid acquisition start trigger channel specified.\n");
993 err = ME_ERRNO_INVALID_ACQ_START_TRIG_CHAN;
994 goto ERROR;
995 }
996
997 if ((acq_ticks < ME4600_AI_MIN_ACQ_TICKS)
998 || (acq_ticks > ME4600_AI_MAX_ACQ_TICKS)) {
999 PERROR
1000 ("Invalid acquisition start trigger argument specified.\n");
1001 err = ME_ERRNO_INVALID_ACQ_START_ARG;
1002 goto ERROR;
1003 }
1004
1005 switch (trigger->iScanStartTrigType) {
1006
1007 case ME_TRIG_TYPE_TIMER:
1008 if ((scan_ticks < ME4600_AI_MIN_SCAN_TICKS)
1009 || (scan_ticks > ME4600_AI_MAX_SCAN_TICKS)
1010 || (scan_ticks < count * conv_ticks)
1011 ) {
1012 PERROR("Invalid scan start argument specified.\n");
1013 err = ME_ERRNO_INVALID_SCAN_START_ARG;
1014 goto ERROR;
1015 }
1016 break;
1017
1018 case ME_TRIG_TYPE_EXT_DIGITAL:
1019 if (trigger->iAcqStartTrigType != ME_TRIG_TYPE_EXT_DIGITAL) {
1020 PERROR
1021 ("Invalid scan start trigger type specified (Acq is HW digital)\n");
1022 err = ME_ERRNO_INVALID_SCAN_START_TRIG_TYPE;
1023 goto ERROR;
1024 }
1025 break;
1026
1027 case ME_TRIG_TYPE_EXT_ANALOG:
1028 if (trigger->iAcqStartTrigType != ME_TRIG_TYPE_EXT_ANALOG) {
1029 PERROR
1030 ("Invalid scan start trigger type specified (Acq is HW analog)\n");
1031 err = ME_ERRNO_INVALID_SCAN_START_TRIG_TYPE;
1032 goto ERROR;
1033 }
1034 break;
1035
1036 case ME_TRIG_TYPE_FOLLOW:
1037 break;
1038
1039 default:
1040 PERROR("Invalid scan start trigger type specified.\n");
1041 err = ME_ERRNO_INVALID_SCAN_START_TRIG_TYPE;
1042 goto ERROR;
1043 break;
1044 }
1045
1046 switch (trigger->iConvStartTrigType) {
1047
1048 case ME_TRIG_TYPE_TIMER:
1049 if ((conv_ticks < ME4600_AI_MIN_CHAN_TICKS)
1050 || (conv_ticks > ME4600_AI_MAX_CHAN_TICKS)) {
1051 PERROR
1052 ("Invalid conv start trigger argument specified.\n");
1053 err = ME_ERRNO_INVALID_CONV_START_ARG;
1054 goto ERROR;
1055 }
1056 break;
1057
1058 case ME_TRIG_TYPE_EXT_DIGITAL:
1059 if ((trigger->iScanStartTrigType != ME_TRIG_TYPE_FOLLOW)
1060 || (trigger->iAcqStartTrigType !=
1061 ME_TRIG_TYPE_EXT_DIGITAL)) {
1062 PERROR("Invalid conv start trigger type specified.\n");
1063 err = ME_ERRNO_INVALID_CONV_START_TRIG_TYPE;
1064 goto ERROR;
1065 }
1066 break;
1067
1068 case ME_TRIG_TYPE_EXT_ANALOG:
1069 if ((trigger->iScanStartTrigType != ME_TRIG_TYPE_FOLLOW)
1070 || (trigger->iAcqStartTrigType !=
1071 ME_TRIG_TYPE_EXT_ANALOG)) {
1072 PERROR("Invalid conv start trigger type specified.\n");
1073 err = ME_ERRNO_INVALID_CONV_START_TRIG_TYPE;
1074 goto ERROR;
1075 }
1076 break;
1077
1078 default:
1079 PERROR("Invalid conv start trigger type specified.\n");
1080 err = ME_ERRNO_INVALID_CONV_START_TRIG_TYPE;
1081 goto ERROR;
1082
1083 break;
1084 }
1085 /**
1086 * Aceptable settings:
1087 * iScanStopTrigType : iAcqStopTrigType
1088 *
1089 * ME_TRIG_TYPE_NONE : ME_TRIG_TYPE_NONE -> infinite count with manual stop
1090 * ME_TRIG_TYPE_NONE : ME_TRIG_TYPE_COUNT -> stop after getting iScanStopCount list of values (iScanStopCount * count)
1091 * ME_TRIG_TYPE_COUNT : ME_TRIG_TYPE_FOLLOW -> stop after getting iAcqStopCount values (it can stops in midle of the list)
1092 */
1093 switch (trigger->iScanStopTrigType) {
1094
1095 case ME_TRIG_TYPE_NONE:
1096 break;
1097
1098 case ME_TRIG_TYPE_COUNT:
1099 if (trigger->iScanStopCount <= 0) {
1100 PERROR("Invalid scan stop argument specified.\n");
1101 err = ME_ERRNO_INVALID_SCAN_STOP_ARG;
1102 goto ERROR;
1103 }
1104 break;
1105
1106 default:
1107 PERROR("Invalid scan stop trigger type specified.\n");
1108 err = ME_ERRNO_INVALID_SCAN_STOP_TRIG_TYPE;
1109 goto ERROR;
1110 break;
1111 }
1112
1113 switch (trigger->iAcqStopTrigType) {
1114
1115 case ME_TRIG_TYPE_NONE:
1116 if (trigger->iScanStopTrigType != ME_TRIG_TYPE_NONE) {
1117 PERROR("Invalid acq stop trigger type specified.\n");
1118 err = ME_ERRNO_INVALID_ACQ_STOP_TRIG_TYPE;
1119 goto ERROR;
1120 }
1121 break;
1122
1123 case ME_TRIG_TYPE_FOLLOW:
1124 if (trigger->iScanStopTrigType != ME_TRIG_TYPE_COUNT) {
1125 PERROR("Invalid acq stop trigger type specified.\n");
1126 err = ME_ERRNO_INVALID_ACQ_STOP_TRIG_TYPE;
1127 goto ERROR;
1128 }
1129 break;
1130
1131 case ME_TRIG_TYPE_COUNT:
1132 if (trigger->iScanStopTrigType != ME_TRIG_TYPE_NONE) {
1133 PERROR("Invalid acq stop trigger type specified.\n");
1134 err = ME_ERRNO_INVALID_ACQ_STOP_TRIG_TYPE;
1135 goto ERROR;
1136 }
1137
1138 if (trigger->iAcqStopCount <= 0) {
1139 PERROR
1140 ("Invalid acquisition or scan stop argument specified.\n");
1141 err = ME_ERRNO_INVALID_ACQ_STOP_ARG;
1142 goto ERROR;
1143 }
1144 break;
1145
1146 default:
1147 PERROR("Invalid acq stop trigger type specified.\n");
1148 err = ME_ERRNO_INVALID_ACQ_STOP_TRIG_TYPE;
1149 goto ERROR;
1150 break;
1151 }
1152
1153 if ((count <= 0) || (count > ME4600_AI_LIST_COUNT)) {
1154 PERROR("Invalid channel list count specified.\n");
1155 err = ME_ERRNO_INVALID_CONFIG_LIST_COUNT;
1156 goto ERROR;
1157 }
1158 ///This is general limitation
1159 // if (fifo_irq_threshold < 0 || fifo_irq_threshold >= ME4600_AI_CIRC_BUF_COUNT)
1160 ///This is limitation from Windows. I use it for compatibility.
1161 if (fifo_irq_threshold < 0
1162 || fifo_irq_threshold >= ME4600_AI_FIFO_COUNT) {
1163 PERROR("Invalid fifo irq threshold specified.\n");
1164 err = ME_ERRNO_INVALID_FIFO_IRQ_THRESHOLD;
1165 goto ERROR;
1166 }
1167
1168 if ((config_list[0].iRef == ME_REF_AI_DIFFERENTIAL)
1169 && (instance->channels == 16)) {
1170 PERROR
1171 ("Differential reference is not available on this subdevice.\n");
1172 err = ME_ERRNO_INVALID_REF;
1173 goto ERROR;
1174 }
1175
1176 if (flags & ME_IO_STREAM_CONFIG_SAMPLE_AND_HOLD) {
1177 if (!instance->sh) {
1178 PERROR
1179 ("Sample and hold is not available for this board.\n");
1180 err = ME_ERRNO_INVALID_FLAGS;
1181 goto ERROR;
1182 }
1183 if (config_list[0].iRef == ME_REF_AI_DIFFERENTIAL) {
1184 PERROR
1185 ("Sample and hold is not available in differential mode.\n");
1186 err = ME_ERRNO_INVALID_FLAGS;
1187 goto ERROR;
1188 }
1189 }
1190
1191 for (i = 0; i < count; i++) {
1192 if ((config_list[i].iStreamConfig < 0)
1193 || (config_list[i].iStreamConfig >= instance->ranges_len)) {
1194 PERROR("Invalid stream config specified.\n");
1195 err = ME_ERRNO_INVALID_STREAM_CONFIG;
1196 goto ERROR;
1197 }
1198
1199 if ((config_list[i].iRef != ME_REF_AI_GROUND)
1200 && (config_list[i].iRef != ME_REF_AI_DIFFERENTIAL)) {
1201 PERROR("Invalid references in the list. Ref=0x%x\n",
1202 config_list[i].iRef);
1203 err = ME_ERRNO_INVALID_REF;
1204 goto ERROR;
1205 }
1206
1207 if (config_list[i].iStreamConfig % 2) { // StreamConfig: 1 or 3
1208 if (config_list[i].iRef == ME_REF_AI_DIFFERENTIAL) {
1209 PERROR
1210 ("Only bipolar modes support differential measurement.\n");
1211 err = ME_ERRNO_INVALID_REF;
1212 goto ERROR;
1213 }
1214 }
1215
1216 if (config_list[i].iRef != config_list[0].iRef) {
1217 PERROR
1218 ("Not all references in the configuration list are equal. Ref[0]=0x%x Ref[%d]=0x%x\n",
1219 config_list[0].iRef, i, config_list[i].iRef);
1220 err = ME_ERRNO_INVALID_REF;
1221 goto ERROR;
1222 }
1223
1224 if ((config_list[i].iRef == ME_REF_AI_DIFFERENTIAL)
1225 && (config_list[i].iChannel >= 16)) {
1226 PERROR("Channel not available in differential mode.\n");
1227 err = ME_ERRNO_INVALID_CHANNEL;
1228 goto ERROR;
1229 }
1230
1231 if ((config_list[i].iChannel < 0)
1232 || (config_list[i].iChannel >= instance->channels)) {
1233 PERROR("Invalid channel number specified.\n");
1234 err = ME_ERRNO_INVALID_CHANNEL;
1235 goto ERROR;
1236 }
1237 }
1238
1239 // Check settings - end
1240
1241 //Cancel control task
1242 PDEBUG("Cancel control task.\n");
1243 instance->ai_control_task_flag = 0;
1244 cancel_delayed_work(&instance->ai_control_task);
1245
1246 // Work around from Keith Hartley - begin
1247 if (trigger->iScanStartTrigType == ME_TRIG_TYPE_TIMER) {
1248 if (count == 1) {
1249 // The hardware does not work properly with a non-zero scan time
1250 // if there is only ONE channel in the channel list. In this case
1251 // we must set the scan time to zero and use the channel time.
1252
1253 conv_ticks = scan_ticks;
1254 trigger->iScanStartTrigType = ME_TRIG_TYPE_FOLLOW;
1255 } else if (scan_ticks == count * conv_ticks) {
1256 // Another hardware problem. If the number of scan ticks is
1257 // exactly equal to the number of channel ticks multiplied by
1258 // the number of channels then the sampling rate is reduced
1259 // by half.
1260 trigger->iScanStartTrigType = ME_TRIG_TYPE_FOLLOW;
1261 }
1262 }
1263 // Work around from Keith Hartley - end
1264
1265 spin_lock_irqsave(&instance->subdevice_lock, cpu_flags);
1266
1267 if (inl(instance->status_reg) & ME4600_AI_STATUS_BIT_FSM) {
1268 PERROR("Subdevice is busy.\n");
1269 spin_unlock_irqrestore(&instance->subdevice_lock, cpu_flags);
1270 ME_SUBDEVICE_EXIT;
1271 return ME_ERRNO_SUBDEVICE_BUSY;
1272 }
1273
1274 instance->status = ai_status_none;
1275 spin_lock_irqsave(instance->ctrl_reg_lock, cpu_flags);
1276 // Stop all actions. Block all interrupts. Clear (disable) FIFOs.
1277 ctrl =
1278 ME4600_AI_CTRL_BIT_LE_IRQ_RESET | ME4600_AI_CTRL_BIT_HF_IRQ_RESET |
1279 ME4600_AI_CTRL_BIT_SC_IRQ_RESET;
1280
1281 tmp = inl(instance->ctrl_reg);
1282 // Preserve EXT IRQ and OFFSET settings. Clean other bits.
1283 tmp &=
1284 (ME4600_AI_CTRL_BIT_EX_IRQ | ME4600_AI_CTRL_BIT_EX_IRQ_RESET |
1285 ME4600_AI_CTRL_BIT_FULLSCALE | ME4600_AI_CTRL_BIT_OFFSET);
1286
1287 // Send it to register.
1288 outl(tmp | ctrl, instance->ctrl_reg);
1289 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
1290 instance->ctrl_reg - instance->reg_base, tmp | ctrl);
1291
1292 // Enable channel fifo -> data fifo in stream_start().
1293 ctrl |= ME4600_AI_CTRL_BIT_CHANNEL_FIFO;
1294 outl(tmp | ctrl, instance->ctrl_reg);
1295 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
1296 instance->ctrl_reg - instance->reg_base, tmp | ctrl);
1297 spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
1298
1299 // Write the channel list
1300 for (i = 0; i < count; i++) {
1301 entry = config_list[i].iChannel;
1302
1303 switch (config_list[i].iStreamConfig) {
1304 case 0: //BIPOLAR 10V
1305 /*
1306 // ME4600_AI_LIST_RANGE_BIPOLAR_10 = 0x0000
1307 // 'entry |= ME4600_AI_LIST_RANGE_BIPOLAR_10' <== Do nothing. Removed.
1308 entry |= ME4600_AI_LIST_RANGE_BIPOLAR_10;
1309 */
1310 break;
1311 case 1: //UNIPOLAR 10V
1312 entry |= ME4600_AI_LIST_RANGE_UNIPOLAR_10;
1313 break;
1314 case 2: //BIPOLAR 2.5V
1315 entry |= ME4600_AI_LIST_RANGE_BIPOLAR_2_5;
1316 break;
1317 case 3: //UNIPOLAR 2.5V
1318 entry |= ME4600_AI_LIST_RANGE_UNIPOLAR_2_5;
1319 break;
1320 default:
1321 PERROR_CRITICAL("UNCHECK ERROR in config_list!\n");
1322 PERROR_CRITICAL
1323 ("WRONG range\nPosition:%d Range:0x%04X\n", i,
1324 config_list[i].iStreamConfig);
1325 goto VERIFY_ERROR;
1326 break;
1327 }
1328
1329 switch (config_list[i].iRef) {
1330 case ME_REF_AI_GROUND: //SINGLE ENDED
1331 /*
1332 // ME4600_AI_LIST_INPUT_SINGLE_ENDED = 0x0000
1333 // 'entry |= ME4600_AI_LIST_INPUT_SINGLE_ENDED' ==> Do nothing. Removed.
1334 entry |= ME4600_AI_LIST_INPUT_SINGLE_ENDED;
1335 */ break;
1336 case ME_REF_AI_DIFFERENTIAL: //DIFFERENTIAL
1337 entry |= ME4600_AI_LIST_INPUT_DIFFERENTIAL;
1338 break;
1339 default:
1340 PERROR_CRITICAL("UNCHECK ERROR in config_list!\n");
1341 PERROR_CRITICAL
1342 ("WRONG reference\nPosition:%d Reference:0x%04X\n",
1343 i, config_list[i].iRef);
1344 goto VERIFY_ERROR;
1345 break;
1346 }
1347
1348 //Add last entry flag
1349 if (i == (count - 1)) {
1350 entry |= ME4600_AI_LIST_LAST_ENTRY;
1351 }
1352
1353 outl(entry, instance->channel_list_reg);
1354 PDEBUG_REG("channel_list_reg outl(0x%lX+0x%lX)=0x%x\n",
1355 instance->reg_base,
1356 instance->channel_list_reg - instance->reg_base,
1357 entry);
1358 }
1359
1360 // Set triggering registers
1361 --acq_ticks;
1362 outl(acq_ticks, instance->chan_pre_timer_reg);
1363 PDEBUG_REG("chan_pre_timer_reg outl(0x%lX+0x%lX)=0x%llX\n",
1364 instance->reg_base,
1365 instance->chan_pre_timer_reg - instance->reg_base,
1366 acq_ticks);
1367 outl(acq_ticks, instance->scan_pre_timer_low_reg);
1368 PDEBUG_REG("scan_pre_timer_low_reg outl(0x%lX+0x%lX)=0x%llX\n",
1369 instance->reg_base,
1370 instance->scan_pre_timer_low_reg - instance->reg_base,
1371 acq_ticks & 0xFFFFFFFF);
1372 outl((acq_ticks >> 32), instance->scan_pre_timer_high_reg);
1373 PDEBUG_REG("scan_pre_timer_high_reg outl(0x%lX+0x%lX)=0x%llX\n",
1374 instance->reg_base,
1375 instance->scan_pre_timer_high_reg - instance->reg_base,
1376 (acq_ticks >> 32) & 0xFFFFFFFF);
1377
1378 // Set triggers
1379 switch (trigger->iAcqStartTrigType) {
1380 // Internal
1381 case ME_TRIG_TYPE_SW:
1382 // Nothing to set.
1383 break;
1384
1385 // External
1386 case ME_TRIG_TYPE_EXT_ANALOG:
1387 ctrl |= ME4600_AI_CTRL_BIT_EX_TRIG_ANALOG;
1388 case ME_TRIG_TYPE_EXT_DIGITAL:
1389 ctrl |= ME4600_AI_CTRL_BIT_EX_TRIG;
1390
1391 // External trigger needs edge's definition
1392 switch (trigger->iAcqStartTrigEdge) {
1393 case ME_TRIG_EDGE_RISING:
1394 // Nothing to set.
1395 break;
1396
1397 case ME_TRIG_EDGE_FALLING:
1398 ctrl |= ME4600_AI_CTRL_BIT_EX_TRIG_FALLING;
1399 break;
1400
1401 case ME_TRIG_EDGE_ANY:
1402 ctrl |=
1403 ME4600_AI_CTRL_BIT_EX_TRIG_FALLING |
1404 ME4600_AI_CTRL_BIT_EX_TRIG_BOTH;
1405 break;
1406
1407 default:
1408 PERROR_CRITICAL
1409 ("UNCHECK TRIGGER EDGE in triggers structure!\n");
1410 PERROR_CRITICAL
1411 ("WRONG acquisition start trigger:0x%04X.\n",
1412 trigger->iAcqStartTrigEdge);
1413 err = ME_ERRNO_INVALID_ACQ_START_TRIG_EDGE;
1414 goto VERIFY_ERROR;
1415 break;
1416 }
1417 break;
1418
1419 default:
1420 PERROR_CRITICAL("UNCHECK TRIGGER in triggers structure!\n");
1421 PERROR_CRITICAL("WRONG acquisition start trigger:0x%04X.\n",
1422 trigger->iAcqStartTrigType);
1423 err = ME_ERRNO_INVALID_ACQ_START_TRIG_TYPE;
1424 goto VERIFY_ERROR;
1425 break;
1426 }
1427
1428 switch (trigger->iScanStartTrigType) {
1429 case ME_TRIG_TYPE_TIMER:
1430 --scan_ticks;
1431 outl(scan_ticks, instance->scan_timer_low_reg);
1432 PDEBUG_REG("scan_timer_low_reg outl(0x%lX+0x%lX)=0x%llX\n",
1433 instance->reg_base,
1434 instance->scan_timer_low_reg - instance->reg_base,
1435 scan_ticks & 0xFFFFFFFF);
1436 outl((scan_ticks >> 32), instance->scan_timer_high_reg);
1437 PDEBUG_REG("scan_timer_high_reg outl(0x%lX+0x%lX)=0x%llX\n",
1438 instance->reg_base,
1439 instance->scan_timer_high_reg - instance->reg_base,
1440 (scan_ticks >> 32) & 0xFFFFFFFF);
1441
1442 if (trigger->iAcqStartTrigType == ME_TRIG_TYPE_SW) {
1443 ctrl |= ME4600_AI_CTRL_BIT_MODE_0;
1444 } else {
1445 ctrl |= ME4600_AI_CTRL_BIT_MODE_1;
1446 }
1447 break;
1448
1449 case ME_TRIG_TYPE_EXT_DIGITAL:
1450 case ME_TRIG_TYPE_EXT_ANALOG:
1451 outl(0, instance->scan_timer_low_reg);
1452 PDEBUG_REG("scan_timer_low_reg outl(0x%lX+0x%lX)=0x%x\n",
1453 instance->reg_base,
1454 instance->scan_timer_low_reg - instance->reg_base,
1455 0);
1456 outl(0, instance->scan_timer_high_reg);
1457 PDEBUG_REG("scan_timer_high_reg outl(0x%lX+0x%lX)=0x%x\n",
1458 instance->reg_base,
1459 instance->scan_timer_high_reg - instance->reg_base,
1460 0);
1461 ctrl |= ME4600_AI_CTRL_BIT_MODE_2;
1462 break;
1463
1464 case ME_TRIG_TYPE_FOLLOW:
1465 outl(0, instance->scan_timer_low_reg);
1466 PDEBUG_REG("scan_timer_low_reg outl(0x%lX+0x%lX)=0x%x\n",
1467 instance->reg_base,
1468 instance->scan_timer_low_reg - instance->reg_base,
1469 0);
1470 outl(0, instance->scan_timer_high_reg);
1471 PDEBUG_REG("scan_timer_high_reg outl(0x%lX+0x%lX)=0x%x\n",
1472 instance->reg_base,
1473 instance->scan_timer_high_reg - instance->reg_base,
1474 0);
1475
1476 if (trigger->iAcqStartTrigType == ME_TRIG_TYPE_SW) {
1477 ctrl |= ME4600_AI_CTRL_BIT_MODE_0;
1478 } else {
1479 ctrl |= ME4600_AI_CTRL_BIT_MODE_1;
1480 }
1481 break;
1482
1483 default:
1484 PERROR_CRITICAL("UNCHECK TRIGGER in triggers structure!\n");
1485 PERROR_CRITICAL("WRONG scan start trigger:0x%04X.\n",
1486 trigger->iScanStartTrigType);
1487 err = ME_ERRNO_INVALID_SCAN_START_TRIG_TYPE;
1488 goto VERIFY_ERROR;
1489 break;
1490 }
1491
1492 switch (trigger->iConvStartTrigType) {
1493
1494 case ME_TRIG_TYPE_TIMER:
1495 --conv_ticks;
1496 outl(conv_ticks, instance->chan_timer_reg);
1497 PDEBUG_REG("chan_timer_reg outl(0x%lX+0x%lX)=0x%llX\n",
1498 instance->reg_base,
1499 instance->chan_timer_reg - instance->reg_base,
1500 conv_ticks);
1501 break;
1502
1503 case ME_TRIG_TYPE_EXT_DIGITAL:
1504 case ME_TRIG_TYPE_EXT_ANALOG:
1505 outl(0, instance->chan_timer_reg);
1506 PDEBUG_REG("chan_timer_reg outl(0x%lX+0x%lX)=0x%x\n",
1507 instance->reg_base,
1508 instance->chan_timer_reg - instance->reg_base, 0);
1509 ctrl |= ME4600_AI_CTRL_BIT_MODE_0 | ME4600_AI_CTRL_BIT_MODE_1;
1510 break;
1511
1512 default:
1513 PERROR_CRITICAL("UNCHECK TRIGGER in triggers structure!\n");
1514 PERROR_CRITICAL("WRONG conv start trigger:0x%04X.\n",
1515 trigger->iConvStartTrigType);
1516 err = ME_ERRNO_INVALID_CONV_START_TRIG_TYPE;
1517 goto VERIFY_ERROR;
1518
1519 break;
1520 }
1521
1522 //Sample & Hold feature
1523 if (flags & ME_IO_STREAM_CONFIG_SAMPLE_AND_HOLD) {
1524 if (instance->sh) {
1525 ctrl |= ME4600_AI_CTRL_BIT_SAMPLE_HOLD;
1526 } else {
1527 PERROR_CRITICAL("UNCHECK S&H feature!\n");
1528 err = ME_ERRNO_INVALID_FLAGS;
1529 goto VERIFY_ERROR;
1530 }
1531 }
1532 //Enable IRQs sources but leave latches blocked.
1533 ctrl |= (ME4600_AI_CTRL_BIT_HF_IRQ | ME4600_AI_CTRL_BIT_SC_IRQ | ME4600_AI_CTRL_BIT_LE_IRQ); //The last IRQ source (ME4600_AI_CTRL_BIT_LE_IRQ) is unused!
1534
1535 //Everything is good. Finalize
1536 spin_lock_irqsave(instance->ctrl_reg_lock, cpu_flags);
1537 tmp = inl(instance->ctrl_reg);
1538
1539 //Preserve EXT IRQ and OFFSET settings. Clean other bits.
1540 tmp &=
1541 (ME4600_AI_CTRL_BIT_EX_IRQ | ME4600_AI_CTRL_BIT_EX_IRQ_RESET |
1542 ME4600_AI_CTRL_BIT_FULLSCALE | ME4600_AI_CTRL_BIT_OFFSET);
1543
1544 // write the control word
1545 outl(ctrl | tmp, instance->ctrl_reg);
1546 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
1547 instance->ctrl_reg - instance->reg_base, ctrl | tmp);
1548 spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
1549
1550 //Set the global parameters end exit.
1551 instance->chan_list_len = count;
1552 instance->fifo_irq_threshold = fifo_irq_threshold;
1553
1554 if (trigger->iAcqStopTrigType == ME_TRIG_TYPE_COUNT) {
1555 data_required =
1556 (unsigned long long)trigger->iAcqStopCount *
1557 (unsigned long long)count;
1558 if (data_required > UINT_MAX)
1559 data_required = UINT_MAX;
1560 instance->data_required = (unsigned int)data_required;
1561 } else if (trigger->iScanStopTrigType == ME_TRIG_TYPE_COUNT)
1562 instance->data_required =
1563 (unsigned long long)trigger->iScanStopCount;
1564 else
1565 instance->data_required = 0;
1566
1567 // Mark subdevice as configured to work in stream mode.
1568 instance->status = ai_status_stream_configured;
1569
1570 // Deinit single config. Set all entries to NOT_CONFIGURED.
1571 for (i = 0; i < instance->channels; i++) {
1572 instance->single_config[i].status =
1573 ME_SINGLE_CHANNEL_NOT_CONFIGURED;
1574 }
1575
1576 VERIFY_ERROR: // Error in code. Wrong setting check. This should never ever happend!
1577 spin_unlock_irqrestore(&instance->subdevice_lock, cpu_flags);
1578 ERROR: // Error in settings.
1579 ME_SUBDEVICE_EXIT;
1580
1581 return err;
1582 }
1583
1584 static int me4600_ai_io_stream_new_values(me_subdevice_t *subdevice,
1585 struct file *filep,
1586 int time_out, int *count, int flags)
1587 {
1588 me4600_ai_subdevice_t *instance;
1589 int err = ME_ERRNO_SUCCESS;
1590 unsigned long t;
1591 unsigned long j;
1592 int volatile head;
1593
1594 PDEBUG("executed. idx=0\n");
1595
1596 if (flags) {
1597 PERROR("Invalid flag specified.\n");
1598 return ME_ERRNO_INVALID_FLAGS;
1599 }
1600
1601 if (time_out < 0) {
1602 PERROR("Invalid time_out specified.\n");
1603 return ME_ERRNO_INVALID_TIMEOUT;
1604 }
1605
1606 if (time_out) {
1607 t = (time_out * HZ) / 1000;
1608
1609 if (t == 0)
1610 t = 1;
1611 } else { // Max time.
1612 t = LONG_MAX;
1613 }
1614
1615 instance = (me4600_ai_subdevice_t *) subdevice;
1616
1617 ME_SUBDEVICE_ENTER;
1618
1619 j = jiffies;
1620
1621 while (1) {
1622 // Only runing device can generate break.
1623 head = instance->circ_buf.head;
1624 wait_event_interruptible_timeout(instance->wait_queue,
1625 ((head !=
1626 instance->circ_buf.head)
1627 ||
1628 ((instance->status <=
1629 ai_status_stream_run_wait)
1630 && (instance->status >=
1631 ai_status_stream_end_wait))),
1632 t);
1633
1634 if (head != instance->circ_buf.head) { // New data in buffer.
1635 break;
1636 } else if (instance->status == ai_status_stream_end) { // End of work.
1637 break;
1638 } else if (instance->status == ai_status_stream_fifo_error) {
1639 err = ME_ERRNO_FIFO_BUFFER_OVERFLOW;
1640 break;
1641 } else if (instance->status == ai_status_stream_buffer_error) {
1642 err = ME_ERRNO_RING_BUFFER_OVERFLOW;
1643 break;
1644 } else if (instance->status == ai_status_stream_error) {
1645 err = ME_ERRNO_INTERNAL;
1646 break;
1647 } else if ((jiffies - j) >= t) {
1648 PERROR("Wait on values timed out.\n");
1649 err = ME_ERRNO_TIMEOUT;
1650 break;
1651 } else if (signal_pending(current)) {
1652 PERROR("Wait on values interrupted from signal.\n");
1653 err = ME_ERRNO_SIGNAL;
1654 break;
1655 }
1656 // Correct timeout.
1657 t -= jiffies - j;
1658 }
1659
1660 *count = me_circ_buf_values(&instance->circ_buf);
1661
1662 ME_SUBDEVICE_EXIT;
1663
1664 return err;
1665 }
1666
1667 static inline int me4600_ai_io_stream_read_get_value(me4600_ai_subdevice_t *
1668 instance, int *values,
1669 const int count,
1670 const int flags)
1671 {
1672 int n;
1673 int i;
1674 uint32_t value;
1675
1676 ///Checking how many datas can be copied.
1677 n = me_circ_buf_values(&instance->circ_buf);
1678 if (n <= 0)
1679 return 0;
1680
1681 if (n > count)
1682 n = count;
1683
1684 if (flags & ME_IO_STREAM_READ_FRAMES) {
1685 if (n < instance->chan_list_len) //Not enough data!
1686 return 0;
1687 n -= n % instance->chan_list_len;
1688 }
1689
1690 for (i = 0; i < n; i++) {
1691 value = *(instance->circ_buf.buf + instance->circ_buf.tail);
1692 if (put_user(value, values + i)) {
1693 PERROR("Cannot copy new values to user.\n");
1694 return -ME_ERRNO_INTERNAL;
1695 }
1696 instance->circ_buf.tail++;
1697 instance->circ_buf.tail &= instance->circ_buf.mask;
1698 }
1699 return n;
1700 }
1701
1702 static int me4600_ai_io_stream_read(me_subdevice_t *subdevice,
1703 struct file *filep,
1704 int read_mode,
1705 int *values, int *count, int flags)
1706 {
1707 me4600_ai_subdevice_t *instance;
1708 int err = ME_ERRNO_SUCCESS;
1709 int ret;
1710
1711 int c = *count;
1712 int min = c;
1713
1714 PDEBUG("executed. idx=0\n");
1715
1716 if (flags & ~ME_IO_STREAM_READ_FRAMES) {
1717 PERROR("Invalid flag specified.\n");
1718 return ME_ERRNO_INVALID_FLAGS;
1719 }
1720
1721 if (!values || !count) {
1722 PERROR("Request has invalid pointer.\n");
1723 return ME_ERRNO_INVALID_POINTER;
1724 }
1725
1726 if (c < 0) {
1727 PERROR("Request has invalid value's counter.\n");
1728 return ME_ERRNO_INVALID_VALUE_COUNT;
1729 }
1730
1731 if ((read_mode != ME_READ_MODE_BLOCKING)
1732 && (read_mode != ME_READ_MODE_NONBLOCKING)) {
1733 PERROR("Invalid read mode specified.\n");
1734 return ME_ERRNO_INVALID_READ_MODE;
1735 }
1736
1737 if (c == 0) { //You get what you want! Nothing more or less.
1738 return ME_ERRNO_SUCCESS;
1739 }
1740
1741 instance = (me4600_ai_subdevice_t *) subdevice;
1742 ME_SUBDEVICE_ENTER;
1743
1744 //Check if subdevice is configured.
1745 if (instance->chan_list_len <= 0) {
1746 PERROR("Subdevice wasn't configured.\n");
1747 ME_SUBDEVICE_EXIT;
1748 return ME_ERRNO_PREVIOUS_CONFIG;
1749 }
1750
1751 if (flags & ME_IO_STREAM_READ_FRAMES) {
1752 if (c < instance->chan_list_len) { //Not enough data requested.
1753 PERROR
1754 ("When using FRAME_READ mode minimal size is defined by channel list.\n");
1755 ME_SUBDEVICE_EXIT;
1756 return ME_ERRNO_INVALID_VALUE_COUNT;
1757 }
1758 }
1759
1760 if (c > (ME4600_AI_CIRC_BUF_COUNT - instance->chan_list_len)) { // To return acceptable amount of data when user pass too big value.
1761 min = ME4600_AI_CIRC_BUF_COUNT - instance->chan_list_len;
1762 }
1763
1764 if (flags & ME_IO_STREAM_READ_FRAMES) {
1765 //Wait for whole list.
1766 if (read_mode == ME_READ_MODE_BLOCKING) {
1767 min = c - (c % instance->chan_list_len);
1768 }
1769
1770 if (read_mode == ME_READ_MODE_NONBLOCKING) {
1771 min = instance->chan_list_len;
1772 }
1773 }
1774
1775 if ((inl(instance->status_reg) & ME4600_AI_STATUS_BIT_FSM)) { //Working
1776 //If blocking mode -> wait for data.
1777 if ((me_circ_buf_values(&instance->circ_buf) < min)
1778 && (read_mode == ME_READ_MODE_BLOCKING)) {
1779 wait_event_interruptible(instance->wait_queue,
1780 ((me_circ_buf_values
1781 (&instance->circ_buf) >= min)
1782 || !(inl(instance->status_reg)
1783 &
1784 ME4600_AI_STATUS_BIT_FSM)));
1785
1786 if (signal_pending(current)) {
1787 PERROR
1788 ("Wait on values interrupted from signal.\n");
1789 err = ME_ERRNO_SIGNAL;
1790 }
1791 }
1792 }
1793
1794 ret = me4600_ai_io_stream_read_get_value(instance, values, c, flags);
1795 if (ret < 0) {
1796 err = -ret;
1797 *count = 0;
1798 } else if (ret == 0) {
1799 *count = 0;
1800 if (instance->status == ai_status_stream_fifo_error) {
1801 err = ME_ERRNO_FIFO_BUFFER_OVERFLOW;
1802 instance->status = ai_status_stream_end;
1803 } else if (instance->status == ai_status_stream_buffer_error) {
1804 err = ME_ERRNO_RING_BUFFER_OVERFLOW;
1805 instance->status = ai_status_stream_end;
1806 } else if (instance->status == ai_status_stream_end) {
1807 err = ME_ERRNO_SUBDEVICE_NOT_RUNNING;
1808 } else if (instance->status == ai_status_stream_error) {
1809 err = ME_ERRNO_INTERNAL;
1810 } else if (instance->status == ai_status_none) {
1811 PDEBUG("Stream canceled.\n");
1812 err = ME_ERRNO_INTERNAL;
1813 }
1814 } else {
1815 *count = ret;
1816 }
1817
1818 ME_SUBDEVICE_EXIT;
1819
1820 return err;
1821 }
1822
1823 /** @brief Stop aqusation. Preserve FIFOs.
1824 *
1825 * @param instance The subdevice instance (pointer).
1826 */
1827
1828 static int ai_stop_immediately(me4600_ai_subdevice_t *instance)
1829 {
1830 unsigned long cpu_flags = 0;
1831 volatile uint32_t ctrl;
1832 const int timeout = HZ / 10; //100ms
1833 int i;
1834
1835 for (i = 0; i <= timeout; i++) {
1836 spin_lock_irqsave(instance->ctrl_reg_lock, cpu_flags);
1837 ctrl = inl(instance->ctrl_reg);
1838 ctrl &= ~ME4600_AI_CTRL_BIT_STOP;
1839 ctrl |=
1840 (ME4600_AI_CTRL_BIT_IMMEDIATE_STOP |
1841 ME4600_AI_CTRL_BIT_HF_IRQ_RESET |
1842 ME4600_AI_CTRL_BIT_SC_IRQ_RESET);
1843 outl(ctrl, instance->ctrl_reg);
1844 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
1845 instance->reg_base,
1846 instance->ctrl_reg - instance->reg_base, ctrl);
1847 spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
1848
1849 if (!(inl(instance->status_reg) & ME4600_AI_STATUS_BIT_FSM)) { // Exit.
1850 break;
1851 }
1852
1853 PINFO("Wait for stop: %d\n", i + 1);
1854 //Still working!
1855 set_current_state(TASK_INTERRUPTIBLE);
1856 schedule_timeout(1);
1857 }
1858
1859 if (i > timeout) {
1860 PERROR_CRITICAL("FSM IS BUSY!\n");
1861 return ME_ERRNO_INTERNAL;
1862 }
1863
1864 return ME_ERRNO_SUCCESS;
1865 }
1866
1867 static int me4600_ai_io_stream_start(me_subdevice_t *subdevice,
1868 struct file *filep,
1869 int start_mode, int time_out, int flags)
1870 {
1871 me4600_ai_subdevice_t *instance;
1872 int err = ME_ERRNO_SUCCESS;
1873 unsigned long cpu_flags = 0;
1874 unsigned long ref;
1875 unsigned long delay = 0;
1876
1877 volatile uint32_t tmp;
1878
1879 PDEBUG("executed. idx=0\n");
1880
1881 instance = (me4600_ai_subdevice_t *) subdevice;
1882
1883 if (flags) {
1884 PERROR("Invalid flag specified.\n");
1885 return ME_ERRNO_INVALID_FLAGS;
1886 }
1887
1888 if ((start_mode != ME_START_MODE_BLOCKING)
1889 && (start_mode != ME_START_MODE_NONBLOCKING)) {
1890 PERROR("Invalid start mode specified.\n");
1891 return ME_ERRNO_INVALID_START_MODE;
1892 }
1893
1894 if (time_out < 0) {
1895 PERROR("Invalid timeout specified.\n");
1896 return ME_ERRNO_INVALID_TIMEOUT;
1897 }
1898
1899 if (time_out) {
1900 delay = (time_out * HZ) / 1000;
1901
1902 if (delay == 0)
1903 delay = 1;
1904 }
1905
1906 ME_SUBDEVICE_ENTER
1907 spin_lock_irqsave(instance->ctrl_reg_lock, cpu_flags);
1908
1909 tmp = inl(instance->ctrl_reg);
1910
1911 if ((tmp & ME4600_AI_STATUS_BIT_FSM)) {
1912 PERROR("Conversion is already running.\n");
1913 spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
1914 err = ME_ERRNO_SUBDEVICE_BUSY;
1915 goto ERROR;
1916 }
1917
1918 if (instance->chan_list_len == 0) { //Not configured!
1919 PERROR("Subdevice is not configured to work in stream mode!\n");
1920 spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
1921 err = ME_ERRNO_PREVIOUS_CONFIG;
1922 goto ERROR;
1923 }
1924
1925 if (!(tmp & (ME4600_AI_CTRL_BIT_MODE_0 | ME4600_AI_CTRL_BIT_MODE_1 | ME4600_AI_CTRL_BIT_MODE_2))) { //Mode 0 = single work => no stream config
1926 PERROR("Subdevice is configured to work in single mode.\n");
1927 spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
1928 err = ME_ERRNO_PREVIOUS_CONFIG;
1929 goto ERROR;
1930 }
1931 //Reset stop bits.
1932 tmp |= ME4600_AI_CTRL_BIT_IMMEDIATE_STOP | ME4600_AI_CTRL_BIT_STOP;
1933 outl(tmp, instance->ctrl_reg);
1934 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
1935 instance->ctrl_reg - instance->reg_base, tmp);
1936
1937 //Start datas' FIFO.
1938 tmp |= ME4600_AI_CTRL_BIT_DATA_FIFO;
1939 //Free stop bits.
1940 tmp &= ~(ME4600_AI_CTRL_BIT_IMMEDIATE_STOP | ME4600_AI_CTRL_BIT_STOP);
1941 outl(tmp, instance->ctrl_reg);
1942 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
1943 instance->ctrl_reg - instance->reg_base, tmp);
1944 spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
1945
1946 //Cancel control task
1947 PDEBUG("Cancel control task.\n");
1948 instance->ai_control_task_flag = 0;
1949 cancel_delayed_work(&instance->ai_control_task);
1950
1951 //Set the starting values.
1952 instance->ISM.global_read = 0;
1953 instance->ISM.read = 0;
1954 //Clear circular buffer
1955 instance->circ_buf.head = 0;
1956 instance->circ_buf.tail = 0;
1957
1958 //Set everything.
1959 ai_data_acquisition_logic(instance);
1960
1961 //Set status to 'wait for start'
1962 instance->status = ai_status_stream_run_wait;
1963
1964 // Set control task's timeout
1965 instance->timeout.delay = delay;
1966 instance->timeout.start_time = jiffies;
1967
1968 //Lets go! Start work
1969 inl(instance->start_reg);
1970 PDEBUG_REG("start_reg inl(0x%lX+0x%lX)\n", instance->reg_base,
1971 instance->start_reg - instance->reg_base);
1972
1973 // Schedule control task
1974 instance->ai_control_task_flag = 1;
1975 queue_delayed_work(instance->me4600_workqueue,
1976 &instance->ai_control_task, 1);
1977
1978 PDEVELOP("Delay:%ld\n", delay);
1979
1980 if (start_mode == ME_START_MODE_BLOCKING) { //Wait for start.
1981 ref = jiffies;
1982 //Only runing process will interrupt this call. Events are signaled when status change. Extra timeout add for safe reason.
1983 wait_event_interruptible_timeout(instance->wait_queue,
1984 (instance->status !=
1985 ai_status_stream_run_wait),
1986 (delay) ? delay +
1987 1 : LONG_MAX);
1988
1989 if ((instance->status != ai_status_stream_run)
1990 && (instance->status != ai_status_stream_end)) {
1991 PDEBUG("Starting stream canceled. %d\n",
1992 instance->status);
1993 err = ME_ERRNO_CANCELLED;
1994 }
1995
1996 if (signal_pending(current)) {
1997 PERROR("Wait on start of state machine interrupted.\n");
1998 instance->status = ai_status_none;
1999 ai_stop_isr(instance);
2000 err = ME_ERRNO_SIGNAL;
2001 } else if ((delay) && ((jiffies - ref) > delay)) {
2002 if (instance->status != ai_status_stream_run) {
2003 if (instance->status == ai_status_stream_end) {
2004 PDEBUG("Timeout reached.\n");
2005 } else if ((jiffies - ref) > delay + 1) {
2006 PERROR
2007 ("Timeout reached. Not handled by control task!\n");
2008 ai_stop_isr(instance);
2009 instance->status =
2010 ai_status_stream_error;
2011 } else {
2012 PERROR
2013 ("Timeout reached. Signal come but status is strange: %d\n",
2014 instance->status);
2015 ai_stop_isr(instance);
2016 instance->status =
2017 ai_status_stream_error;
2018 }
2019
2020 instance->ai_control_task_flag = 0;
2021 cancel_delayed_work(&instance->ai_control_task);
2022 err = ME_ERRNO_TIMEOUT;
2023 }
2024 }
2025 }
2026 #ifdef MEDEBUG_INFO
2027 tmp = inl(instance->ctrl_reg);
2028 PDEBUG_REG("ctrl_reg inl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
2029 instance->ctrl_reg - instance->reg_base, tmp);
2030
2031 PINFO("STATUS_BIT_FSM=%s.\n",
2032 (tmp & ME4600_AI_STATUS_BIT_FSM) ? "on" : "off");
2033 PINFO("CTRL_BIT_HF_IRQ=%s.\n",
2034 (tmp & ME4600_AI_CTRL_BIT_HF_IRQ) ? "enable" : "disable");
2035 PINFO("CTRL_BIT_HF_IRQ_RESET=%s.\n",
2036 (tmp & ME4600_AI_CTRL_BIT_HF_IRQ_RESET) ? "reset" : "work");
2037 PINFO("CTRL_BIT_SC_IRQ=%s.\n",
2038 (tmp & ME4600_AI_CTRL_BIT_SC_IRQ) ? "enable" : "disable");
2039 PINFO("CTRL_BIT_SC_RELOAD=%s.\n",
2040 (tmp & ME4600_AI_CTRL_BIT_SC_RELOAD) ? "on" : "off");
2041 PINFO("CTRL_BIT_SC_IRQ_RESET=%s.\n",
2042 (tmp & ME4600_AI_CTRL_BIT_SC_IRQ_RESET) ? "reset" : "work");
2043 #endif
2044
2045 ERROR:
2046 ME_SUBDEVICE_EXIT;
2047
2048 return err;
2049 }
2050
2051 static int me4600_ai_io_stream_status(me_subdevice_t *subdevice,
2052 struct file *filep,
2053 int wait,
2054 int *status, int *values, int flags)
2055 {
2056 me4600_ai_subdevice_t *instance;
2057 int err = ME_ERRNO_SUCCESS;
2058
2059 PDEBUG("executed. idx=0\n");
2060
2061 instance = (me4600_ai_subdevice_t *) subdevice;
2062
2063 if (flags) {
2064 PERROR("Invalid flag specified.\n");
2065 return ME_ERRNO_INVALID_FLAGS;
2066 }
2067
2068 ME_SUBDEVICE_ENTER;
2069
2070 switch (instance->status) {
2071 case ai_status_single_configured:
2072 case ai_status_stream_configured:
2073 case ai_status_stream_end:
2074 case ai_status_stream_fifo_error:
2075 case ai_status_stream_buffer_error:
2076 case ai_status_stream_error:
2077 *status = ME_STATUS_IDLE;
2078 break;
2079
2080 case ai_status_stream_run_wait:
2081 case ai_status_stream_run:
2082 case ai_status_stream_end_wait:
2083 *status = ME_STATUS_BUSY;
2084 break;
2085
2086 case ai_status_none:
2087 default:
2088 *status =
2089 (inl(instance->status_reg) & ME4600_AI_STATUS_BIT_FSM) ?
2090 ME_STATUS_BUSY : ME_STATUS_IDLE;
2091 break;
2092 }
2093
2094 if ((wait == ME_WAIT_IDLE) && (*status == ME_STATUS_BUSY)) {
2095 // Only runing process will interrupt this call. Events are signaled when status change. Extra timeout add for safe reason.
2096 wait_event_interruptible_timeout(instance->wait_queue,
2097 ((instance->status !=
2098 ai_status_stream_run_wait)
2099 && (instance->status !=
2100 ai_status_stream_run)
2101 && (instance->status !=
2102 ai_status_stream_end_wait)),
2103 LONG_MAX);
2104
2105 if (instance->status != ai_status_stream_end) {
2106 PDEBUG("Wait for IDLE canceled. %d\n",
2107 instance->status);
2108 err = ME_ERRNO_CANCELLED;
2109 }
2110
2111 if (signal_pending(current)) {
2112 PERROR("Wait for IDLE interrupted.\n");
2113 instance->status = ai_status_none;
2114 ai_stop_isr(instance);
2115 err = ME_ERRNO_SIGNAL;
2116 }
2117
2118 *status = ME_STATUS_IDLE;
2119 }
2120
2121 *values = me_circ_buf_values(&instance->circ_buf);
2122 PDEBUG("me_circ_buf_values(&instance->circ_buf)=%d.\n", *values);
2123
2124 ME_SUBDEVICE_EXIT;
2125
2126 return err;
2127 }
2128
2129 static int me4600_ai_io_stream_stop(me_subdevice_t *subdevice,
2130 struct file *filep,
2131 int stop_mode, int flags)
2132 {
2133 /**
2134 @note Stop is implemented only in blocking mode.
2135 @note Function return when state machine is stoped.
2136 */
2137 me4600_ai_subdevice_t *instance;
2138 unsigned long cpu_flags;
2139 uint32_t ctrl;
2140 int ret;
2141
2142 PDEBUG("executed. idx=0\n");
2143
2144 if (flags) {
2145 PERROR("Invalid flag specified.\n");
2146 return ME_ERRNO_INVALID_FLAGS;
2147 }
2148
2149 if ((stop_mode != ME_STOP_MODE_IMMEDIATE)
2150 && (stop_mode != ME_STOP_MODE_LAST_VALUE)) {
2151 PERROR("Invalid stop mode specified.\n");
2152 return ME_ERRNO_INVALID_STOP_MODE;
2153 }
2154
2155 instance = (me4600_ai_subdevice_t *) subdevice;
2156
2157 ME_SUBDEVICE_ENTER;
2158
2159 // Mark as stopping. => Software stop.
2160 instance->status = ai_status_stream_end_wait;
2161
2162 if (stop_mode == ME_STOP_MODE_IMMEDIATE) {
2163 ret = ai_stop_immediately(instance);
2164
2165 if (ret) {
2166 PERROR("FSM is still busy.\n");
2167 ME_SUBDEVICE_EXIT;
2168 return ME_ERRNO_SUBDEVICE_BUSY;
2169 }
2170 instance->ai_control_task_flag = 0;
2171
2172 } else if (stop_mode == ME_STOP_MODE_LAST_VALUE) {
2173 // Set stop bit in registry.
2174 spin_lock_irqsave(instance->ctrl_reg_lock, cpu_flags);
2175 ctrl = inl(instance->ctrl_reg);
2176 ctrl |= ME4600_AI_CTRL_BIT_STOP;
2177 outl(ctrl, instance->ctrl_reg);
2178 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
2179 instance->reg_base,
2180 instance->ctrl_reg - instance->reg_base, ctrl);
2181 spin_unlock_irqrestore(instance->ctrl_reg_lock, cpu_flags);
2182
2183 // Only runing process will interrupt this call. Events are signaled when status change.
2184 wait_event_interruptible_timeout(instance->wait_queue,
2185 (instance->status !=
2186 ai_status_stream_end_wait),
2187 LONG_MAX);
2188
2189 if (instance->status != ai_status_stream_end) {
2190 PDEBUG("Stopping stream canceled.\n");
2191 ret = ME_ERRNO_CANCELLED;
2192 }
2193
2194 if (signal_pending(current)) {
2195 PERROR("Stopping stream interrupted.\n");
2196 instance->status = ai_status_none;
2197 ret = ME_ERRNO_SIGNAL;
2198 }
2199 // End of work.
2200 ai_stop_immediately(instance);
2201
2202 }
2203
2204 ret = ai_read_data_pooling(instance);
2205 if (ret > 0) { // Everything fine. More datas put to software buffer.
2206 instance->status = ai_status_stream_end;
2207 ret = ME_ERRNO_SUCCESS;
2208 // Signal that we put last data to software buffer.
2209 wake_up_interruptible_all(&instance->wait_queue);
2210 } else if (ret == 0) { // Everything fine. No more datas in FIFO.
2211 instance->status = ai_status_stream_end;
2212 ret = ME_ERRNO_SUCCESS;
2213 } else if (ret == -ME_ERRNO_RING_BUFFER_OVERFLOW) { // Stop is unsuccessful, buffer is overflow.
2214 instance->status = ai_status_stream_buffer_error;
2215 ret = ME_ERRNO_SUCCESS;
2216 } else { // Stop is unsuccessful
2217 instance->status = ai_status_stream_end;
2218 ret = -ret;
2219 }
2220
2221 ME_SUBDEVICE_EXIT;
2222
2223 return ret;
2224 }
2225
2226 static int me4600_ai_query_range_by_min_max(me_subdevice_t *subdevice,
2227 int unit,
2228 int *min,
2229 int *max, int *maxdata, int *range)
2230 {
2231 me4600_ai_subdevice_t *instance;
2232 int i;
2233 int r = -1;
2234 int diff = 21E6;
2235
2236 PDEBUG("executed. idx=0\n");
2237
2238 instance = (me4600_ai_subdevice_t *) subdevice;
2239
2240 if ((*max - *min) < 0) {
2241 PERROR("Invalid minimum and maximum values specified.\n");
2242 return ME_ERRNO_INVALID_MIN_MAX;
2243 }
2244
2245 if ((unit == ME_UNIT_VOLT) || (unit == ME_UNIT_ANY)) {
2246 for (i = 0; i < instance->ranges_len; i++) {
2247 if ((instance->ranges[i].min <= *min)
2248 && ((instance->ranges[i].max + 1000) >= *max)) {
2249 if ((instance->ranges[i].max -
2250 instance->ranges[i].min) - (*max - *min) <
2251 diff) {
2252 r = i;
2253 diff =
2254 (instance->ranges[i].max -
2255 instance->ranges[i].min) - (*max -
2256 *min);
2257 }
2258 }
2259 }
2260
2261 if (r < 0) {
2262 PERROR("No matching range found.\n");
2263 return ME_ERRNO_NO_RANGE;
2264 } else {
2265 *min = instance->ranges[r].min;
2266 *max = instance->ranges[r].max;
2267 *maxdata = ME4600_AI_MAX_DATA;
2268 *range = r;
2269 }
2270 } else {
2271 PERROR("Invalid physical unit specified.\n");
2272 return ME_ERRNO_INVALID_UNIT;
2273 }
2274
2275 return ME_ERRNO_SUCCESS;
2276 }
2277
2278 static int me4600_ai_query_number_ranges(me_subdevice_t *subdevice,
2279 int unit, int *count)
2280 {
2281 me4600_ai_subdevice_t *instance;
2282
2283 PDEBUG("executed. idx=0\n");
2284
2285 instance = (me4600_ai_subdevice_t *) subdevice;
2286
2287 if ((unit == ME_UNIT_VOLT) || (unit == ME_UNIT_ANY)) {
2288 *count = instance->ranges_len;
2289 } else {
2290 *count = 0;
2291 }
2292
2293 return ME_ERRNO_SUCCESS;
2294 }
2295
2296 static int me4600_ai_query_range_info(me_subdevice_t *subdevice,
2297 int range,
2298 int *unit,
2299 int *min, int *max, int *maxdata)
2300 {
2301 me4600_ai_subdevice_t *instance;
2302
2303 PDEBUG("executed. idx=0\n");
2304
2305 instance = (me4600_ai_subdevice_t *) subdevice;
2306
2307 if ((range < instance->ranges_len) && (range >= 0)) {
2308 *unit = ME_UNIT_VOLT;
2309 *min = instance->ranges[range].min;
2310 *max = instance->ranges[range].max;
2311 *maxdata = ME4600_AI_MAX_DATA;
2312 } else {
2313 PERROR("Invalid range number specified.\n");
2314 return ME_ERRNO_INVALID_RANGE;
2315 }
2316
2317 return ME_ERRNO_SUCCESS;
2318 }
2319
2320 static int me4600_ai_query_timer(me_subdevice_t *subdevice,
2321 int timer,
2322 int *base_frequency,
2323 long long *min_ticks, long long *max_ticks)
2324 {
2325 me4600_ai_subdevice_t *instance;
2326
2327 PDEBUG("executed. idx=0\n");
2328
2329 instance = (me4600_ai_subdevice_t *) subdevice;
2330
2331 switch (timer) {
2332
2333 case ME_TIMER_ACQ_START:
2334 *base_frequency = ME4600_AI_BASE_FREQUENCY;
2335 *min_ticks = ME4600_AI_MIN_ACQ_TICKS;
2336 *max_ticks = ME4600_AI_MAX_ACQ_TICKS;
2337 break;
2338
2339 case ME_TIMER_SCAN_START:
2340 *base_frequency = ME4600_AI_BASE_FREQUENCY;
2341 *min_ticks = ME4600_AI_MIN_SCAN_TICKS;
2342 *max_ticks = ME4600_AI_MAX_SCAN_TICKS;
2343 break;
2344
2345 case ME_TIMER_CONV_START:
2346 *base_frequency = ME4600_AI_BASE_FREQUENCY;
2347 *min_ticks = ME4600_AI_MIN_CHAN_TICKS;
2348 *max_ticks = ME4600_AI_MAX_CHAN_TICKS;
2349 break;
2350
2351 default:
2352 PERROR("Invalid timer specified.(0x%04x)\n", timer);
2353
2354 return ME_ERRNO_INVALID_TIMER;
2355 }
2356
2357 return ME_ERRNO_SUCCESS;
2358 }
2359
2360 static int me4600_ai_query_number_channels(me_subdevice_t *subdevice,
2361 int *number)
2362 {
2363 me4600_ai_subdevice_t *instance;
2364
2365 PDEBUG("executed. idx=0\n");
2366
2367 instance = (me4600_ai_subdevice_t *) subdevice;
2368 *number = instance->channels;
2369
2370 return ME_ERRNO_SUCCESS;
2371 }
2372
2373 static int me4600_ai_query_subdevice_type(me_subdevice_t *subdevice,
2374 int *type, int *subtype)
2375 {
2376 PDEBUG("executed. idx=0\n");
2377
2378 *type = ME_TYPE_AI;
2379 *subtype = ME_SUBTYPE_STREAMING;
2380
2381 return ME_ERRNO_SUCCESS;
2382 }
2383
2384 static int me4600_ai_query_subdevice_caps(me_subdevice_t *subdevice, int *caps)
2385 {
2386 PDEBUG("executed. idx=0\n");
2387
2388 *caps =
2389 ME_CAPS_AI_TRIG_SYNCHRONOUS | ME_CAPS_AI_FIFO |
2390 ME_CAPS_AI_FIFO_THRESHOLD;
2391
2392 return ME_ERRNO_SUCCESS;
2393 }
2394
2395 static int me4600_ai_query_subdevice_caps_args(struct me_subdevice *subdevice,
2396 int cap, int *args, int count)
2397 {
2398 me4600_ai_subdevice_t *instance;
2399 int err = ME_ERRNO_SUCCESS;
2400
2401 instance = (me4600_ai_subdevice_t *) subdevice;
2402
2403 PDEBUG("executed. idx=0\n");
2404
2405 if (count != 1) {
2406 PERROR("Invalid capability argument count.\n");
2407 return ME_ERRNO_INVALID_CAP_ARG_COUNT;
2408 }
2409
2410 switch (cap) {
2411 case ME_CAP_AI_FIFO_SIZE:
2412 args[0] = ME4600_AI_FIFO_COUNT;
2413 break;
2414
2415 case ME_CAP_AI_BUFFER_SIZE:
2416 args[0] =
2417 (instance->circ_buf.buf) ? ME4600_AI_CIRC_BUF_COUNT : 0;
2418 break;
2419
2420 default:
2421 PERROR("Invalid capability.\n");
2422 err = ME_ERRNO_INVALID_CAP;
2423 args[0] = 0;
2424 }
2425
2426 return err;
2427 }
2428
2429 void ai_limited_isr(me4600_ai_subdevice_t *instance, const uint32_t irq_status,
2430 const uint32_t ctrl_status)
2431 {
2432 int to_read;
2433
2434 if (!instance->fifo_irq_threshold) { //No threshold provided. SC ends work. HF need reseting.
2435 if (irq_status & ME4600_IRQ_STATUS_BIT_SC) {
2436 if (ai_read_data(instance, instance->ISM.next) != instance->ISM.next) { //ERROR!
2437 PERROR
2438 ("Limited amounts aqusition with TH=0: Circular buffer full!\n");
2439 instance->status =
2440 ai_status_stream_buffer_error;
2441 } else {
2442 instance->status = ai_status_stream_end;
2443 }
2444 //End of work.
2445 ai_stop_isr(instance);
2446 } else if (irq_status & ME4600_IRQ_STATUS_BIT_AI_HF) {
2447 instance->ISM.global_read += ME4600_AI_FIFO_HALF;
2448
2449 if (ai_read_data(instance, ME4600_AI_FIFO_HALF) != ME4600_AI_FIFO_HALF) { //ERROR!
2450 PERROR
2451 ("Limited amounts aqusition with TH = 0: Circular buffer full!\n");
2452 //End of work.
2453 ai_stop_isr(instance);
2454 instance->status =
2455 ai_status_stream_buffer_error;
2456 } else {
2457 //Continue.
2458 ai_limited_ISM(instance, irq_status);
2459 }
2460 }
2461 //Signal user.
2462 wake_up_interruptible_all(&instance->wait_queue);
2463 } else //if(instance->fifo_irq_threshold)
2464 {
2465 if (irq_status & ME4600_IRQ_STATUS_BIT_SC) {
2466 instance->ISM.read = 0;
2467 if ((instance->fifo_irq_threshold < ME4600_AI_FIFO_HALF)
2468 && (!(ctrl_status & ME4600_AI_STATUS_BIT_HF_DATA)))
2469 {
2470 to_read =
2471 ME4600_AI_FIFO_HALF -
2472 (ME4600_AI_FIFO_HALF %
2473 instance->fifo_irq_threshold);
2474 PDEBUG
2475 ("Limited amounts aqusition with TH != 0: Not fast enough data aqusition! correction=%d\n",
2476 to_read);
2477 } else {
2478 to_read = instance->ISM.next;
2479 }
2480 instance->ISM.global_read += to_read;
2481
2482 ai_reschedule_SC(instance);
2483
2484 if (ai_read_data(instance, to_read) != to_read) { //ERROR!
2485 PERROR
2486 ("Limited amounts aqusition with TH != 0: Circular buffer full!\n");
2487 //End of work.
2488 ai_stop_isr(instance);
2489 instance->status =
2490 ai_status_stream_buffer_error;
2491 } else {
2492 //Continue.
2493 ai_limited_ISM(instance, irq_status);
2494 }
2495
2496 //Signal user.
2497 wake_up_interruptible_all(&instance->wait_queue);
2498 } else if (irq_status & ME4600_IRQ_STATUS_BIT_AI_HF) {
2499 instance->ISM.read += ME4600_AI_FIFO_HALF;
2500 instance->ISM.global_read += ME4600_AI_FIFO_HALF;
2501
2502 if (ai_read_data(instance, ME4600_AI_FIFO_HALF) != ME4600_AI_FIFO_HALF) { //ERROR!
2503 PERROR
2504 ("Limited amounts aqusition with TH != 0: Circular buffer full!\n");
2505 ai_stop_isr(instance);
2506
2507 instance->status =
2508 ai_status_stream_buffer_error;
2509 //Signal user.
2510 wake_up_interruptible_all(&instance->
2511 wait_queue);
2512 } else {
2513 //Countinue.
2514 ai_limited_ISM(instance, irq_status);
2515 }
2516 }
2517
2518 if (instance->ISM.global_read >= instance->data_required) { //End of work. Next paranoid pice of code: '>=' instead od '==' only to be sure.
2519 ai_stop_isr(instance);
2520 if (instance->status < ai_status_stream_end) {
2521 instance->status = ai_status_stream_end;
2522 }
2523 #ifdef MEDEBUG_ERROR
2524 if (instance->ISM.global_read > instance->data_required) { //This is security check case. This should never ever happend!
2525 PERROR
2526 ("Limited amounts aqusition: Read more data than necessary! data_required=%d < read=%d\n",
2527 instance->data_required,
2528 instance->ISM.global_read);
2529 //Signal error (warning??).
2530 instance->status = ai_status_stream_error;
2531 }
2532 #endif
2533 }
2534 }
2535 }
2536
2537 void ai_infinite_isr(me4600_ai_subdevice_t *instance,
2538 const uint32_t irq_status, const uint32_t ctrl_status)
2539 {
2540 int to_read;
2541
2542 if (irq_status & ME4600_IRQ_STATUS_BIT_SC) { //next chunck of data -> read fifo
2543 //Set new state in ISM.
2544 if ((instance->fifo_irq_threshold < ME4600_AI_FIFO_HALF) && (!(ctrl_status & ME4600_AI_STATUS_BIT_HF_DATA))) { //There is more data than we ecpected. Propably we aren't fast enough. Read as many as possible.
2545 if (instance->fifo_irq_threshold) {
2546 to_read =
2547 ME4600_AI_FIFO_HALF -
2548 (ME4600_AI_FIFO_HALF %
2549 instance->fifo_irq_threshold);
2550 if (to_read > instance->fifo_irq_threshold) {
2551 PDEBUG
2552 ("Infinite aqusition: Not fast enough data aqusition! TH != 0: correction=%d\n",
2553 to_read);
2554 }
2555 } else { //No threshold specified.
2556 to_read = ME4600_AI_FIFO_HALF;
2557 }
2558 } else {
2559 to_read = instance->ISM.next;
2560 }
2561
2562 instance->ISM.read += to_read;
2563
2564 //Get data
2565 if (ai_read_data(instance, to_read) != to_read) { //ERROR!
2566 PERROR("Infinite aqusition: Circular buffer full!\n");
2567 ai_stop_isr(instance);
2568 instance->status = ai_status_stream_buffer_error;
2569 } else {
2570 ai_infinite_ISM(instance);
2571 instance->ISM.global_read += instance->ISM.read;
2572 instance->ISM.read = 0;
2573 }
2574
2575 //Signal data to user
2576 wake_up_interruptible_all(&instance->wait_queue);
2577 } else if (irq_status & ME4600_IRQ_STATUS_BIT_AI_HF) { //fifo is half full -> read fifo Large blocks only!
2578 instance->ISM.read += ME4600_AI_FIFO_HALF;
2579
2580 if (ai_read_data(instance, ME4600_AI_FIFO_HALF) != ME4600_AI_FIFO_HALF) { //ERROR!
2581 PERROR("Infinite aqusition: Circular buffer full!\n");
2582 ai_stop_isr(instance);
2583 instance->status = ai_status_stream_buffer_error;
2584
2585 //Signal it.
2586 wake_up_interruptible_all(&instance->wait_queue);
2587 } else {
2588 ai_infinite_ISM(instance);
2589 }
2590 }
2591 }
2592
2593 static irqreturn_t me4600_ai_isr(int irq, void *dev_id)
2594 { /// @note This is time critical function!
2595 uint32_t irq_status;
2596 uint32_t ctrl_status;
2597 me4600_ai_subdevice_t *instance = dev_id;
2598 //int to_read;
2599
2600 PDEBUG("executed. idx=0\n");
2601
2602 if (irq != instance->irq) {
2603 PERROR("Incorrect interrupt num: %d.\n", irq);
2604 return IRQ_NONE;
2605 }
2606
2607 irq_status = inl(instance->irq_status_reg);
2608 if (!
2609 (irq_status &
2610 (ME4600_IRQ_STATUS_BIT_AI_HF | ME4600_IRQ_STATUS_BIT_SC))) {
2611 #ifdef MEDEBUG_INFO
2612 if ((irq_status & (ME4600_IRQ_STATUS_BIT_AI_HF | ME4600_IRQ_STATUS_BIT_SC | ME4600_IRQ_STATUS_BIT_LE)) == ME4600_IRQ_STATUS_BIT_LE) { //This is security check case. LE is unused. This should never ever happend.
2613 PINFO
2614 ("%ld Shared interrupt. %s(): irq_status_reg=LE_IRQ\n",
2615 jiffies, __func__);
2616 } else {
2617 PINFO
2618 ("%ld Shared interrupt. %s(): irq_status_reg=0x%04X\n",
2619 jiffies, __func__, irq_status);
2620 }
2621 #endif
2622 return IRQ_NONE;
2623 }
2624
2625 if (!instance->circ_buf.buf) { //Security check.
2626 PERROR_CRITICAL("CIRCULAR BUFFER NOT EXISTS!\n");
2627 ai_stop_isr(instance);
2628 return IRQ_HANDLED;
2629 }
2630 //Get the status register.
2631 ctrl_status = inl(instance->status_reg);
2632
2633 #ifdef MEDEBUG_INFO
2634 if (irq_status & ME4600_IRQ_STATUS_BIT_AI_HF)
2635 PINFO("HF interrupt active\n");
2636 if (irq_status & ME4600_IRQ_STATUS_BIT_SC)
2637 PINFO("SC interrupt active\n");
2638 if (irq_status & ME4600_IRQ_STATUS_BIT_LE)
2639 PINFO("LE interrupt active\n");
2640 #endif
2641
2642 //This is safety check!
2643 if ((irq_status & ME4600_IRQ_STATUS_BIT_AI_HF)
2644 && (ctrl_status & ME4600_AI_STATUS_BIT_HF_DATA)) {
2645 PDEBUG("HF interrupt active but FIFO under half\n");
2646 //Reset HF interrupt latch.
2647 spin_lock(instance->ctrl_reg_lock);
2648 outl(ctrl_status | ME4600_AI_CTRL_BIT_HF_IRQ_RESET,
2649 instance->ctrl_reg);
2650 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
2651 instance->reg_base,
2652 instance->ctrl_reg - instance->reg_base,
2653 ctrl_status);
2654 outl(ctrl_status, instance->ctrl_reg);
2655 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
2656 instance->reg_base,
2657 instance->ctrl_reg - instance->reg_base,
2658 ctrl_status);
2659 spin_unlock(instance->ctrl_reg_lock);
2660 return IRQ_HANDLED;
2661 }
2662 #ifdef MEDEBUG_INFO
2663 PINFO("STATUS_BIT_FSM=%s.\n",
2664 (ctrl_status & ME4600_AI_STATUS_BIT_FSM) ? "on" : "off");
2665
2666 PINFO("STATUS_BIT_EF_CHANNEL=%s.\n",
2667 (ctrl_status & ME4600_AI_STATUS_BIT_EF_CHANNEL) ? "not empty" :
2668 "empty");
2669 PINFO("STATUS_BIT_HF_CHANNEL=%s.\n",
2670 (ctrl_status & ME4600_AI_STATUS_BIT_HF_CHANNEL) ? " < HF" :
2671 " > HF");
2672 PINFO("STATUS_BIT_FF_CHANNEL=%s.\n",
2673 (ctrl_status & ME4600_AI_STATUS_BIT_FF_CHANNEL) ? "not full" :
2674 "full");
2675
2676 PINFO("STATUS_BIT_EF_DATA=%s.\n",
2677 (ctrl_status & ME4600_AI_STATUS_BIT_EF_DATA) ? "not empty" :
2678 "empty");
2679 PINFO("STATUS_BIT_HF_DATA=%s.\n",
2680 (ctrl_status & ME4600_AI_STATUS_BIT_HF_DATA) ? " < HF" : " > HF");
2681 PINFO("STATUS_BIT_FF_DATA=%s.\n",
2682 (ctrl_status & ME4600_AI_STATUS_BIT_FF_DATA) ? "not full" :
2683 "full");
2684
2685 PINFO("CTRL_BIT_HF_IRQ=%s.\n",
2686 (ctrl_status & ME4600_AI_CTRL_BIT_HF_IRQ) ? "enable" : "disable");
2687 PINFO("CTRL_BIT_HF_IRQ_RESET=%s.\n",
2688 (ctrl_status & ME4600_AI_CTRL_BIT_HF_IRQ_RESET) ? "reset" :
2689 "work");
2690 PINFO("CTRL_BIT_SC_IRQ=%s.\n",
2691 (ctrl_status & ME4600_AI_CTRL_BIT_SC_IRQ) ? "enable" : "disable");
2692 PINFO("CTRL_BIT_SC_RELOAD=%s.\n",
2693 (ctrl_status & ME4600_AI_CTRL_BIT_SC_RELOAD) ? "on" : "off");
2694 PINFO("CTRL_BIT_SC_IRQ_RESET=%s.\n",
2695 (ctrl_status & ME4600_AI_CTRL_BIT_SC_IRQ_RESET) ? "reset" :
2696 "work");
2697 #endif
2698
2699 //Look for overflow error.
2700 if (!(ctrl_status & ME4600_AI_STATUS_BIT_FF_DATA)) {
2701 //FIFO is full. Read datas and reset all settings.
2702 PERROR("FIFO overflow.\n");
2703 ai_read_data(instance, ME4600_AI_FIFO_COUNT);
2704 ai_stop_isr(instance);
2705
2706 instance->status = ai_status_stream_fifo_error;
2707 //Signal it.
2708 wake_up_interruptible_all(&instance->wait_queue);
2709
2710 return IRQ_HANDLED;
2711 }
2712
2713 if (!instance->data_required) { //This is infinite aqusition.
2714 #ifdef MEDEBUG_ERROR
2715 if ((irq_status &
2716 (ME4600_IRQ_STATUS_BIT_AI_HF | ME4600_IRQ_STATUS_BIT_SC))
2717 ==
2718 (ME4600_IRQ_STATUS_BIT_AI_HF | ME4600_IRQ_STATUS_BIT_SC)) {
2719 ///In infinite mode only one interrupt source should be reported!
2720 PERROR
2721 ("Error in ISM! Infinite aqusition: HF and SC interrupts active! threshold=%d next=%d ctrl=0x%04X irq_status_reg=0x%04X",
2722 instance->fifo_irq_threshold, instance->ISM.next,
2723 ctrl_status, irq_status);
2724 }
2725 #endif
2726
2727 ai_infinite_isr(instance, irq_status, ctrl_status);
2728
2729 #ifdef MEDEBUG_INFO
2730 ctrl_status = inl(instance->ctrl_reg);
2731 #endif
2732 } else {
2733
2734 ai_limited_isr(instance, irq_status, ctrl_status);
2735 ctrl_status = inl(instance->status_reg);
2736 if (!(ctrl_status & (ME4600_AI_STATUS_BIT_HF_DATA | ME4600_AI_CTRL_BIT_HF_IRQ_RESET))) { //HF active, but we have more than half already => HF will never come
2737 PDEBUG
2738 ("MISSED HF. data_required=%d ISM.read=%d ISM.global=%d ISM.next=%d\n",
2739 instance->data_required, instance->ISM.read,
2740 instance->ISM.global_read, instance->ISM.next);
2741 ai_limited_isr(instance, ME4600_IRQ_STATUS_BIT_AI_HF,
2742 ctrl_status);
2743 }
2744 }
2745
2746 #ifdef MEDEBUG_INFO
2747 PINFO("STATUS_BIT_FSM=%s.\n",
2748 (ctrl_status & ME4600_AI_STATUS_BIT_FSM) ? "on" : "off");
2749
2750 PINFO("STATUS_BIT_EF_CHANNEL=%s.\n",
2751 (ctrl_status & ME4600_AI_STATUS_BIT_EF_CHANNEL) ? "not empty" :
2752 "empty");
2753 PINFO("STATUS_BIT_HF_CHANNEL=%s.\n",
2754 (ctrl_status & ME4600_AI_STATUS_BIT_HF_CHANNEL) ? " < HF" :
2755 " > HF");
2756 PINFO("STATUS_BIT_FF_CHANNEL=%s.\n",
2757 (ctrl_status & ME4600_AI_STATUS_BIT_FF_CHANNEL) ? "not full" :
2758 "full");
2759
2760 PINFO("STATUS_BIT_EF_DATA=%s.\n",
2761 (ctrl_status & ME4600_AI_STATUS_BIT_EF_DATA) ? "not empty" :
2762 "empty");
2763 PINFO("STATUS_BIT_HF_DATA=%s.\n",
2764 (ctrl_status & ME4600_AI_STATUS_BIT_HF_DATA) ? " < HF" : " > HF");
2765 PINFO("STATUS_BIT_FF_DATA=%s.\n",
2766 (ctrl_status & ME4600_AI_STATUS_BIT_FF_DATA) ? "not full" :
2767 "full");
2768
2769 PINFO("CTRL_BIT_HF_IRQ_RESET=%s.\n",
2770 (ctrl_status & ME4600_AI_CTRL_BIT_HF_IRQ_RESET) ? "reset" :
2771 "work");
2772 PINFO("CTRL_BIT_SC_IRQ=%s.\n",
2773 (ctrl_status & ME4600_AI_CTRL_BIT_SC_IRQ) ? "enable" : "disable");
2774 PINFO("CTRL_BIT_SC_RELOAD=%s.\n",
2775 (ctrl_status & ME4600_AI_CTRL_BIT_SC_RELOAD) ? "on" : "off");
2776 PINFO("CTRL_BIT_SC_IRQ_RESET=%s.\n",
2777 (ctrl_status & ME4600_AI_CTRL_BIT_SC_IRQ_RESET) ? "reset" :
2778 "work");
2779 PINFO("%ld END\n", jiffies);
2780 #endif
2781
2782 return IRQ_HANDLED;
2783 }
2784
2785 /** @brief Stop aqusation of data. Reset interrupts' laches. Clear data's FIFO.
2786 *
2787 * @param instance The subdevice instance (pointer).
2788 */
2789 inline void ai_stop_isr(me4600_ai_subdevice_t *instance)
2790 { /// @note This is soft time critical function!
2791 register uint32_t tmp;
2792
2793 spin_lock(instance->ctrl_reg_lock);
2794 //Stop all. Reset interrupt laches. Reset data FIFO.
2795 tmp = inl(instance->ctrl_reg);
2796 tmp |=
2797 (ME4600_AI_CTRL_BIT_IMMEDIATE_STOP | ME4600_AI_CTRL_BIT_HF_IRQ_RESET
2798 | ME4600_AI_CTRL_BIT_LE_IRQ_RESET |
2799 ME4600_AI_CTRL_BIT_SC_IRQ_RESET);
2800 tmp &= ~ME4600_AI_CTRL_BIT_DATA_FIFO;
2801 outl(tmp, instance->ctrl_reg);
2802 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
2803 instance->ctrl_reg - instance->reg_base, tmp);
2804 spin_unlock(instance->ctrl_reg_lock);
2805 }
2806
2807 /** @brief Copy data from fifo to circular buffer.
2808 *
2809 * @param instance The subdevice instance (pointer).
2810 * @param count The number of requested data.
2811 *
2812 * @return On success: Number of copied values.
2813 * @return On error: -ME_ERRNO_RING_BUFFER_OVERFLOW.
2814 */
2815 static inline int ai_read_data(me4600_ai_subdevice_t *instance,
2816 const int count)
2817 { /// @note This is time critical function!
2818 int c = count;
2819 int empty_space;
2820 int copied = 0;
2821 int i, j;
2822
2823 empty_space = me_circ_buf_space_to_end(&instance->circ_buf);
2824 if (empty_space <= 0) {
2825 PDEBUG("Circular buffer full.\n");
2826 return -ME_ERRNO_RING_BUFFER_OVERFLOW;
2827 }
2828
2829 if (empty_space < c) { //Copy first part. Max to end of buffer.
2830 PDEBUG
2831 ("Try to copy %d values from FIFO to circular buffer (pass 1).\n",
2832 empty_space);
2833 for (i = 0; i < empty_space; i++) {
2834 *(instance->circ_buf.buf + instance->circ_buf.head) =
2835 (inw(instance->data_reg) ^ 0x8000);
2836 instance->circ_buf.head++;
2837 }
2838 instance->circ_buf.head &= instance->circ_buf.mask;
2839 c -= empty_space;
2840 copied = empty_space;
2841
2842 empty_space = me_circ_buf_space_to_end(&instance->circ_buf);
2843 }
2844
2845 if (empty_space > 0) {
2846 j = (empty_space < c) ? empty_space : c;
2847 PDEBUG
2848 ("Try to copy %d values from FIFO to circular buffer (pass 2).\n",
2849 c);
2850 for (i = 0; i < j; i++) {
2851 *(instance->circ_buf.buf + instance->circ_buf.head) =
2852 (inw(instance->data_reg) ^ 0x8000);
2853 instance->circ_buf.head++;
2854 }
2855 instance->circ_buf.head &= instance->circ_buf.mask;
2856 copied += j;
2857 }
2858 return copied;
2859 }
2860
2861 inline void ai_infinite_ISM(me4600_ai_subdevice_t *instance)
2862 { /// @note This is time critical function!
2863 register volatile uint32_t ctrl_set, ctrl_reset, tmp;
2864
2865 if (instance->fifo_irq_threshold < ME4600_AI_FIFO_MAX_SC) { // Only sample counter with reloadnig is working. Reset it.
2866 PINFO
2867 ("Only sample counter with reloadnig is working. Reset it.\n");
2868 ctrl_set = ME4600_AI_CTRL_BIT_SC_IRQ_RESET;
2869 ctrl_reset = ~ME4600_AI_CTRL_BIT_SC_IRQ_RESET;
2870 } else if (instance->fifo_irq_threshold == instance->ISM.read) { //This is SC interrupt for large block. The whole section is done. Reset SC_IRQ an HF_IRQ and start everything again from beginning.
2871 PINFO
2872 ("This is SC interrupt for large block. The whole section is done. Reset SC_IRQ an HF_IRQ and start everything again from beginning.\n");
2873 ctrl_set =
2874 ME4600_AI_CTRL_BIT_SC_IRQ_RESET |
2875 ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2876 ctrl_reset =
2877 ~(ME4600_AI_CTRL_BIT_SC_IRQ_RESET |
2878 ME4600_AI_CTRL_BIT_HF_IRQ_RESET);
2879 } else if (instance->fifo_irq_threshold >= (ME4600_AI_FIFO_MAX_SC + instance->ISM.read)) { //This is HF interrupt for large block.The next interrupt should be from HF, also. Reset HF.
2880 PINFO
2881 ("This is HF interrupt for large block.The next interrupt should be from HF, also. Reset HF.\n");
2882 ctrl_set = ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2883 ctrl_reset = ~ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2884 } else { //This is HF interrupt for large block.The next interrupt should be from SC. Don't reset HF!
2885 PINFO
2886 ("This is HF interrupt for large block.The next interrupt should be from SC. Don't reset HF!\n");
2887 ctrl_set = ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2888 ctrl_reset = 0xFFFFFFFF;
2889 }
2890
2891 //Reset interrupt latch.
2892 spin_lock(instance->ctrl_reg_lock);
2893 tmp = inl(instance->ctrl_reg);
2894 PINFO("ctrl=0x%x ctrl_set=0x%x ctrl_reset=0x%x\n", tmp, ctrl_set,
2895 ctrl_reset);
2896 tmp |= ctrl_set;
2897 outl(tmp, instance->ctrl_reg);
2898 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
2899 instance->ctrl_reg - instance->reg_base, tmp);
2900 if (ctrl_reset != 0xFFFFFFFF) {
2901 outl(tmp & ctrl_reset, instance->ctrl_reg);
2902 PDEBUG_REG("ctrl_reset outl(0x%lX+0x%lX)=0x%x\n",
2903 instance->reg_base,
2904 instance->ctrl_reg - instance->reg_base,
2905 tmp & ctrl_reset);
2906 }
2907 spin_unlock(instance->ctrl_reg_lock);
2908
2909 }
2910
2911 inline void ai_limited_ISM(me4600_ai_subdevice_t *instance,
2912 uint32_t irq_status)
2913 { /// @note This is time critical function!
2914 register volatile uint32_t ctrl_set, ctrl_reset = 0xFFFFFFFF, tmp;
2915
2916 if (!instance->fifo_irq_threshold) { //No threshold provided. SC ends work.
2917 PINFO("No threshold provided. SC ends work.\n");
2918 ctrl_set = ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2919 if (instance->data_required > (ME4600_AI_FIFO_COUNT - 1 + instance->ISM.global_read)) { //HF need reseting.
2920 ctrl_reset &= ~ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2921 }
2922 } else //if(instance->fifo_irq_threshold)
2923 {
2924 if (irq_status & ME4600_IRQ_STATUS_BIT_AI_HF) {
2925 PINFO("Threshold provided. Clear HF latch.\n");
2926 ctrl_set = ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2927
2928 if (instance->fifo_irq_threshold >= (ME4600_AI_FIFO_MAX_SC + instance->ISM.read)) { //This is not the last one. HF need reseting.
2929 PINFO
2930 ("The next interrupt is HF. HF need be activating.\n");
2931 ctrl_reset = ~ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2932 }
2933 }
2934
2935 if (irq_status & ME4600_IRQ_STATUS_BIT_SC) {
2936 PINFO("Threshold provided. Restart SC.\n");
2937 ctrl_set = ME4600_AI_CTRL_BIT_SC_IRQ_RESET;
2938 ctrl_reset &= ~ME4600_AI_CTRL_BIT_SC_IRQ_RESET;
2939
2940 if (instance->fifo_irq_threshold >= ME4600_AI_FIFO_MAX_SC) { //This is not the last one. HF need to be activating.
2941 PINFO
2942 ("The next interrupt is HF. HF need to be activating.\n");
2943 ctrl_reset &= ~ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
2944 }
2945 }
2946 }
2947
2948 //Reset interrupt latch.
2949 spin_lock(instance->ctrl_reg_lock);
2950 tmp = inl(instance->ctrl_reg);
2951 tmp |= ctrl_set;
2952 outl(tmp, instance->ctrl_reg);
2953 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
2954 instance->ctrl_reg - instance->reg_base, tmp);
2955
2956 if (ctrl_reset != 0xFFFFFFFF) {
2957 outl(tmp & ctrl_reset, instance->ctrl_reg);
2958 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
2959 instance->reg_base,
2960 instance->ctrl_reg - instance->reg_base,
2961 tmp & ctrl_reset);
2962 }
2963 spin_unlock(instance->ctrl_reg_lock);
2964
2965 }
2966
2967 /** @brief Last chunck of datas. We must reschedule sample counter.
2968 * @note Last chunck.
2969 * Leaving SC_RELOAD doesn't do any harm, but in some bad case can make extra interrupts.
2970 * @warning When threshold is wrongly set some IRQ are lost.(!!!)
2971 */
2972 inline void ai_reschedule_SC(me4600_ai_subdevice_t *instance)
2973 {
2974 register uint32_t rest;
2975
2976 if (instance->data_required <= instance->ISM.global_read)
2977 return;
2978
2979 rest = instance->data_required - instance->ISM.global_read;
2980 if (rest < instance->fifo_irq_threshold) { //End of work soon ....
2981 PDEBUG("Rescheduling SC from %d to %d.\n",
2982 instance->fifo_irq_threshold, rest);
2983 /// @note Write new value to SC <== DANGER! This is not safe solution! We can miss some inputs.
2984 outl(rest, instance->sample_counter_reg);
2985 PDEBUG_REG("sample_counter_reg outl(0x%lX+0x%lX)=0x%x\n",
2986 instance->reg_base,
2987 instance->sample_counter_reg - instance->reg_base,
2988 rest);
2989 instance->fifo_irq_threshold = rest;
2990
2991 if (rest < ME4600_AI_FIFO_MAX_SC) {
2992 instance->ISM.next = rest;
2993 } else {
2994 instance->ISM.next = rest % ME4600_AI_FIFO_HALF;
2995 if (instance->ISM.next + ME4600_AI_FIFO_HALF <
2996 ME4600_AI_FIFO_MAX_SC) {
2997 instance->ISM.next += ME4600_AI_FIFO_HALF;
2998 }
2999 }
3000 }
3001 }
3002
3003 /** Start the ISM. All must be reseted before enter to this function. */
3004 inline void ai_data_acquisition_logic(me4600_ai_subdevice_t *instance)
3005 {
3006 register uint32_t tmp;
3007
3008 if (!instance->data_required) { //This is infinite aqusition.
3009 if (!instance->fifo_irq_threshold) { //No threshold provided. Set SC to 0.5*FIFO. Clear the SC's latch.
3010 //Set the sample counter
3011 outl(ME4600_AI_FIFO_HALF, instance->sample_counter_reg);
3012 PDEBUG_REG
3013 ("sample_counter_reg outl(0x%lX+0x%lX)=0x%x\n",
3014 instance->reg_base,
3015 instance->sample_counter_reg - instance->reg_base,
3016 ME4600_AI_FIFO_HALF);
3017 } else { //Threshold provided. Set SC to treshold. Clear the SC's latch.
3018 //Set the sample counter
3019 outl(instance->fifo_irq_threshold,
3020 instance->sample_counter_reg);
3021 PDEBUG_REG
3022 ("sample_counter_reg outl(0x%lX+0x%lX)=0x%x\n",
3023 instance->reg_base,
3024 instance->sample_counter_reg - instance->reg_base,
3025 instance->fifo_irq_threshold);
3026 }
3027
3028 if (instance->fifo_irq_threshold < ME4600_AI_FIFO_MAX_SC) { //Enable only sample counter's interrupt. Set reload bit. Clear the SC's latch.
3029 spin_lock(instance->ctrl_reg_lock);
3030 tmp = inl(instance->ctrl_reg);
3031 tmp |= ME4600_AI_CTRL_BIT_SC_RELOAD;
3032 tmp &= ~ME4600_AI_CTRL_BIT_SC_IRQ_RESET;
3033 outl(tmp, instance->ctrl_reg);
3034 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
3035 instance->reg_base,
3036 instance->ctrl_reg - instance->reg_base,
3037 tmp);
3038 spin_unlock(instance->ctrl_reg_lock);
3039 if (!instance->fifo_irq_threshold) { //No threshold provided. Set ISM.next to 0.5*FIFO.
3040 instance->ISM.next = ME4600_AI_FIFO_HALF;
3041 } else { //Threshold provided. Set ISM.next to treshold.
3042 instance->ISM.next =
3043 instance->fifo_irq_threshold;
3044 }
3045 } else { //Enable sample counter's and HF's interrupts.
3046 spin_lock(instance->ctrl_reg_lock);
3047 tmp = inl(instance->ctrl_reg);
3048 tmp |= ME4600_AI_CTRL_BIT_SC_RELOAD;
3049 tmp &=
3050 ~(ME4600_AI_CTRL_BIT_SC_IRQ_RESET |
3051 ME4600_AI_CTRL_BIT_HF_IRQ_RESET);
3052 outl(tmp, instance->ctrl_reg);
3053 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
3054 instance->reg_base,
3055 instance->ctrl_reg - instance->reg_base,
3056 tmp);
3057 spin_unlock(instance->ctrl_reg_lock);
3058
3059 instance->ISM.next =
3060 instance->fifo_irq_threshold % ME4600_AI_FIFO_HALF;
3061 if (instance->ISM.next + ME4600_AI_FIFO_HALF <
3062 ME4600_AI_FIFO_MAX_SC) {
3063 instance->ISM.next += ME4600_AI_FIFO_HALF;
3064 }
3065 }
3066 } else { //This aqusition is limited to set number of data.
3067 if (instance->fifo_irq_threshold >= instance->data_required) { //Stupid situation.
3068 instance->fifo_irq_threshold = 0;
3069 PDEBUG
3070 ("Stupid situation: data_required(%d) < threshold(%d).\n",
3071 instance->fifo_irq_threshold,
3072 instance->data_required);
3073 }
3074
3075 if (!instance->fifo_irq_threshold) { //No threshold provided. Easy case: HF=read and SC=end.
3076 //Set the sample counter to data_required.
3077 outl(instance->data_required,
3078 instance->sample_counter_reg);
3079 PDEBUG_REG
3080 ("sample_counter_reg outl(0x%lX+0x%lX)=0x%x\n",
3081 instance->reg_base,
3082 instance->sample_counter_reg - instance->reg_base,
3083 instance->data_required);
3084
3085 //Reset the latches of sample counter and HF (if SC>FIFO).
3086 //No SC reload!
3087 spin_lock(instance->ctrl_reg_lock);
3088 tmp = inl(instance->ctrl_reg);
3089 tmp &=
3090 ~(ME4600_AI_CTRL_BIT_SC_IRQ_RESET |
3091 ME4600_AI_CTRL_BIT_SC_RELOAD);
3092 if (instance->data_required >
3093 (ME4600_AI_FIFO_COUNT - 1)) {
3094 tmp &= ~ME4600_AI_CTRL_BIT_HF_IRQ_RESET;
3095 instance->ISM.next =
3096 instance->data_required %
3097 ME4600_AI_FIFO_HALF;
3098 instance->ISM.next += ME4600_AI_FIFO_HALF;
3099
3100 } else {
3101 instance->ISM.next = instance->data_required;
3102 }
3103 outl(tmp, instance->ctrl_reg);
3104 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
3105 instance->reg_base,
3106 instance->ctrl_reg - instance->reg_base,
3107 tmp);
3108 spin_unlock(instance->ctrl_reg_lock);
3109
3110 } else { //The most general case. We have concret numbe of required data and threshold. SC=TH
3111 //Set the sample counter to threshold.
3112 outl(instance->fifo_irq_threshold,
3113 instance->sample_counter_reg);
3114 PDEBUG_REG
3115 ("sample_counter_reg outl(0x%lX+0x%lX)=0x%x\n",
3116 instance->reg_base,
3117 instance->sample_counter_reg - instance->reg_base,
3118 instance->fifo_irq_threshold);
3119
3120 spin_lock(instance->ctrl_reg_lock);
3121 tmp = inl(instance->ctrl_reg);
3122 //In this moment we are sure that SC will come more than once.
3123 tmp |= ME4600_AI_CTRL_BIT_SC_RELOAD;
3124
3125 if (instance->fifo_irq_threshold < ME4600_AI_FIFO_MAX_SC) { //The threshold is so small that we do need HF.
3126 tmp &= ~ME4600_AI_CTRL_BIT_SC_IRQ_RESET;
3127 instance->ISM.next =
3128 instance->fifo_irq_threshold;
3129 } else { //The threshold is large. The HF must be use.
3130 tmp &=
3131 ~(ME4600_AI_CTRL_BIT_SC_IRQ_RESET |
3132 ME4600_AI_CTRL_BIT_HF_IRQ_RESET);
3133 instance->ISM.next =
3134 instance->fifo_irq_threshold %
3135 ME4600_AI_FIFO_HALF;
3136 if (instance->ISM.next + ME4600_AI_FIFO_HALF <
3137 ME4600_AI_FIFO_MAX_SC) {
3138 instance->ISM.next +=
3139 ME4600_AI_FIFO_HALF;
3140 }
3141 }
3142 outl(tmp, instance->ctrl_reg);
3143 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
3144 instance->reg_base,
3145 instance->ctrl_reg - instance->reg_base,
3146 tmp);
3147 spin_unlock(instance->ctrl_reg_lock);
3148 }
3149 }
3150 }
3151
3152 static int ai_mux_toggler(me4600_ai_subdevice_t *instance)
3153 {
3154 uint32_t tmp;
3155
3156 PDEBUG("executed. idx=0\n");
3157
3158 outl(0, instance->scan_pre_timer_low_reg);
3159 PDEBUG_REG("scan_pre_timer_low_reg outl(0x%lX+0x%lX)=0x%x\n",
3160 instance->reg_base,
3161 instance->scan_pre_timer_low_reg - instance->reg_base, 0);
3162 outl(0, instance->scan_pre_timer_high_reg);
3163 PDEBUG_REG("scan_pre_timer_high_reg outl(0x%lX+0x%lX)=0x%x\n",
3164 instance->reg_base,
3165 instance->scan_pre_timer_high_reg - instance->reg_base, 0);
3166 outl(0, instance->scan_timer_low_reg);
3167 PDEBUG_REG("scan_timer_low_reg outl(0x%lX+0x%lX)=0x%x\n",
3168 instance->reg_base,
3169 instance->scan_timer_low_reg - instance->reg_base, 0);
3170 outl(0, instance->scan_timer_high_reg);
3171 PDEBUG_REG("scan_timer_high_reg outl(0x%lX+0x%lX)=0x%x\n",
3172 instance->reg_base,
3173 instance->scan_timer_high_reg - instance->reg_base, 0);
3174 outl(65, instance->chan_timer_reg);
3175 PDEBUG_REG("chan_timer_reg outl(0x%lX+0x%lX)=0x%x\n",
3176 instance->reg_base,
3177 instance->chan_timer_reg - instance->reg_base, 65);
3178 outl(65, instance->chan_pre_timer_reg);
3179 PDEBUG_REG("chan_pre_timer_reg outl(0x%lX+0x%lX)=0x%x\n",
3180 instance->reg_base,
3181 instance->chan_pre_timer_reg - instance->reg_base, 65);
3182
3183 // Turn on internal reference.
3184 tmp = inl(instance->ctrl_reg);
3185 tmp |= ME4600_AI_CTRL_BIT_FULLSCALE;
3186 outl(tmp, instance->ctrl_reg);
3187 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
3188 instance->ctrl_reg - instance->reg_base, tmp);
3189
3190 // Clear data and channel fifo.
3191 tmp &=
3192 ~(ME4600_AI_CTRL_BIT_CHANNEL_FIFO | ME4600_AI_CTRL_BIT_DATA_FIFO);
3193 outl(tmp, instance->ctrl_reg);
3194 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
3195 instance->ctrl_reg - instance->reg_base, tmp);
3196 tmp |= ME4600_AI_CTRL_BIT_CHANNEL_FIFO | ME4600_AI_CTRL_BIT_DATA_FIFO;
3197 outl(tmp, instance->ctrl_reg);
3198 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
3199 instance->ctrl_reg - instance->reg_base, tmp);
3200
3201 // Write channel entry.
3202 outl(ME4600_AI_LIST_INPUT_DIFFERENTIAL |
3203 ME4600_AI_LIST_RANGE_UNIPOLAR_2_5 | 31,
3204 instance->channel_list_reg);
3205 PDEBUG_REG("channel_list_reg outl(0x%lX+0x%lX)=0x%x\n",
3206 instance->reg_base,
3207 instance->channel_list_reg - instance->reg_base,
3208 ME4600_AI_LIST_INPUT_DIFFERENTIAL |
3209 ME4600_AI_LIST_RANGE_UNIPOLAR_2_5 | 31);
3210
3211 // Start conversion.
3212 inl(instance->start_reg);
3213 PDEBUG_REG("start_reg inl(0x%lX+0x%lX)\n", instance->reg_base,
3214 instance->start_reg - instance->reg_base);
3215 udelay(10);
3216
3217 // Clear data and channel fifo.
3218 tmp &=
3219 ~(ME4600_AI_CTRL_BIT_CHANNEL_FIFO | ME4600_AI_CTRL_BIT_DATA_FIFO);
3220 outl(tmp, instance->ctrl_reg);
3221 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
3222 instance->ctrl_reg - instance->reg_base, tmp);
3223 tmp |= ME4600_AI_CTRL_BIT_CHANNEL_FIFO | ME4600_AI_CTRL_BIT_DATA_FIFO;
3224 outl(tmp, instance->ctrl_reg);
3225 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
3226 instance->ctrl_reg - instance->reg_base, tmp);
3227
3228 // Write channel entry.
3229 // ME4600_AI_LIST_INPUT_SINGLE_ENDED | ME4600_AI_LIST_RANGE_BIPOLAR_10 <= 0x0000
3230 outl(ME4600_AI_LIST_INPUT_SINGLE_ENDED |
3231 ME4600_AI_LIST_RANGE_BIPOLAR_10, instance->channel_list_reg);
3232 PDEBUG_REG("channel_list_reg outl(0x%lX+0x%lX)=0x%x\n",
3233 instance->reg_base,
3234 instance->channel_list_reg - instance->reg_base,
3235 ME4600_AI_LIST_INPUT_SINGLE_ENDED |
3236 ME4600_AI_LIST_RANGE_BIPOLAR_10);
3237
3238 // Start conversion.
3239 inl(instance->start_reg);
3240 PDEBUG_REG("start_reg inl(0x%lX+0x%lX)\n", instance->reg_base,
3241 instance->start_reg - instance->reg_base);
3242 udelay(10);
3243
3244 // Clear control register.
3245 tmp &= (ME4600_AI_CTRL_BIT_EX_IRQ | ME4600_AI_CTRL_BIT_EX_IRQ_RESET);
3246 outl(tmp, instance->ctrl_reg);
3247 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
3248 instance->ctrl_reg - instance->reg_base, tmp);
3249
3250 return ME_ERRNO_SUCCESS;
3251 }
3252
3253 /** @brief Copy rest of data from fifo to circular buffer.
3254 * @note Helper for STOP command. After FSM is stopped.
3255 * @note This is slow function that copy all remainig data from FIFO to buffer.
3256 *
3257 * @param instance The subdevice instance (pointer).
3258 *
3259 * @return On success: Number of copied values.
3260 * @return On error: Negative error code -ME_ERRNO_RING_BUFFER_OVERFLOW.
3261 */
3262 static inline int ai_read_data_pooling(me4600_ai_subdevice_t *instance)
3263 { /// @note This is time critical function!
3264 int empty_space;
3265 int copied = 0;
3266 int status = ME_ERRNO_SUCCESS;
3267
3268 PDEBUG("Space left in circular buffer = %d.\n",
3269 me_circ_buf_space(&instance->circ_buf));
3270
3271 while ((empty_space = me_circ_buf_space(&instance->circ_buf))) {
3272 if (!(status = inl(instance->status_reg) & ME4600_AI_STATUS_BIT_EF_DATA)) { //No more data. status = ME_ERRNO_SUCCESS = 0
3273 break;
3274 }
3275 *(instance->circ_buf.buf + instance->circ_buf.head) =
3276 (inw(instance->data_reg) ^ 0x8000);
3277 instance->circ_buf.head++;
3278 instance->circ_buf.head &= instance->circ_buf.mask;
3279 }
3280
3281 #ifdef MEDEBUG_ERROR
3282 if (!status)
3283 PDEBUG
3284 ("Copied all remaining datas (%d) from FIFO to circular buffer.\n",
3285 copied);
3286 else {
3287 PDEBUG("No more empty space in buffer.\n");
3288 PDEBUG("Copied %d datas from FIFO to circular buffer.\n",
3289 copied);
3290 PDEBUG("FIFO still not empty.\n");
3291 }
3292 #endif
3293 return (!status) ? copied : -ME_ERRNO_RING_BUFFER_OVERFLOW;
3294 }
3295
3296 static void me4600_ai_work_control_task(struct work_struct *work)
3297 {
3298 me4600_ai_subdevice_t *instance;
3299 uint32_t status;
3300 uint32_t ctrl;
3301 unsigned long cpu_flags = 0;
3302 int reschedule = 0;
3303 int signaling = 0;
3304
3305 instance =
3306 container_of((void *)work, me4600_ai_subdevice_t, ai_control_task);
3307 PINFO("<%s: %ld> executed.\n", __func__, jiffies);
3308
3309 status = inl(instance->status_reg);
3310 PDEBUG_REG("status_reg inl(0x%lX+0x%lX)=0x%x\n", instance->reg_base,
3311 instance->status_reg - instance->reg_base, status);
3312
3313 switch (instance->status) { // Checking actual mode.
3314 // Not configured for work.
3315 case ai_status_none:
3316 break;
3317
3318 //This are stable modes. No need to do anything. (?)
3319 case ai_status_single_configured:
3320 case ai_status_stream_configured:
3321 case ai_status_stream_fifo_error:
3322 case ai_status_stream_buffer_error:
3323 case ai_status_stream_error:
3324 PERROR("Shouldn't be running!.\n");
3325 break;
3326
3327 // Stream modes
3328 case ai_status_stream_run_wait:
3329 if (status & ME4600_AI_STATUS_BIT_FSM) { // ISM started..
3330 instance->status = ai_status_stream_run;
3331 // Signal the end of wait for start.
3332 signaling = 1;
3333 // Wait now for stop.
3334 reschedule = 1;
3335 break;
3336
3337 // Check timeout.
3338 if ((instance->timeout.delay) && ((jiffies - instance->timeout.start_time) >= instance->timeout.delay)) { // Timeout
3339 PDEBUG("Timeout reached.\n");
3340 // Stop all actions. No conditions! Block interrupts. Reset FIFO => Too late!
3341 ai_stop_isr(instance);
3342
3343 instance->status = ai_status_stream_end;
3344
3345 // Signal the end.
3346 signaling = 1;
3347 }
3348 }
3349 break;
3350
3351 case ai_status_stream_run:
3352 // Wait for stop ISM.
3353 reschedule = 1;
3354 break;
3355
3356 case ai_status_stream_end_wait:
3357 if (!(status & ME4600_AI_STATUS_BIT_FSM)) { // ISM stoped. Overwrite ISR.
3358 instance->status = ai_status_stream_end;
3359 // Signal the end of wait for stop.
3360 signaling = 1;
3361 } else {
3362 // Wait for stop ISM.
3363 reschedule = 1;
3364 }
3365 break;
3366
3367 case ai_status_stream_end:
3368 //End work.
3369 if (status & ME4600_AI_STATUS_BIT_FSM) { // Still working? Stop it!
3370 PERROR
3371 ("Status is 'ai_status_stream_end' but hardware is still working!\n");
3372 spin_lock_irqsave(instance->ctrl_reg_lock, cpu_flags);
3373 ctrl = inl(instance->ctrl_reg);
3374 ctrl |=
3375 (ME4600_AI_CTRL_BIT_IMMEDIATE_STOP |
3376 ME4600_AI_CTRL_BIT_HF_IRQ_RESET |
3377 ME4600_AI_CTRL_BIT_SC_IRQ_RESET);
3378 outl(ctrl, instance->ctrl_reg);
3379 PDEBUG_REG("ctrl_reg outl(0x%lX+0x%lX)=0x%x\n",
3380 instance->reg_base,
3381 instance->ctrl_reg - instance->reg_base,
3382 ctrl);
3383 spin_unlock_irqrestore(instance->ctrl_reg_lock,
3384 cpu_flags);
3385 }
3386 break;
3387
3388 default:
3389 PERROR_CRITICAL("Status is in wrong state (%d)!\n",
3390 instance->status);
3391 instance->status = ai_status_stream_error;
3392 // Signal the end.
3393 signaling = 1;
3394 break;
3395
3396 }
3397
3398 if (signaling) { //Signal it.
3399 wake_up_interruptible_all(&instance->wait_queue);
3400 }
3401
3402 if (instance->ai_control_task_flag && reschedule) { // Reschedule task
3403 queue_delayed_work(instance->me4600_workqueue,
3404 &instance->ai_control_task, 1);
3405 } else {
3406 PINFO("<%s> Ending control task.\n", __func__);
3407 }
3408
3409 }
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