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rtc: move power of 2 periodic frequency check down into drivers
[linux-2.6/mini2440.git] / drivers / net / tulip / uli526x.c
blob00cbc5251dccd16d083c69a93664fa5bb627e991
1 /*
2 This program is free software; you can redistribute it and/or
3 modify it under the terms of the GNU General Public License
4 as published by the Free Software Foundation; either version 2
5 of the License, or (at your option) any later version.
6
7 This program is distributed in the hope that it will be useful,
8 but WITHOUT ANY WARRANTY; without even the implied warranty of
9 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 GNU General Public License for more details.
11
12
13 */
14
15 #define DRV_NAME "uli526x"
16 #define DRV_VERSION "0.9.3"
17 #define DRV_RELDATE "2005-7-29"
18
19 #include <linux/module.h>
20
21 #include <linux/kernel.h>
22 #include <linux/string.h>
23 #include <linux/timer.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/slab.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/skbuff.h>
34 #include <linux/delay.h>
35 #include <linux/spinlock.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/bitops.h>
38
39 #include <asm/processor.h>
40 #include <asm/io.h>
41 #include <asm/dma.h>
42 #include <asm/uaccess.h>
43
44
45 /* Board/System/Debug information/definition ---------------- */
46 #define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/
47 #define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/
48
49 #define ULI526X_IO_SIZE 0x100
50 #define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */
51 #define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */
52 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
53 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
54 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
55 #define TX_BUF_ALLOC 0x600
56 #define RX_ALLOC_SIZE 0x620
57 #define ULI526X_RESET 1
58 #define CR0_DEFAULT 0
59 #define CR6_DEFAULT 0x22200000
60 #define CR7_DEFAULT 0x180c1
61 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
62 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
63 #define MAX_PACKET_SIZE 1514
64 #define ULI5261_MAX_MULTICAST 14
65 #define RX_COPY_SIZE 100
66 #define MAX_CHECK_PACKET 0x8000
67
68 #define ULI526X_10MHF 0
69 #define ULI526X_100MHF 1
70 #define ULI526X_10MFD 4
71 #define ULI526X_100MFD 5
72 #define ULI526X_AUTO 8
73
74 #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
75 #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
76 #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
77 #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
78 #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
79 #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
80
81 #define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
82 #define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */
83 #define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */
84
85 #define ULI526X_DBUG(dbug_now, msg, value) if (uli526x_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))
86
87 #define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
88
89
90 /* CR9 definition: SROM/MII */
91 #define CR9_SROM_READ 0x4800
92 #define CR9_SRCS 0x1
93 #define CR9_SRCLK 0x2
94 #define CR9_CRDOUT 0x8
95 #define SROM_DATA_0 0x0
96 #define SROM_DATA_1 0x4
97 #define PHY_DATA_1 0x20000
98 #define PHY_DATA_0 0x00000
99 #define MDCLKH 0x10000
100
101 #define PHY_POWER_DOWN 0x800
102
103 #define SROM_V41_CODE 0x14
104
105 #define SROM_CLK_WRITE(data, ioaddr) \
106 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
107 udelay(5); \
108 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
109 udelay(5); \
110 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
111 udelay(5);
112
113 /* Structure/enum declaration ------------------------------- */
114 struct tx_desc {
115 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
116 char *tx_buf_ptr; /* Data for us */
117 struct tx_desc *next_tx_desc;
118 } __attribute__(( aligned(32) ));
119
120 struct rx_desc {
121 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
122 struct sk_buff *rx_skb_ptr; /* Data for us */
123 struct rx_desc *next_rx_desc;
124 } __attribute__(( aligned(32) ));
125
126 struct uli526x_board_info {
127 u32 chip_id; /* Chip vendor/Device ID */
128 struct net_device *next_dev; /* next device */
129 struct pci_dev *pdev; /* PCI device */
130 spinlock_t lock;
131
132 long ioaddr; /* I/O base address */
133 u32 cr0_data;
134 u32 cr5_data;
135 u32 cr6_data;
136 u32 cr7_data;
137 u32 cr15_data;
138
139 /* pointer for memory physical address */
140 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
141 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
142 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
143 dma_addr_t first_tx_desc_dma;
144 dma_addr_t first_rx_desc_dma;
145
146 /* descriptor pointer */
147 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
148 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
149 unsigned char *desc_pool_ptr; /* descriptor pool memory */
150 struct tx_desc *first_tx_desc;
151 struct tx_desc *tx_insert_ptr;
152 struct tx_desc *tx_remove_ptr;
153 struct rx_desc *first_rx_desc;
154 struct rx_desc *rx_insert_ptr;
155 struct rx_desc *rx_ready_ptr; /* packet come pointer */
156 unsigned long tx_packet_cnt; /* transmitted packet count */
157 unsigned long rx_avail_cnt; /* available rx descriptor count */
158 unsigned long interval_rx_cnt; /* rx packet count a callback time */
159
160 u16 dbug_cnt;
161 u16 NIC_capability; /* NIC media capability */
162 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
163
164 u8 media_mode; /* user specify media mode */
165 u8 op_mode; /* real work media mode */
166 u8 phy_addr;
167 u8 link_failed; /* Ever link failed */
168 u8 wait_reset; /* Hardware failed, need to reset */
169 struct timer_list timer;
170
171 /* System defined statistic counter */
172 struct net_device_stats stats;
173
174 /* Driver defined statistic counter */
175 unsigned long tx_fifo_underrun;
176 unsigned long tx_loss_carrier;
177 unsigned long tx_no_carrier;
178 unsigned long tx_late_collision;
179 unsigned long tx_excessive_collision;
180 unsigned long tx_jabber_timeout;
181 unsigned long reset_count;
182 unsigned long reset_cr8;
183 unsigned long reset_fatal;
184 unsigned long reset_TXtimeout;
185
186 /* NIC SROM data */
187 unsigned char srom[128];
188 u8 init;
189 };
190
191 enum uli526x_offsets {
192 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
193 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
194 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
195 DCR15 = 0x78
196 };
197
198 enum uli526x_CR6_bits {
199 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
200 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
201 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
202 };
203
204 /* Global variable declaration ----------------------------- */
205 static int __devinitdata printed_version;
206 static char version[] __devinitdata =
207 KERN_INFO DRV_NAME ": ULi M5261/M5263 net driver, version "
208 DRV_VERSION " (" DRV_RELDATE ")\n";
209
210 static int uli526x_debug;
211 static unsigned char uli526x_media_mode = ULI526X_AUTO;
212 static u32 uli526x_cr6_user_set;
213
214 /* For module input parameter */
215 static int debug;
216 static u32 cr6set;
217 static int mode = 8;
218
219 /* function declaration ------------------------------------- */
220 static int uli526x_open(struct net_device *);
221 static int uli526x_start_xmit(struct sk_buff *, struct net_device *);
222 static int uli526x_stop(struct net_device *);
223 static struct net_device_stats * uli526x_get_stats(struct net_device *);
224 static void uli526x_set_filter_mode(struct net_device *);
225 static const struct ethtool_ops netdev_ethtool_ops;
226 static u16 read_srom_word(long, int);
227 static irqreturn_t uli526x_interrupt(int, void *);
228 #ifdef CONFIG_NET_POLL_CONTROLLER
229 static void uli526x_poll(struct net_device *dev);
230 #endif
231 static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
232 static void allocate_rx_buffer(struct uli526x_board_info *);
233 static void update_cr6(u32, unsigned long);
234 static void send_filter_frame(struct net_device *, int);
235 static u16 phy_read(unsigned long, u8, u8, u32);
236 static u16 phy_readby_cr10(unsigned long, u8, u8);
237 static void phy_write(unsigned long, u8, u8, u16, u32);
238 static void phy_writeby_cr10(unsigned long, u8, u8, u16);
239 static void phy_write_1bit(unsigned long, u32, u32);
240 static u16 phy_read_1bit(unsigned long, u32);
241 static u8 uli526x_sense_speed(struct uli526x_board_info *);
242 static void uli526x_process_mode(struct uli526x_board_info *);
243 static void uli526x_timer(unsigned long);
244 static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *);
245 static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *);
246 static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *);
247 static void uli526x_dynamic_reset(struct net_device *);
248 static void uli526x_free_rxbuffer(struct uli526x_board_info *);
249 static void uli526x_init(struct net_device *);
250 static void uli526x_set_phyxcer(struct uli526x_board_info *);
251
252 /* ULI526X network board routine ---------------------------- */
253
254 /*
255 * Search ULI526X board, allocate space and register it
256 */
257
258 static int __devinit uli526x_init_one (struct pci_dev *pdev,
259 const struct pci_device_id *ent)
260 {
261 struct uli526x_board_info *db; /* board information structure */
262 struct net_device *dev;
263 int i, err;
264
265 ULI526X_DBUG(0, "uli526x_init_one()", 0);
266
267 if (!printed_version++)
268 printk(version);
269
270 /* Init network device */
271 dev = alloc_etherdev(sizeof(*db));
272 if (dev == NULL)
273 return -ENOMEM;
274 SET_NETDEV_DEV(dev, &pdev->dev);
275
276 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
277 printk(KERN_WARNING DRV_NAME ": 32-bit PCI DMA not available.\n");
278 err = -ENODEV;
279 goto err_out_free;
280 }
281
282 /* Enable Master/IO access, Disable memory access */
283 err = pci_enable_device(pdev);
284 if (err)
285 goto err_out_free;
286
287 if (!pci_resource_start(pdev, 0)) {
288 printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
289 err = -ENODEV;
290 goto err_out_disable;
291 }
292
293 if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) {
294 printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
295 err = -ENODEV;
296 goto err_out_disable;
297 }
298
299 if (pci_request_regions(pdev, DRV_NAME)) {
300 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
301 err = -ENODEV;
302 goto err_out_disable;
303 }
304
305 /* Init system & device */
306 db = netdev_priv(dev);
307
308 /* Allocate Tx/Rx descriptor memory */
309 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
310 if(db->desc_pool_ptr == NULL)
311 {
312 err = -ENOMEM;
313 goto err_out_nomem;
314 }
315 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
316 if(db->buf_pool_ptr == NULL)
317 {
318 err = -ENOMEM;
319 goto err_out_nomem;
320 }
321
322 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
323 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
324 db->buf_pool_start = db->buf_pool_ptr;
325 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
326
327 db->chip_id = ent->driver_data;
328 db->ioaddr = pci_resource_start(pdev, 0);
329
330 db->pdev = pdev;
331 db->init = 1;
332
333 dev->base_addr = db->ioaddr;
334 dev->irq = pdev->irq;
335 pci_set_drvdata(pdev, dev);
336
337 /* Register some necessary functions */
338 dev->open = &uli526x_open;
339 dev->hard_start_xmit = &uli526x_start_xmit;
340 dev->stop = &uli526x_stop;
341 dev->get_stats = &uli526x_get_stats;
342 dev->set_multicast_list = &uli526x_set_filter_mode;
343 dev->ethtool_ops = &netdev_ethtool_ops;
344 #ifdef CONFIG_NET_POLL_CONTROLLER
345 dev->poll_controller = &uli526x_poll;
346 #endif
347 spin_lock_init(&db->lock);
348
349
350 /* read 64 word srom data */
351 for (i = 0; i < 64; i++)
352 ((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i));
353
354 /* Set Node address */
355 if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) /* SROM absent, so read MAC address from ID Table */
356 {
357 outl(0x10000, db->ioaddr + DCR0); //Diagnosis mode
358 outl(0x1c0, db->ioaddr + DCR13); //Reset dianostic pointer port
359 outl(0, db->ioaddr + DCR14); //Clear reset port
360 outl(0x10, db->ioaddr + DCR14); //Reset ID Table pointer
361 outl(0, db->ioaddr + DCR14); //Clear reset port
362 outl(0, db->ioaddr + DCR13); //Clear CR13
363 outl(0x1b0, db->ioaddr + DCR13); //Select ID Table access port
364 //Read MAC address from CR14
365 for (i = 0; i < 6; i++)
366 dev->dev_addr[i] = inl(db->ioaddr + DCR14);
367 //Read end
368 outl(0, db->ioaddr + DCR13); //Clear CR13
369 outl(0, db->ioaddr + DCR0); //Clear CR0
370 udelay(10);
371 }
372 else /*Exist SROM*/
373 {
374 for (i = 0; i < 6; i++)
375 dev->dev_addr[i] = db->srom[20 + i];
376 }
377 err = register_netdev (dev);
378 if (err)
379 goto err_out_res;
380
381 printk(KERN_INFO "%s: ULi M%04lx at pci%s, %pM, irq %d.\n",
382 dev->name,ent->driver_data >> 16,pci_name(pdev),
383 dev->dev_addr, dev->irq);
384
385 pci_set_master(pdev);
386
387 return 0;
388
389 err_out_res:
390 pci_release_regions(pdev);
391 err_out_nomem:
392 if(db->desc_pool_ptr)
393 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
394 db->desc_pool_ptr, db->desc_pool_dma_ptr);
395
396 if(db->buf_pool_ptr != NULL)
397 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
398 db->buf_pool_ptr, db->buf_pool_dma_ptr);
399 err_out_disable:
400 pci_disable_device(pdev);
401 err_out_free:
402 pci_set_drvdata(pdev, NULL);
403 free_netdev(dev);
404
405 return err;
406 }
407
408
409 static void __devexit uli526x_remove_one (struct pci_dev *pdev)
410 {
411 struct net_device *dev = pci_get_drvdata(pdev);
412 struct uli526x_board_info *db = netdev_priv(dev);
413
414 ULI526X_DBUG(0, "uli526x_remove_one()", 0);
415
416 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
417 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
418 db->desc_pool_dma_ptr);
419 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
420 db->buf_pool_ptr, db->buf_pool_dma_ptr);
421 unregister_netdev(dev);
422 pci_release_regions(pdev);
423 free_netdev(dev); /* free board information */
424 pci_set_drvdata(pdev, NULL);
425 pci_disable_device(pdev);
426 ULI526X_DBUG(0, "uli526x_remove_one() exit", 0);
427 }
428
429
430 /*
431 * Open the interface.
432 * The interface is opened whenever "ifconfig" activates it.
433 */
434
435 static int uli526x_open(struct net_device *dev)
436 {
437 int ret;
438 struct uli526x_board_info *db = netdev_priv(dev);
439
440 ULI526X_DBUG(0, "uli526x_open", 0);
441
442 /* system variable init */
443 db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set;
444 db->tx_packet_cnt = 0;
445 db->rx_avail_cnt = 0;
446 db->link_failed = 1;
447 netif_carrier_off(dev);
448 db->wait_reset = 0;
449
450 db->NIC_capability = 0xf; /* All capability*/
451 db->PHY_reg4 = 0x1e0;
452
453 /* CR6 operation mode decision */
454 db->cr6_data |= ULI526X_TXTH_256;
455 db->cr0_data = CR0_DEFAULT;
456
457 /* Initialize ULI526X board */
458 uli526x_init(dev);
459
460 ret = request_irq(dev->irq, &uli526x_interrupt, IRQF_SHARED, dev->name, dev);
461 if (ret)
462 return ret;
463
464 /* Active System Interface */
465 netif_wake_queue(dev);
466
467 /* set and active a timer process */
468 init_timer(&db->timer);
469 db->timer.expires = ULI526X_TIMER_WUT + HZ * 2;
470 db->timer.data = (unsigned long)dev;
471 db->timer.function = &uli526x_timer;
472 add_timer(&db->timer);
473
474 return 0;
475 }
476
477
478 /* Initialize ULI526X board
479 * Reset ULI526X board
480 * Initialize TX/Rx descriptor chain structure
481 * Send the set-up frame
482 * Enable Tx/Rx machine
483 */
484
485 static void uli526x_init(struct net_device *dev)
486 {
487 struct uli526x_board_info *db = netdev_priv(dev);
488 unsigned long ioaddr = db->ioaddr;
489 u8 phy_tmp;
490 u8 timeout;
491 u16 phy_value;
492 u16 phy_reg_reset;
493
494
495 ULI526X_DBUG(0, "uli526x_init()", 0);
496
497 /* Reset M526x MAC controller */
498 outl(ULI526X_RESET, ioaddr + DCR0); /* RESET MAC */
499 udelay(100);
500 outl(db->cr0_data, ioaddr + DCR0);
501 udelay(5);
502
503 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
504 db->phy_addr = 1;
505 for(phy_tmp=0;phy_tmp<32;phy_tmp++)
506 {
507 phy_value=phy_read(db->ioaddr,phy_tmp,3,db->chip_id);//peer add
508 if(phy_value != 0xffff&&phy_value!=0)
509 {
510 db->phy_addr = phy_tmp;
511 break;
512 }
513 }
514 if(phy_tmp == 32)
515 printk(KERN_WARNING "Can not find the phy address!!!");
516 /* Parser SROM and media mode */
517 db->media_mode = uli526x_media_mode;
518
519 /* phyxcer capability setting */
520 phy_reg_reset = phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id);
521 phy_reg_reset = (phy_reg_reset | 0x8000);
522 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg_reset, db->chip_id);
523
524 /* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management
525 * functions") or phy data sheet for details on phy reset
526 */
527 udelay(500);
528 timeout = 10;
529 while (timeout-- &&
530 phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id) & 0x8000)
531 udelay(100);
532
533 /* Process Phyxcer Media Mode */
534 uli526x_set_phyxcer(db);
535
536 /* Media Mode Process */
537 if ( !(db->media_mode & ULI526X_AUTO) )
538 db->op_mode = db->media_mode; /* Force Mode */
539
540 /* Initialize Transmit/Receive decriptor and CR3/4 */
541 uli526x_descriptor_init(db, ioaddr);
542
543 /* Init CR6 to program M526X operation */
544 update_cr6(db->cr6_data, ioaddr);
545
546 /* Send setup frame */
547 send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */
548
549 /* Init CR7, interrupt active bit */
550 db->cr7_data = CR7_DEFAULT;
551 outl(db->cr7_data, ioaddr + DCR7);
552
553 /* Init CR15, Tx jabber and Rx watchdog timer */
554 outl(db->cr15_data, ioaddr + DCR15);
555
556 /* Enable ULI526X Tx/Rx function */
557 db->cr6_data |= CR6_RXSC | CR6_TXSC;
558 update_cr6(db->cr6_data, ioaddr);
559 }
560
561
562 /*
563 * Hardware start transmission.
564 * Send a packet to media from the upper layer.
565 */
566
567 static int uli526x_start_xmit(struct sk_buff *skb, struct net_device *dev)
568 {
569 struct uli526x_board_info *db = netdev_priv(dev);
570 struct tx_desc *txptr;
571 unsigned long flags;
572
573 ULI526X_DBUG(0, "uli526x_start_xmit", 0);
574
575 /* Resource flag check */
576 netif_stop_queue(dev);
577
578 /* Too large packet check */
579 if (skb->len > MAX_PACKET_SIZE) {
580 printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
581 dev_kfree_skb(skb);
582 return 0;
583 }
584
585 spin_lock_irqsave(&db->lock, flags);
586
587 /* No Tx resource check, it never happen nromally */
588 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
589 spin_unlock_irqrestore(&db->lock, flags);
590 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n", db->tx_packet_cnt);
591 return 1;
592 }
593
594 /* Disable NIC interrupt */
595 outl(0, dev->base_addr + DCR7);
596
597 /* transmit this packet */
598 txptr = db->tx_insert_ptr;
599 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
600 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
601
602 /* Point to next transmit free descriptor */
603 db->tx_insert_ptr = txptr->next_tx_desc;
604
605 /* Transmit Packet Process */
606 if ( (db->tx_packet_cnt < TX_DESC_CNT) ) {
607 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
608 db->tx_packet_cnt++; /* Ready to send */
609 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
610 dev->trans_start = jiffies; /* saved time stamp */
611 }
612
613 /* Tx resource check */
614 if ( db->tx_packet_cnt < TX_FREE_DESC_CNT )
615 netif_wake_queue(dev);
616
617 /* Restore CR7 to enable interrupt */
618 spin_unlock_irqrestore(&db->lock, flags);
619 outl(db->cr7_data, dev->base_addr + DCR7);
620
621 /* free this SKB */
622 dev_kfree_skb(skb);
623
624 return 0;
625 }
626
627
628 /*
629 * Stop the interface.
630 * The interface is stopped when it is brought.
631 */
632
633 static int uli526x_stop(struct net_device *dev)
634 {
635 struct uli526x_board_info *db = netdev_priv(dev);
636 unsigned long ioaddr = dev->base_addr;
637
638 ULI526X_DBUG(0, "uli526x_stop", 0);
639
640 /* disable system */
641 netif_stop_queue(dev);
642
643 /* deleted timer */
644 del_timer_sync(&db->timer);
645
646 /* Reset & stop ULI526X board */
647 outl(ULI526X_RESET, ioaddr + DCR0);
648 udelay(5);
649 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
650
651 /* free interrupt */
652 free_irq(dev->irq, dev);
653
654 /* free allocated rx buffer */
655 uli526x_free_rxbuffer(db);
656
657 #if 0
658 /* show statistic counter */
659 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
660 db->tx_fifo_underrun, db->tx_excessive_collision,
661 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
662 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
663 db->reset_fatal, db->reset_TXtimeout);
664 #endif
665
666 return 0;
667 }
668
669
670 /*
671 * M5261/M5263 insterrupt handler
672 * receive the packet to upper layer, free the transmitted packet
673 */
674
675 static irqreturn_t uli526x_interrupt(int irq, void *dev_id)
676 {
677 struct net_device *dev = dev_id;
678 struct uli526x_board_info *db = netdev_priv(dev);
679 unsigned long ioaddr = dev->base_addr;
680 unsigned long flags;
681
682 spin_lock_irqsave(&db->lock, flags);
683 outl(0, ioaddr + DCR7);
684
685 /* Got ULI526X status */
686 db->cr5_data = inl(ioaddr + DCR5);
687 outl(db->cr5_data, ioaddr + DCR5);
688 if ( !(db->cr5_data & 0x180c1) ) {
689 /* Restore CR7 to enable interrupt mask */
690 outl(db->cr7_data, ioaddr + DCR7);
691 spin_unlock_irqrestore(&db->lock, flags);
692 return IRQ_HANDLED;
693 }
694
695 /* Check system status */
696 if (db->cr5_data & 0x2000) {
697 /* system bus error happen */
698 ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
699 db->reset_fatal++;
700 db->wait_reset = 1; /* Need to RESET */
701 spin_unlock_irqrestore(&db->lock, flags);
702 return IRQ_HANDLED;
703 }
704
705 /* Received the coming packet */
706 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
707 uli526x_rx_packet(dev, db);
708
709 /* reallocate rx descriptor buffer */
710 if (db->rx_avail_cnt<RX_DESC_CNT)
711 allocate_rx_buffer(db);
712
713 /* Free the transmitted descriptor */
714 if ( db->cr5_data & 0x01)
715 uli526x_free_tx_pkt(dev, db);
716
717 /* Restore CR7 to enable interrupt mask */
718 outl(db->cr7_data, ioaddr + DCR7);
719
720 spin_unlock_irqrestore(&db->lock, flags);
721 return IRQ_HANDLED;
722 }
723
724 #ifdef CONFIG_NET_POLL_CONTROLLER
725 static void uli526x_poll(struct net_device *dev)
726 {
727 /* ISR grabs the irqsave lock, so this should be safe */
728 uli526x_interrupt(dev->irq, dev);
729 }
730 #endif
731
732 /*
733 * Free TX resource after TX complete
734 */
735
736 static void uli526x_free_tx_pkt(struct net_device *dev, struct uli526x_board_info * db)
737 {
738 struct tx_desc *txptr;
739 u32 tdes0;
740
741 txptr = db->tx_remove_ptr;
742 while(db->tx_packet_cnt) {
743 tdes0 = le32_to_cpu(txptr->tdes0);
744 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
745 if (tdes0 & 0x80000000)
746 break;
747
748 /* A packet sent completed */
749 db->tx_packet_cnt--;
750 db->stats.tx_packets++;
751
752 /* Transmit statistic counter */
753 if ( tdes0 != 0x7fffffff ) {
754 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
755 db->stats.collisions += (tdes0 >> 3) & 0xf;
756 db->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
757 if (tdes0 & TDES0_ERR_MASK) {
758 db->stats.tx_errors++;
759 if (tdes0 & 0x0002) { /* UnderRun */
760 db->tx_fifo_underrun++;
761 if ( !(db->cr6_data & CR6_SFT) ) {
762 db->cr6_data = db->cr6_data | CR6_SFT;
763 update_cr6(db->cr6_data, db->ioaddr);
764 }
765 }
766 if (tdes0 & 0x0100)
767 db->tx_excessive_collision++;
768 if (tdes0 & 0x0200)
769 db->tx_late_collision++;
770 if (tdes0 & 0x0400)
771 db->tx_no_carrier++;
772 if (tdes0 & 0x0800)
773 db->tx_loss_carrier++;
774 if (tdes0 & 0x4000)
775 db->tx_jabber_timeout++;
776 }
777 }
778
779 txptr = txptr->next_tx_desc;
780 }/* End of while */
781
782 /* Update TX remove pointer to next */
783 db->tx_remove_ptr = txptr;
784
785 /* Resource available check */
786 if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT )
787 netif_wake_queue(dev); /* Active upper layer, send again */
788 }
789
790
791 /*
792 * Receive the come packet and pass to upper layer
793 */
794
795 static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db)
796 {
797 struct rx_desc *rxptr;
798 struct sk_buff *skb;
799 int rxlen;
800 u32 rdes0;
801
802 rxptr = db->rx_ready_ptr;
803
804 while(db->rx_avail_cnt) {
805 rdes0 = le32_to_cpu(rxptr->rdes0);
806 if (rdes0 & 0x80000000) /* packet owner check */
807 {
808 break;
809 }
810
811 db->rx_avail_cnt--;
812 db->interval_rx_cnt++;
813
814 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
815 if ( (rdes0 & 0x300) != 0x300) {
816 /* A packet without First/Last flag */
817 /* reuse this SKB */
818 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
819 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
820 } else {
821 /* A packet with First/Last flag */
822 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
823
824 /* error summary bit check */
825 if (rdes0 & 0x8000) {
826 /* This is a error packet */
827 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
828 db->stats.rx_errors++;
829 if (rdes0 & 1)
830 db->stats.rx_fifo_errors++;
831 if (rdes0 & 2)
832 db->stats.rx_crc_errors++;
833 if (rdes0 & 0x80)
834 db->stats.rx_length_errors++;
835 }
836
837 if ( !(rdes0 & 0x8000) ||
838 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
839 skb = rxptr->rx_skb_ptr;
840
841 /* Good packet, send to upper layer */
842 /* Shorst packet used new SKB */
843 if ( (rxlen < RX_COPY_SIZE) &&
844 ( (skb = dev_alloc_skb(rxlen + 2) )
845 != NULL) ) {
846 /* size less than COPY_SIZE, allocate a rxlen SKB */
847 skb_reserve(skb, 2); /* 16byte align */
848 memcpy(skb_put(skb, rxlen),
849 skb_tail_pointer(rxptr->rx_skb_ptr),
850 rxlen);
851 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
852 } else
853 skb_put(skb, rxlen);
854
855 skb->protocol = eth_type_trans(skb, dev);
856 netif_rx(skb);
857 db->stats.rx_packets++;
858 db->stats.rx_bytes += rxlen;
859
860 } else {
861 /* Reuse SKB buffer when the packet is error */
862 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
863 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
864 }
865 }
866
867 rxptr = rxptr->next_rx_desc;
868 }
869
870 db->rx_ready_ptr = rxptr;
871 }
872
873
874 /*
875 * Get statistics from driver.
876 */
877
878 static struct net_device_stats * uli526x_get_stats(struct net_device *dev)
879 {
880 struct uli526x_board_info *db = netdev_priv(dev);
881
882 ULI526X_DBUG(0, "uli526x_get_stats", 0);
883 return &db->stats;
884 }
885
886
887 /*
888 * Set ULI526X multicast address
889 */
890
891 static void uli526x_set_filter_mode(struct net_device * dev)
892 {
893 struct uli526x_board_info *db = netdev_priv(dev);
894 unsigned long flags;
895
896 ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
897 spin_lock_irqsave(&db->lock, flags);
898
899 if (dev->flags & IFF_PROMISC) {
900 ULI526X_DBUG(0, "Enable PROM Mode", 0);
901 db->cr6_data |= CR6_PM | CR6_PBF;
902 update_cr6(db->cr6_data, db->ioaddr);
903 spin_unlock_irqrestore(&db->lock, flags);
904 return;
905 }
906
907 if (dev->flags & IFF_ALLMULTI || dev->mc_count > ULI5261_MAX_MULTICAST) {
908 ULI526X_DBUG(0, "Pass all multicast address", dev->mc_count);
909 db->cr6_data &= ~(CR6_PM | CR6_PBF);
910 db->cr6_data |= CR6_PAM;
911 spin_unlock_irqrestore(&db->lock, flags);
912 return;
913 }
914
915 ULI526X_DBUG(0, "Set multicast address", dev->mc_count);
916 send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */
917 spin_unlock_irqrestore(&db->lock, flags);
918 }
919
920 static void
921 ULi_ethtool_gset(struct uli526x_board_info *db, struct ethtool_cmd *ecmd)
922 {
923 ecmd->supported = (SUPPORTED_10baseT_Half |
924 SUPPORTED_10baseT_Full |
925 SUPPORTED_100baseT_Half |
926 SUPPORTED_100baseT_Full |
927 SUPPORTED_Autoneg |
928 SUPPORTED_MII);
929
930 ecmd->advertising = (ADVERTISED_10baseT_Half |
931 ADVERTISED_10baseT_Full |
932 ADVERTISED_100baseT_Half |
933 ADVERTISED_100baseT_Full |
934 ADVERTISED_Autoneg |
935 ADVERTISED_MII);
936
937
938 ecmd->port = PORT_MII;
939 ecmd->phy_address = db->phy_addr;
940
941 ecmd->transceiver = XCVR_EXTERNAL;
942
943 ecmd->speed = 10;
944 ecmd->duplex = DUPLEX_HALF;
945
946 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
947 {
948 ecmd->speed = 100;
949 }
950 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
951 {
952 ecmd->duplex = DUPLEX_FULL;
953 }
954 if(db->link_failed)
955 {
956 ecmd->speed = -1;
957 ecmd->duplex = -1;
958 }
959
960 if (db->media_mode & ULI526X_AUTO)
961 {
962 ecmd->autoneg = AUTONEG_ENABLE;
963 }
964 }
965
966 static void netdev_get_drvinfo(struct net_device *dev,
967 struct ethtool_drvinfo *info)
968 {
969 struct uli526x_board_info *np = netdev_priv(dev);
970
971 strcpy(info->driver, DRV_NAME);
972 strcpy(info->version, DRV_VERSION);
973 if (np->pdev)
974 strcpy(info->bus_info, pci_name(np->pdev));
975 else
976 sprintf(info->bus_info, "EISA 0x%lx %d",
977 dev->base_addr, dev->irq);
978 }
979
980 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) {
981 struct uli526x_board_info *np = netdev_priv(dev);
982
983 ULi_ethtool_gset(np, cmd);
984
985 return 0;
986 }
987
988 static u32 netdev_get_link(struct net_device *dev) {
989 struct uli526x_board_info *np = netdev_priv(dev);
990
991 if(np->link_failed)
992 return 0;
993 else
994 return 1;
995 }
996
997 static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
998 {
999 wol->supported = WAKE_PHY | WAKE_MAGIC;
1000 wol->wolopts = 0;
1001 }
1002
1003 static const struct ethtool_ops netdev_ethtool_ops = {
1004 .get_drvinfo = netdev_get_drvinfo,
1005 .get_settings = netdev_get_settings,
1006 .get_link = netdev_get_link,
1007 .get_wol = uli526x_get_wol,
1008 };
1009
1010 /*
1011 * A periodic timer routine
1012 * Dynamic media sense, allocate Rx buffer...
1013 */
1014
1015 static void uli526x_timer(unsigned long data)
1016 {
1017 u32 tmp_cr8;
1018 unsigned char tmp_cr12=0;
1019 struct net_device *dev = (struct net_device *) data;
1020 struct uli526x_board_info *db = netdev_priv(dev);
1021 unsigned long flags;
1022 u8 TmpSpeed=10;
1023
1024 //ULI526X_DBUG(0, "uli526x_timer()", 0);
1025 spin_lock_irqsave(&db->lock, flags);
1026
1027
1028 /* Dynamic reset ULI526X : system error or transmit time-out */
1029 tmp_cr8 = inl(db->ioaddr + DCR8);
1030 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1031 db->reset_cr8++;
1032 db->wait_reset = 1;
1033 }
1034 db->interval_rx_cnt = 0;
1035
1036 /* TX polling kick monitor */
1037 if ( db->tx_packet_cnt &&
1038 time_after(jiffies, dev->trans_start + ULI526X_TX_KICK) ) {
1039 outl(0x1, dev->base_addr + DCR1); // Tx polling again
1040
1041 // TX Timeout
1042 if ( time_after(jiffies, dev->trans_start + ULI526X_TX_TIMEOUT) ) {
1043 db->reset_TXtimeout++;
1044 db->wait_reset = 1;
1045 printk( "%s: Tx timeout - resetting\n",
1046 dev->name);
1047 }
1048 }
1049
1050 if (db->wait_reset) {
1051 ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1052 db->reset_count++;
1053 uli526x_dynamic_reset(dev);
1054 db->timer.expires = ULI526X_TIMER_WUT;
1055 add_timer(&db->timer);
1056 spin_unlock_irqrestore(&db->lock, flags);
1057 return;
1058 }
1059
1060 /* Link status check, Dynamic media type change */
1061 if((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)!=0)
1062 tmp_cr12 = 3;
1063
1064 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1065 /* Link Failed */
1066 ULI526X_DBUG(0, "Link Failed", tmp_cr12);
1067 netif_carrier_off(dev);
1068 printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name);
1069 db->link_failed = 1;
1070
1071 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1072 /* AUTO don't need */
1073 if ( !(db->media_mode & 0x8) )
1074 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1075
1076 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1077 if (db->media_mode & ULI526X_AUTO) {
1078 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1079 update_cr6(db->cr6_data, db->ioaddr);
1080 }
1081 } else
1082 if ((tmp_cr12 & 0x3) && db->link_failed) {
1083 ULI526X_DBUG(0, "Link link OK", tmp_cr12);
1084 db->link_failed = 0;
1085
1086 /* Auto Sense Speed */
1087 if ( (db->media_mode & ULI526X_AUTO) &&
1088 uli526x_sense_speed(db) )
1089 db->link_failed = 1;
1090 uli526x_process_mode(db);
1091
1092 if(db->link_failed==0)
1093 {
1094 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
1095 {
1096 TmpSpeed = 100;
1097 }
1098 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
1099 {
1100 printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Full duplex\n",dev->name,TmpSpeed);
1101 }
1102 else
1103 {
1104 printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Half duplex\n",dev->name,TmpSpeed);
1105 }
1106 netif_carrier_on(dev);
1107 }
1108 /* SHOW_MEDIA_TYPE(db->op_mode); */
1109 }
1110 else if(!(tmp_cr12 & 0x3) && db->link_failed)
1111 {
1112 if(db->init==1)
1113 {
1114 printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name);
1115 netif_carrier_off(dev);
1116 }
1117 }
1118 db->init=0;
1119
1120 /* Timer active again */
1121 db->timer.expires = ULI526X_TIMER_WUT;
1122 add_timer(&db->timer);
1123 spin_unlock_irqrestore(&db->lock, flags);
1124 }
1125
1126
1127 /*
1128 * Stop ULI526X board
1129 * Free Tx/Rx allocated memory
1130 * Init system variable
1131 */
1132
1133 static void uli526x_reset_prepare(struct net_device *dev)
1134 {
1135 struct uli526x_board_info *db = netdev_priv(dev);
1136
1137 /* Sopt MAC controller */
1138 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1139 update_cr6(db->cr6_data, dev->base_addr);
1140 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1141 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1142
1143 /* Disable upper layer interface */
1144 netif_stop_queue(dev);
1145
1146 /* Free Rx Allocate buffer */
1147 uli526x_free_rxbuffer(db);
1148
1149 /* system variable init */
1150 db->tx_packet_cnt = 0;
1151 db->rx_avail_cnt = 0;
1152 db->link_failed = 1;
1153 db->init=1;
1154 db->wait_reset = 0;
1155 }
1156
1157
1158 /*
1159 * Dynamic reset the ULI526X board
1160 * Stop ULI526X board
1161 * Free Tx/Rx allocated memory
1162 * Reset ULI526X board
1163 * Re-initialize ULI526X board
1164 */
1165
1166 static void uli526x_dynamic_reset(struct net_device *dev)
1167 {
1168 ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1169
1170 uli526x_reset_prepare(dev);
1171
1172 /* Re-initialize ULI526X board */
1173 uli526x_init(dev);
1174
1175 /* Restart upper layer interface */
1176 netif_wake_queue(dev);
1177 }
1178
1179
1180 #ifdef CONFIG_PM
1181
1182 /*
1183 * Suspend the interface.
1184 */
1185
1186 static int uli526x_suspend(struct pci_dev *pdev, pm_message_t state)
1187 {
1188 struct net_device *dev = pci_get_drvdata(pdev);
1189 pci_power_t power_state;
1190 int err;
1191
1192 ULI526X_DBUG(0, "uli526x_suspend", 0);
1193
1194 if (!netdev_priv(dev))
1195 return 0;
1196
1197 pci_save_state(pdev);
1198
1199 if (!netif_running(dev))
1200 return 0;
1201
1202 netif_device_detach(dev);
1203 uli526x_reset_prepare(dev);
1204
1205 power_state = pci_choose_state(pdev, state);
1206 pci_enable_wake(pdev, power_state, 0);
1207 err = pci_set_power_state(pdev, power_state);
1208 if (err) {
1209 netif_device_attach(dev);
1210 /* Re-initialize ULI526X board */
1211 uli526x_init(dev);
1212 /* Restart upper layer interface */
1213 netif_wake_queue(dev);
1214 }
1215
1216 return err;
1217 }
1218
1219 /*
1220 * Resume the interface.
1221 */
1222
1223 static int uli526x_resume(struct pci_dev *pdev)
1224 {
1225 struct net_device *dev = pci_get_drvdata(pdev);
1226 int err;
1227
1228 ULI526X_DBUG(0, "uli526x_resume", 0);
1229
1230 if (!netdev_priv(dev))
1231 return 0;
1232
1233 pci_restore_state(pdev);
1234
1235 if (!netif_running(dev))
1236 return 0;
1237
1238 err = pci_set_power_state(pdev, PCI_D0);
1239 if (err) {
1240 printk(KERN_WARNING "%s: Could not put device into D0\n",
1241 dev->name);
1242 return err;
1243 }
1244
1245 netif_device_attach(dev);
1246 /* Re-initialize ULI526X board */
1247 uli526x_init(dev);
1248 /* Restart upper layer interface */
1249 netif_wake_queue(dev);
1250
1251 return 0;
1252 }
1253
1254 #else /* !CONFIG_PM */
1255
1256 #define uli526x_suspend NULL
1257 #define uli526x_resume NULL
1258
1259 #endif /* !CONFIG_PM */
1260
1261
1262 /*
1263 * free all allocated rx buffer
1264 */
1265
1266 static void uli526x_free_rxbuffer(struct uli526x_board_info * db)
1267 {
1268 ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1269
1270 /* free allocated rx buffer */
1271 while (db->rx_avail_cnt) {
1272 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1273 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1274 db->rx_avail_cnt--;
1275 }
1276 }
1277
1278
1279 /*
1280 * Reuse the SK buffer
1281 */
1282
1283 static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb)
1284 {
1285 struct rx_desc *rxptr = db->rx_insert_ptr;
1286
1287 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1288 rxptr->rx_skb_ptr = skb;
1289 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1290 skb_tail_pointer(skb),
1291 RX_ALLOC_SIZE,
1292 PCI_DMA_FROMDEVICE));
1293 wmb();
1294 rxptr->rdes0 = cpu_to_le32(0x80000000);
1295 db->rx_avail_cnt++;
1296 db->rx_insert_ptr = rxptr->next_rx_desc;
1297 } else
1298 ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1299 }
1300
1301
1302 /*
1303 * Initialize transmit/Receive descriptor
1304 * Using Chain structure, and allocate Tx/Rx buffer
1305 */
1306
1307 static void uli526x_descriptor_init(struct uli526x_board_info *db, unsigned long ioaddr)
1308 {
1309 struct tx_desc *tmp_tx;
1310 struct rx_desc *tmp_rx;
1311 unsigned char *tmp_buf;
1312 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1313 dma_addr_t tmp_buf_dma;
1314 int i;
1315
1316 ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1317
1318 /* tx descriptor start pointer */
1319 db->tx_insert_ptr = db->first_tx_desc;
1320 db->tx_remove_ptr = db->first_tx_desc;
1321 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1322
1323 /* rx descriptor start pointer */
1324 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1325 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1326 db->rx_insert_ptr = db->first_rx_desc;
1327 db->rx_ready_ptr = db->first_rx_desc;
1328 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1329
1330 /* Init Transmit chain */
1331 tmp_buf = db->buf_pool_start;
1332 tmp_buf_dma = db->buf_pool_dma_start;
1333 tmp_tx_dma = db->first_tx_desc_dma;
1334 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1335 tmp_tx->tx_buf_ptr = tmp_buf;
1336 tmp_tx->tdes0 = cpu_to_le32(0);
1337 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1338 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1339 tmp_tx_dma += sizeof(struct tx_desc);
1340 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1341 tmp_tx->next_tx_desc = tmp_tx + 1;
1342 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1343 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1344 }
1345 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1346 tmp_tx->next_tx_desc = db->first_tx_desc;
1347
1348 /* Init Receive descriptor chain */
1349 tmp_rx_dma=db->first_rx_desc_dma;
1350 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1351 tmp_rx->rdes0 = cpu_to_le32(0);
1352 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1353 tmp_rx_dma += sizeof(struct rx_desc);
1354 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1355 tmp_rx->next_rx_desc = tmp_rx + 1;
1356 }
1357 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1358 tmp_rx->next_rx_desc = db->first_rx_desc;
1359
1360 /* pre-allocate Rx buffer */
1361 allocate_rx_buffer(db);
1362 }
1363
1364
1365 /*
1366 * Update CR6 value
1367 * Firstly stop ULI526X, then written value and start
1368 */
1369
1370 static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1371 {
1372
1373 outl(cr6_data, ioaddr + DCR6);
1374 udelay(5);
1375 }
1376
1377
1378 /*
1379 * Send a setup frame for M5261/M5263
1380 * This setup frame initialize ULI526X address filter mode
1381 */
1382
1383 #ifdef __BIG_ENDIAN
1384 #define FLT_SHIFT 16
1385 #else
1386 #define FLT_SHIFT 0
1387 #endif
1388
1389 static void send_filter_frame(struct net_device *dev, int mc_cnt)
1390 {
1391 struct uli526x_board_info *db = netdev_priv(dev);
1392 struct dev_mc_list *mcptr;
1393 struct tx_desc *txptr;
1394 u16 * addrptr;
1395 u32 * suptr;
1396 int i;
1397
1398 ULI526X_DBUG(0, "send_filter_frame()", 0);
1399
1400 txptr = db->tx_insert_ptr;
1401 suptr = (u32 *) txptr->tx_buf_ptr;
1402
1403 /* Node address */
1404 addrptr = (u16 *) dev->dev_addr;
1405 *suptr++ = addrptr[0] << FLT_SHIFT;
1406 *suptr++ = addrptr[1] << FLT_SHIFT;
1407 *suptr++ = addrptr[2] << FLT_SHIFT;
1408
1409 /* broadcast address */
1410 *suptr++ = 0xffff << FLT_SHIFT;
1411 *suptr++ = 0xffff << FLT_SHIFT;
1412 *suptr++ = 0xffff << FLT_SHIFT;
1413
1414 /* fit the multicast address */
1415 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1416 addrptr = (u16 *) mcptr->dmi_addr;
1417 *suptr++ = addrptr[0] << FLT_SHIFT;
1418 *suptr++ = addrptr[1] << FLT_SHIFT;
1419 *suptr++ = addrptr[2] << FLT_SHIFT;
1420 }
1421
1422 for (; i<14; i++) {
1423 *suptr++ = 0xffff << FLT_SHIFT;
1424 *suptr++ = 0xffff << FLT_SHIFT;
1425 *suptr++ = 0xffff << FLT_SHIFT;
1426 }
1427
1428 /* prepare the setup frame */
1429 db->tx_insert_ptr = txptr->next_tx_desc;
1430 txptr->tdes1 = cpu_to_le32(0x890000c0);
1431
1432 /* Resource Check and Send the setup packet */
1433 if (db->tx_packet_cnt < TX_DESC_CNT) {
1434 /* Resource Empty */
1435 db->tx_packet_cnt++;
1436 txptr->tdes0 = cpu_to_le32(0x80000000);
1437 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1438 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1439 update_cr6(db->cr6_data, dev->base_addr);
1440 dev->trans_start = jiffies;
1441 } else
1442 printk(KERN_ERR DRV_NAME ": No Tx resource - Send_filter_frame!\n");
1443 }
1444
1445
1446 /*
1447 * Allocate rx buffer,
1448 * As possible as allocate maxiumn Rx buffer
1449 */
1450
1451 static void allocate_rx_buffer(struct uli526x_board_info *db)
1452 {
1453 struct rx_desc *rxptr;
1454 struct sk_buff *skb;
1455
1456 rxptr = db->rx_insert_ptr;
1457
1458 while(db->rx_avail_cnt < RX_DESC_CNT) {
1459 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1460 break;
1461 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1462 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1463 skb_tail_pointer(skb),
1464 RX_ALLOC_SIZE,
1465 PCI_DMA_FROMDEVICE));
1466 wmb();
1467 rxptr->rdes0 = cpu_to_le32(0x80000000);
1468 rxptr = rxptr->next_rx_desc;
1469 db->rx_avail_cnt++;
1470 }
1471
1472 db->rx_insert_ptr = rxptr;
1473 }
1474
1475
1476 /*
1477 * Read one word data from the serial ROM
1478 */
1479
1480 static u16 read_srom_word(long ioaddr, int offset)
1481 {
1482 int i;
1483 u16 srom_data = 0;
1484 long cr9_ioaddr = ioaddr + DCR9;
1485
1486 outl(CR9_SROM_READ, cr9_ioaddr);
1487 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1488
1489 /* Send the Read Command 110b */
1490 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1491 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1492 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1493
1494 /* Send the offset */
1495 for (i = 5; i >= 0; i--) {
1496 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1497 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1498 }
1499
1500 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1501
1502 for (i = 16; i > 0; i--) {
1503 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1504 udelay(5);
1505 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1506 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1507 udelay(5);
1508 }
1509
1510 outl(CR9_SROM_READ, cr9_ioaddr);
1511 return srom_data;
1512 }
1513
1514
1515 /*
1516 * Auto sense the media mode
1517 */
1518
1519 static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1520 {
1521 u8 ErrFlag = 0;
1522 u16 phy_mode;
1523
1524 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1525 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1526
1527 if ( (phy_mode & 0x24) == 0x24 ) {
1528
1529 phy_mode = ((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)<<7);
1530 if(phy_mode&0x8000)
1531 phy_mode = 0x8000;
1532 else if(phy_mode&0x4000)
1533 phy_mode = 0x4000;
1534 else if(phy_mode&0x2000)
1535 phy_mode = 0x2000;
1536 else
1537 phy_mode = 0x1000;
1538
1539 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1540 switch (phy_mode) {
1541 case 0x1000: db->op_mode = ULI526X_10MHF; break;
1542 case 0x2000: db->op_mode = ULI526X_10MFD; break;
1543 case 0x4000: db->op_mode = ULI526X_100MHF; break;
1544 case 0x8000: db->op_mode = ULI526X_100MFD; break;
1545 default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break;
1546 }
1547 } else {
1548 db->op_mode = ULI526X_10MHF;
1549 ULI526X_DBUG(0, "Link Failed :", phy_mode);
1550 ErrFlag = 1;
1551 }
1552
1553 return ErrFlag;
1554 }
1555
1556
1557 /*
1558 * Set 10/100 phyxcer capability
1559 * AUTO mode : phyxcer register4 is NIC capability
1560 * Force mode: phyxcer register4 is the force media
1561 */
1562
1563 static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1564 {
1565 u16 phy_reg;
1566
1567 /* Phyxcer capability setting */
1568 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1569
1570 if (db->media_mode & ULI526X_AUTO) {
1571 /* AUTO Mode */
1572 phy_reg |= db->PHY_reg4;
1573 } else {
1574 /* Force Mode */
1575 switch(db->media_mode) {
1576 case ULI526X_10MHF: phy_reg |= 0x20; break;
1577 case ULI526X_10MFD: phy_reg |= 0x40; break;
1578 case ULI526X_100MHF: phy_reg |= 0x80; break;
1579 case ULI526X_100MFD: phy_reg |= 0x100; break;
1580 }
1581
1582 }
1583
1584 /* Write new capability to Phyxcer Reg4 */
1585 if ( !(phy_reg & 0x01e0)) {
1586 phy_reg|=db->PHY_reg4;
1587 db->media_mode|=ULI526X_AUTO;
1588 }
1589 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1590
1591 /* Restart Auto-Negotiation */
1592 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1593 udelay(50);
1594 }
1595
1596
1597 /*
1598 * Process op-mode
1599 AUTO mode : PHY controller in Auto-negotiation Mode
1600 * Force mode: PHY controller in force mode with HUB
1601 * N-way force capability with SWITCH
1602 */
1603
1604 static void uli526x_process_mode(struct uli526x_board_info *db)
1605 {
1606 u16 phy_reg;
1607
1608 /* Full Duplex Mode Check */
1609 if (db->op_mode & 0x4)
1610 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1611 else
1612 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1613
1614 update_cr6(db->cr6_data, db->ioaddr);
1615
1616 /* 10/100M phyxcer force mode need */
1617 if ( !(db->media_mode & 0x8)) {
1618 /* Forece Mode */
1619 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1620 if ( !(phy_reg & 0x1) ) {
1621 /* parter without N-Way capability */
1622 phy_reg = 0x0;
1623 switch(db->op_mode) {
1624 case ULI526X_10MHF: phy_reg = 0x0; break;
1625 case ULI526X_10MFD: phy_reg = 0x100; break;
1626 case ULI526X_100MHF: phy_reg = 0x2000; break;
1627 case ULI526X_100MFD: phy_reg = 0x2100; break;
1628 }
1629 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
1630 }
1631 }
1632 }
1633
1634
1635 /*
1636 * Write a word to Phy register
1637 */
1638
1639 static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id)
1640 {
1641 u16 i;
1642 unsigned long ioaddr;
1643
1644 if(chip_id == PCI_ULI5263_ID)
1645 {
1646 phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
1647 return;
1648 }
1649 /* M5261/M5263 Chip */
1650 ioaddr = iobase + DCR9;
1651
1652 /* Send 33 synchronization clock to Phy controller */
1653 for (i = 0; i < 35; i++)
1654 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1655
1656 /* Send start command(01) to Phy */
1657 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1658 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1659
1660 /* Send write command(01) to Phy */
1661 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1662 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1663
1664 /* Send Phy address */
1665 for (i = 0x10; i > 0; i = i >> 1)
1666 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1667
1668 /* Send register address */
1669 for (i = 0x10; i > 0; i = i >> 1)
1670 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1671
1672 /* written trasnition */
1673 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1674 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1675
1676 /* Write a word data to PHY controller */
1677 for ( i = 0x8000; i > 0; i >>= 1)
1678 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1679
1680 }
1681
1682
1683 /*
1684 * Read a word data from phy register
1685 */
1686
1687 static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1688 {
1689 int i;
1690 u16 phy_data;
1691 unsigned long ioaddr;
1692
1693 if(chip_id == PCI_ULI5263_ID)
1694 return phy_readby_cr10(iobase, phy_addr, offset);
1695 /* M5261/M5263 Chip */
1696 ioaddr = iobase + DCR9;
1697
1698 /* Send 33 synchronization clock to Phy controller */
1699 for (i = 0; i < 35; i++)
1700 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1701
1702 /* Send start command(01) to Phy */
1703 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1704 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1705
1706 /* Send read command(10) to Phy */
1707 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1708 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1709
1710 /* Send Phy address */
1711 for (i = 0x10; i > 0; i = i >> 1)
1712 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1713
1714 /* Send register address */
1715 for (i = 0x10; i > 0; i = i >> 1)
1716 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1717
1718 /* Skip transition state */
1719 phy_read_1bit(ioaddr, chip_id);
1720
1721 /* read 16bit data */
1722 for (phy_data = 0, i = 0; i < 16; i++) {
1723 phy_data <<= 1;
1724 phy_data |= phy_read_1bit(ioaddr, chip_id);
1725 }
1726
1727 return phy_data;
1728 }
1729
1730 static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
1731 {
1732 unsigned long ioaddr,cr10_value;
1733
1734 ioaddr = iobase + DCR10;
1735 cr10_value = phy_addr;
1736 cr10_value = (cr10_value<<5) + offset;
1737 cr10_value = (cr10_value<<16) + 0x08000000;
1738 outl(cr10_value,ioaddr);
1739 udelay(1);
1740 while(1)
1741 {
1742 cr10_value = inl(ioaddr);
1743 if(cr10_value&0x10000000)
1744 break;
1745 }
1746 return (cr10_value&0x0ffff);
1747 }
1748
1749 static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data)
1750 {
1751 unsigned long ioaddr,cr10_value;
1752
1753 ioaddr = iobase + DCR10;
1754 cr10_value = phy_addr;
1755 cr10_value = (cr10_value<<5) + offset;
1756 cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
1757 outl(cr10_value,ioaddr);
1758 udelay(1);
1759 }
1760 /*
1761 * Write one bit data to Phy Controller
1762 */
1763
1764 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
1765 {
1766 outl(phy_data , ioaddr); /* MII Clock Low */
1767 udelay(1);
1768 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1769 udelay(1);
1770 outl(phy_data , ioaddr); /* MII Clock Low */
1771 udelay(1);
1772 }
1773
1774
1775 /*
1776 * Read one bit phy data from PHY controller
1777 */
1778
1779 static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
1780 {
1781 u16 phy_data;
1782
1783 outl(0x50000 , ioaddr);
1784 udelay(1);
1785 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1786 outl(0x40000 , ioaddr);
1787 udelay(1);
1788
1789 return phy_data;
1790 }
1791
1792
1793 static struct pci_device_id uli526x_pci_tbl[] = {
1794 { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID },
1795 { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID },
1796 { 0, }
1797 };
1798 MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl);
1799
1800
1801 static struct pci_driver uli526x_driver = {
1802 .name = "uli526x",
1803 .id_table = uli526x_pci_tbl,
1804 .probe = uli526x_init_one,
1805 .remove = __devexit_p(uli526x_remove_one),
1806 .suspend = uli526x_suspend,
1807 .resume = uli526x_resume,
1808 };
1809
1810 MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1811 MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1812 MODULE_LICENSE("GPL");
1813
1814 module_param(debug, int, 0644);
1815 module_param(mode, int, 0);
1816 module_param(cr6set, int, 0);
1817 MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)");
1818 MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1819
1820 /* Description:
1821 * when user used insmod to add module, system invoked init_module()
1822 * to register the services.
1823 */
1824
1825 static int __init uli526x_init_module(void)
1826 {
1827
1828 printk(version);
1829 printed_version = 1;
1830
1831 ULI526X_DBUG(0, "init_module() ", debug);
1832
1833 if (debug)
1834 uli526x_debug = debug; /* set debug flag */
1835 if (cr6set)
1836 uli526x_cr6_user_set = cr6set;
1837
1838 switch (mode) {
1839 case ULI526X_10MHF:
1840 case ULI526X_100MHF:
1841 case ULI526X_10MFD:
1842 case ULI526X_100MFD:
1843 uli526x_media_mode = mode;
1844 break;
1845 default:
1846 uli526x_media_mode = ULI526X_AUTO;
1847 break;
1848 }
1849
1850 return pci_register_driver(&uli526x_driver);
1851 }
1852
1853
1854 /*
1855 * Description:
1856 * when user used rmmod to delete module, system invoked clean_module()
1857 * to un-register all registered services.
1858 */
1859
1860 static void __exit uli526x_cleanup_module(void)
1861 {
1862 ULI526X_DBUG(0, "uli526x_clean_module() ", debug);
1863 pci_unregister_driver(&uli526x_driver);
1864 }
1865
1866 module_init(uli526x_init_module);
1867 module_exit(uli526x_cleanup_module);
Support for the Chinese Samsung S3C2440 based development boards