1 /* ------------------------------------------------------------------------- */
2 /* i2c-iop3xx.c i2c driver algorithms for Intel XScale IOP3xx & IXP46x */
3 /* ------------------------------------------------------------------------- */
4 /* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
5 * <Peter dot Milne at D hyphen TACQ dot com>
7 * With acknowledgements to i2c-algo-ibm_ocp.c by
8 * Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com
10 * And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund:
12 * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund
14 * And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>,
15 * Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com>
17 * Major cleanup by Deepak Saxena <dsaxena@plexity.net>, 01/2005:
19 * - Use driver model to pass per-chip info instead of hardcoding and #ifdefs
20 * - Use ioremap/__raw_readl/__raw_writel instead of direct dereference
21 * - Make it work with IXP46x chips
22 * - Cleanup function names, coding style, etc
24 * - writing to slave address causes latchup on iop331.
25 * fix: driver refuses to address self.
27 * This program is free software; you can redistribute it and/or modify
28 * it under the terms of the GNU General Public License as published by
29 * the Free Software Foundation, version 2.
32 #include <linux/interrupt.h>
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/delay.h>
36 #include <linux/slab.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/sched.h>
40 #include <linux/platform_device.h>
41 #include <linux/i2c.h>
45 #include "i2c-iop3xx.h"
47 /* global unit counter */
50 static inline unsigned char
51 iic_cook_addr(struct i2c_msg
*msg
)
55 addr
= (msg
->addr
<< 1);
57 if (msg
->flags
& I2C_M_RD
)
63 if (msg
->flags
& I2C_M_REV_DIR_ADDR
)
70 iop3xx_i2c_reset(struct i2c_algo_iop3xx_data
*iop3xx_adap
)
72 /* Follows devman 9.3 */
73 __raw_writel(IOP3XX_ICR_UNIT_RESET
, iop3xx_adap
->ioaddr
+ CR_OFFSET
);
74 __raw_writel(IOP3XX_ISR_CLEARBITS
, iop3xx_adap
->ioaddr
+ SR_OFFSET
);
75 __raw_writel(0, iop3xx_adap
->ioaddr
+ CR_OFFSET
);
79 iop3xx_i2c_enable(struct i2c_algo_iop3xx_data
*iop3xx_adap
)
81 u32 cr
= IOP3XX_ICR_GCD
| IOP3XX_ICR_SCLEN
| IOP3XX_ICR_UE
;
84 * Every time unit enable is asserted, GPOD needs to be cleared
85 * on IOP321 to avoid data corruption on the bus.
87 #ifdef CONFIG_ARCH_IOP321
88 #define IOP321_GPOD_I2C0 0x00c0 /* clear these bits to enable ch0 */
89 #define IOP321_GPOD_I2C1 0x0030 /* clear these bits to enable ch1 */
91 *IOP321_GPOD
&= (iop3xx_adap
->id
== 0) ? ~IOP321_GPOD_I2C0
:
94 /* NB SR bits not same position as CR IE bits :-( */
95 iop3xx_adap
->SR_enabled
=
96 IOP3XX_ISR_ALD
| IOP3XX_ISR_BERRD
|
97 IOP3XX_ISR_RXFULL
| IOP3XX_ISR_TXEMPTY
;
99 cr
|= IOP3XX_ICR_ALD_IE
| IOP3XX_ICR_BERR_IE
|
100 IOP3XX_ICR_RXFULL_IE
| IOP3XX_ICR_TXEMPTY_IE
;
102 __raw_writel(cr
, iop3xx_adap
->ioaddr
+ CR_OFFSET
);
106 iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data
*iop3xx_adap
)
108 unsigned long cr
= __raw_readl(iop3xx_adap
->ioaddr
+ CR_OFFSET
);
110 cr
&= ~(IOP3XX_ICR_MSTART
| IOP3XX_ICR_TBYTE
|
111 IOP3XX_ICR_MSTOP
| IOP3XX_ICR_SCLEN
);
113 __raw_writel(cr
, iop3xx_adap
->ioaddr
+ CR_OFFSET
);
117 * NB: the handler has to clear the source of the interrupt!
118 * Then it passes the SR flags of interest to BH via adap data
121 iop3xx_i2c_irq_handler(int this_irq
, void *dev_id
, struct pt_regs
*regs
)
123 struct i2c_algo_iop3xx_data
*iop3xx_adap
= dev_id
;
124 u32 sr
= __raw_readl(iop3xx_adap
->ioaddr
+ SR_OFFSET
);
126 if ((sr
&= iop3xx_adap
->SR_enabled
)) {
127 __raw_writel(sr
, iop3xx_adap
->ioaddr
+ SR_OFFSET
);
128 iop3xx_adap
->SR_received
|= sr
;
129 wake_up_interruptible(&iop3xx_adap
->waitq
);
134 /* check all error conditions, clear them , report most important */
136 iop3xx_i2c_error(u32 sr
)
140 if ((sr
& IOP3XX_ISR_BERRD
)) {
141 if ( !rc
) rc
= -I2C_ERR_BERR
;
143 if ((sr
& IOP3XX_ISR_ALD
)) {
144 if ( !rc
) rc
= -I2C_ERR_ALD
;
150 iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data
*iop3xx_adap
)
155 spin_lock_irqsave(&iop3xx_adap
->lock
, flags
);
156 sr
= iop3xx_adap
->SR_received
;
157 iop3xx_adap
->SR_received
= 0;
158 spin_unlock_irqrestore(&iop3xx_adap
->lock
, flags
);
164 * sleep until interrupted, then recover and analyse the SR
167 typedef int (* compare_func
)(unsigned test
, unsigned mask
);
168 /* returns 1 on correct comparison */
171 iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data
*iop3xx_adap
,
172 unsigned flags
, unsigned* status
,
173 compare_func compare
)
181 interrupted
= wait_event_interruptible_timeout (
183 (done
= compare( sr
= iop3xx_i2c_get_srstat(iop3xx_adap
) ,flags
)),
186 if ((rc
= iop3xx_i2c_error(sr
)) < 0) {
189 } else if (!interrupted
) {
201 * Concrete compare_funcs
204 all_bits_clear(unsigned test
, unsigned mask
)
206 return (test
& mask
) == 0;
210 any_bits_set(unsigned test
, unsigned mask
)
212 return (test
& mask
) != 0;
216 iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data
*iop3xx_adap
, int *status
)
218 return iop3xx_i2c_wait_event(
220 IOP3XX_ISR_TXEMPTY
| IOP3XX_ISR_ALD
| IOP3XX_ISR_BERRD
,
221 status
, any_bits_set
);
225 iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data
*iop3xx_adap
, int *status
)
227 return iop3xx_i2c_wait_event(
229 IOP3XX_ISR_RXFULL
| IOP3XX_ISR_ALD
| IOP3XX_ISR_BERRD
,
230 status
, any_bits_set
);
234 iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data
*iop3xx_adap
, int *status
)
236 return iop3xx_i2c_wait_event(
237 iop3xx_adap
, IOP3XX_ISR_UNITBUSY
, status
, all_bits_clear
);
241 iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data
*iop3xx_adap
,
244 unsigned long cr
= __raw_readl(iop3xx_adap
->ioaddr
+ CR_OFFSET
);
248 /* avoid writing to my slave address (hangs on 80331),
249 * forbidden in Intel developer manual
251 if (msg
->addr
== MYSAR
) {
255 __raw_writel(iic_cook_addr(msg
), iop3xx_adap
->ioaddr
+ DBR_OFFSET
);
257 cr
&= ~(IOP3XX_ICR_MSTOP
| IOP3XX_ICR_NACK
);
258 cr
|= IOP3XX_ICR_MSTART
| IOP3XX_ICR_TBYTE
;
260 __raw_writel(cr
, iop3xx_adap
->ioaddr
+ CR_OFFSET
);
261 rc
= iop3xx_i2c_wait_tx_done(iop3xx_adap
, &status
);
267 iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data
*iop3xx_adap
, char byte
,
270 unsigned long cr
= __raw_readl(iop3xx_adap
->ioaddr
+ CR_OFFSET
);
274 __raw_writel(byte
, iop3xx_adap
->ioaddr
+ DBR_OFFSET
);
275 cr
&= ~IOP3XX_ICR_MSTART
;
277 cr
|= IOP3XX_ICR_MSTOP
;
279 cr
&= ~IOP3XX_ICR_MSTOP
;
281 cr
|= IOP3XX_ICR_TBYTE
;
282 __raw_writel(cr
, iop3xx_adap
->ioaddr
+ CR_OFFSET
);
283 rc
= iop3xx_i2c_wait_tx_done(iop3xx_adap
, &status
);
289 iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data
*iop3xx_adap
, char* byte
,
292 unsigned long cr
= __raw_readl(iop3xx_adap
->ioaddr
+ CR_OFFSET
);
296 cr
&= ~IOP3XX_ICR_MSTART
;
299 cr
|= IOP3XX_ICR_MSTOP
| IOP3XX_ICR_NACK
;
301 cr
&= ~(IOP3XX_ICR_MSTOP
| IOP3XX_ICR_NACK
);
303 cr
|= IOP3XX_ICR_TBYTE
;
304 __raw_writel(cr
, iop3xx_adap
->ioaddr
+ CR_OFFSET
);
306 rc
= iop3xx_i2c_wait_rx_done(iop3xx_adap
, &status
);
308 *byte
= __raw_readl(iop3xx_adap
->ioaddr
+ DBR_OFFSET
);
314 iop3xx_i2c_writebytes(struct i2c_adapter
*i2c_adap
, const char *buf
, int count
)
316 struct i2c_algo_iop3xx_data
*iop3xx_adap
= i2c_adap
->algo_data
;
320 for (ii
= 0; rc
== 0 && ii
!= count
; ++ii
)
321 rc
= iop3xx_i2c_write_byte(iop3xx_adap
, buf
[ii
], ii
==count
-1);
326 iop3xx_i2c_readbytes(struct i2c_adapter
*i2c_adap
, char *buf
, int count
)
328 struct i2c_algo_iop3xx_data
*iop3xx_adap
= i2c_adap
->algo_data
;
332 for (ii
= 0; rc
== 0 && ii
!= count
; ++ii
)
333 rc
= iop3xx_i2c_read_byte(iop3xx_adap
, &buf
[ii
], ii
==count
-1);
339 * Description: This function implements combined transactions. Combined
340 * transactions consist of combinations of reading and writing blocks of data.
341 * FROM THE SAME ADDRESS
342 * Each transfer (i.e. a read or a write) is separated by a repeated start
346 iop3xx_i2c_handle_msg(struct i2c_adapter
*i2c_adap
, struct i2c_msg
* pmsg
)
348 struct i2c_algo_iop3xx_data
*iop3xx_adap
= i2c_adap
->algo_data
;
351 rc
= iop3xx_i2c_send_target_addr(iop3xx_adap
, pmsg
);
356 if ((pmsg
->flags
&I2C_M_RD
)) {
357 return iop3xx_i2c_readbytes(i2c_adap
, pmsg
->buf
, pmsg
->len
);
359 return iop3xx_i2c_writebytes(i2c_adap
, pmsg
->buf
, pmsg
->len
);
364 * master_xfer() - main read/write entry
367 iop3xx_i2c_master_xfer(struct i2c_adapter
*i2c_adap
, struct i2c_msg
*msgs
,
370 struct i2c_algo_iop3xx_data
*iop3xx_adap
= i2c_adap
->algo_data
;
375 iop3xx_i2c_wait_idle(iop3xx_adap
, &status
);
376 iop3xx_i2c_reset(iop3xx_adap
);
377 iop3xx_i2c_enable(iop3xx_adap
);
379 for (im
= 0; ret
== 0 && im
!= num
; im
++) {
380 ret
= iop3xx_i2c_handle_msg(i2c_adap
, &msgs
[im
]);
383 iop3xx_i2c_transaction_cleanup(iop3xx_adap
);
392 iop3xx_i2c_algo_control(struct i2c_adapter
*adapter
, unsigned int cmd
,
399 iop3xx_i2c_func(struct i2c_adapter
*adap
)
401 return I2C_FUNC_I2C
| I2C_FUNC_SMBUS_EMUL
;
404 static const struct i2c_algorithm iop3xx_i2c_algo
= {
405 .master_xfer
= iop3xx_i2c_master_xfer
,
406 .algo_control
= iop3xx_i2c_algo_control
,
407 .functionality
= iop3xx_i2c_func
,
411 iop3xx_i2c_remove(struct platform_device
*pdev
)
413 struct i2c_adapter
*padapter
= platform_get_drvdata(pdev
);
414 struct i2c_algo_iop3xx_data
*adapter_data
=
415 (struct i2c_algo_iop3xx_data
*)padapter
->algo_data
;
416 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
417 unsigned long cr
= __raw_readl(adapter_data
->ioaddr
+ CR_OFFSET
);
420 * Disable the actual HW unit
422 cr
&= ~(IOP3XX_ICR_ALD_IE
| IOP3XX_ICR_BERR_IE
|
423 IOP3XX_ICR_RXFULL_IE
| IOP3XX_ICR_TXEMPTY_IE
);
424 __raw_writel(cr
, adapter_data
->ioaddr
+ CR_OFFSET
);
426 iounmap((void __iomem
*)adapter_data
->ioaddr
);
427 release_mem_region(res
->start
, IOP3XX_I2C_IO_SIZE
);
431 platform_set_drvdata(pdev
, NULL
);
437 iop3xx_i2c_probe(struct platform_device
*pdev
)
439 struct resource
*res
;
441 struct i2c_adapter
*new_adapter
;
442 struct i2c_algo_iop3xx_data
*adapter_data
;
444 new_adapter
= kzalloc(sizeof(struct i2c_adapter
), GFP_KERNEL
);
450 adapter_data
= kzalloc(sizeof(struct i2c_algo_iop3xx_data
), GFP_KERNEL
);
456 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
462 if (!request_mem_region(res
->start
, IOP3XX_I2C_IO_SIZE
, pdev
->name
)) {
467 /* set the adapter enumeration # */
468 adapter_data
->id
= i2c_id
++;
470 adapter_data
->ioaddr
= (u32
)ioremap(res
->start
, IOP3XX_I2C_IO_SIZE
);
471 if (!adapter_data
->ioaddr
) {
476 irq
= platform_get_irq(pdev
, 0);
481 ret
= request_irq(irq
, iop3xx_i2c_irq_handler
, 0,
482 pdev
->name
, adapter_data
);
489 memcpy(new_adapter
->name
, pdev
->name
, strlen(pdev
->name
));
490 new_adapter
->id
= I2C_HW_IOP3XX
;
491 new_adapter
->owner
= THIS_MODULE
;
492 new_adapter
->dev
.parent
= &pdev
->dev
;
495 * Default values...should these come in from board code?
497 new_adapter
->timeout
= 100;
498 new_adapter
->retries
= 3;
499 new_adapter
->algo
= &iop3xx_i2c_algo
;
501 init_waitqueue_head(&adapter_data
->waitq
);
502 spin_lock_init(&adapter_data
->lock
);
504 iop3xx_i2c_reset(adapter_data
);
505 iop3xx_i2c_enable(adapter_data
);
507 platform_set_drvdata(pdev
, new_adapter
);
508 new_adapter
->algo_data
= adapter_data
;
510 i2c_add_adapter(new_adapter
);
515 iounmap((void __iomem
*)adapter_data
->ioaddr
);
518 release_mem_region(res
->start
, IOP3XX_I2C_IO_SIZE
);
531 static struct platform_driver iop3xx_i2c_driver
= {
532 .probe
= iop3xx_i2c_probe
,
533 .remove
= iop3xx_i2c_remove
,
535 .owner
= THIS_MODULE
,
536 .name
= "IOP3xx-I2C",
541 i2c_iop3xx_init (void)
543 return platform_driver_register(&iop3xx_i2c_driver
);
547 i2c_iop3xx_exit (void)
549 platform_driver_unregister(&iop3xx_i2c_driver
);
553 module_init (i2c_iop3xx_init
);
554 module_exit (i2c_iop3xx_exit
);
556 MODULE_AUTHOR("D-TACQ Solutions Ltd <www.d-tacq.com>");
557 MODULE_DESCRIPTION("IOP3xx iic algorithm and driver");
558 MODULE_LICENSE("GPL");