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ACPI: add ACPICA version in sysfs
[linux-2.6/mini2440.git] / drivers / atm / idt77252.c
blobf40786121948c4bc1cbd7cea1c14291704e1c982
1 /*******************************************************************
2 * ident "$Id: idt77252.c,v 1.2 2001/11/11 08:13:54 ecd Exp $"
3 *
4 * $Author: ecd $
5 * $Date: 2001/11/11 08:13:54 $
6 *
7 * Copyright (c) 2000 ATecoM GmbH
8 *
9 * The author may be reached at ecd@atecom.com.
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
30 *
31 *******************************************************************/
32 static char const rcsid[] =
33 "$Id: idt77252.c,v 1.2 2001/11/11 08:13:54 ecd Exp $";
34
35
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/poison.h>
39 #include <linux/skbuff.h>
40 #include <linux/kernel.h>
41 #include <linux/vmalloc.h>
42 #include <linux/netdevice.h>
43 #include <linux/atmdev.h>
44 #include <linux/atm.h>
45 #include <linux/delay.h>
46 #include <linux/init.h>
47 #include <linux/bitops.h>
48 #include <linux/wait.h>
49 #include <linux/jiffies.h>
50 #include <asm/semaphore.h>
51 #include <asm/io.h>
52 #include <asm/uaccess.h>
53 #include <asm/atomic.h>
54 #include <asm/byteorder.h>
55
56 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
57 #include "suni.h"
58 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
59
60
61 #include "idt77252.h"
62 #include "idt77252_tables.h"
63
64 static unsigned int vpibits = 1;
65
66
67 #define CONFIG_ATM_IDT77252_SEND_IDLE 1
68
69
70 /*
71 * Debug HACKs.
72 */
73 #define DEBUG_MODULE 1
74 #undef HAVE_EEPROM /* does not work, yet. */
75
76 #ifdef CONFIG_ATM_IDT77252_DEBUG
77 static unsigned long debug = DBG_GENERAL;
78 #endif
79
80
81 #define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY)
82
83
84 /*
85 * SCQ Handling.
86 */
87 static struct scq_info *alloc_scq(struct idt77252_dev *, int);
88 static void free_scq(struct idt77252_dev *, struct scq_info *);
89 static int queue_skb(struct idt77252_dev *, struct vc_map *,
90 struct sk_buff *, int oam);
91 static void drain_scq(struct idt77252_dev *, struct vc_map *);
92 static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *);
93 static void fill_scd(struct idt77252_dev *, struct scq_info *, int);
94
95 /*
96 * FBQ Handling.
97 */
98 static int push_rx_skb(struct idt77252_dev *,
99 struct sk_buff *, int queue);
100 static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *);
101 static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *);
102 static void recycle_rx_pool_skb(struct idt77252_dev *,
103 struct rx_pool *);
104 static void add_rx_skb(struct idt77252_dev *, int queue,
105 unsigned int size, unsigned int count);
106
107 /*
108 * RSQ Handling.
109 */
110 static int init_rsq(struct idt77252_dev *);
111 static void deinit_rsq(struct idt77252_dev *);
112 static void idt77252_rx(struct idt77252_dev *);
113
114 /*
115 * TSQ handling.
116 */
117 static int init_tsq(struct idt77252_dev *);
118 static void deinit_tsq(struct idt77252_dev *);
119 static void idt77252_tx(struct idt77252_dev *);
120
121
122 /*
123 * ATM Interface.
124 */
125 static void idt77252_dev_close(struct atm_dev *dev);
126 static int idt77252_open(struct atm_vcc *vcc);
127 static void idt77252_close(struct atm_vcc *vcc);
128 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb);
129 static int idt77252_send_oam(struct atm_vcc *vcc, void *cell,
130 int flags);
131 static void idt77252_phy_put(struct atm_dev *dev, unsigned char value,
132 unsigned long addr);
133 static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr);
134 static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos,
135 int flags);
136 static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos,
137 char *page);
138 static void idt77252_softint(struct work_struct *work);
139
140
141 static struct atmdev_ops idt77252_ops =
142 {
143 .dev_close = idt77252_dev_close,
144 .open = idt77252_open,
145 .close = idt77252_close,
146 .send = idt77252_send,
147 .send_oam = idt77252_send_oam,
148 .phy_put = idt77252_phy_put,
149 .phy_get = idt77252_phy_get,
150 .change_qos = idt77252_change_qos,
151 .proc_read = idt77252_proc_read,
152 .owner = THIS_MODULE
153 };
154
155 static struct idt77252_dev *idt77252_chain = NULL;
156 static unsigned int idt77252_sram_write_errors = 0;
157
158 /*****************************************************************************/
159 /* */
160 /* I/O and Utility Bus */
161 /* */
162 /*****************************************************************************/
163
164 static void
165 waitfor_idle(struct idt77252_dev *card)
166 {
167 u32 stat;
168
169 stat = readl(SAR_REG_STAT);
170 while (stat & SAR_STAT_CMDBZ)
171 stat = readl(SAR_REG_STAT);
172 }
173
174 static u32
175 read_sram(struct idt77252_dev *card, unsigned long addr)
176 {
177 unsigned long flags;
178 u32 value;
179
180 spin_lock_irqsave(&card->cmd_lock, flags);
181 writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD);
182 waitfor_idle(card);
183 value = readl(SAR_REG_DR0);
184 spin_unlock_irqrestore(&card->cmd_lock, flags);
185 return value;
186 }
187
188 static void
189 write_sram(struct idt77252_dev *card, unsigned long addr, u32 value)
190 {
191 unsigned long flags;
192
193 if ((idt77252_sram_write_errors == 0) &&
194 (((addr > card->tst[0] + card->tst_size - 2) &&
195 (addr < card->tst[0] + card->tst_size)) ||
196 ((addr > card->tst[1] + card->tst_size - 2) &&
197 (addr < card->tst[1] + card->tst_size)))) {
198 printk("%s: ERROR: TST JMP section at %08lx written: %08x\n",
199 card->name, addr, value);
200 }
201
202 spin_lock_irqsave(&card->cmd_lock, flags);
203 writel(value, SAR_REG_DR0);
204 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
205 waitfor_idle(card);
206 spin_unlock_irqrestore(&card->cmd_lock, flags);
207 }
208
209 static u8
210 read_utility(void *dev, unsigned long ubus_addr)
211 {
212 struct idt77252_dev *card = dev;
213 unsigned long flags;
214 u8 value;
215
216 if (!card) {
217 printk("Error: No such device.\n");
218 return -1;
219 }
220
221 spin_lock_irqsave(&card->cmd_lock, flags);
222 writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD);
223 waitfor_idle(card);
224 value = readl(SAR_REG_DR0);
225 spin_unlock_irqrestore(&card->cmd_lock, flags);
226 return value;
227 }
228
229 static void
230 write_utility(void *dev, unsigned long ubus_addr, u8 value)
231 {
232 struct idt77252_dev *card = dev;
233 unsigned long flags;
234
235 if (!card) {
236 printk("Error: No such device.\n");
237 return;
238 }
239
240 spin_lock_irqsave(&card->cmd_lock, flags);
241 writel((u32) value, SAR_REG_DR0);
242 writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD);
243 waitfor_idle(card);
244 spin_unlock_irqrestore(&card->cmd_lock, flags);
245 }
246
247 #ifdef HAVE_EEPROM
248 static u32 rdsrtab[] =
249 {
250 SAR_GP_EECS | SAR_GP_EESCLK,
251 0,
252 SAR_GP_EESCLK, /* 0 */
253 0,
254 SAR_GP_EESCLK, /* 0 */
255 0,
256 SAR_GP_EESCLK, /* 0 */
257 0,
258 SAR_GP_EESCLK, /* 0 */
259 0,
260 SAR_GP_EESCLK, /* 0 */
261 SAR_GP_EEDO,
262 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
263 0,
264 SAR_GP_EESCLK, /* 0 */
265 SAR_GP_EEDO,
266 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
267 };
268
269 static u32 wrentab[] =
270 {
271 SAR_GP_EECS | SAR_GP_EESCLK,
272 0,
273 SAR_GP_EESCLK, /* 0 */
274 0,
275 SAR_GP_EESCLK, /* 0 */
276 0,
277 SAR_GP_EESCLK, /* 0 */
278 0,
279 SAR_GP_EESCLK, /* 0 */
280 SAR_GP_EEDO,
281 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
282 SAR_GP_EEDO,
283 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
284 0,
285 SAR_GP_EESCLK, /* 0 */
286 0,
287 SAR_GP_EESCLK /* 0 */
288 };
289
290 static u32 rdtab[] =
291 {
292 SAR_GP_EECS | SAR_GP_EESCLK,
293 0,
294 SAR_GP_EESCLK, /* 0 */
295 0,
296 SAR_GP_EESCLK, /* 0 */
297 0,
298 SAR_GP_EESCLK, /* 0 */
299 0,
300 SAR_GP_EESCLK, /* 0 */
301 0,
302 SAR_GP_EESCLK, /* 0 */
303 0,
304 SAR_GP_EESCLK, /* 0 */
305 SAR_GP_EEDO,
306 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
307 SAR_GP_EEDO,
308 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
309 };
310
311 static u32 wrtab[] =
312 {
313 SAR_GP_EECS | SAR_GP_EESCLK,
314 0,
315 SAR_GP_EESCLK, /* 0 */
316 0,
317 SAR_GP_EESCLK, /* 0 */
318 0,
319 SAR_GP_EESCLK, /* 0 */
320 0,
321 SAR_GP_EESCLK, /* 0 */
322 0,
323 SAR_GP_EESCLK, /* 0 */
324 0,
325 SAR_GP_EESCLK, /* 0 */
326 SAR_GP_EEDO,
327 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
328 0,
329 SAR_GP_EESCLK /* 0 */
330 };
331
332 static u32 clktab[] =
333 {
334 0,
335 SAR_GP_EESCLK,
336 0,
337 SAR_GP_EESCLK,
338 0,
339 SAR_GP_EESCLK,
340 0,
341 SAR_GP_EESCLK,
342 0,
343 SAR_GP_EESCLK,
344 0,
345 SAR_GP_EESCLK,
346 0,
347 SAR_GP_EESCLK,
348 0,
349 SAR_GP_EESCLK,
350 0
351 };
352
353 static u32
354 idt77252_read_gp(struct idt77252_dev *card)
355 {
356 u32 gp;
357
358 gp = readl(SAR_REG_GP);
359 #if 0
360 printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0");
361 #endif
362 return gp;
363 }
364
365 static void
366 idt77252_write_gp(struct idt77252_dev *card, u32 value)
367 {
368 unsigned long flags;
369
370 #if 0
371 printk("WR: %s %s %s\n", value & SAR_GP_EECS ? " " : "/CS",
372 value & SAR_GP_EESCLK ? "HIGH" : "LOW ",
373 value & SAR_GP_EEDO ? "1" : "0");
374 #endif
375
376 spin_lock_irqsave(&card->cmd_lock, flags);
377 waitfor_idle(card);
378 writel(value, SAR_REG_GP);
379 spin_unlock_irqrestore(&card->cmd_lock, flags);
380 }
381
382 static u8
383 idt77252_eeprom_read_status(struct idt77252_dev *card)
384 {
385 u8 byte;
386 u32 gp;
387 int i, j;
388
389 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
390
391 for (i = 0; i < sizeof(rdsrtab)/sizeof(rdsrtab[0]); i++) {
392 idt77252_write_gp(card, gp | rdsrtab[i]);
393 udelay(5);
394 }
395 idt77252_write_gp(card, gp | SAR_GP_EECS);
396 udelay(5);
397
398 byte = 0;
399 for (i = 0, j = 0; i < 8; i++) {
400 byte <<= 1;
401
402 idt77252_write_gp(card, gp | clktab[j++]);
403 udelay(5);
404
405 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
406
407 idt77252_write_gp(card, gp | clktab[j++]);
408 udelay(5);
409 }
410 idt77252_write_gp(card, gp | SAR_GP_EECS);
411 udelay(5);
412
413 return byte;
414 }
415
416 static u8
417 idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset)
418 {
419 u8 byte;
420 u32 gp;
421 int i, j;
422
423 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
424
425 for (i = 0; i < sizeof(rdtab)/sizeof(rdtab[0]); i++) {
426 idt77252_write_gp(card, gp | rdtab[i]);
427 udelay(5);
428 }
429 idt77252_write_gp(card, gp | SAR_GP_EECS);
430 udelay(5);
431
432 for (i = 0, j = 0; i < 8; i++) {
433 idt77252_write_gp(card, gp | clktab[j++] |
434 (offset & 1 ? SAR_GP_EEDO : 0));
435 udelay(5);
436
437 idt77252_write_gp(card, gp | clktab[j++] |
438 (offset & 1 ? SAR_GP_EEDO : 0));
439 udelay(5);
440
441 offset >>= 1;
442 }
443 idt77252_write_gp(card, gp | SAR_GP_EECS);
444 udelay(5);
445
446 byte = 0;
447 for (i = 0, j = 0; i < 8; i++) {
448 byte <<= 1;
449
450 idt77252_write_gp(card, gp | clktab[j++]);
451 udelay(5);
452
453 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
454
455 idt77252_write_gp(card, gp | clktab[j++]);
456 udelay(5);
457 }
458 idt77252_write_gp(card, gp | SAR_GP_EECS);
459 udelay(5);
460
461 return byte;
462 }
463
464 static void
465 idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data)
466 {
467 u32 gp;
468 int i, j;
469
470 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
471
472 for (i = 0; i < sizeof(wrentab)/sizeof(wrentab[0]); i++) {
473 idt77252_write_gp(card, gp | wrentab[i]);
474 udelay(5);
475 }
476 idt77252_write_gp(card, gp | SAR_GP_EECS);
477 udelay(5);
478
479 for (i = 0; i < sizeof(wrtab)/sizeof(wrtab[0]); i++) {
480 idt77252_write_gp(card, gp | wrtab[i]);
481 udelay(5);
482 }
483 idt77252_write_gp(card, gp | SAR_GP_EECS);
484 udelay(5);
485
486 for (i = 0, j = 0; i < 8; i++) {
487 idt77252_write_gp(card, gp | clktab[j++] |
488 (offset & 1 ? SAR_GP_EEDO : 0));
489 udelay(5);
490
491 idt77252_write_gp(card, gp | clktab[j++] |
492 (offset & 1 ? SAR_GP_EEDO : 0));
493 udelay(5);
494
495 offset >>= 1;
496 }
497 idt77252_write_gp(card, gp | SAR_GP_EECS);
498 udelay(5);
499
500 for (i = 0, j = 0; i < 8; i++) {
501 idt77252_write_gp(card, gp | clktab[j++] |
502 (data & 1 ? SAR_GP_EEDO : 0));
503 udelay(5);
504
505 idt77252_write_gp(card, gp | clktab[j++] |
506 (data & 1 ? SAR_GP_EEDO : 0));
507 udelay(5);
508
509 data >>= 1;
510 }
511 idt77252_write_gp(card, gp | SAR_GP_EECS);
512 udelay(5);
513 }
514
515 static void
516 idt77252_eeprom_init(struct idt77252_dev *card)
517 {
518 u32 gp;
519
520 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
521
522 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
523 udelay(5);
524 idt77252_write_gp(card, gp | SAR_GP_EECS);
525 udelay(5);
526 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
527 udelay(5);
528 idt77252_write_gp(card, gp | SAR_GP_EECS);
529 udelay(5);
530 }
531 #endif /* HAVE_EEPROM */
532
533
534 #ifdef CONFIG_ATM_IDT77252_DEBUG
535 static void
536 dump_tct(struct idt77252_dev *card, int index)
537 {
538 unsigned long tct;
539 int i;
540
541 tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE);
542
543 printk("%s: TCT %x:", card->name, index);
544 for (i = 0; i < 8; i++) {
545 printk(" %08x", read_sram(card, tct + i));
546 }
547 printk("\n");
548 }
549
550 static void
551 idt77252_tx_dump(struct idt77252_dev *card)
552 {
553 struct atm_vcc *vcc;
554 struct vc_map *vc;
555 int i;
556
557 printk("%s\n", __FUNCTION__);
558 for (i = 0; i < card->tct_size; i++) {
559 vc = card->vcs[i];
560 if (!vc)
561 continue;
562
563 vcc = NULL;
564 if (vc->rx_vcc)
565 vcc = vc->rx_vcc;
566 else if (vc->tx_vcc)
567 vcc = vc->tx_vcc;
568
569 if (!vcc)
570 continue;
571
572 printk("%s: Connection %d:\n", card->name, vc->index);
573 dump_tct(card, vc->index);
574 }
575 }
576 #endif
577
578
579 /*****************************************************************************/
580 /* */
581 /* SCQ Handling */
582 /* */
583 /*****************************************************************************/
584
585 static int
586 sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue)
587 {
588 struct sb_pool *pool = &card->sbpool[queue];
589 int index;
590
591 index = pool->index;
592 while (pool->skb[index]) {
593 index = (index + 1) & FBQ_MASK;
594 if (index == pool->index)
595 return -ENOBUFS;
596 }
597
598 pool->skb[index] = skb;
599 IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index);
600
601 pool->index = (index + 1) & FBQ_MASK;
602 return 0;
603 }
604
605 static void
606 sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb)
607 {
608 unsigned int queue, index;
609 u32 handle;
610
611 handle = IDT77252_PRV_POOL(skb);
612
613 queue = POOL_QUEUE(handle);
614 if (queue > 3)
615 return;
616
617 index = POOL_INDEX(handle);
618 if (index > FBQ_SIZE - 1)
619 return;
620
621 card->sbpool[queue].skb[index] = NULL;
622 }
623
624 static struct sk_buff *
625 sb_pool_skb(struct idt77252_dev *card, u32 handle)
626 {
627 unsigned int queue, index;
628
629 queue = POOL_QUEUE(handle);
630 if (queue > 3)
631 return NULL;
632
633 index = POOL_INDEX(handle);
634 if (index > FBQ_SIZE - 1)
635 return NULL;
636
637 return card->sbpool[queue].skb[index];
638 }
639
640 static struct scq_info *
641 alloc_scq(struct idt77252_dev *card, int class)
642 {
643 struct scq_info *scq;
644
645 scq = kzalloc(sizeof(struct scq_info), GFP_KERNEL);
646 if (!scq)
647 return NULL;
648 scq->base = pci_alloc_consistent(card->pcidev, SCQ_SIZE,
649 &scq->paddr);
650 if (scq->base == NULL) {
651 kfree(scq);
652 return NULL;
653 }
654 memset(scq->base, 0, SCQ_SIZE);
655
656 scq->next = scq->base;
657 scq->last = scq->base + (SCQ_ENTRIES - 1);
658 atomic_set(&scq->used, 0);
659
660 spin_lock_init(&scq->lock);
661 spin_lock_init(&scq->skblock);
662
663 skb_queue_head_init(&scq->transmit);
664 skb_queue_head_init(&scq->pending);
665
666 TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n",
667 scq->base, scq->next, scq->last, (unsigned long long)scq->paddr);
668
669 return scq;
670 }
671
672 static void
673 free_scq(struct idt77252_dev *card, struct scq_info *scq)
674 {
675 struct sk_buff *skb;
676 struct atm_vcc *vcc;
677
678 pci_free_consistent(card->pcidev, SCQ_SIZE,
679 scq->base, scq->paddr);
680
681 while ((skb = skb_dequeue(&scq->transmit))) {
682 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
683 skb->len, PCI_DMA_TODEVICE);
684
685 vcc = ATM_SKB(skb)->vcc;
686 if (vcc->pop)
687 vcc->pop(vcc, skb);
688 else
689 dev_kfree_skb(skb);
690 }
691
692 while ((skb = skb_dequeue(&scq->pending))) {
693 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
694 skb->len, PCI_DMA_TODEVICE);
695
696 vcc = ATM_SKB(skb)->vcc;
697 if (vcc->pop)
698 vcc->pop(vcc, skb);
699 else
700 dev_kfree_skb(skb);
701 }
702
703 kfree(scq);
704 }
705
706
707 static int
708 push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb)
709 {
710 struct scq_info *scq = vc->scq;
711 unsigned long flags;
712 struct scqe *tbd;
713 int entries;
714
715 TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next);
716
717 atomic_inc(&scq->used);
718 entries = atomic_read(&scq->used);
719 if (entries > (SCQ_ENTRIES - 1)) {
720 atomic_dec(&scq->used);
721 goto out;
722 }
723
724 skb_queue_tail(&scq->transmit, skb);
725
726 spin_lock_irqsave(&vc->lock, flags);
727 if (vc->estimator) {
728 struct atm_vcc *vcc = vc->tx_vcc;
729 struct sock *sk = sk_atm(vcc);
730
731 vc->estimator->cells += (skb->len + 47) / 48;
732 if (atomic_read(&sk->sk_wmem_alloc) >
733 (sk->sk_sndbuf >> 1)) {
734 u32 cps = vc->estimator->maxcps;
735
736 vc->estimator->cps = cps;
737 vc->estimator->avcps = cps << 5;
738 if (vc->lacr < vc->init_er) {
739 vc->lacr = vc->init_er;
740 writel(TCMDQ_LACR | (vc->lacr << 16) |
741 vc->index, SAR_REG_TCMDQ);
742 }
743 }
744 }
745 spin_unlock_irqrestore(&vc->lock, flags);
746
747 tbd = &IDT77252_PRV_TBD(skb);
748
749 spin_lock_irqsave(&scq->lock, flags);
750 scq->next->word_1 = cpu_to_le32(tbd->word_1 |
751 SAR_TBD_TSIF | SAR_TBD_GTSI);
752 scq->next->word_2 = cpu_to_le32(tbd->word_2);
753 scq->next->word_3 = cpu_to_le32(tbd->word_3);
754 scq->next->word_4 = cpu_to_le32(tbd->word_4);
755
756 if (scq->next == scq->last)
757 scq->next = scq->base;
758 else
759 scq->next++;
760
761 write_sram(card, scq->scd,
762 scq->paddr +
763 (u32)((unsigned long)scq->next - (unsigned long)scq->base));
764 spin_unlock_irqrestore(&scq->lock, flags);
765
766 scq->trans_start = jiffies;
767
768 if (test_and_clear_bit(VCF_IDLE, &vc->flags)) {
769 writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index,
770 SAR_REG_TCMDQ);
771 }
772
773 TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used));
774
775 XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n",
776 card->name, atomic_read(&scq->used),
777 read_sram(card, scq->scd + 1), scq->next);
778
779 return 0;
780
781 out:
782 if (time_after(jiffies, scq->trans_start + HZ)) {
783 printk("%s: Error pushing TBD for %d.%d\n",
784 card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci);
785 #ifdef CONFIG_ATM_IDT77252_DEBUG
786 idt77252_tx_dump(card);
787 #endif
788 scq->trans_start = jiffies;
789 }
790
791 return -ENOBUFS;
792 }
793
794
795 static void
796 drain_scq(struct idt77252_dev *card, struct vc_map *vc)
797 {
798 struct scq_info *scq = vc->scq;
799 struct sk_buff *skb;
800 struct atm_vcc *vcc;
801
802 TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n",
803 card->name, atomic_read(&scq->used), scq->next);
804
805 skb = skb_dequeue(&scq->transmit);
806 if (skb) {
807 TXPRINTK("%s: freeing skb at %p.\n", card->name, skb);
808
809 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
810 skb->len, PCI_DMA_TODEVICE);
811
812 vcc = ATM_SKB(skb)->vcc;
813
814 if (vcc->pop)
815 vcc->pop(vcc, skb);
816 else
817 dev_kfree_skb(skb);
818
819 atomic_inc(&vcc->stats->tx);
820 }
821
822 atomic_dec(&scq->used);
823
824 spin_lock(&scq->skblock);
825 while ((skb = skb_dequeue(&scq->pending))) {
826 if (push_on_scq(card, vc, skb)) {
827 skb_queue_head(&vc->scq->pending, skb);
828 break;
829 }
830 }
831 spin_unlock(&scq->skblock);
832 }
833
834 static int
835 queue_skb(struct idt77252_dev *card, struct vc_map *vc,
836 struct sk_buff *skb, int oam)
837 {
838 struct atm_vcc *vcc;
839 struct scqe *tbd;
840 unsigned long flags;
841 int error;
842 int aal;
843
844 if (skb->len == 0) {
845 printk("%s: invalid skb->len (%d)\n", card->name, skb->len);
846 return -EINVAL;
847 }
848
849 TXPRINTK("%s: Sending %d bytes of data.\n",
850 card->name, skb->len);
851
852 tbd = &IDT77252_PRV_TBD(skb);
853 vcc = ATM_SKB(skb)->vcc;
854
855 IDT77252_PRV_PADDR(skb) = pci_map_single(card->pcidev, skb->data,
856 skb->len, PCI_DMA_TODEVICE);
857
858 error = -EINVAL;
859
860 if (oam) {
861 if (skb->len != 52)
862 goto errout;
863
864 tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU;
865 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
866 tbd->word_3 = 0x00000000;
867 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
868 (skb->data[2] << 8) | (skb->data[3] << 0);
869
870 if (test_bit(VCF_RSV, &vc->flags))
871 vc = card->vcs[0];
872
873 goto done;
874 }
875
876 if (test_bit(VCF_RSV, &vc->flags)) {
877 printk("%s: Trying to transmit on reserved VC\n", card->name);
878 goto errout;
879 }
880
881 aal = vcc->qos.aal;
882
883 switch (aal) {
884 case ATM_AAL0:
885 case ATM_AAL34:
886 if (skb->len > 52)
887 goto errout;
888
889 if (aal == ATM_AAL0)
890 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 |
891 ATM_CELL_PAYLOAD;
892 else
893 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 |
894 ATM_CELL_PAYLOAD;
895
896 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
897 tbd->word_3 = 0x00000000;
898 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
899 (skb->data[2] << 8) | (skb->data[3] << 0);
900 break;
901
902 case ATM_AAL5:
903 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len;
904 tbd->word_2 = IDT77252_PRV_PADDR(skb);
905 tbd->word_3 = skb->len;
906 tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) |
907 (vcc->vci << SAR_TBD_VCI_SHIFT);
908 break;
909
910 case ATM_AAL1:
911 case ATM_AAL2:
912 default:
913 printk("%s: Traffic type not supported.\n", card->name);
914 error = -EPROTONOSUPPORT;
915 goto errout;
916 }
917
918 done:
919 spin_lock_irqsave(&vc->scq->skblock, flags);
920 skb_queue_tail(&vc->scq->pending, skb);
921
922 while ((skb = skb_dequeue(&vc->scq->pending))) {
923 if (push_on_scq(card, vc, skb)) {
924 skb_queue_head(&vc->scq->pending, skb);
925 break;
926 }
927 }
928 spin_unlock_irqrestore(&vc->scq->skblock, flags);
929
930 return 0;
931
932 errout:
933 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
934 skb->len, PCI_DMA_TODEVICE);
935 return error;
936 }
937
938 static unsigned long
939 get_free_scd(struct idt77252_dev *card, struct vc_map *vc)
940 {
941 int i;
942
943 for (i = 0; i < card->scd_size; i++) {
944 if (!card->scd2vc[i]) {
945 card->scd2vc[i] = vc;
946 vc->scd_index = i;
947 return card->scd_base + i * SAR_SRAM_SCD_SIZE;
948 }
949 }
950 return 0;
951 }
952
953 static void
954 fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
955 {
956 write_sram(card, scq->scd, scq->paddr);
957 write_sram(card, scq->scd + 1, 0x00000000);
958 write_sram(card, scq->scd + 2, 0xffffffff);
959 write_sram(card, scq->scd + 3, 0x00000000);
960 }
961
962 static void
963 clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
964 {
965 return;
966 }
967
968 /*****************************************************************************/
969 /* */
970 /* RSQ Handling */
971 /* */
972 /*****************************************************************************/
973
974 static int
975 init_rsq(struct idt77252_dev *card)
976 {
977 struct rsq_entry *rsqe;
978
979 card->rsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE,
980 &card->rsq.paddr);
981 if (card->rsq.base == NULL) {
982 printk("%s: can't allocate RSQ.\n", card->name);
983 return -1;
984 }
985 memset(card->rsq.base, 0, RSQSIZE);
986
987 card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1;
988 card->rsq.next = card->rsq.last;
989 for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++)
990 rsqe->word_4 = 0;
991
992 writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base,
993 SAR_REG_RSQH);
994 writel(card->rsq.paddr, SAR_REG_RSQB);
995
996 IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name,
997 (unsigned long) card->rsq.base,
998 readl(SAR_REG_RSQB));
999 IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n",
1000 card->name,
1001 readl(SAR_REG_RSQH),
1002 readl(SAR_REG_RSQB),
1003 readl(SAR_REG_RSQT));
1004
1005 return 0;
1006 }
1007
1008 static void
1009 deinit_rsq(struct idt77252_dev *card)
1010 {
1011 pci_free_consistent(card->pcidev, RSQSIZE,
1012 card->rsq.base, card->rsq.paddr);
1013 }
1014
1015 static void
1016 dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe)
1017 {
1018 struct atm_vcc *vcc;
1019 struct sk_buff *skb;
1020 struct rx_pool *rpp;
1021 struct vc_map *vc;
1022 u32 header, vpi, vci;
1023 u32 stat;
1024 int i;
1025
1026 stat = le32_to_cpu(rsqe->word_4);
1027
1028 if (stat & SAR_RSQE_IDLE) {
1029 RXPRINTK("%s: message about inactive connection.\n",
1030 card->name);
1031 return;
1032 }
1033
1034 skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2));
1035 if (skb == NULL) {
1036 printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n",
1037 card->name, __FUNCTION__,
1038 le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2),
1039 le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4));
1040 return;
1041 }
1042
1043 header = le32_to_cpu(rsqe->word_1);
1044 vpi = (header >> 16) & 0x00ff;
1045 vci = (header >> 0) & 0xffff;
1046
1047 RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n",
1048 card->name, vpi, vci, skb, skb->data);
1049
1050 if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) {
1051 printk("%s: SDU received for out-of-range vc %u.%u\n",
1052 card->name, vpi, vci);
1053 recycle_rx_skb(card, skb);
1054 return;
1055 }
1056
1057 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1058 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1059 printk("%s: SDU received on non RX vc %u.%u\n",
1060 card->name, vpi, vci);
1061 recycle_rx_skb(card, skb);
1062 return;
1063 }
1064
1065 vcc = vc->rx_vcc;
1066
1067 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(skb),
1068 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1069
1070 if ((vcc->qos.aal == ATM_AAL0) ||
1071 (vcc->qos.aal == ATM_AAL34)) {
1072 struct sk_buff *sb;
1073 unsigned char *cell;
1074 u32 aal0;
1075
1076 cell = skb->data;
1077 for (i = (stat & SAR_RSQE_CELLCNT); i; i--) {
1078 if ((sb = dev_alloc_skb(64)) == NULL) {
1079 printk("%s: Can't allocate buffers for aal0.\n",
1080 card->name);
1081 atomic_add(i, &vcc->stats->rx_drop);
1082 break;
1083 }
1084 if (!atm_charge(vcc, sb->truesize)) {
1085 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n",
1086 card->name);
1087 atomic_add(i - 1, &vcc->stats->rx_drop);
1088 dev_kfree_skb(sb);
1089 break;
1090 }
1091 aal0 = (vpi << ATM_HDR_VPI_SHIFT) |
1092 (vci << ATM_HDR_VCI_SHIFT);
1093 aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0;
1094 aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0;
1095
1096 *((u32 *) sb->data) = aal0;
1097 skb_put(sb, sizeof(u32));
1098 memcpy(skb_put(sb, ATM_CELL_PAYLOAD),
1099 cell, ATM_CELL_PAYLOAD);
1100
1101 ATM_SKB(sb)->vcc = vcc;
1102 __net_timestamp(sb);
1103 vcc->push(vcc, sb);
1104 atomic_inc(&vcc->stats->rx);
1105
1106 cell += ATM_CELL_PAYLOAD;
1107 }
1108
1109 recycle_rx_skb(card, skb);
1110 return;
1111 }
1112 if (vcc->qos.aal != ATM_AAL5) {
1113 printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n",
1114 card->name, vcc->qos.aal);
1115 recycle_rx_skb(card, skb);
1116 return;
1117 }
1118 skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD;
1119
1120 rpp = &vc->rcv.rx_pool;
1121
1122 rpp->len += skb->len;
1123 if (!rpp->count++)
1124 rpp->first = skb;
1125 *rpp->last = skb;
1126 rpp->last = &skb->next;
1127
1128 if (stat & SAR_RSQE_EPDU) {
1129 unsigned char *l1l2;
1130 unsigned int len;
1131
1132 l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6);
1133
1134 len = (l1l2[0] << 8) | l1l2[1];
1135 len = len ? len : 0x10000;
1136
1137 RXPRINTK("%s: PDU has %d bytes.\n", card->name, len);
1138
1139 if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) {
1140 RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. "
1141 "(CDC: %08x)\n",
1142 card->name, len, rpp->len, readl(SAR_REG_CDC));
1143 recycle_rx_pool_skb(card, rpp);
1144 atomic_inc(&vcc->stats->rx_err);
1145 return;
1146 }
1147 if (stat & SAR_RSQE_CRC) {
1148 RXPRINTK("%s: AAL5 CRC error.\n", card->name);
1149 recycle_rx_pool_skb(card, rpp);
1150 atomic_inc(&vcc->stats->rx_err);
1151 return;
1152 }
1153 if (rpp->count > 1) {
1154 struct sk_buff *sb;
1155
1156 skb = dev_alloc_skb(rpp->len);
1157 if (!skb) {
1158 RXPRINTK("%s: Can't alloc RX skb.\n",
1159 card->name);
1160 recycle_rx_pool_skb(card, rpp);
1161 atomic_inc(&vcc->stats->rx_err);
1162 return;
1163 }
1164 if (!atm_charge(vcc, skb->truesize)) {
1165 recycle_rx_pool_skb(card, rpp);
1166 dev_kfree_skb(skb);
1167 return;
1168 }
1169 sb = rpp->first;
1170 for (i = 0; i < rpp->count; i++) {
1171 memcpy(skb_put(skb, sb->len),
1172 sb->data, sb->len);
1173 sb = sb->next;
1174 }
1175
1176 recycle_rx_pool_skb(card, rpp);
1177
1178 skb_trim(skb, len);
1179 ATM_SKB(skb)->vcc = vcc;
1180 __net_timestamp(skb);
1181
1182 vcc->push(vcc, skb);
1183 atomic_inc(&vcc->stats->rx);
1184
1185 return;
1186 }
1187
1188 skb->next = NULL;
1189 flush_rx_pool(card, rpp);
1190
1191 if (!atm_charge(vcc, skb->truesize)) {
1192 recycle_rx_skb(card, skb);
1193 return;
1194 }
1195
1196 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1197 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1198 sb_pool_remove(card, skb);
1199
1200 skb_trim(skb, len);
1201 ATM_SKB(skb)->vcc = vcc;
1202 __net_timestamp(skb);
1203
1204 vcc->push(vcc, skb);
1205 atomic_inc(&vcc->stats->rx);
1206
1207 if (skb->truesize > SAR_FB_SIZE_3)
1208 add_rx_skb(card, 3, SAR_FB_SIZE_3, 1);
1209 else if (skb->truesize > SAR_FB_SIZE_2)
1210 add_rx_skb(card, 2, SAR_FB_SIZE_2, 1);
1211 else if (skb->truesize > SAR_FB_SIZE_1)
1212 add_rx_skb(card, 1, SAR_FB_SIZE_1, 1);
1213 else
1214 add_rx_skb(card, 0, SAR_FB_SIZE_0, 1);
1215 return;
1216 }
1217 }
1218
1219 static void
1220 idt77252_rx(struct idt77252_dev *card)
1221 {
1222 struct rsq_entry *rsqe;
1223
1224 if (card->rsq.next == card->rsq.last)
1225 rsqe = card->rsq.base;
1226 else
1227 rsqe = card->rsq.next + 1;
1228
1229 if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) {
1230 RXPRINTK("%s: no entry in RSQ.\n", card->name);
1231 return;
1232 }
1233
1234 do {
1235 dequeue_rx(card, rsqe);
1236 rsqe->word_4 = 0;
1237 card->rsq.next = rsqe;
1238 if (card->rsq.next == card->rsq.last)
1239 rsqe = card->rsq.base;
1240 else
1241 rsqe = card->rsq.next + 1;
1242 } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID);
1243
1244 writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base,
1245 SAR_REG_RSQH);
1246 }
1247
1248 static void
1249 idt77252_rx_raw(struct idt77252_dev *card)
1250 {
1251 struct sk_buff *queue;
1252 u32 head, tail;
1253 struct atm_vcc *vcc;
1254 struct vc_map *vc;
1255 struct sk_buff *sb;
1256
1257 if (card->raw_cell_head == NULL) {
1258 u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1));
1259 card->raw_cell_head = sb_pool_skb(card, handle);
1260 }
1261
1262 queue = card->raw_cell_head;
1263 if (!queue)
1264 return;
1265
1266 head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16);
1267 tail = readl(SAR_REG_RAWCT);
1268
1269 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(queue),
1270 queue->end - queue->head - 16,
1271 PCI_DMA_FROMDEVICE);
1272
1273 while (head != tail) {
1274 unsigned int vpi, vci, pti;
1275 u32 header;
1276
1277 header = le32_to_cpu(*(u32 *) &queue->data[0]);
1278
1279 vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT;
1280 vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT;
1281 pti = (header & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT;
1282
1283 #ifdef CONFIG_ATM_IDT77252_DEBUG
1284 if (debug & DBG_RAW_CELL) {
1285 int i;
1286
1287 printk("%s: raw cell %x.%02x.%04x.%x.%x\n",
1288 card->name, (header >> 28) & 0x000f,
1289 (header >> 20) & 0x00ff,
1290 (header >> 4) & 0xffff,
1291 (header >> 1) & 0x0007,
1292 (header >> 0) & 0x0001);
1293 for (i = 16; i < 64; i++)
1294 printk(" %02x", queue->data[i]);
1295 printk("\n");
1296 }
1297 #endif
1298
1299 if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) {
1300 RPRINTK("%s: SDU received for out-of-range vc %u.%u\n",
1301 card->name, vpi, vci);
1302 goto drop;
1303 }
1304
1305 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1306 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1307 RPRINTK("%s: SDU received on non RX vc %u.%u\n",
1308 card->name, vpi, vci);
1309 goto drop;
1310 }
1311
1312 vcc = vc->rx_vcc;
1313
1314 if (vcc->qos.aal != ATM_AAL0) {
1315 RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n",
1316 card->name, vpi, vci);
1317 atomic_inc(&vcc->stats->rx_drop);
1318 goto drop;
1319 }
1320
1321 if ((sb = dev_alloc_skb(64)) == NULL) {
1322 printk("%s: Can't allocate buffers for AAL0.\n",
1323 card->name);
1324 atomic_inc(&vcc->stats->rx_err);
1325 goto drop;
1326 }
1327
1328 if (!atm_charge(vcc, sb->truesize)) {
1329 RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n",
1330 card->name);
1331 dev_kfree_skb(sb);
1332 goto drop;
1333 }
1334
1335 *((u32 *) sb->data) = header;
1336 skb_put(sb, sizeof(u32));
1337 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), &(queue->data[16]),
1338 ATM_CELL_PAYLOAD);
1339
1340 ATM_SKB(sb)->vcc = vcc;
1341 __net_timestamp(sb);
1342 vcc->push(vcc, sb);
1343 atomic_inc(&vcc->stats->rx);
1344
1345 drop:
1346 skb_pull(queue, 64);
1347
1348 head = IDT77252_PRV_PADDR(queue)
1349 + (queue->data - queue->head - 16);
1350
1351 if (queue->len < 128) {
1352 struct sk_buff *next;
1353 u32 handle;
1354
1355 head = le32_to_cpu(*(u32 *) &queue->data[0]);
1356 handle = le32_to_cpu(*(u32 *) &queue->data[4]);
1357
1358 next = sb_pool_skb(card, handle);
1359 recycle_rx_skb(card, queue);
1360
1361 if (next) {
1362 card->raw_cell_head = next;
1363 queue = card->raw_cell_head;
1364 pci_dma_sync_single_for_cpu(card->pcidev,
1365 IDT77252_PRV_PADDR(queue),
1366 queue->end - queue->data,
1367 PCI_DMA_FROMDEVICE);
1368 } else {
1369 card->raw_cell_head = NULL;
1370 printk("%s: raw cell queue overrun\n",
1371 card->name);
1372 break;
1373 }
1374 }
1375 }
1376 }
1377
1378
1379 /*****************************************************************************/
1380 /* */
1381 /* TSQ Handling */
1382 /* */
1383 /*****************************************************************************/
1384
1385 static int
1386 init_tsq(struct idt77252_dev *card)
1387 {
1388 struct tsq_entry *tsqe;
1389
1390 card->tsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE,
1391 &card->tsq.paddr);
1392 if (card->tsq.base == NULL) {
1393 printk("%s: can't allocate TSQ.\n", card->name);
1394 return -1;
1395 }
1396 memset(card->tsq.base, 0, TSQSIZE);
1397
1398 card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1;
1399 card->tsq.next = card->tsq.last;
1400 for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++)
1401 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1402
1403 writel(card->tsq.paddr, SAR_REG_TSQB);
1404 writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base,
1405 SAR_REG_TSQH);
1406
1407 return 0;
1408 }
1409
1410 static void
1411 deinit_tsq(struct idt77252_dev *card)
1412 {
1413 pci_free_consistent(card->pcidev, TSQSIZE,
1414 card->tsq.base, card->tsq.paddr);
1415 }
1416
1417 static void
1418 idt77252_tx(struct idt77252_dev *card)
1419 {
1420 struct tsq_entry *tsqe;
1421 unsigned int vpi, vci;
1422 struct vc_map *vc;
1423 u32 conn, stat;
1424
1425 if (card->tsq.next == card->tsq.last)
1426 tsqe = card->tsq.base;
1427 else
1428 tsqe = card->tsq.next + 1;
1429
1430 TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe,
1431 card->tsq.base, card->tsq.next, card->tsq.last);
1432 TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n",
1433 readl(SAR_REG_TSQB),
1434 readl(SAR_REG_TSQT),
1435 readl(SAR_REG_TSQH));
1436
1437 stat = le32_to_cpu(tsqe->word_2);
1438
1439 if (stat & SAR_TSQE_INVALID)
1440 return;
1441
1442 do {
1443 TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe,
1444 le32_to_cpu(tsqe->word_1),
1445 le32_to_cpu(tsqe->word_2));
1446
1447 switch (stat & SAR_TSQE_TYPE) {
1448 case SAR_TSQE_TYPE_TIMER:
1449 TXPRINTK("%s: Timer RollOver detected.\n", card->name);
1450 break;
1451
1452 case SAR_TSQE_TYPE_IDLE:
1453
1454 conn = le32_to_cpu(tsqe->word_1);
1455
1456 if (SAR_TSQE_TAG(stat) == 0x10) {
1457 #ifdef NOTDEF
1458 printk("%s: Connection %d halted.\n",
1459 card->name,
1460 le32_to_cpu(tsqe->word_1) & 0x1fff);
1461 #endif
1462 break;
1463 }
1464
1465 vc = card->vcs[conn & 0x1fff];
1466 if (!vc) {
1467 printk("%s: could not find VC from conn %d\n",
1468 card->name, conn & 0x1fff);
1469 break;
1470 }
1471
1472 printk("%s: Connection %d IDLE.\n",
1473 card->name, vc->index);
1474
1475 set_bit(VCF_IDLE, &vc->flags);
1476 break;
1477
1478 case SAR_TSQE_TYPE_TSR:
1479
1480 conn = le32_to_cpu(tsqe->word_1);
1481
1482 vc = card->vcs[conn & 0x1fff];
1483 if (!vc) {
1484 printk("%s: no VC at index %d\n",
1485 card->name,
1486 le32_to_cpu(tsqe->word_1) & 0x1fff);
1487 break;
1488 }
1489
1490 drain_scq(card, vc);
1491 break;
1492
1493 case SAR_TSQE_TYPE_TBD_COMP:
1494
1495 conn = le32_to_cpu(tsqe->word_1);
1496
1497 vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff;
1498 vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff;
1499
1500 if (vpi >= (1 << card->vpibits) ||
1501 vci >= (1 << card->vcibits)) {
1502 printk("%s: TBD complete: "
1503 "out of range VPI.VCI %u.%u\n",
1504 card->name, vpi, vci);
1505 break;
1506 }
1507
1508 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1509 if (!vc) {
1510 printk("%s: TBD complete: "
1511 "no VC at VPI.VCI %u.%u\n",
1512 card->name, vpi, vci);
1513 break;
1514 }
1515
1516 drain_scq(card, vc);
1517 break;
1518 }
1519
1520 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1521
1522 card->tsq.next = tsqe;
1523 if (card->tsq.next == card->tsq.last)
1524 tsqe = card->tsq.base;
1525 else
1526 tsqe = card->tsq.next + 1;
1527
1528 TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe,
1529 card->tsq.base, card->tsq.next, card->tsq.last);
1530
1531 stat = le32_to_cpu(tsqe->word_2);
1532
1533 } while (!(stat & SAR_TSQE_INVALID));
1534
1535 writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base,
1536 SAR_REG_TSQH);
1537
1538 XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n",
1539 card->index, readl(SAR_REG_TSQH),
1540 readl(SAR_REG_TSQT), card->tsq.next);
1541 }
1542
1543
1544 static void
1545 tst_timer(unsigned long data)
1546 {
1547 struct idt77252_dev *card = (struct idt77252_dev *)data;
1548 unsigned long base, idle, jump;
1549 unsigned long flags;
1550 u32 pc;
1551 int e;
1552
1553 spin_lock_irqsave(&card->tst_lock, flags);
1554
1555 base = card->tst[card->tst_index];
1556 idle = card->tst[card->tst_index ^ 1];
1557
1558 if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) {
1559 jump = base + card->tst_size - 2;
1560
1561 pc = readl(SAR_REG_NOW) >> 2;
1562 if ((pc ^ idle) & ~(card->tst_size - 1)) {
1563 mod_timer(&card->tst_timer, jiffies + 1);
1564 goto out;
1565 }
1566
1567 clear_bit(TST_SWITCH_WAIT, &card->tst_state);
1568
1569 card->tst_index ^= 1;
1570 write_sram(card, jump, TSTE_OPC_JMP | (base << 2));
1571
1572 base = card->tst[card->tst_index];
1573 idle = card->tst[card->tst_index ^ 1];
1574
1575 for (e = 0; e < card->tst_size - 2; e++) {
1576 if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) {
1577 write_sram(card, idle + e,
1578 card->soft_tst[e].tste & TSTE_MASK);
1579 card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE);
1580 }
1581 }
1582 }
1583
1584 if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) {
1585
1586 for (e = 0; e < card->tst_size - 2; e++) {
1587 if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) {
1588 write_sram(card, idle + e,
1589 card->soft_tst[e].tste & TSTE_MASK);
1590 card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE);
1591 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1592 }
1593 }
1594
1595 jump = base + card->tst_size - 2;
1596
1597 write_sram(card, jump, TSTE_OPC_NULL);
1598 set_bit(TST_SWITCH_WAIT, &card->tst_state);
1599
1600 mod_timer(&card->tst_timer, jiffies + 1);
1601 }
1602
1603 out:
1604 spin_unlock_irqrestore(&card->tst_lock, flags);
1605 }
1606
1607 static int
1608 __fill_tst(struct idt77252_dev *card, struct vc_map *vc,
1609 int n, unsigned int opc)
1610 {
1611 unsigned long cl, avail;
1612 unsigned long idle;
1613 int e, r;
1614 u32 data;
1615
1616 avail = card->tst_size - 2;
1617 for (e = 0; e < avail; e++) {
1618 if (card->soft_tst[e].vc == NULL)
1619 break;
1620 }
1621 if (e >= avail) {
1622 printk("%s: No free TST entries found\n", card->name);
1623 return -1;
1624 }
1625
1626 NPRINTK("%s: conn %d: first TST entry at %d.\n",
1627 card->name, vc ? vc->index : -1, e);
1628
1629 r = n;
1630 cl = avail;
1631 data = opc & TSTE_OPC_MASK;
1632 if (vc && (opc != TSTE_OPC_NULL))
1633 data = opc | vc->index;
1634
1635 idle = card->tst[card->tst_index ^ 1];
1636
1637 /*
1638 * Fill Soft TST.
1639 */
1640 while (r > 0) {
1641 if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) {
1642 if (vc)
1643 card->soft_tst[e].vc = vc;
1644 else
1645 card->soft_tst[e].vc = (void *)-1;
1646
1647 card->soft_tst[e].tste = data;
1648 if (timer_pending(&card->tst_timer))
1649 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1650 else {
1651 write_sram(card, idle + e, data);
1652 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1653 }
1654
1655 cl -= card->tst_size;
1656 r--;
1657 }
1658
1659 if (++e == avail)
1660 e = 0;
1661 cl += n;
1662 }
1663
1664 return 0;
1665 }
1666
1667 static int
1668 fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc)
1669 {
1670 unsigned long flags;
1671 int res;
1672
1673 spin_lock_irqsave(&card->tst_lock, flags);
1674
1675 res = __fill_tst(card, vc, n, opc);
1676
1677 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1678 if (!timer_pending(&card->tst_timer))
1679 mod_timer(&card->tst_timer, jiffies + 1);
1680
1681 spin_unlock_irqrestore(&card->tst_lock, flags);
1682 return res;
1683 }
1684
1685 static int
1686 __clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1687 {
1688 unsigned long idle;
1689 int e;
1690
1691 idle = card->tst[card->tst_index ^ 1];
1692
1693 for (e = 0; e < card->tst_size - 2; e++) {
1694 if (card->soft_tst[e].vc == vc) {
1695 card->soft_tst[e].vc = NULL;
1696
1697 card->soft_tst[e].tste = TSTE_OPC_VAR;
1698 if (timer_pending(&card->tst_timer))
1699 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1700 else {
1701 write_sram(card, idle + e, TSTE_OPC_VAR);
1702 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1703 }
1704 }
1705 }
1706
1707 return 0;
1708 }
1709
1710 static int
1711 clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1712 {
1713 unsigned long flags;
1714 int res;
1715
1716 spin_lock_irqsave(&card->tst_lock, flags);
1717
1718 res = __clear_tst(card, vc);
1719
1720 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1721 if (!timer_pending(&card->tst_timer))
1722 mod_timer(&card->tst_timer, jiffies + 1);
1723
1724 spin_unlock_irqrestore(&card->tst_lock, flags);
1725 return res;
1726 }
1727
1728 static int
1729 change_tst(struct idt77252_dev *card, struct vc_map *vc,
1730 int n, unsigned int opc)
1731 {
1732 unsigned long flags;
1733 int res;
1734
1735 spin_lock_irqsave(&card->tst_lock, flags);
1736
1737 __clear_tst(card, vc);
1738 res = __fill_tst(card, vc, n, opc);
1739
1740 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1741 if (!timer_pending(&card->tst_timer))
1742 mod_timer(&card->tst_timer, jiffies + 1);
1743
1744 spin_unlock_irqrestore(&card->tst_lock, flags);
1745 return res;
1746 }
1747
1748
1749 static int
1750 set_tct(struct idt77252_dev *card, struct vc_map *vc)
1751 {
1752 unsigned long tct;
1753
1754 tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE);
1755
1756 switch (vc->class) {
1757 case SCHED_CBR:
1758 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1759 card->name, tct, vc->scq->scd);
1760
1761 write_sram(card, tct + 0, TCT_CBR | vc->scq->scd);
1762 write_sram(card, tct + 1, 0);
1763 write_sram(card, tct + 2, 0);
1764 write_sram(card, tct + 3, 0);
1765 write_sram(card, tct + 4, 0);
1766 write_sram(card, tct + 5, 0);
1767 write_sram(card, tct + 6, 0);
1768 write_sram(card, tct + 7, 0);
1769 break;
1770
1771 case SCHED_UBR:
1772 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1773 card->name, tct, vc->scq->scd);
1774
1775 write_sram(card, tct + 0, TCT_UBR | vc->scq->scd);
1776 write_sram(card, tct + 1, 0);
1777 write_sram(card, tct + 2, TCT_TSIF);
1778 write_sram(card, tct + 3, TCT_HALT | TCT_IDLE);
1779 write_sram(card, tct + 4, 0);
1780 write_sram(card, tct + 5, vc->init_er);
1781 write_sram(card, tct + 6, 0);
1782 write_sram(card, tct + 7, TCT_FLAG_UBR);
1783 break;
1784
1785 case SCHED_VBR:
1786 case SCHED_ABR:
1787 default:
1788 return -ENOSYS;
1789 }
1790
1791 return 0;
1792 }
1793
1794 /*****************************************************************************/
1795 /* */
1796 /* FBQ Handling */
1797 /* */
1798 /*****************************************************************************/
1799
1800 static __inline__ int
1801 idt77252_fbq_level(struct idt77252_dev *card, int queue)
1802 {
1803 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f;
1804 }
1805
1806 static __inline__ int
1807 idt77252_fbq_full(struct idt77252_dev *card, int queue)
1808 {
1809 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f;
1810 }
1811
1812 static int
1813 push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue)
1814 {
1815 unsigned long flags;
1816 u32 handle;
1817 u32 addr;
1818
1819 skb->data = skb->tail = skb->head;
1820 skb->len = 0;
1821
1822 skb_reserve(skb, 16);
1823
1824 switch (queue) {
1825 case 0:
1826 skb_put(skb, SAR_FB_SIZE_0);
1827 break;
1828 case 1:
1829 skb_put(skb, SAR_FB_SIZE_1);
1830 break;
1831 case 2:
1832 skb_put(skb, SAR_FB_SIZE_2);
1833 break;
1834 case 3:
1835 skb_put(skb, SAR_FB_SIZE_3);
1836 break;
1837 default:
1838 dev_kfree_skb(skb);
1839 return -1;
1840 }
1841
1842 if (idt77252_fbq_full(card, queue))
1843 return -1;
1844
1845 memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32));
1846
1847 handle = IDT77252_PRV_POOL(skb);
1848 addr = IDT77252_PRV_PADDR(skb);
1849
1850 spin_lock_irqsave(&card->cmd_lock, flags);
1851 writel(handle, card->fbq[queue]);
1852 writel(addr, card->fbq[queue]);
1853 spin_unlock_irqrestore(&card->cmd_lock, flags);
1854
1855 return 0;
1856 }
1857
1858 static void
1859 add_rx_skb(struct idt77252_dev *card, int queue,
1860 unsigned int size, unsigned int count)
1861 {
1862 struct sk_buff *skb;
1863 dma_addr_t paddr;
1864 u32 handle;
1865
1866 while (count--) {
1867 skb = dev_alloc_skb(size);
1868 if (!skb)
1869 return;
1870
1871 if (sb_pool_add(card, skb, queue)) {
1872 printk("%s: SB POOL full\n", __FUNCTION__);
1873 goto outfree;
1874 }
1875
1876 paddr = pci_map_single(card->pcidev, skb->data,
1877 skb->end - skb->data,
1878 PCI_DMA_FROMDEVICE);
1879 IDT77252_PRV_PADDR(skb) = paddr;
1880
1881 if (push_rx_skb(card, skb, queue)) {
1882 printk("%s: FB QUEUE full\n", __FUNCTION__);
1883 goto outunmap;
1884 }
1885 }
1886
1887 return;
1888
1889 outunmap:
1890 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1891 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1892
1893 handle = IDT77252_PRV_POOL(skb);
1894 card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL;
1895
1896 outfree:
1897 dev_kfree_skb(skb);
1898 }
1899
1900
1901 static void
1902 recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb)
1903 {
1904 u32 handle = IDT77252_PRV_POOL(skb);
1905 int err;
1906
1907 pci_dma_sync_single_for_device(card->pcidev, IDT77252_PRV_PADDR(skb),
1908 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1909
1910 err = push_rx_skb(card, skb, POOL_QUEUE(handle));
1911 if (err) {
1912 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1913 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1914 sb_pool_remove(card, skb);
1915 dev_kfree_skb(skb);
1916 }
1917 }
1918
1919 static void
1920 flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp)
1921 {
1922 rpp->len = 0;
1923 rpp->count = 0;
1924 rpp->first = NULL;
1925 rpp->last = &rpp->first;
1926 }
1927
1928 static void
1929 recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp)
1930 {
1931 struct sk_buff *skb, *next;
1932 int i;
1933
1934 skb = rpp->first;
1935 for (i = 0; i < rpp->count; i++) {
1936 next = skb->next;
1937 skb->next = NULL;
1938 recycle_rx_skb(card, skb);
1939 skb = next;
1940 }
1941 flush_rx_pool(card, rpp);
1942 }
1943
1944 /*****************************************************************************/
1945 /* */
1946 /* ATM Interface */
1947 /* */
1948 /*****************************************************************************/
1949
1950 static void
1951 idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr)
1952 {
1953 write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value);
1954 }
1955
1956 static unsigned char
1957 idt77252_phy_get(struct atm_dev *dev, unsigned long addr)
1958 {
1959 return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff));
1960 }
1961
1962 static inline int
1963 idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam)
1964 {
1965 struct atm_dev *dev = vcc->dev;
1966 struct idt77252_dev *card = dev->dev_data;
1967 struct vc_map *vc = vcc->dev_data;
1968 int err;
1969
1970 if (vc == NULL) {
1971 printk("%s: NULL connection in send().\n", card->name);
1972 atomic_inc(&vcc->stats->tx_err);
1973 dev_kfree_skb(skb);
1974 return -EINVAL;
1975 }
1976 if (!test_bit(VCF_TX, &vc->flags)) {
1977 printk("%s: Trying to transmit on a non-tx VC.\n", card->name);
1978 atomic_inc(&vcc->stats->tx_err);
1979 dev_kfree_skb(skb);
1980 return -EINVAL;
1981 }
1982
1983 switch (vcc->qos.aal) {
1984 case ATM_AAL0:
1985 case ATM_AAL1:
1986 case ATM_AAL5:
1987 break;
1988 default:
1989 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
1990 atomic_inc(&vcc->stats->tx_err);
1991 dev_kfree_skb(skb);
1992 return -EINVAL;
1993 }
1994
1995 if (skb_shinfo(skb)->nr_frags != 0) {
1996 printk("%s: No scatter-gather yet.\n", card->name);
1997 atomic_inc(&vcc->stats->tx_err);
1998 dev_kfree_skb(skb);
1999 return -EINVAL;
2000 }
2001 ATM_SKB(skb)->vcc = vcc;
2002
2003 err = queue_skb(card, vc, skb, oam);
2004 if (err) {
2005 atomic_inc(&vcc->stats->tx_err);
2006 dev_kfree_skb(skb);
2007 return err;
2008 }
2009
2010 return 0;
2011 }
2012
2013 int
2014 idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb)
2015 {
2016 return idt77252_send_skb(vcc, skb, 0);
2017 }
2018
2019 static int
2020 idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags)
2021 {
2022 struct atm_dev *dev = vcc->dev;
2023 struct idt77252_dev *card = dev->dev_data;
2024 struct sk_buff *skb;
2025
2026 skb = dev_alloc_skb(64);
2027 if (!skb) {
2028 printk("%s: Out of memory in send_oam().\n", card->name);
2029 atomic_inc(&vcc->stats->tx_err);
2030 return -ENOMEM;
2031 }
2032 atomic_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc);
2033
2034 memcpy(skb_put(skb, 52), cell, 52);
2035
2036 return idt77252_send_skb(vcc, skb, 1);
2037 }
2038
2039 static __inline__ unsigned int
2040 idt77252_fls(unsigned int x)
2041 {
2042 int r = 1;
2043
2044 if (x == 0)
2045 return 0;
2046 if (x & 0xffff0000) {
2047 x >>= 16;
2048 r += 16;
2049 }
2050 if (x & 0xff00) {
2051 x >>= 8;
2052 r += 8;
2053 }
2054 if (x & 0xf0) {
2055 x >>= 4;
2056 r += 4;
2057 }
2058 if (x & 0xc) {
2059 x >>= 2;
2060 r += 2;
2061 }
2062 if (x & 0x2)
2063 r += 1;
2064 return r;
2065 }
2066
2067 static u16
2068 idt77252_int_to_atmfp(unsigned int rate)
2069 {
2070 u16 m, e;
2071
2072 if (rate == 0)
2073 return 0;
2074 e = idt77252_fls(rate) - 1;
2075 if (e < 9)
2076 m = (rate - (1 << e)) << (9 - e);
2077 else if (e == 9)
2078 m = (rate - (1 << e));
2079 else /* e > 9 */
2080 m = (rate - (1 << e)) >> (e - 9);
2081 return 0x4000 | (e << 9) | m;
2082 }
2083
2084 static u8
2085 idt77252_rate_logindex(struct idt77252_dev *card, int pcr)
2086 {
2087 u16 afp;
2088
2089 afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr);
2090 if (pcr < 0)
2091 return rate_to_log[(afp >> 5) & 0x1ff];
2092 return rate_to_log[((afp >> 5) + 1) & 0x1ff];
2093 }
2094
2095 static void
2096 idt77252_est_timer(unsigned long data)
2097 {
2098 struct vc_map *vc = (struct vc_map *)data;
2099 struct idt77252_dev *card = vc->card;
2100 struct rate_estimator *est;
2101 unsigned long flags;
2102 u32 rate, cps;
2103 u64 ncells;
2104 u8 lacr;
2105
2106 spin_lock_irqsave(&vc->lock, flags);
2107 est = vc->estimator;
2108 if (!est)
2109 goto out;
2110
2111 ncells = est->cells;
2112
2113 rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval);
2114 est->last_cells = ncells;
2115 est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log;
2116 est->cps = (est->avcps + 0x1f) >> 5;
2117
2118 cps = est->cps;
2119 if (cps < (est->maxcps >> 4))
2120 cps = est->maxcps >> 4;
2121
2122 lacr = idt77252_rate_logindex(card, cps);
2123 if (lacr > vc->max_er)
2124 lacr = vc->max_er;
2125
2126 if (lacr != vc->lacr) {
2127 vc->lacr = lacr;
2128 writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ);
2129 }
2130
2131 est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2132 add_timer(&est->timer);
2133
2134 out:
2135 spin_unlock_irqrestore(&vc->lock, flags);
2136 }
2137
2138 static struct rate_estimator *
2139 idt77252_init_est(struct vc_map *vc, int pcr)
2140 {
2141 struct rate_estimator *est;
2142
2143 est = kzalloc(sizeof(struct rate_estimator), GFP_KERNEL);
2144 if (!est)
2145 return NULL;
2146 est->maxcps = pcr < 0 ? -pcr : pcr;
2147 est->cps = est->maxcps;
2148 est->avcps = est->cps << 5;
2149
2150 est->interval = 2; /* XXX: make this configurable */
2151 est->ewma_log = 2; /* XXX: make this configurable */
2152 init_timer(&est->timer);
2153 est->timer.data = (unsigned long)vc;
2154 est->timer.function = idt77252_est_timer;
2155
2156 est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2157 add_timer(&est->timer);
2158
2159 return est;
2160 }
2161
2162 static int
2163 idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc,
2164 struct atm_vcc *vcc, struct atm_qos *qos)
2165 {
2166 int tst_free, tst_used, tst_entries;
2167 unsigned long tmpl, modl;
2168 int tcr, tcra;
2169
2170 if ((qos->txtp.max_pcr == 0) &&
2171 (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) {
2172 printk("%s: trying to open a CBR VC with cell rate = 0\n",
2173 card->name);
2174 return -EINVAL;
2175 }
2176
2177 tst_used = 0;
2178 tst_free = card->tst_free;
2179 if (test_bit(VCF_TX, &vc->flags))
2180 tst_used = vc->ntste;
2181 tst_free += tst_used;
2182
2183 tcr = atm_pcr_goal(&qos->txtp);
2184 tcra = tcr >= 0 ? tcr : -tcr;
2185
2186 TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra);
2187
2188 tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2);
2189 modl = tmpl % (unsigned long)card->utopia_pcr;
2190
2191 tst_entries = (int) (tmpl / card->utopia_pcr);
2192 if (tcr > 0) {
2193 if (modl > 0)
2194 tst_entries++;
2195 } else if (tcr == 0) {
2196 tst_entries = tst_free - SAR_TST_RESERVED;
2197 if (tst_entries <= 0) {
2198 printk("%s: no CBR bandwidth free.\n", card->name);
2199 return -ENOSR;
2200 }
2201 }
2202
2203 if (tst_entries == 0) {
2204 printk("%s: selected CBR bandwidth < granularity.\n",
2205 card->name);
2206 return -EINVAL;
2207 }
2208
2209 if (tst_entries > (tst_free - SAR_TST_RESERVED)) {
2210 printk("%s: not enough CBR bandwidth free.\n", card->name);
2211 return -ENOSR;
2212 }
2213
2214 vc->ntste = tst_entries;
2215
2216 card->tst_free = tst_free - tst_entries;
2217 if (test_bit(VCF_TX, &vc->flags)) {
2218 if (tst_used == tst_entries)
2219 return 0;
2220
2221 OPRINTK("%s: modify %d -> %d entries in TST.\n",
2222 card->name, tst_used, tst_entries);
2223 change_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2224 return 0;
2225 }
2226
2227 OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries);
2228 fill_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2229 return 0;
2230 }
2231
2232 static int
2233 idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc,
2234 struct atm_vcc *vcc, struct atm_qos *qos)
2235 {
2236 unsigned long flags;
2237 int tcr;
2238
2239 spin_lock_irqsave(&vc->lock, flags);
2240 if (vc->estimator) {
2241 del_timer(&vc->estimator->timer);
2242 kfree(vc->estimator);
2243 vc->estimator = NULL;
2244 }
2245 spin_unlock_irqrestore(&vc->lock, flags);
2246
2247 tcr = atm_pcr_goal(&qos->txtp);
2248 if (tcr == 0)
2249 tcr = card->link_pcr;
2250
2251 vc->estimator = idt77252_init_est(vc, tcr);
2252
2253 vc->class = SCHED_UBR;
2254 vc->init_er = idt77252_rate_logindex(card, tcr);
2255 vc->lacr = vc->init_er;
2256 if (tcr < 0)
2257 vc->max_er = vc->init_er;
2258 else
2259 vc->max_er = 0xff;
2260
2261 return 0;
2262 }
2263
2264 static int
2265 idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc,
2266 struct atm_vcc *vcc, struct atm_qos *qos)
2267 {
2268 int error;
2269
2270 if (test_bit(VCF_TX, &vc->flags))
2271 return -EBUSY;
2272
2273 switch (qos->txtp.traffic_class) {
2274 case ATM_CBR:
2275 vc->class = SCHED_CBR;
2276 break;
2277
2278 case ATM_UBR:
2279 vc->class = SCHED_UBR;
2280 break;
2281
2282 case ATM_VBR:
2283 case ATM_ABR:
2284 default:
2285 return -EPROTONOSUPPORT;
2286 }
2287
2288 vc->scq = alloc_scq(card, vc->class);
2289 if (!vc->scq) {
2290 printk("%s: can't get SCQ.\n", card->name);
2291 return -ENOMEM;
2292 }
2293
2294 vc->scq->scd = get_free_scd(card, vc);
2295 if (vc->scq->scd == 0) {
2296 printk("%s: no SCD available.\n", card->name);
2297 free_scq(card, vc->scq);
2298 return -ENOMEM;
2299 }
2300
2301 fill_scd(card, vc->scq, vc->class);
2302
2303 if (set_tct(card, vc)) {
2304 printk("%s: class %d not supported.\n",
2305 card->name, qos->txtp.traffic_class);
2306
2307 card->scd2vc[vc->scd_index] = NULL;
2308 free_scq(card, vc->scq);
2309 return -EPROTONOSUPPORT;
2310 }
2311
2312 switch (vc->class) {
2313 case SCHED_CBR:
2314 error = idt77252_init_cbr(card, vc, vcc, qos);
2315 if (error) {
2316 card->scd2vc[vc->scd_index] = NULL;
2317 free_scq(card, vc->scq);
2318 return error;
2319 }
2320
2321 clear_bit(VCF_IDLE, &vc->flags);
2322 writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ);
2323 break;
2324
2325 case SCHED_UBR:
2326 error = idt77252_init_ubr(card, vc, vcc, qos);
2327 if (error) {
2328 card->scd2vc[vc->scd_index] = NULL;
2329 free_scq(card, vc->scq);
2330 return error;
2331 }
2332
2333 set_bit(VCF_IDLE, &vc->flags);
2334 break;
2335 }
2336
2337 vc->tx_vcc = vcc;
2338 set_bit(VCF_TX, &vc->flags);
2339 return 0;
2340 }
2341
2342 static int
2343 idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc,
2344 struct atm_vcc *vcc, struct atm_qos *qos)
2345 {
2346 unsigned long flags;
2347 unsigned long addr;
2348 u32 rcte = 0;
2349
2350 if (test_bit(VCF_RX, &vc->flags))
2351 return -EBUSY;
2352
2353 vc->rx_vcc = vcc;
2354 set_bit(VCF_RX, &vc->flags);
2355
2356 if ((vcc->vci == 3) || (vcc->vci == 4))
2357 return 0;
2358
2359 flush_rx_pool(card, &vc->rcv.rx_pool);
2360
2361 rcte |= SAR_RCTE_CONNECTOPEN;
2362 rcte |= SAR_RCTE_RAWCELLINTEN;
2363
2364 switch (qos->aal) {
2365 case ATM_AAL0:
2366 rcte |= SAR_RCTE_RCQ;
2367 break;
2368 case ATM_AAL1:
2369 rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */
2370 break;
2371 case ATM_AAL34:
2372 rcte |= SAR_RCTE_AAL34;
2373 break;
2374 case ATM_AAL5:
2375 rcte |= SAR_RCTE_AAL5;
2376 break;
2377 default:
2378 rcte |= SAR_RCTE_RCQ;
2379 break;
2380 }
2381
2382 if (qos->aal != ATM_AAL5)
2383 rcte |= SAR_RCTE_FBP_1;
2384 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2)
2385 rcte |= SAR_RCTE_FBP_3;
2386 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1)
2387 rcte |= SAR_RCTE_FBP_2;
2388 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0)
2389 rcte |= SAR_RCTE_FBP_1;
2390 else
2391 rcte |= SAR_RCTE_FBP_01;
2392
2393 addr = card->rct_base + (vc->index << 2);
2394
2395 OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr);
2396 write_sram(card, addr, rcte);
2397
2398 spin_lock_irqsave(&card->cmd_lock, flags);
2399 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD);
2400 waitfor_idle(card);
2401 spin_unlock_irqrestore(&card->cmd_lock, flags);
2402
2403 return 0;
2404 }
2405
2406 static int
2407 idt77252_open(struct atm_vcc *vcc)
2408 {
2409 struct atm_dev *dev = vcc->dev;
2410 struct idt77252_dev *card = dev->dev_data;
2411 struct vc_map *vc;
2412 unsigned int index;
2413 unsigned int inuse;
2414 int error;
2415 int vci = vcc->vci;
2416 short vpi = vcc->vpi;
2417
2418 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC)
2419 return 0;
2420
2421 if (vpi >= (1 << card->vpibits)) {
2422 printk("%s: unsupported VPI: %d\n", card->name, vpi);
2423 return -EINVAL;
2424 }
2425
2426 if (vci >= (1 << card->vcibits)) {
2427 printk("%s: unsupported VCI: %d\n", card->name, vci);
2428 return -EINVAL;
2429 }
2430
2431 set_bit(ATM_VF_ADDR, &vcc->flags);
2432
2433 down(&card->mutex);
2434
2435 OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci);
2436
2437 switch (vcc->qos.aal) {
2438 case ATM_AAL0:
2439 case ATM_AAL1:
2440 case ATM_AAL5:
2441 break;
2442 default:
2443 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
2444 up(&card->mutex);
2445 return -EPROTONOSUPPORT;
2446 }
2447
2448 index = VPCI2VC(card, vpi, vci);
2449 if (!card->vcs[index]) {
2450 card->vcs[index] = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2451 if (!card->vcs[index]) {
2452 printk("%s: can't alloc vc in open()\n", card->name);
2453 up(&card->mutex);
2454 return -ENOMEM;
2455 }
2456 card->vcs[index]->card = card;
2457 card->vcs[index]->index = index;
2458
2459 spin_lock_init(&card->vcs[index]->lock);
2460 }
2461 vc = card->vcs[index];
2462
2463 vcc->dev_data = vc;
2464
2465 IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n",
2466 card->name, vc->index, vcc->vpi, vcc->vci,
2467 vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--",
2468 vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--",
2469 vcc->qos.rxtp.max_sdu);
2470
2471 inuse = 0;
2472 if (vcc->qos.txtp.traffic_class != ATM_NONE &&
2473 test_bit(VCF_TX, &vc->flags))
2474 inuse = 1;
2475 if (vcc->qos.rxtp.traffic_class != ATM_NONE &&
2476 test_bit(VCF_RX, &vc->flags))
2477 inuse += 2;
2478
2479 if (inuse) {
2480 printk("%s: %s vci already in use.\n", card->name,
2481 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
2482 up(&card->mutex);
2483 return -EADDRINUSE;
2484 }
2485
2486 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2487 error = idt77252_init_tx(card, vc, vcc, &vcc->qos);
2488 if (error) {
2489 up(&card->mutex);
2490 return error;
2491 }
2492 }
2493
2494 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2495 error = idt77252_init_rx(card, vc, vcc, &vcc->qos);
2496 if (error) {
2497 up(&card->mutex);
2498 return error;
2499 }
2500 }
2501
2502 set_bit(ATM_VF_READY, &vcc->flags);
2503
2504 up(&card->mutex);
2505 return 0;
2506 }
2507
2508 static void
2509 idt77252_close(struct atm_vcc *vcc)
2510 {
2511 struct atm_dev *dev = vcc->dev;
2512 struct idt77252_dev *card = dev->dev_data;
2513 struct vc_map *vc = vcc->dev_data;
2514 unsigned long flags;
2515 unsigned long addr;
2516 unsigned long timeout;
2517
2518 down(&card->mutex);
2519
2520 IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n",
2521 card->name, vc->index, vcc->vpi, vcc->vci);
2522
2523 clear_bit(ATM_VF_READY, &vcc->flags);
2524
2525 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2526
2527 spin_lock_irqsave(&vc->lock, flags);
2528 clear_bit(VCF_RX, &vc->flags);
2529 vc->rx_vcc = NULL;
2530 spin_unlock_irqrestore(&vc->lock, flags);
2531
2532 if ((vcc->vci == 3) || (vcc->vci == 4))
2533 goto done;
2534
2535 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2536
2537 spin_lock_irqsave(&card->cmd_lock, flags);
2538 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD);
2539 waitfor_idle(card);
2540 spin_unlock_irqrestore(&card->cmd_lock, flags);
2541
2542 if (vc->rcv.rx_pool.count) {
2543 DPRINTK("%s: closing a VC with pending rx buffers.\n",
2544 card->name);
2545
2546 recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2547 }
2548 }
2549
2550 done:
2551 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2552
2553 spin_lock_irqsave(&vc->lock, flags);
2554 clear_bit(VCF_TX, &vc->flags);
2555 clear_bit(VCF_IDLE, &vc->flags);
2556 clear_bit(VCF_RSV, &vc->flags);
2557 vc->tx_vcc = NULL;
2558
2559 if (vc->estimator) {
2560 del_timer(&vc->estimator->timer);
2561 kfree(vc->estimator);
2562 vc->estimator = NULL;
2563 }
2564 spin_unlock_irqrestore(&vc->lock, flags);
2565
2566 timeout = 5 * 1000;
2567 while (atomic_read(&vc->scq->used) > 0) {
2568 timeout = msleep_interruptible(timeout);
2569 if (!timeout)
2570 break;
2571 }
2572 if (!timeout)
2573 printk("%s: SCQ drain timeout: %u used\n",
2574 card->name, atomic_read(&vc->scq->used));
2575
2576 writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ);
2577 clear_scd(card, vc->scq, vc->class);
2578
2579 if (vc->class == SCHED_CBR) {
2580 clear_tst(card, vc);
2581 card->tst_free += vc->ntste;
2582 vc->ntste = 0;
2583 }
2584
2585 card->scd2vc[vc->scd_index] = NULL;
2586 free_scq(card, vc->scq);
2587 }
2588
2589 up(&card->mutex);
2590 }
2591
2592 static int
2593 idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
2594 {
2595 struct atm_dev *dev = vcc->dev;
2596 struct idt77252_dev *card = dev->dev_data;
2597 struct vc_map *vc = vcc->dev_data;
2598 int error = 0;
2599
2600 down(&card->mutex);
2601
2602 if (qos->txtp.traffic_class != ATM_NONE) {
2603 if (!test_bit(VCF_TX, &vc->flags)) {
2604 error = idt77252_init_tx(card, vc, vcc, qos);
2605 if (error)
2606 goto out;
2607 } else {
2608 switch (qos->txtp.traffic_class) {
2609 case ATM_CBR:
2610 error = idt77252_init_cbr(card, vc, vcc, qos);
2611 if (error)
2612 goto out;
2613 break;
2614
2615 case ATM_UBR:
2616 error = idt77252_init_ubr(card, vc, vcc, qos);
2617 if (error)
2618 goto out;
2619
2620 if (!test_bit(VCF_IDLE, &vc->flags)) {
2621 writel(TCMDQ_LACR | (vc->lacr << 16) |
2622 vc->index, SAR_REG_TCMDQ);
2623 }
2624 break;
2625
2626 case ATM_VBR:
2627 case ATM_ABR:
2628 error = -EOPNOTSUPP;
2629 goto out;
2630 }
2631 }
2632 }
2633
2634 if ((qos->rxtp.traffic_class != ATM_NONE) &&
2635 !test_bit(VCF_RX, &vc->flags)) {
2636 error = idt77252_init_rx(card, vc, vcc, qos);
2637 if (error)
2638 goto out;
2639 }
2640
2641 memcpy(&vcc->qos, qos, sizeof(struct atm_qos));
2642
2643 set_bit(ATM_VF_HASQOS, &vcc->flags);
2644
2645 out:
2646 up(&card->mutex);
2647 return error;
2648 }
2649
2650 static int
2651 idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2652 {
2653 struct idt77252_dev *card = dev->dev_data;
2654 int i, left;
2655
2656 left = (int) *pos;
2657 if (!left--)
2658 return sprintf(page, "IDT77252 Interrupts:\n");
2659 if (!left--)
2660 return sprintf(page, "TSIF: %lu\n", card->irqstat[15]);
2661 if (!left--)
2662 return sprintf(page, "TXICP: %lu\n", card->irqstat[14]);
2663 if (!left--)
2664 return sprintf(page, "TSQF: %lu\n", card->irqstat[12]);
2665 if (!left--)
2666 return sprintf(page, "TMROF: %lu\n", card->irqstat[11]);
2667 if (!left--)
2668 return sprintf(page, "PHYI: %lu\n", card->irqstat[10]);
2669 if (!left--)
2670 return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]);
2671 if (!left--)
2672 return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]);
2673 if (!left--)
2674 return sprintf(page, "RSQF: %lu\n", card->irqstat[6]);
2675 if (!left--)
2676 return sprintf(page, "EPDU: %lu\n", card->irqstat[5]);
2677 if (!left--)
2678 return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]);
2679 if (!left--)
2680 return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]);
2681 if (!left--)
2682 return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]);
2683 if (!left--)
2684 return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]);
2685 if (!left--)
2686 return sprintf(page, "IDT77252 Transmit Connection Table:\n");
2687
2688 for (i = 0; i < card->tct_size; i++) {
2689 unsigned long tct;
2690 struct atm_vcc *vcc;
2691 struct vc_map *vc;
2692 char *p;
2693
2694 vc = card->vcs[i];
2695 if (!vc)
2696 continue;
2697
2698 vcc = NULL;
2699 if (vc->tx_vcc)
2700 vcc = vc->tx_vcc;
2701 if (!vcc)
2702 continue;
2703 if (left--)
2704 continue;
2705
2706 p = page;
2707 p += sprintf(p, " %4u: %u.%u: ", i, vcc->vpi, vcc->vci);
2708 tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE);
2709
2710 for (i = 0; i < 8; i++)
2711 p += sprintf(p, " %08x", read_sram(card, tct + i));
2712 p += sprintf(p, "\n");
2713 return p - page;
2714 }
2715 return 0;
2716 }
2717
2718 /*****************************************************************************/
2719 /* */
2720 /* Interrupt handler */
2721 /* */
2722 /*****************************************************************************/
2723
2724 static void
2725 idt77252_collect_stat(struct idt77252_dev *card)
2726 {
2727 u32 cdc, vpec, icc;
2728
2729 cdc = readl(SAR_REG_CDC);
2730 vpec = readl(SAR_REG_VPEC);
2731 icc = readl(SAR_REG_ICC);
2732
2733 #ifdef NOTDEF
2734 printk("%s:", card->name);
2735
2736 if (cdc & 0x7f0000) {
2737 char *s = "";
2738
2739 printk(" [");
2740 if (cdc & (1 << 22)) {
2741 printk("%sRM ID", s);
2742 s = " | ";
2743 }
2744 if (cdc & (1 << 21)) {
2745 printk("%sCON TAB", s);
2746 s = " | ";
2747 }
2748 if (cdc & (1 << 20)) {
2749 printk("%sNO FB", s);
2750 s = " | ";
2751 }
2752 if (cdc & (1 << 19)) {
2753 printk("%sOAM CRC", s);
2754 s = " | ";
2755 }
2756 if (cdc & (1 << 18)) {
2757 printk("%sRM CRC", s);
2758 s = " | ";
2759 }
2760 if (cdc & (1 << 17)) {
2761 printk("%sRM FIFO", s);
2762 s = " | ";
2763 }
2764 if (cdc & (1 << 16)) {
2765 printk("%sRX FIFO", s);
2766 s = " | ";
2767 }
2768 printk("]");
2769 }
2770
2771 printk(" CDC %04x, VPEC %04x, ICC: %04x\n",
2772 cdc & 0xffff, vpec & 0xffff, icc & 0xffff);
2773 #endif
2774 }
2775
2776 static irqreturn_t
2777 idt77252_interrupt(int irq, void *dev_id)
2778 {
2779 struct idt77252_dev *card = dev_id;
2780 u32 stat;
2781
2782 stat = readl(SAR_REG_STAT) & 0xffff;
2783 if (!stat) /* no interrupt for us */
2784 return IRQ_NONE;
2785
2786 if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) {
2787 printk("%s: Re-entering irq_handler()\n", card->name);
2788 goto out;
2789 }
2790
2791 writel(stat, SAR_REG_STAT); /* reset interrupt */
2792
2793 if (stat & SAR_STAT_TSIF) { /* entry written to TSQ */
2794 INTPRINTK("%s: TSIF\n", card->name);
2795 card->irqstat[15]++;
2796 idt77252_tx(card);
2797 }
2798 if (stat & SAR_STAT_TXICP) { /* Incomplete CS-PDU has */
2799 INTPRINTK("%s: TXICP\n", card->name);
2800 card->irqstat[14]++;
2801 #ifdef CONFIG_ATM_IDT77252_DEBUG
2802 idt77252_tx_dump(card);
2803 #endif
2804 }
2805 if (stat & SAR_STAT_TSQF) { /* TSQ 7/8 full */
2806 INTPRINTK("%s: TSQF\n", card->name);
2807 card->irqstat[12]++;
2808 idt77252_tx(card);
2809 }
2810 if (stat & SAR_STAT_TMROF) { /* Timer overflow */
2811 INTPRINTK("%s: TMROF\n", card->name);
2812 card->irqstat[11]++;
2813 idt77252_collect_stat(card);
2814 }
2815
2816 if (stat & SAR_STAT_EPDU) { /* Got complete CS-PDU */
2817 INTPRINTK("%s: EPDU\n", card->name);
2818 card->irqstat[5]++;
2819 idt77252_rx(card);
2820 }
2821 if (stat & SAR_STAT_RSQAF) { /* RSQ is 7/8 full */
2822 INTPRINTK("%s: RSQAF\n", card->name);
2823 card->irqstat[1]++;
2824 idt77252_rx(card);
2825 }
2826 if (stat & SAR_STAT_RSQF) { /* RSQ is full */
2827 INTPRINTK("%s: RSQF\n", card->name);
2828 card->irqstat[6]++;
2829 idt77252_rx(card);
2830 }
2831 if (stat & SAR_STAT_RAWCF) { /* Raw cell received */
2832 INTPRINTK("%s: RAWCF\n", card->name);
2833 card->irqstat[4]++;
2834 idt77252_rx_raw(card);
2835 }
2836
2837 if (stat & SAR_STAT_PHYI) { /* PHY device interrupt */
2838 INTPRINTK("%s: PHYI", card->name);
2839 card->irqstat[10]++;
2840 if (card->atmdev->phy && card->atmdev->phy->interrupt)
2841 card->atmdev->phy->interrupt(card->atmdev);
2842 }
2843
2844 if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A |
2845 SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) {
2846
2847 writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG);
2848
2849 INTPRINTK("%s: FBQA: %04x\n", card->name, stat);
2850
2851 if (stat & SAR_STAT_FBQ0A)
2852 card->irqstat[2]++;
2853 if (stat & SAR_STAT_FBQ1A)
2854 card->irqstat[3]++;
2855 if (stat & SAR_STAT_FBQ2A)
2856 card->irqstat[7]++;
2857 if (stat & SAR_STAT_FBQ3A)
2858 card->irqstat[8]++;
2859
2860 schedule_work(&card->tqueue);
2861 }
2862
2863 out:
2864 clear_bit(IDT77252_BIT_INTERRUPT, &card->flags);
2865 return IRQ_HANDLED;
2866 }
2867
2868 static void
2869 idt77252_softint(struct work_struct *work)
2870 {
2871 struct idt77252_dev *card =
2872 container_of(work, struct idt77252_dev, tqueue);
2873 u32 stat;
2874 int done;
2875
2876 for (done = 1; ; done = 1) {
2877 stat = readl(SAR_REG_STAT) >> 16;
2878
2879 if ((stat & 0x0f) < SAR_FBQ0_HIGH) {
2880 add_rx_skb(card, 0, SAR_FB_SIZE_0, 32);
2881 done = 0;
2882 }
2883
2884 stat >>= 4;
2885 if ((stat & 0x0f) < SAR_FBQ1_HIGH) {
2886 add_rx_skb(card, 1, SAR_FB_SIZE_1, 32);
2887 done = 0;
2888 }
2889
2890 stat >>= 4;
2891 if ((stat & 0x0f) < SAR_FBQ2_HIGH) {
2892 add_rx_skb(card, 2, SAR_FB_SIZE_2, 32);
2893 done = 0;
2894 }
2895
2896 stat >>= 4;
2897 if ((stat & 0x0f) < SAR_FBQ3_HIGH) {
2898 add_rx_skb(card, 3, SAR_FB_SIZE_3, 32);
2899 done = 0;
2900 }
2901
2902 if (done)
2903 break;
2904 }
2905
2906 writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG);
2907 }
2908
2909
2910 static int
2911 open_card_oam(struct idt77252_dev *card)
2912 {
2913 unsigned long flags;
2914 unsigned long addr;
2915 struct vc_map *vc;
2916 int vpi, vci;
2917 int index;
2918 u32 rcte;
2919
2920 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2921 for (vci = 3; vci < 5; vci++) {
2922 index = VPCI2VC(card, vpi, vci);
2923
2924 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2925 if (!vc) {
2926 printk("%s: can't alloc vc\n", card->name);
2927 return -ENOMEM;
2928 }
2929 vc->index = index;
2930 card->vcs[index] = vc;
2931
2932 flush_rx_pool(card, &vc->rcv.rx_pool);
2933
2934 rcte = SAR_RCTE_CONNECTOPEN |
2935 SAR_RCTE_RAWCELLINTEN |
2936 SAR_RCTE_RCQ |
2937 SAR_RCTE_FBP_1;
2938
2939 addr = card->rct_base + (vc->index << 2);
2940 write_sram(card, addr, rcte);
2941
2942 spin_lock_irqsave(&card->cmd_lock, flags);
2943 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2),
2944 SAR_REG_CMD);
2945 waitfor_idle(card);
2946 spin_unlock_irqrestore(&card->cmd_lock, flags);
2947 }
2948 }
2949
2950 return 0;
2951 }
2952
2953 static void
2954 close_card_oam(struct idt77252_dev *card)
2955 {
2956 unsigned long flags;
2957 unsigned long addr;
2958 struct vc_map *vc;
2959 int vpi, vci;
2960 int index;
2961
2962 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2963 for (vci = 3; vci < 5; vci++) {
2964 index = VPCI2VC(card, vpi, vci);
2965 vc = card->vcs[index];
2966
2967 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2968
2969 spin_lock_irqsave(&card->cmd_lock, flags);
2970 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2),
2971 SAR_REG_CMD);
2972 waitfor_idle(card);
2973 spin_unlock_irqrestore(&card->cmd_lock, flags);
2974
2975 if (vc->rcv.rx_pool.count) {
2976 DPRINTK("%s: closing a VC "
2977 "with pending rx buffers.\n",
2978 card->name);
2979
2980 recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2981 }
2982 }
2983 }
2984 }
2985
2986 static int
2987 open_card_ubr0(struct idt77252_dev *card)
2988 {
2989 struct vc_map *vc;
2990
2991 vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL);
2992 if (!vc) {
2993 printk("%s: can't alloc vc\n", card->name);
2994 return -ENOMEM;
2995 }
2996 card->vcs[0] = vc;
2997 vc->class = SCHED_UBR0;
2998
2999 vc->scq = alloc_scq(card, vc->class);
3000 if (!vc->scq) {
3001 printk("%s: can't get SCQ.\n", card->name);
3002 return -ENOMEM;
3003 }
3004
3005 card->scd2vc[0] = vc;
3006 vc->scd_index = 0;
3007 vc->scq->scd = card->scd_base;
3008
3009 fill_scd(card, vc->scq, vc->class);
3010
3011 write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base);
3012 write_sram(card, card->tct_base + 1, 0);
3013 write_sram(card, card->tct_base + 2, 0);
3014 write_sram(card, card->tct_base + 3, 0);
3015 write_sram(card, card->tct_base + 4, 0);
3016 write_sram(card, card->tct_base + 5, 0);
3017 write_sram(card, card->tct_base + 6, 0);
3018 write_sram(card, card->tct_base + 7, TCT_FLAG_UBR);
3019
3020 clear_bit(VCF_IDLE, &vc->flags);
3021 writel(TCMDQ_START | 0, SAR_REG_TCMDQ);
3022 return 0;
3023 }
3024
3025 static int
3026 idt77252_dev_open(struct idt77252_dev *card)
3027 {
3028 u32 conf;
3029
3030 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
3031 printk("%s: SAR not yet initialized.\n", card->name);
3032 return -1;
3033 }
3034
3035 conf = SAR_CFG_RXPTH| /* enable receive path */
3036 SAR_RX_DELAY | /* interrupt on complete PDU */
3037 SAR_CFG_RAWIE | /* interrupt enable on raw cells */
3038 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */
3039 SAR_CFG_TMOIE | /* interrupt on timer overflow */
3040 SAR_CFG_FBIE | /* interrupt on low free buffers */
3041 SAR_CFG_TXEN | /* transmit operation enable */
3042 SAR_CFG_TXINT | /* interrupt on transmit status */
3043 SAR_CFG_TXUIE | /* interrupt on transmit underrun */
3044 SAR_CFG_TXSFI | /* interrupt on TSQ almost full */
3045 SAR_CFG_PHYIE /* enable PHY interrupts */
3046 ;
3047
3048 #ifdef CONFIG_ATM_IDT77252_RCV_ALL
3049 /* Test RAW cell receive. */
3050 conf |= SAR_CFG_VPECA;
3051 #endif
3052
3053 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3054
3055 if (open_card_oam(card)) {
3056 printk("%s: Error initializing OAM.\n", card->name);
3057 return -1;
3058 }
3059
3060 if (open_card_ubr0(card)) {
3061 printk("%s: Error initializing UBR0.\n", card->name);
3062 return -1;
3063 }
3064
3065 IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name);
3066 return 0;
3067 }
3068
3069 void
3070 idt77252_dev_close(struct atm_dev *dev)
3071 {
3072 struct idt77252_dev *card = dev->dev_data;
3073 u32 conf;
3074
3075 close_card_oam(card);
3076
3077 conf = SAR_CFG_RXPTH | /* enable receive path */
3078 SAR_RX_DELAY | /* interrupt on complete PDU */
3079 SAR_CFG_RAWIE | /* interrupt enable on raw cells */
3080 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */
3081 SAR_CFG_TMOIE | /* interrupt on timer overflow */
3082 SAR_CFG_FBIE | /* interrupt on low free buffers */
3083 SAR_CFG_TXEN | /* transmit operation enable */
3084 SAR_CFG_TXINT | /* interrupt on transmit status */
3085 SAR_CFG_TXUIE | /* interrupt on xmit underrun */
3086 SAR_CFG_TXSFI /* interrupt on TSQ almost full */
3087 ;
3088
3089 writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG);
3090
3091 DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name);
3092 }
3093
3094
3095 /*****************************************************************************/
3096 /* */
3097 /* Initialisation and Deinitialization of IDT77252 */
3098 /* */
3099 /*****************************************************************************/
3100
3101
3102 static void
3103 deinit_card(struct idt77252_dev *card)
3104 {
3105 struct sk_buff *skb;
3106 int i, j;
3107
3108 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
3109 printk("%s: SAR not yet initialized.\n", card->name);
3110 return;
3111 }
3112 DIPRINTK("idt77252: deinitialize card %u\n", card->index);
3113
3114 writel(0, SAR_REG_CFG);
3115
3116 if (card->atmdev)
3117 atm_dev_deregister(card->atmdev);
3118
3119 for (i = 0; i < 4; i++) {
3120 for (j = 0; j < FBQ_SIZE; j++) {
3121 skb = card->sbpool[i].skb[j];
3122 if (skb) {
3123 pci_unmap_single(card->pcidev,
3124 IDT77252_PRV_PADDR(skb),
3125 skb->end - skb->data,
3126 PCI_DMA_FROMDEVICE);
3127 card->sbpool[i].skb[j] = NULL;
3128 dev_kfree_skb(skb);
3129 }
3130 }
3131 }
3132
3133 vfree(card->soft_tst);
3134
3135 vfree(card->scd2vc);
3136
3137 vfree(card->vcs);
3138
3139 if (card->raw_cell_hnd) {
3140 pci_free_consistent(card->pcidev, 2 * sizeof(u32),
3141 card->raw_cell_hnd, card->raw_cell_paddr);
3142 }
3143
3144 if (card->rsq.base) {
3145 DIPRINTK("%s: Release RSQ ...\n", card->name);
3146 deinit_rsq(card);
3147 }
3148
3149 if (card->tsq.base) {
3150 DIPRINTK("%s: Release TSQ ...\n", card->name);
3151 deinit_tsq(card);
3152 }
3153
3154 DIPRINTK("idt77252: Release IRQ.\n");
3155 free_irq(card->pcidev->irq, card);
3156
3157 for (i = 0; i < 4; i++) {
3158 if (card->fbq[i])
3159 iounmap(card->fbq[i]);
3160 }
3161
3162 if (card->membase)
3163 iounmap(card->membase);
3164
3165 clear_bit(IDT77252_BIT_INIT, &card->flags);
3166 DIPRINTK("%s: Card deinitialized.\n", card->name);
3167 }
3168
3169
3170 static int __devinit
3171 init_sram(struct idt77252_dev *card)
3172 {
3173 int i;
3174
3175 for (i = 0; i < card->sramsize; i += 4)
3176 write_sram(card, (i >> 2), 0);
3177
3178 /* set SRAM layout for THIS card */
3179 if (card->sramsize == (512 * 1024)) {
3180 card->tct_base = SAR_SRAM_TCT_128_BASE;
3181 card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1)
3182 / SAR_SRAM_TCT_SIZE;
3183 card->rct_base = SAR_SRAM_RCT_128_BASE;
3184 card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1)
3185 / SAR_SRAM_RCT_SIZE;
3186 card->rt_base = SAR_SRAM_RT_128_BASE;
3187 card->scd_base = SAR_SRAM_SCD_128_BASE;
3188 card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1)
3189 / SAR_SRAM_SCD_SIZE;
3190 card->tst[0] = SAR_SRAM_TST1_128_BASE;
3191 card->tst[1] = SAR_SRAM_TST2_128_BASE;
3192 card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1;
3193 card->abrst_base = SAR_SRAM_ABRSTD_128_BASE;
3194 card->abrst_size = SAR_ABRSTD_SIZE_8K;
3195 card->fifo_base = SAR_SRAM_FIFO_128_BASE;
3196 card->fifo_size = SAR_RXFD_SIZE_32K;
3197 } else {
3198 card->tct_base = SAR_SRAM_TCT_32_BASE;
3199 card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1)
3200 / SAR_SRAM_TCT_SIZE;
3201 card->rct_base = SAR_SRAM_RCT_32_BASE;
3202 card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1)
3203 / SAR_SRAM_RCT_SIZE;
3204 card->rt_base = SAR_SRAM_RT_32_BASE;
3205 card->scd_base = SAR_SRAM_SCD_32_BASE;
3206 card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1)
3207 / SAR_SRAM_SCD_SIZE;
3208 card->tst[0] = SAR_SRAM_TST1_32_BASE;
3209 card->tst[1] = SAR_SRAM_TST2_32_BASE;
3210 card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1);
3211 card->abrst_base = SAR_SRAM_ABRSTD_32_BASE;
3212 card->abrst_size = SAR_ABRSTD_SIZE_1K;
3213 card->fifo_base = SAR_SRAM_FIFO_32_BASE;
3214 card->fifo_size = SAR_RXFD_SIZE_4K;
3215 }
3216
3217 /* Initialize TCT */
3218 for (i = 0; i < card->tct_size; i++) {
3219 write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0);
3220 write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0);
3221 write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0);
3222 write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0);
3223 write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0);
3224 write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0);
3225 write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0);
3226 write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0);
3227 }
3228
3229 /* Initialize RCT */
3230 for (i = 0; i < card->rct_size; i++) {
3231 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE,
3232 (u32) SAR_RCTE_RAWCELLINTEN);
3233 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1,
3234 (u32) 0);
3235 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2,
3236 (u32) 0);
3237 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3,
3238 (u32) 0xffffffff);
3239 }
3240
3241 writel((SAR_FBQ0_LOW << 28) | 0x00000000 | 0x00000000 |
3242 (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0);
3243 writel((SAR_FBQ1_LOW << 28) | 0x00000000 | 0x00000000 |
3244 (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1);
3245 writel((SAR_FBQ2_LOW << 28) | 0x00000000 | 0x00000000 |
3246 (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2);
3247 writel((SAR_FBQ3_LOW << 28) | 0x00000000 | 0x00000000 |
3248 (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3);
3249
3250 /* Initialize rate table */
3251 for (i = 0; i < 256; i++) {
3252 write_sram(card, card->rt_base + i, log_to_rate[i]);
3253 }
3254
3255 for (i = 0; i < 128; i++) {
3256 unsigned int tmp;
3257
3258 tmp = rate_to_log[(i << 2) + 0] << 0;
3259 tmp |= rate_to_log[(i << 2) + 1] << 8;
3260 tmp |= rate_to_log[(i << 2) + 2] << 16;
3261 tmp |= rate_to_log[(i << 2) + 3] << 24;
3262 write_sram(card, card->rt_base + 256 + i, tmp);
3263 }
3264
3265 #if 0 /* Fill RDF and AIR tables. */
3266 for (i = 0; i < 128; i++) {
3267 unsigned int tmp;
3268
3269 tmp = RDF[0][(i << 1) + 0] << 16;
3270 tmp |= RDF[0][(i << 1) + 1] << 0;
3271 write_sram(card, card->rt_base + 512 + i, tmp);
3272 }
3273
3274 for (i = 0; i < 128; i++) {
3275 unsigned int tmp;
3276
3277 tmp = AIR[0][(i << 1) + 0] << 16;
3278 tmp |= AIR[0][(i << 1) + 1] << 0;
3279 write_sram(card, card->rt_base + 640 + i, tmp);
3280 }
3281 #endif
3282
3283 IPRINTK("%s: initialize rate table ...\n", card->name);
3284 writel(card->rt_base << 2, SAR_REG_RTBL);
3285
3286 /* Initialize TSTs */
3287 IPRINTK("%s: initialize TST ...\n", card->name);
3288 card->tst_free = card->tst_size - 2; /* last two are jumps */
3289
3290 for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++)
3291 write_sram(card, i, TSTE_OPC_VAR);
3292 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3293 idt77252_sram_write_errors = 1;
3294 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3295 idt77252_sram_write_errors = 0;
3296 for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++)
3297 write_sram(card, i, TSTE_OPC_VAR);
3298 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3299 idt77252_sram_write_errors = 1;
3300 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3301 idt77252_sram_write_errors = 0;
3302
3303 card->tst_index = 0;
3304 writel(card->tst[0] << 2, SAR_REG_TSTB);
3305
3306 /* Initialize ABRSTD and Receive FIFO */
3307 IPRINTK("%s: initialize ABRSTD ...\n", card->name);
3308 writel(card->abrst_size | (card->abrst_base << 2),
3309 SAR_REG_ABRSTD);
3310
3311 IPRINTK("%s: initialize receive fifo ...\n", card->name);
3312 writel(card->fifo_size | (card->fifo_base << 2),
3313 SAR_REG_RXFD);
3314
3315 IPRINTK("%s: SRAM initialization complete.\n", card->name);
3316 return 0;
3317 }
3318
3319 static int __devinit
3320 init_card(struct atm_dev *dev)
3321 {
3322 struct idt77252_dev *card = dev->dev_data;
3323 struct pci_dev *pcidev = card->pcidev;
3324 unsigned long tmpl, modl;
3325 unsigned int linkrate, rsvdcr;
3326 unsigned int tst_entries;
3327 struct net_device *tmp;
3328 char tname[10];
3329
3330 u32 size;
3331 u_char pci_byte;
3332 u32 conf;
3333 int i, k;
3334
3335 if (test_bit(IDT77252_BIT_INIT, &card->flags)) {
3336 printk("Error: SAR already initialized.\n");
3337 return -1;
3338 }
3339
3340 /*****************************************************************/
3341 /* P C I C O N F I G U R A T I O N */
3342 /*****************************************************************/
3343
3344 /* Set PCI Retry-Timeout and TRDY timeout */
3345 IPRINTK("%s: Checking PCI retries.\n", card->name);
3346 if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) {
3347 printk("%s: can't read PCI retry timeout.\n", card->name);
3348 deinit_card(card);
3349 return -1;
3350 }
3351 if (pci_byte != 0) {
3352 IPRINTK("%s: PCI retry timeout: %d, set to 0.\n",
3353 card->name, pci_byte);
3354 if (pci_write_config_byte(pcidev, 0x40, 0) != 0) {
3355 printk("%s: can't set PCI retry timeout.\n",
3356 card->name);
3357 deinit_card(card);
3358 return -1;
3359 }
3360 }
3361 IPRINTK("%s: Checking PCI TRDY.\n", card->name);
3362 if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) {
3363 printk("%s: can't read PCI TRDY timeout.\n", card->name);
3364 deinit_card(card);
3365 return -1;
3366 }
3367 if (pci_byte != 0) {
3368 IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n",
3369 card->name, pci_byte);
3370 if (pci_write_config_byte(pcidev, 0x41, 0) != 0) {
3371 printk("%s: can't set PCI TRDY timeout.\n", card->name);
3372 deinit_card(card);
3373 return -1;
3374 }
3375 }
3376 /* Reset Timer register */
3377 if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) {
3378 printk("%s: resetting timer overflow.\n", card->name);
3379 writel(SAR_STAT_TMROF, SAR_REG_STAT);
3380 }
3381 IPRINTK("%s: Request IRQ ... ", card->name);
3382 if (request_irq(pcidev->irq, idt77252_interrupt, IRQF_DISABLED|IRQF_SHARED,
3383 card->name, card) != 0) {
3384 printk("%s: can't allocate IRQ.\n", card->name);
3385 deinit_card(card);
3386 return -1;
3387 }
3388 IPRINTK("got %d.\n", pcidev->irq);
3389
3390 /*****************************************************************/
3391 /* C H E C K A N D I N I T S R A M */
3392 /*****************************************************************/
3393
3394 IPRINTK("%s: Initializing SRAM\n", card->name);
3395
3396 /* preset size of connecton table, so that init_sram() knows about it */
3397 conf = SAR_CFG_TX_FIFO_SIZE_9 | /* Use maximum fifo size */
3398 SAR_CFG_RXSTQ_SIZE_8k | /* Receive Status Queue is 8k */
3399 SAR_CFG_IDLE_CLP | /* Set CLP on idle cells */
3400 #ifndef CONFIG_ATM_IDT77252_SEND_IDLE
3401 SAR_CFG_NO_IDLE | /* Do not send idle cells */
3402 #endif
3403 0;
3404
3405 if (card->sramsize == (512 * 1024))
3406 conf |= SAR_CFG_CNTBL_1k;
3407 else
3408 conf |= SAR_CFG_CNTBL_512;
3409
3410 switch (vpibits) {
3411 case 0:
3412 conf |= SAR_CFG_VPVCS_0;
3413 break;
3414 default:
3415 case 1:
3416 conf |= SAR_CFG_VPVCS_1;
3417 break;
3418 case 2:
3419 conf |= SAR_CFG_VPVCS_2;
3420 break;
3421 case 8:
3422 conf |= SAR_CFG_VPVCS_8;
3423 break;
3424 }
3425
3426 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3427
3428 if (init_sram(card) < 0)
3429 return -1;
3430
3431 /********************************************************************/
3432 /* A L L O C R A M A N D S E T V A R I O U S T H I N G S */
3433 /********************************************************************/
3434 /* Initialize TSQ */
3435 if (0 != init_tsq(card)) {
3436 deinit_card(card);
3437 return -1;
3438 }
3439 /* Initialize RSQ */
3440 if (0 != init_rsq(card)) {
3441 deinit_card(card);
3442 return -1;
3443 }
3444
3445 card->vpibits = vpibits;
3446 if (card->sramsize == (512 * 1024)) {
3447 card->vcibits = 10 - card->vpibits;
3448 } else {
3449 card->vcibits = 9 - card->vpibits;
3450 }
3451
3452 card->vcimask = 0;
3453 for (k = 0, i = 1; k < card->vcibits; k++) {
3454 card->vcimask |= i;
3455 i <<= 1;
3456 }
3457
3458 IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name);
3459 writel(0, SAR_REG_VPM);
3460
3461 /* Little Endian Order */
3462 writel(0, SAR_REG_GP);
3463
3464 /* Initialize RAW Cell Handle Register */
3465 card->raw_cell_hnd = pci_alloc_consistent(card->pcidev, 2 * sizeof(u32),
3466 &card->raw_cell_paddr);
3467 if (!card->raw_cell_hnd) {
3468 printk("%s: memory allocation failure.\n", card->name);
3469 deinit_card(card);
3470 return -1;
3471 }
3472 memset(card->raw_cell_hnd, 0, 2 * sizeof(u32));
3473 writel(card->raw_cell_paddr, SAR_REG_RAWHND);
3474 IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name,
3475 card->raw_cell_hnd);
3476
3477 size = sizeof(struct vc_map *) * card->tct_size;
3478 IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size);
3479 if (NULL == (card->vcs = vmalloc(size))) {
3480 printk("%s: memory allocation failure.\n", card->name);
3481 deinit_card(card);
3482 return -1;
3483 }
3484 memset(card->vcs, 0, size);
3485
3486 size = sizeof(struct vc_map *) * card->scd_size;
3487 IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n",
3488 card->name, size);
3489 if (NULL == (card->scd2vc = vmalloc(size))) {
3490 printk("%s: memory allocation failure.\n", card->name);
3491 deinit_card(card);
3492 return -1;
3493 }
3494 memset(card->scd2vc, 0, size);
3495
3496 size = sizeof(struct tst_info) * (card->tst_size - 2);
3497 IPRINTK("%s: allocate %d byte for TST to VC mapping.\n",
3498 card->name, size);
3499 if (NULL == (card->soft_tst = vmalloc(size))) {
3500 printk("%s: memory allocation failure.\n", card->name);
3501 deinit_card(card);
3502 return -1;
3503 }
3504 for (i = 0; i < card->tst_size - 2; i++) {
3505 card->soft_tst[i].tste = TSTE_OPC_VAR;
3506 card->soft_tst[i].vc = NULL;
3507 }
3508
3509 if (dev->phy == NULL) {
3510 printk("%s: No LT device defined.\n", card->name);
3511 deinit_card(card);
3512 return -1;
3513 }
3514 if (dev->phy->ioctl == NULL) {
3515 printk("%s: LT had no IOCTL funtion defined.\n", card->name);
3516 deinit_card(card);
3517 return -1;
3518 }
3519
3520 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
3521 /*
3522 * this is a jhs hack to get around special functionality in the
3523 * phy driver for the atecom hardware; the functionality doesn't
3524 * exist in the linux atm suni driver
3525 *
3526 * it isn't the right way to do things, but as the guy from NIST
3527 * said, talking about their measurement of the fine structure
3528 * constant, "it's good enough for government work."
3529 */
3530 linkrate = 149760000;
3531 #endif
3532
3533 card->link_pcr = (linkrate / 8 / 53);
3534 printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n",
3535 card->name, linkrate, card->link_pcr);
3536
3537 #ifdef CONFIG_ATM_IDT77252_SEND_IDLE
3538 card->utopia_pcr = card->link_pcr;
3539 #else
3540 card->utopia_pcr = (160000000 / 8 / 54);
3541 #endif
3542
3543 rsvdcr = 0;
3544 if (card->utopia_pcr > card->link_pcr)
3545 rsvdcr = card->utopia_pcr - card->link_pcr;
3546
3547 tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2);
3548 modl = tmpl % (unsigned long)card->utopia_pcr;
3549 tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr);
3550 if (modl)
3551 tst_entries++;
3552 card->tst_free -= tst_entries;
3553 fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL);
3554
3555 #ifdef HAVE_EEPROM
3556 idt77252_eeprom_init(card);
3557 printk("%s: EEPROM: %02x:", card->name,
3558 idt77252_eeprom_read_status(card));
3559
3560 for (i = 0; i < 0x80; i++) {
3561 printk(" %02x",
3562 idt77252_eeprom_read_byte(card, i)
3563 );
3564 }
3565 printk("\n");
3566 #endif /* HAVE_EEPROM */
3567
3568 /*
3569 * XXX: <hack>
3570 */
3571 sprintf(tname, "eth%d", card->index);
3572 tmp = dev_get_by_name(tname); /* jhs: was "tmp = dev_get(tname);" */
3573 if (tmp) {
3574 memcpy(card->atmdev->esi, tmp->dev_addr, 6);
3575
3576 printk("%s: ESI %02x:%02x:%02x:%02x:%02x:%02x\n",
3577 card->name, card->atmdev->esi[0], card->atmdev->esi[1],
3578 card->atmdev->esi[2], card->atmdev->esi[3],
3579 card->atmdev->esi[4], card->atmdev->esi[5]);
3580 }
3581 /*
3582 * XXX: </hack>
3583 */
3584
3585 /* Set Maximum Deficit Count for now. */
3586 writel(0xffff, SAR_REG_MDFCT);
3587
3588 set_bit(IDT77252_BIT_INIT, &card->flags);
3589
3590 XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name);
3591 return 0;
3592 }
3593
3594
3595 /*****************************************************************************/
3596 /* */
3597 /* Probing of IDT77252 ABR SAR */
3598 /* */
3599 /*****************************************************************************/
3600
3601
3602 static int __devinit
3603 idt77252_preset(struct idt77252_dev *card)
3604 {
3605 u16 pci_command;
3606
3607 /*****************************************************************/
3608 /* P C I C O N F I G U R A T I O N */
3609 /*****************************************************************/
3610
3611 XPRINTK("%s: Enable PCI master and memory access for SAR.\n",
3612 card->name);
3613 if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) {
3614 printk("%s: can't read PCI_COMMAND.\n", card->name);
3615 deinit_card(card);
3616 return -1;
3617 }
3618 if (!(pci_command & PCI_COMMAND_IO)) {
3619 printk("%s: PCI_COMMAND: %04x (???)\n",
3620 card->name, pci_command);
3621 deinit_card(card);
3622 return (-1);
3623 }
3624 pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
3625 if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) {
3626 printk("%s: can't write PCI_COMMAND.\n", card->name);
3627 deinit_card(card);
3628 return -1;
3629 }
3630 /*****************************************************************/
3631 /* G E N E R I C R E S E T */
3632 /*****************************************************************/
3633
3634 /* Software reset */
3635 writel(SAR_CFG_SWRST, SAR_REG_CFG);
3636 mdelay(1);
3637 writel(0, SAR_REG_CFG);
3638
3639 IPRINTK("%s: Software resetted.\n", card->name);
3640 return 0;
3641 }
3642
3643
3644 static unsigned long __devinit
3645 probe_sram(struct idt77252_dev *card)
3646 {
3647 u32 data, addr;
3648
3649 writel(0, SAR_REG_DR0);
3650 writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD);
3651
3652 for (addr = 0x4000; addr < 0x80000; addr += 0x4000) {
3653 writel(ATM_POISON, SAR_REG_DR0);
3654 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
3655
3656 writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD);
3657 data = readl(SAR_REG_DR0);
3658
3659 if (data != 0)
3660 break;
3661 }
3662
3663 return addr * sizeof(u32);
3664 }
3665
3666 static int __devinit
3667 idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id)
3668 {
3669 static struct idt77252_dev **last = &idt77252_chain;
3670 static int index = 0;
3671
3672 unsigned long membase, srambase;
3673 struct idt77252_dev *card;
3674 struct atm_dev *dev;
3675 ushort revision = 0;
3676 int i, err;
3677
3678
3679 if ((err = pci_enable_device(pcidev))) {
3680 printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev));
3681 return err;
3682 }
3683
3684 if (pci_read_config_word(pcidev, PCI_REVISION_ID, &revision)) {
3685 printk("idt77252-%d: can't read PCI_REVISION_ID\n", index);
3686 err = -ENODEV;
3687 goto err_out_disable_pdev;
3688 }
3689
3690 card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL);
3691 if (!card) {
3692 printk("idt77252-%d: can't allocate private data\n", index);
3693 err = -ENOMEM;
3694 goto err_out_disable_pdev;
3695 }
3696 card->revision = revision;
3697 card->index = index;
3698 card->pcidev = pcidev;
3699 sprintf(card->name, "idt77252-%d", card->index);
3700
3701 INIT_WORK(&card->tqueue, idt77252_softint);
3702
3703 membase = pci_resource_start(pcidev, 1);
3704 srambase = pci_resource_start(pcidev, 2);
3705
3706 init_MUTEX(&card->mutex);
3707 spin_lock_init(&card->cmd_lock);
3708 spin_lock_init(&card->tst_lock);
3709
3710 init_timer(&card->tst_timer);
3711 card->tst_timer.data = (unsigned long)card;
3712 card->tst_timer.function = tst_timer;
3713
3714 /* Do the I/O remapping... */
3715 card->membase = ioremap(membase, 1024);
3716 if (!card->membase) {
3717 printk("%s: can't ioremap() membase\n", card->name);
3718 err = -EIO;
3719 goto err_out_free_card;
3720 }
3721
3722 if (idt77252_preset(card)) {
3723 printk("%s: preset failed\n", card->name);
3724 err = -EIO;
3725 goto err_out_iounmap;
3726 }
3727
3728 dev = atm_dev_register("idt77252", &idt77252_ops, -1, NULL);
3729 if (!dev) {
3730 printk("%s: can't register atm device\n", card->name);
3731 err = -EIO;
3732 goto err_out_iounmap;
3733 }
3734 dev->dev_data = card;
3735 card->atmdev = dev;
3736
3737 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
3738 suni_init(dev);
3739 if (!dev->phy) {
3740 printk("%s: can't init SUNI\n", card->name);
3741 err = -EIO;
3742 goto err_out_deinit_card;
3743 }
3744 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
3745
3746 card->sramsize = probe_sram(card);
3747
3748 for (i = 0; i < 4; i++) {
3749 card->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4);
3750 if (!card->fbq[i]) {
3751 printk("%s: can't ioremap() FBQ%d\n", card->name, i);
3752 err = -EIO;
3753 goto err_out_deinit_card;
3754 }
3755 }
3756
3757 printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n",
3758 card->name, ((revision > 1) && (revision < 25)) ?
3759 'A' + revision - 1 : '?', membase, srambase,
3760 card->sramsize / 1024);
3761
3762 if (init_card(dev)) {
3763 printk("%s: init_card failed\n", card->name);
3764 err = -EIO;
3765 goto err_out_deinit_card;
3766 }
3767
3768 dev->ci_range.vpi_bits = card->vpibits;
3769 dev->ci_range.vci_bits = card->vcibits;
3770 dev->link_rate = card->link_pcr;
3771
3772 if (dev->phy->start)
3773 dev->phy->start(dev);
3774
3775 if (idt77252_dev_open(card)) {
3776 printk("%s: dev_open failed\n", card->name);
3777 err = -EIO;
3778 goto err_out_stop;
3779 }
3780
3781 *last = card;
3782 last = &card->next;
3783 index++;
3784
3785 return 0;
3786
3787 err_out_stop:
3788 if (dev->phy->stop)
3789 dev->phy->stop(dev);
3790
3791 err_out_deinit_card:
3792 deinit_card(card);
3793
3794 err_out_iounmap:
3795 iounmap(card->membase);
3796
3797 err_out_free_card:
3798 kfree(card);
3799
3800 err_out_disable_pdev:
3801 pci_disable_device(pcidev);
3802 return err;
3803 }
3804
3805 static struct pci_device_id idt77252_pci_tbl[] =
3806 {
3807 { PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_IDT_IDT77252,
3808 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
3809 { 0, }
3810 };
3811
3812 MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl);
3813
3814 static struct pci_driver idt77252_driver = {
3815 .name = "idt77252",
3816 .id_table = idt77252_pci_tbl,
3817 .probe = idt77252_init_one,
3818 };
3819
3820 static int __init idt77252_init(void)
3821 {
3822 struct sk_buff *skb;
3823
3824 printk("%s: at %p\n", __FUNCTION__, idt77252_init);
3825
3826 if (sizeof(skb->cb) < sizeof(struct atm_skb_data) +
3827 sizeof(struct idt77252_skb_prv)) {
3828 printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n",
3829 __FUNCTION__, (unsigned long) sizeof(skb->cb),
3830 (unsigned long) sizeof(struct atm_skb_data) +
3831 sizeof(struct idt77252_skb_prv));
3832 return -EIO;
3833 }
3834
3835 return pci_register_driver(&idt77252_driver);
3836 }
3837
3838 static void __exit idt77252_exit(void)
3839 {
3840 struct idt77252_dev *card;
3841 struct atm_dev *dev;
3842
3843 pci_unregister_driver(&idt77252_driver);
3844
3845 while (idt77252_chain) {
3846 card = idt77252_chain;
3847 dev = card->atmdev;
3848 idt77252_chain = card->next;
3849
3850 if (dev->phy->stop)
3851 dev->phy->stop(dev);
3852 deinit_card(card);
3853 pci_disable_device(card->pcidev);
3854 kfree(card);
3855 }
3856
3857 DIPRINTK("idt77252: finished cleanup-module().\n");
3858 }
3859
3860 module_init(idt77252_init);
3861 module_exit(idt77252_exit);
3862
3863 MODULE_LICENSE("GPL");
3864
3865 module_param(vpibits, uint, 0);
3866 MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)");
3867 #ifdef CONFIG_ATM_IDT77252_DEBUG
3868 module_param(debug, ulong, 0644);
3869 MODULE_PARM_DESC(debug, "debug bitmap, see drivers/atm/idt77252.h");
3870 #endif
3871
3872 MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>");
3873 MODULE_DESCRIPTION("IDT77252 ABR SAR Driver");
Support for the Chinese Samsung S3C2440 based development boards