drivers/ide/ide-dma-sff.c

   1 #include <linux/types.h>
   2 #include <linux/kernel.h>
   3 #include <linux/ide.h>
   4 #include <linux/scatterlist.h>
   5 #include <linux/dma-mapping.h>
   6 #include <linux/io.h>
   7
   8 /**
   9  *      config_drive_for_dma    -       attempt to activate IDE DMA
  10  *      @drive: the drive to place in DMA mode
  11  *
  12  *      If the drive supports at least mode 2 DMA or UDMA of any kind
  13  *      then attempt to place it into DMA mode. Drives that are known to
  14  *      support DMA but predate the DMA properties or that are known
  15  *      to have DMA handling bugs are also set up appropriately based
  16  *      on the good/bad drive lists.
  17  */
  18
  19 int config_drive_for_dma(ide_drive_t *drive)
  20 {
  21         ide_hwif_t *hwif = drive->hwif;
  22         u16 *id = drive->id;
  23
  24         if (drive->media != ide_disk) {
  25                 if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA)
  26                         return 0;
  27         }
  28
  29         /*
  30          * Enable DMA on any drive that has
  31          * UltraDMA (mode 0/1/2/3/4/5/6) enabled
  32          */
  33         if ((id[ATA_ID_FIELD_VALID] & 4) &&
  34             ((id[ATA_ID_UDMA_MODES] >> 8) & 0x7f))
  35                 return 1;
  36
  37         /*
  38          * Enable DMA on any drive that has mode2 DMA
  39          * (multi or single) enabled
  40          */
  41         if (id[ATA_ID_FIELD_VALID] & 2) /* regular DMA */
  42                 if ((id[ATA_ID_MWDMA_MODES] & 0x404) == 0x404 ||
  43                     (id[ATA_ID_SWDMA_MODES] & 0x404) == 0x404)
  44                         return 1;
  45
  46         /* Consult the list of known "good" drives */
  47         if (ide_dma_good_drive(drive))
  48                 return 1;
  49
  50         return 0;
  51 }
  52
  53 /**
  54  *      ide_dma_host_set        -       Enable/disable DMA on a host
  55  *      @drive: drive to control
  56  *
  57  *      Enable/disable DMA on an IDE controller following generic
  58  *      bus-mastering IDE controller behaviour.
  59  */
  60
  61 void ide_dma_host_set(ide_drive_t *drive, int on)
  62 {
  63         ide_hwif_t *hwif = drive->hwif;
  64         u8 unit = drive->dn & 1;
  65         u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
  66
  67         if (on)
  68                 dma_stat |= (1 << (5 + unit));
  69         else
  70                 dma_stat &= ~(1 << (5 + unit));
  71
  72         if (hwif->host_flags & IDE_HFLAG_MMIO)
  73                 writeb(dma_stat,
  74                        (void __iomem *)(hwif->dma_base + ATA_DMA_STATUS));
  75         else
  76                 outb(dma_stat, hwif->dma_base + ATA_DMA_STATUS);
  77 }
  78 EXPORT_SYMBOL_GPL(ide_dma_host_set);
  79
  80 /**
  81  *      ide_build_dmatable      -       build IDE DMA table
  82  *
  83  *      ide_build_dmatable() prepares a dma request. We map the command
  84  *      to get the pci bus addresses of the buffers and then build up
  85  *      the PRD table that the IDE layer wants to be fed.
  86  *
  87  *      Most chipsets correctly interpret a length of 0x0000 as 64KB,
  88  *      but at least one (e.g. CS5530) misinterprets it as zero (!).
  89  *      So we break the 64KB entry into two 32KB entries instead.
  90  *
  91  *      Returns the number of built PRD entries if all went okay,
  92  *      returns 0 otherwise.
  93  *
  94  *      May also be invoked from trm290.c
  95  */
  96
  97 int ide_build_dmatable(ide_drive_t *drive, struct request *rq)
  98 {
  99         ide_hwif_t *hwif = drive->hwif;
 100         __le32 *table = (__le32 *)hwif->dmatable_cpu;
 101         unsigned int is_trm290  = (hwif->chipset == ide_trm290) ? 1 : 0;
 102         unsigned int count = 0;
 103         int i;
 104         struct scatterlist *sg;
 105
 106         hwif->sg_nents = ide_build_sglist(drive, rq);
 107         if (hwif->sg_nents == 0)
 108                 return 0;
 109
 110         for_each_sg(hwif->sg_table, sg, hwif->sg_nents, i) {
 111                 u32 cur_addr, cur_len, xcount, bcount;
 112
 113                 cur_addr = sg_dma_address(sg);
 114                 cur_len = sg_dma_len(sg);
 115
 116                 /*
 117                  * Fill in the dma table, without crossing any 64kB boundaries.
 118                  * Most hardware requires 16-bit alignment of all blocks,
 119                  * but the trm290 requires 32-bit alignment.
 120                  */
 121
 122                 while (cur_len) {
 123                         if (count++ >= PRD_ENTRIES)
 124                                 goto use_pio_instead;
 125
 126                         bcount = 0x10000 - (cur_addr & 0xffff);
 127                         if (bcount > cur_len)
 128                                 bcount = cur_len;
 129                         *table++ = cpu_to_le32(cur_addr);
 130                         xcount = bcount & 0xffff;
 131                         if (is_trm290)
 132                                 xcount = ((xcount >> 2) - 1) << 16;
 133                         else if (xcount == 0x0000) {
 134                                 if (count++ >= PRD_ENTRIES)
 135                                         goto use_pio_instead;
 136                                 *table++ = cpu_to_le32(0x8000);
 137                                 *table++ = cpu_to_le32(cur_addr + 0x8000);
 138                                 xcount = 0x8000;
 139                         }
 140                         *table++ = cpu_to_le32(xcount);
 141                         cur_addr += bcount;
 142                         cur_len -= bcount;
 143                 }
 144         }
 145
 146         if (count) {
 147                 if (!is_trm290)
 148                         *--table |= cpu_to_le32(0x80000000);
 149                 return count;
 150         }
 151
 152 use_pio_instead:
 153         printk(KERN_ERR "%s: %s\n", drive->name,
 154                 count ? "DMA table too small" : "empty DMA table?");
 155
 156         ide_destroy_dmatable(drive);
 157
 158         return 0; /* revert to PIO for this request */
 159 }
 160 EXPORT_SYMBOL_GPL(ide_build_dmatable);
 161
 162 /**
 163  *      ide_dma_setup   -       begin a DMA phase
 164  *      @drive: target device
 165  *
 166  *      Build an IDE DMA PRD (IDE speak for scatter gather table)
 167  *      and then set up the DMA transfer registers for a device
 168  *      that follows generic IDE PCI DMA behaviour. Controllers can
 169  *      override this function if they need to
 170  *
 171  *      Returns 0 on success. If a PIO fallback is required then 1
 172  *      is returned.
 173  */
 174
 175 int ide_dma_setup(ide_drive_t *drive)
 176 {
 177         ide_hwif_t *hwif = drive->hwif;
 178         struct request *rq = hwif->hwgroup->rq;
 179         unsigned int reading;
 180         u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
 181         u8 dma_stat;
 182
 183         if (rq_data_dir(rq))
 184                 reading = 0;
 185         else
 186                 reading = 1 << 3;
 187
 188         /* fall back to pio! */
 189         if (!ide_build_dmatable(drive, rq)) {
 190                 ide_map_sg(drive, rq);
 191                 return 1;
 192         }
 193
 194         /* PRD table */
 195         if (hwif->host_flags & IDE_HFLAG_MMIO)
 196                 writel(hwif->dmatable_dma,
 197                        (void __iomem *)(hwif->dma_base + ATA_DMA_TABLE_OFS));
 198         else
 199                 outl(hwif->dmatable_dma, hwif->dma_base + ATA_DMA_TABLE_OFS);
 200
 201         /* specify r/w */
 202         if (mmio)
 203                 writeb(reading, (void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
 204         else
 205                 outb(reading, hwif->dma_base + ATA_DMA_CMD);
 206
 207         /* read DMA status for INTR & ERROR flags */
 208         dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
 209
 210         /* clear INTR & ERROR flags */
 211         if (mmio)
 212                 writeb(dma_stat | 6,
 213                        (void __iomem *)(hwif->dma_base + ATA_DMA_STATUS));
 214         else
 215                 outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
 216
 217         drive->waiting_for_dma = 1;
 218         return 0;
 219 }
 220 EXPORT_SYMBOL_GPL(ide_dma_setup);
 221
 222 /**
 223  *      dma_timer_expiry        -       handle a DMA timeout
 224  *      @drive: Drive that timed out
 225  *
 226  *      An IDE DMA transfer timed out. In the event of an error we ask
 227  *      the driver to resolve the problem, if a DMA transfer is still
 228  *      in progress we continue to wait (arguably we need to add a
 229  *      secondary 'I don't care what the drive thinks' timeout here)
 230  *      Finally if we have an interrupt we let it complete the I/O.
 231  *      But only one time - we clear expiry and if it's still not
 232  *      completed after WAIT_CMD, we error and retry in PIO.
 233  *      This can occur if an interrupt is lost or due to hang or bugs.
 234  */
 235
 236 static int dma_timer_expiry(ide_drive_t *drive)
 237 {
 238         ide_hwif_t *hwif = drive->hwif;
 239         u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
 240
 241         printk(KERN_WARNING "%s: %s: DMA status (0x%02x)\n",
 242                 drive->name, __func__, dma_stat);
 243
 244         if ((dma_stat & 0x18) == 0x18)  /* BUSY Stupid Early Timer !! */
 245                 return WAIT_CMD;
 246
 247         hwif->hwgroup->expiry = NULL;   /* one free ride for now */
 248
 249         /* 1 dmaing, 2 error, 4 intr */
 250         if (dma_stat & 2)       /* ERROR */
 251                 return -1;
 252
 253         if (dma_stat & 1)       /* DMAing */
 254                 return WAIT_CMD;
 255
 256         if (dma_stat & 4)       /* Got an Interrupt */
 257                 return WAIT_CMD;
 258
 259         return 0;       /* Status is unknown -- reset the bus */
 260 }
 261
 262 void ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
 263 {
 264         /* issue cmd to drive */
 265         ide_execute_command(drive, command, &ide_dma_intr, 2 * WAIT_CMD,
 266                             dma_timer_expiry);
 267 }
 268 EXPORT_SYMBOL_GPL(ide_dma_exec_cmd);
 269
 270 void ide_dma_start(ide_drive_t *drive)
 271 {
 272         ide_hwif_t *hwif = drive->hwif;
 273         u8 dma_cmd;
 274
 275         /* Note that this is done *after* the cmd has
 276          * been issued to the drive, as per the BM-IDE spec.
 277          * The Promise Ultra33 doesn't work correctly when
 278          * we do this part before issuing the drive cmd.
 279          */
 280         if (hwif->host_flags & IDE_HFLAG_MMIO) {
 281                 dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
 282                 /* start DMA */
 283                 writeb(dma_cmd | 1,
 284                        (void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
 285         } else {
 286                 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
 287                 outb(dma_cmd | 1, hwif->dma_base + ATA_DMA_CMD);
 288         }
 289
 290         wmb();
 291 }
 292 EXPORT_SYMBOL_GPL(ide_dma_start);
 293
 294 /* returns 1 on error, 0 otherwise */
 295 int ide_dma_end(ide_drive_t *drive)
 296 {
 297         ide_hwif_t *hwif = drive->hwif;
 298         u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
 299         u8 dma_stat = 0, dma_cmd = 0;
 300
 301         drive->waiting_for_dma = 0;
 302
 303         if (mmio) {
 304                 /* get DMA command mode */
 305                 dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
 306                 /* stop DMA */
 307                 writeb(dma_cmd & ~1,
 308                        (void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
 309         } else {
 310                 dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
 311                 outb(dma_cmd & ~1, hwif->dma_base + ATA_DMA_CMD);
 312         }
 313
 314         /* get DMA status */
 315         dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
 316
 317         if (mmio)
 318                 /* clear the INTR & ERROR bits */
 319                 writeb(dma_stat | 6,
 320                        (void __iomem *)(hwif->dma_base + ATA_DMA_STATUS));
 321         else
 322                 outb(dma_stat | 6, hwif->dma_base + ATA_DMA_STATUS);
 323
 324         /* purge DMA mappings */
 325         ide_destroy_dmatable(drive);
 326         /* verify good DMA status */
 327         wmb();
 328         return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
 329 }
 330 EXPORT_SYMBOL_GPL(ide_dma_end);
 331
 332 /* returns 1 if dma irq issued, 0 otherwise */
 333 int ide_dma_test_irq(ide_drive_t *drive)
 334 {
 335         ide_hwif_t *hwif = drive->hwif;
 336         u8 dma_stat = hwif->tp_ops->read_sff_dma_status(hwif);
 337
 338         /* return 1 if INTR asserted */
 339         if ((dma_stat & 4) == 4)
 340                 return 1;
 341
 342         return 0;
 343 }
 344 EXPORT_SYMBOL_GPL(ide_dma_test_irq);
 345
 346 const struct ide_dma_ops sff_dma_ops = {
 347         .dma_host_set           = ide_dma_host_set,
 348         .dma_setup              = ide_dma_setup,
 349         .dma_exec_cmd           = ide_dma_exec_cmd,
 350         .dma_start              = ide_dma_start,
 351         .dma_end                = ide_dma_end,
 352         .dma_test_irq           = ide_dma_test_irq,
 353         .dma_timeout            = ide_dma_timeout,
 354         .dma_lost_irq           = ide_dma_lost_irq,
 355 };
 356 EXPORT_SYMBOL_GPL(sff_dma_ops);