2 * Copyright (c) 2003-2006 Silicon Graphics, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
8 * This program is distributed in the hope that it would be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
12 * You should have received a copy of the GNU General Public
13 * License along with this program; if not, write the Free Software
14 * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 * For further information regarding this notice, see:
18 * http://oss.sgi.com/projects/GenInfo/NoticeExplan
21 #include <linux/module.h>
22 #include <linux/types.h>
23 #include <linux/pci.h>
24 #include <linux/delay.h>
25 #include <linux/hdreg.h>
26 #include <linux/init.h>
27 #include <linux/kernel.h>
28 #include <linux/timer.h>
30 #include <linux/ioport.h>
31 #include <linux/blkdev.h>
32 #include <linux/ioc4.h>
35 #include <linux/ide.h>
37 /* IOC4 Specific Definitions */
38 #define IOC4_CMD_OFFSET 0x100
39 #define IOC4_CTRL_OFFSET 0x120
40 #define IOC4_DMA_OFFSET 0x140
41 #define IOC4_INTR_OFFSET 0x0
43 #define IOC4_TIMING 0x00
44 #define IOC4_DMA_PTR_L 0x01
45 #define IOC4_DMA_PTR_H 0x02
46 #define IOC4_DMA_ADDR_L 0x03
47 #define IOC4_DMA_ADDR_H 0x04
48 #define IOC4_BC_DEV 0x05
49 #define IOC4_BC_MEM 0x06
50 #define IOC4_DMA_CTRL 0x07
51 #define IOC4_DMA_END_ADDR 0x08
53 /* Bits in the IOC4 Control/Status Register */
54 #define IOC4_S_DMA_START 0x01
55 #define IOC4_S_DMA_STOP 0x02
56 #define IOC4_S_DMA_DIR 0x04
57 #define IOC4_S_DMA_ACTIVE 0x08
58 #define IOC4_S_DMA_ERROR 0x10
59 #define IOC4_ATA_MEMERR 0x02
61 /* Read/Write Directions */
62 #define IOC4_DMA_WRITE 0x04
63 #define IOC4_DMA_READ 0x00
65 /* Interrupt Register Offsets */
66 #define IOC4_INTR_REG 0x03
67 #define IOC4_INTR_SET 0x05
68 #define IOC4_INTR_CLEAR 0x07
70 #define IOC4_IDE_CACHELINE_SIZE 128
71 #define IOC4_CMD_CTL_BLK_SIZE 0x20
72 #define IOC4_SUPPORTED_FIRMWARE_REV 46
86 /* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */
87 /* IOC4 has only 1 IDE channel */
88 #define IOC4_PRD_BYTES 16
89 #define IOC4_PRD_ENTRIES (PAGE_SIZE /(4*IOC4_PRD_BYTES))
93 sgiioc4_init_hwif_ports(hw_regs_t
* hw
, unsigned long data_port
,
94 unsigned long ctrl_port
, unsigned long irq_port
)
96 unsigned long reg
= data_port
;
99 /* Registers are word (32 bit) aligned */
100 for (i
= IDE_DATA_OFFSET
; i
<= IDE_STATUS_OFFSET
; i
++)
101 hw
->io_ports
[i
] = reg
+ i
* 4;
104 hw
->io_ports
[IDE_CONTROL_OFFSET
] = ctrl_port
;
107 hw
->io_ports
[IDE_IRQ_OFFSET
] = irq_port
;
111 sgiioc4_maskproc(ide_drive_t
* drive
, int mask
)
113 writeb(mask
? (drive
->ctl
| 2) : (drive
->ctl
& ~2),
114 (void __iomem
*)IDE_CONTROL_REG
);
119 sgiioc4_checkirq(ide_hwif_t
* hwif
)
121 unsigned long intr_addr
=
122 hwif
->io_ports
[IDE_IRQ_OFFSET
] + IOC4_INTR_REG
* 4;
124 if ((u8
)readl((void __iomem
*)intr_addr
) & 0x03)
130 static u8
sgiioc4_INB(unsigned long);
133 sgiioc4_clearirq(ide_drive_t
* drive
)
136 ide_hwif_t
*hwif
= HWIF(drive
);
137 unsigned long other_ir
=
138 hwif
->io_ports
[IDE_IRQ_OFFSET
] + (IOC4_INTR_REG
<< 2);
140 /* Code to check for PCI error conditions */
141 intr_reg
= readl((void __iomem
*)other_ir
);
142 if (intr_reg
& 0x03) { /* Valid IOC4-IDE interrupt */
144 * Using sgiioc4_INB to read the IDE_STATUS_REG has a side effect
145 * of clearing the interrupt. The first read should clear it
146 * if it is set. The second read should return a "clear" status
147 * if it got cleared. If not, then spin for a bit trying to
150 u8 stat
= sgiioc4_INB(IDE_STATUS_REG
);
152 stat
= sgiioc4_INB(IDE_STATUS_REG
);
153 while ((stat
& 0x80) && (count
++ < 100)) {
155 stat
= sgiioc4_INB(IDE_STATUS_REG
);
158 if (intr_reg
& 0x02) {
159 /* Error when transferring DMA data on PCI bus */
160 u32 pci_err_addr_low
, pci_err_addr_high
,
164 readl((void __iomem
*)hwif
->io_ports
[IDE_IRQ_OFFSET
]);
166 readl((void __iomem
*)(hwif
->io_ports
[IDE_IRQ_OFFSET
] + 4));
167 pci_read_config_dword(hwif
->pci_dev
, PCI_COMMAND
,
170 "%s(%s) : PCI Bus Error when doing DMA:"
171 " status-cmd reg is 0x%x\n",
172 __FUNCTION__
, drive
->name
, pci_stat_cmd_reg
);
174 "%s(%s) : PCI Error Address is 0x%x%x\n",
175 __FUNCTION__
, drive
->name
,
176 pci_err_addr_high
, pci_err_addr_low
);
177 /* Clear the PCI Error indicator */
178 pci_write_config_dword(hwif
->pci_dev
, PCI_COMMAND
,
182 /* Clear the Interrupt, Error bits on the IOC4 */
183 writel(0x03, (void __iomem
*)other_ir
);
185 intr_reg
= readl((void __iomem
*)other_ir
);
191 static void sgiioc4_ide_dma_start(ide_drive_t
* drive
)
193 ide_hwif_t
*hwif
= HWIF(drive
);
194 unsigned long ioc4_dma_addr
= hwif
->dma_base
+ IOC4_DMA_CTRL
* 4;
195 unsigned int reg
= readl((void __iomem
*)ioc4_dma_addr
);
196 unsigned int temp_reg
= reg
| IOC4_S_DMA_START
;
198 writel(temp_reg
, (void __iomem
*)ioc4_dma_addr
);
202 sgiioc4_ide_dma_stop(ide_hwif_t
*hwif
, u64 dma_base
)
204 unsigned long ioc4_dma_addr
= dma_base
+ IOC4_DMA_CTRL
* 4;
209 ioc4_dma
= readl((void __iomem
*)ioc4_dma_addr
);
210 while ((ioc4_dma
& IOC4_S_DMA_STOP
) && (count
++ < 200)) {
212 ioc4_dma
= readl((void __iomem
*)ioc4_dma_addr
);
217 /* Stops the IOC4 DMA Engine */
219 sgiioc4_ide_dma_end(ide_drive_t
* drive
)
221 u32 ioc4_dma
, bc_dev
, bc_mem
, num
, valid
= 0, cnt
= 0;
222 ide_hwif_t
*hwif
= HWIF(drive
);
223 unsigned long dma_base
= hwif
->dma_base
;
225 unsigned long *ending_dma
= ide_get_hwifdata(hwif
);
227 writel(IOC4_S_DMA_STOP
, (void __iomem
*)(dma_base
+ IOC4_DMA_CTRL
* 4));
229 ioc4_dma
= sgiioc4_ide_dma_stop(hwif
, dma_base
);
231 if (ioc4_dma
& IOC4_S_DMA_STOP
) {
233 "%s(%s): IOC4 DMA STOP bit is still 1 :"
234 "ioc4_dma_reg 0x%x\n",
235 __FUNCTION__
, drive
->name
, ioc4_dma
);
240 * The IOC4 will DMA 1's to the ending dma area to indicate that
241 * previous data DMA is complete. This is necessary because of relaxed
242 * ordering between register reads and DMA writes on the Altix.
244 while ((cnt
++ < 200) && (!valid
)) {
245 for (num
= 0; num
< 16; num
++) {
246 if (ending_dma
[num
]) {
254 printk(KERN_ERR
"%s(%s) : DMA incomplete\n", __FUNCTION__
,
259 bc_dev
= readl((void __iomem
*)(dma_base
+ IOC4_BC_DEV
* 4));
260 bc_mem
= readl((void __iomem
*)(dma_base
+ IOC4_BC_MEM
* 4));
262 if ((bc_dev
& 0x01FF) || (bc_mem
& 0x1FF)) {
263 if (bc_dev
> bc_mem
+ 8) {
265 "%s(%s): WARNING!! byte_count_dev %d "
266 "!= byte_count_mem %d\n",
267 __FUNCTION__
, drive
->name
, bc_dev
, bc_mem
);
271 drive
->waiting_for_dma
= 0;
272 ide_destroy_dmatable(drive
);
278 sgiioc4_ide_dma_on(ide_drive_t
* drive
)
280 drive
->using_dma
= 1;
285 static void sgiioc4_dma_off_quietly(ide_drive_t
*drive
)
287 drive
->using_dma
= 0;
289 drive
->hwif
->dma_host_off(drive
);
292 static int sgiioc4_ide_dma_check(ide_drive_t
*drive
)
294 /* FIXME: check for available DMA modes */
295 if (ide_config_drive_speed(drive
, XFER_MW_DMA_2
) != 0) {
296 printk(KERN_WARNING
"%s: couldn't set MWDMA2 mode, "
297 "using PIO instead\n", drive
->name
);
303 /* returns 1 if dma irq issued, 0 otherwise */
305 sgiioc4_ide_dma_test_irq(ide_drive_t
* drive
)
307 return sgiioc4_checkirq(HWIF(drive
));
310 static void sgiioc4_dma_host_on(ide_drive_t
* drive
)
314 static void sgiioc4_dma_host_off(ide_drive_t
* drive
)
316 sgiioc4_clearirq(drive
);
320 sgiioc4_ide_dma_lostirq(ide_drive_t
* drive
)
322 HWIF(drive
)->resetproc(drive
);
324 return __ide_dma_lostirq(drive
);
328 sgiioc4_resetproc(ide_drive_t
* drive
)
330 sgiioc4_ide_dma_end(drive
);
331 sgiioc4_clearirq(drive
);
335 sgiioc4_INB(unsigned long port
)
337 u8 reg
= (u8
) readb((void __iomem
*) port
);
339 if ((port
& 0xFFF) == 0x11C) { /* Status register of IOC4 */
340 if (reg
& 0x51) { /* Not busy...check for interrupt */
341 unsigned long other_ir
= port
- 0x110;
342 unsigned int intr_reg
= (u32
) readl((void __iomem
*) other_ir
);
344 /* Clear the Interrupt, Error bits on the IOC4 */
345 if (intr_reg
& 0x03) {
346 writel(0x03, (void __iomem
*) other_ir
);
347 intr_reg
= (u32
) readl((void __iomem
*) other_ir
);
355 /* Creates a dma map for the scatter-gather list entries */
356 static void __devinit
357 ide_dma_sgiioc4(ide_hwif_t
* hwif
, unsigned long dma_base
)
359 void __iomem
*virt_dma_base
;
360 int num_ports
= sizeof (ioc4_dma_regs_t
);
363 printk(KERN_INFO
"%s: BM-DMA at 0x%04lx-0x%04lx\n", hwif
->name
,
364 dma_base
, dma_base
+ num_ports
- 1);
366 if (!request_mem_region(dma_base
, num_ports
, hwif
->name
)) {
368 "%s(%s) -- ERROR, Addresses 0x%p to 0x%p "
370 __FUNCTION__
, hwif
->name
, (void *) dma_base
,
371 (void *) dma_base
+ num_ports
- 1);
372 goto dma_alloc_failure
;
375 virt_dma_base
= ioremap(dma_base
, num_ports
);
376 if (virt_dma_base
== NULL
) {
378 "%s(%s) -- ERROR, Unable to map addresses 0x%lx to 0x%lx\n",
379 __FUNCTION__
, hwif
->name
, dma_base
, dma_base
+ num_ports
- 1);
380 goto dma_remap_failure
;
382 hwif
->dma_base
= (unsigned long) virt_dma_base
;
384 hwif
->dmatable_cpu
= pci_alloc_consistent(hwif
->pci_dev
,
385 IOC4_PRD_ENTRIES
* IOC4_PRD_BYTES
,
386 &hwif
->dmatable_dma
);
388 if (!hwif
->dmatable_cpu
)
389 goto dma_pci_alloc_failure
;
391 hwif
->sg_max_nents
= IOC4_PRD_ENTRIES
;
393 pad
= pci_alloc_consistent(hwif
->pci_dev
, IOC4_IDE_CACHELINE_SIZE
,
394 (dma_addr_t
*) &(hwif
->dma_status
));
397 ide_set_hwifdata(hwif
, pad
);
401 pci_free_consistent(hwif
->pci_dev
,
402 IOC4_PRD_ENTRIES
* IOC4_PRD_BYTES
,
403 hwif
->dmatable_cpu
, hwif
->dmatable_dma
);
405 "%s() -- Error! Unable to allocate DMA Maps for drive %s\n",
406 __FUNCTION__
, hwif
->name
);
408 "Changing from DMA to PIO mode for Drive %s\n", hwif
->name
);
410 dma_pci_alloc_failure
:
411 iounmap(virt_dma_base
);
414 release_mem_region(dma_base
, num_ports
);
417 /* Disable DMA because we couldnot allocate any DMA maps */
422 /* Initializes the IOC4 DMA Engine */
424 sgiioc4_configure_for_dma(int dma_direction
, ide_drive_t
* drive
)
427 ide_hwif_t
*hwif
= HWIF(drive
);
428 unsigned long dma_base
= hwif
->dma_base
;
429 unsigned long ioc4_dma_addr
= dma_base
+ IOC4_DMA_CTRL
* 4;
430 u32 dma_addr
, ending_dma_addr
;
432 ioc4_dma
= readl((void __iomem
*)ioc4_dma_addr
);
434 if (ioc4_dma
& IOC4_S_DMA_ACTIVE
) {
436 "%s(%s):Warning!! DMA from previous transfer was still active\n",
437 __FUNCTION__
, drive
->name
);
438 writel(IOC4_S_DMA_STOP
, (void __iomem
*)ioc4_dma_addr
);
439 ioc4_dma
= sgiioc4_ide_dma_stop(hwif
, dma_base
);
441 if (ioc4_dma
& IOC4_S_DMA_STOP
)
443 "%s(%s) : IOC4 Dma STOP bit is still 1\n",
444 __FUNCTION__
, drive
->name
);
447 ioc4_dma
= readl((void __iomem
*)ioc4_dma_addr
);
448 if (ioc4_dma
& IOC4_S_DMA_ERROR
) {
450 "%s(%s) : Warning!! - DMA Error during Previous"
451 " transfer | status 0x%x\n",
452 __FUNCTION__
, drive
->name
, ioc4_dma
);
453 writel(IOC4_S_DMA_STOP
, (void __iomem
*)ioc4_dma_addr
);
454 ioc4_dma
= sgiioc4_ide_dma_stop(hwif
, dma_base
);
456 if (ioc4_dma
& IOC4_S_DMA_STOP
)
458 "%s(%s) : IOC4 DMA STOP bit is still 1\n",
459 __FUNCTION__
, drive
->name
);
462 /* Address of the Scatter Gather List */
463 dma_addr
= cpu_to_le32(hwif
->dmatable_dma
);
464 writel(dma_addr
, (void __iomem
*)(dma_base
+ IOC4_DMA_PTR_L
* 4));
466 /* Address of the Ending DMA */
467 memset(ide_get_hwifdata(hwif
), 0, IOC4_IDE_CACHELINE_SIZE
);
468 ending_dma_addr
= cpu_to_le32(hwif
->dma_status
);
469 writel(ending_dma_addr
, (void __iomem
*)(dma_base
+ IOC4_DMA_END_ADDR
* 4));
471 writel(dma_direction
, (void __iomem
*)ioc4_dma_addr
);
472 drive
->waiting_for_dma
= 1;
475 /* IOC4 Scatter Gather list Format */
476 /* 128 Bit entries to support 64 bit addresses in the future */
477 /* The Scatter Gather list Entry should be in the BIG-ENDIAN Format */
478 /* --------------------------------------------------------------------- */
479 /* | Upper 32 bits - Zero | Lower 32 bits- address | */
480 /* --------------------------------------------------------------------- */
481 /* | Upper 32 bits - Zero |EOL| 15 unused | 16 Bit Length| */
482 /* --------------------------------------------------------------------- */
483 /* Creates the scatter gather list, DMA Table */
485 sgiioc4_build_dma_table(ide_drive_t
* drive
, struct request
*rq
, int ddir
)
487 ide_hwif_t
*hwif
= HWIF(drive
);
488 unsigned int *table
= hwif
->dmatable_cpu
;
489 unsigned int count
= 0, i
= 1;
490 struct scatterlist
*sg
;
492 hwif
->sg_nents
= i
= ide_build_sglist(drive
, rq
);
495 return 0; /* sglist of length Zero */
498 while (i
&& sg_dma_len(sg
)) {
501 cur_addr
= sg_dma_address(sg
);
502 cur_len
= sg_dma_len(sg
);
505 if (count
++ >= IOC4_PRD_ENTRIES
) {
507 "%s: DMA table too small\n",
509 goto use_pio_instead
;
512 0x10000 - (cur_addr
& 0xffff);
514 if (bcount
> cur_len
)
517 /* put the addr, length in
518 * the IOC4 dma-table format */
521 *table
= cpu_to_be32(cur_addr
);
526 *table
= cpu_to_be32(bcount
);
540 *table
|= cpu_to_be32(0x80000000);
545 pci_unmap_sg(hwif
->pci_dev
, hwif
->sg_table
, hwif
->sg_nents
,
546 hwif
->sg_dma_direction
);
548 return 0; /* revert to PIO for this request */
551 static int sgiioc4_ide_dma_setup(ide_drive_t
*drive
)
553 struct request
*rq
= HWGROUP(drive
)->rq
;
554 unsigned int count
= 0;
558 ddir
= PCI_DMA_TODEVICE
;
560 ddir
= PCI_DMA_FROMDEVICE
;
562 if (!(count
= sgiioc4_build_dma_table(drive
, rq
, ddir
))) {
563 /* try PIO instead of DMA */
564 ide_map_sg(drive
, rq
);
569 /* Writes TO the IOC4 FROM Main Memory */
570 ddir
= IOC4_DMA_READ
;
572 /* Writes FROM the IOC4 TO Main Memory */
573 ddir
= IOC4_DMA_WRITE
;
575 sgiioc4_configure_for_dma(ddir
, drive
);
580 static void __devinit
581 ide_init_sgiioc4(ide_hwif_t
* hwif
)
586 hwif
->ultra_mask
= 0x0; /* Disable Ultra DMA */
587 hwif
->mwdma_mask
= 0x2; /* Multimode-2 DMA */
588 hwif
->swdma_mask
= 0x2;
589 hwif
->tuneproc
= NULL
; /* Sets timing for PIO mode */
590 hwif
->speedproc
= NULL
; /* Sets timing for DMA &/or PIO modes */
591 hwif
->selectproc
= NULL
;/* Use the default routine to select drive */
592 hwif
->reset_poll
= NULL
;/* No HBA specific reset_poll needed */
593 hwif
->pre_reset
= NULL
; /* No HBA specific pre_set needed */
594 hwif
->resetproc
= &sgiioc4_resetproc
;/* Reset DMA engine,
596 hwif
->intrproc
= NULL
; /* Enable or Disable interrupt from drive */
597 hwif
->maskproc
= &sgiioc4_maskproc
; /* Mask on/off NIEN register */
598 hwif
->quirkproc
= NULL
;
599 hwif
->busproc
= NULL
;
601 hwif
->dma_setup
= &sgiioc4_ide_dma_setup
;
602 hwif
->dma_start
= &sgiioc4_ide_dma_start
;
603 hwif
->ide_dma_end
= &sgiioc4_ide_dma_end
;
604 hwif
->ide_dma_check
= &sgiioc4_ide_dma_check
;
605 hwif
->ide_dma_on
= &sgiioc4_ide_dma_on
;
606 hwif
->dma_off_quietly
= &sgiioc4_dma_off_quietly
;
607 hwif
->ide_dma_test_irq
= &sgiioc4_ide_dma_test_irq
;
608 hwif
->dma_host_on
= &sgiioc4_dma_host_on
;
609 hwif
->dma_host_off
= &sgiioc4_dma_host_off
;
610 hwif
->ide_dma_lostirq
= &sgiioc4_ide_dma_lostirq
;
611 hwif
->ide_dma_timeout
= &__ide_dma_timeout
;
613 hwif
->INB
= &sgiioc4_INB
;
617 sgiioc4_ide_setup_pci_device(struct pci_dev
*dev
, ide_pci_device_t
* d
)
619 unsigned long cmd_base
, dma_base
, irqport
;
620 unsigned long bar0
, cmd_phys_base
, ctl
;
621 void __iomem
*virt_base
;
626 * Find an empty HWIF; if none available, return -ENOMEM.
628 for (h
= 0; h
< MAX_HWIFS
; ++h
) {
629 hwif
= &ide_hwifs
[h
];
630 if (hwif
->chipset
== ide_unknown
)
633 if (h
== MAX_HWIFS
) {
634 printk(KERN_ERR
"%s: too many IDE interfaces, no room in table\n", d
->name
);
638 /* Get the CmdBlk and CtrlBlk Base Registers */
639 bar0
= pci_resource_start(dev
, 0);
640 virt_base
= ioremap(bar0
, pci_resource_len(dev
, 0));
641 if (virt_base
== NULL
) {
642 printk(KERN_ERR
"%s: Unable to remap BAR 0 address: 0x%lx\n",
646 cmd_base
= (unsigned long) virt_base
+ IOC4_CMD_OFFSET
;
647 ctl
= (unsigned long) virt_base
+ IOC4_CTRL_OFFSET
;
648 irqport
= (unsigned long) virt_base
+ IOC4_INTR_OFFSET
;
649 dma_base
= pci_resource_start(dev
, 0) + IOC4_DMA_OFFSET
;
651 cmd_phys_base
= bar0
+ IOC4_CMD_OFFSET
;
652 if (!request_mem_region(cmd_phys_base
, IOC4_CMD_CTL_BLK_SIZE
,
655 "%s : %s -- ERROR, Addresses "
656 "0x%p to 0x%p ALREADY in use\n",
657 __FUNCTION__
, hwif
->name
, (void *) cmd_phys_base
,
658 (void *) cmd_phys_base
+ IOC4_CMD_CTL_BLK_SIZE
);
662 if (hwif
->io_ports
[IDE_DATA_OFFSET
] != cmd_base
) {
663 /* Initialize the IO registers */
664 sgiioc4_init_hwif_ports(&hwif
->hw
, cmd_base
, ctl
, irqport
);
665 memcpy(hwif
->io_ports
, hwif
->hw
.io_ports
,
666 sizeof (hwif
->io_ports
));
667 hwif
->noprobe
= !hwif
->io_ports
[IDE_DATA_OFFSET
];
670 hwif
->irq
= dev
->irq
;
671 hwif
->chipset
= ide_pci
;
673 hwif
->channel
= 0; /* Single Channel chip */
674 hwif
->cds
= (struct ide_pci_device_s
*) d
;
675 hwif
->gendev
.parent
= &dev
->dev
;/* setup proper ancestral information */
677 /* The IOC4 uses MMIO rather than Port IO. */
678 default_hwif_mmiops(hwif
);
680 /* Initializing chipset IRQ Registers */
681 writel(0x03, (void __iomem
*)(irqport
+ IOC4_INTR_SET
* 4));
683 ide_init_sgiioc4(hwif
);
686 ide_dma_sgiioc4(hwif
, dma_base
);
688 printk(KERN_INFO
"%s: %s Bus-Master DMA disabled\n",
689 hwif
->name
, d
->name
);
691 if (probe_hwif_init(hwif
))
694 /* Create /proc/ide entries */
695 create_proc_ide_interfaces();
700 static unsigned int __devinit
701 pci_init_sgiioc4(struct pci_dev
*dev
, ide_pci_device_t
* d
)
703 unsigned int class_rev
;
706 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class_rev
);
708 printk(KERN_INFO
"%s: IDE controller at PCI slot %s, revision %d\n",
709 d
->name
, pci_name(dev
), class_rev
);
710 if (class_rev
< IOC4_SUPPORTED_FIRMWARE_REV
) {
711 printk(KERN_ERR
"Skipping %s IDE controller in slot %s: "
712 "firmware is obsolete - please upgrade to revision"
713 "46 or higher\n", d
->name
, pci_name(dev
));
717 ret
= sgiioc4_ide_setup_pci_device(dev
, d
);
722 static ide_pci_device_t sgiioc4_chipset __devinitdata
= {
725 .init_hwif
= ide_init_sgiioc4
,
726 .init_dma
= ide_dma_sgiioc4
,
729 /* SGI IOC4 doesn't have enablebits. */
730 .bootable
= ON_BOARD
,
734 ioc4_ide_attach_one(struct ioc4_driver_data
*idd
)
736 /* PCI-RT does not bring out IDE connection.
737 * Do not attach to this particular IOC4.
739 if (idd
->idd_variant
== IOC4_VARIANT_PCI_RT
)
742 return pci_init_sgiioc4(idd
->idd_pdev
, &sgiioc4_chipset
);
745 static struct ioc4_submodule ioc4_ide_submodule
= {
746 .is_name
= "IOC4_ide",
747 .is_owner
= THIS_MODULE
,
748 .is_probe
= ioc4_ide_attach_one
,
749 /* .is_remove = ioc4_ide_remove_one, */
752 static int __init
ioc4_ide_init(void)
754 return ioc4_register_submodule(&ioc4_ide_submodule
);
757 late_initcall(ioc4_ide_init
); /* Call only after IDE init is done */
759 MODULE_AUTHOR("Aniket Malatpure/Jeremy Higdon");
760 MODULE_DESCRIPTION("IDE PCI driver module for SGI IOC4 Base-IO Card");
761 MODULE_LICENSE("GPL");