arch/x86/kernel/ipi.c

   1 #include <linux/cpumask.h>
   2 #include <linux/interrupt.h>
   3 #include <linux/init.h>
   4
   5 #include <linux/mm.h>
   6 #include <linux/delay.h>
   7 #include <linux/spinlock.h>
   8 #include <linux/kernel_stat.h>
   9 #include <linux/mc146818rtc.h>
  10 #include <linux/cache.h>
  11 #include <linux/cpu.h>
  12 #include <linux/module.h>
  13
  14 #include <asm/smp.h>
  15 #include <asm/mtrr.h>
  16 #include <asm/tlbflush.h>
  17 #include <asm/mmu_context.h>
  18 #include <asm/apic.h>
  19 #include <asm/proto.h>
  20
  21 #ifdef CONFIG_X86_32
  22 #include <mach_apic.h>
  23 /*
  24  * the following functions deal with sending IPIs between CPUs.
  25  *
  26  * We use 'broadcast', CPU->CPU IPIs and self-IPIs too.
  27  */
  28
  29 static inline int __prepare_ICR(unsigned int shortcut, int vector)
  30 {
  31         unsigned int icr = shortcut | APIC_DEST_LOGICAL;
  32
  33         switch (vector) {
  34         default:
  35                 icr |= APIC_DM_FIXED | vector;
  36                 break;
  37         case NMI_VECTOR:
  38                 icr |= APIC_DM_NMI;
  39                 break;
  40         }
  41         return icr;
  42 }
  43
  44 static inline int __prepare_ICR2(unsigned int mask)
  45 {
  46         return SET_APIC_DEST_FIELD(mask);
  47 }
  48
  49 void __send_IPI_shortcut(unsigned int shortcut, int vector)
  50 {
  51         /*
  52          * Subtle. In the case of the 'never do double writes' workaround
  53          * we have to lock out interrupts to be safe.  As we don't care
  54          * of the value read we use an atomic rmw access to avoid costly
  55          * cli/sti.  Otherwise we use an even cheaper single atomic write
  56          * to the APIC.
  57          */
  58         unsigned int cfg;
  59
  60         /*
  61          * Wait for idle.
  62          */
  63         apic_wait_icr_idle();
  64
  65         /*
  66          * No need to touch the target chip field
  67          */
  68         cfg = __prepare_ICR(shortcut, vector);
  69
  70         /*
  71          * Send the IPI. The write to APIC_ICR fires this off.
  72          */
  73         apic_write_around(APIC_ICR, cfg);
  74 }
  75
  76 void send_IPI_self(int vector)
  77 {
  78         __send_IPI_shortcut(APIC_DEST_SELF, vector);
  79 }
  80
  81 /*
  82  * This is used to send an IPI with no shorthand notation (the destination is
  83  * specified in bits 56 to 63 of the ICR).
  84  */
  85 static inline void __send_IPI_dest_field(unsigned long mask, int vector)
  86 {
  87         unsigned long cfg;
  88
  89         /*
  90          * Wait for idle.
  91          */
  92         if (unlikely(vector == NMI_VECTOR))
  93                 safe_apic_wait_icr_idle();
  94         else
  95                 apic_wait_icr_idle();
  96
  97         /*
  98          * prepare target chip field
  99          */
 100         cfg = __prepare_ICR2(mask);
 101         apic_write_around(APIC_ICR2, cfg);
 102
 103         /*
 104          * program the ICR
 105          */
 106         cfg = __prepare_ICR(0, vector);
 107
 108         /*
 109          * Send the IPI. The write to APIC_ICR fires this off.
 110          */
 111         apic_write_around(APIC_ICR, cfg);
 112 }
 113
 114 /*
 115  * This is only used on smaller machines.
 116  */
 117 void send_IPI_mask_bitmask(cpumask_t cpumask, int vector)
 118 {
 119         unsigned long mask = cpus_addr(cpumask)[0];
 120         unsigned long flags;
 121
 122         local_irq_save(flags);
 123         WARN_ON(mask & ~cpus_addr(cpu_online_map)[0]);
 124         __send_IPI_dest_field(mask, vector);
 125         local_irq_restore(flags);
 126 }
 127
 128 void send_IPI_mask_sequence(cpumask_t mask, int vector)
 129 {
 130         unsigned long flags;
 131         unsigned int query_cpu;
 132
 133         /*
 134          * Hack. The clustered APIC addressing mode doesn't allow us to send
 135          * to an arbitrary mask, so I do a unicasts to each CPU instead. This
 136          * should be modified to do 1 message per cluster ID - mbligh
 137          */
 138
 139         local_irq_save(flags);
 140         for_each_possible_cpu(query_cpu) {
 141                 if (cpu_isset(query_cpu, mask)) {
 142                         __send_IPI_dest_field(cpu_to_logical_apicid(query_cpu),
 143                                               vector);
 144                 }
 145         }
 146         local_irq_restore(flags);
 147 }
 148
 149 /* must come after the send_IPI functions above for inlining */
 150 #include <mach_ipi.h>
 151 static int convert_apicid_to_cpu(int apic_id)
 152 {
 153         int i;
 154
 155         for_each_possible_cpu(i) {
 156                 if (per_cpu(x86_cpu_to_apicid, i) == apic_id)
 157                         return i;
 158         }
 159         return -1;
 160 }
 161
 162 int safe_smp_processor_id(void)
 163 {
 164         int apicid, cpuid;
 165
 166         if (!boot_cpu_has(X86_FEATURE_APIC))
 167                 return 0;
 168
 169         apicid = hard_smp_processor_id();
 170         if (apicid == BAD_APICID)
 171                 return 0;
 172
 173         cpuid = convert_apicid_to_cpu(apicid);
 174
 175         return cpuid >= 0 ? cpuid : 0;
 176 }
 177 #endif