2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * SGI UV APIC functions (note: not an Intel compatible APIC)
8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
11 #include <linux/kernel.h>
12 #include <linux/threads.h>
13 #include <linux/cpumask.h>
14 #include <linux/string.h>
15 #include <linux/kernel.h>
16 #include <linux/ctype.h>
17 #include <linux/init.h>
18 #include <linux/sched.h>
19 #include <linux/bootmem.h>
20 #include <linux/module.h>
23 #include <asm/genapic.h>
24 #include <asm/pgtable.h>
25 #include <asm/uv/uv_mmrs.h>
26 #include <asm/uv/uv_hub.h>
28 DEFINE_PER_CPU(struct uv_hub_info_s
, __uv_hub_info
);
29 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info
);
31 struct uv_blade_info
*uv_blade_info
;
32 EXPORT_SYMBOL_GPL(uv_blade_info
);
34 short *uv_node_to_blade
;
35 EXPORT_SYMBOL_GPL(uv_node_to_blade
);
37 short *uv_cpu_to_blade
;
38 EXPORT_SYMBOL_GPL(uv_cpu_to_blade
);
40 short uv_possible_blades
;
41 EXPORT_SYMBOL_GPL(uv_possible_blades
);
43 /* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */
45 static cpumask_t
uv_target_cpus(void)
47 return cpumask_of_cpu(0);
50 static cpumask_t
uv_vector_allocation_domain(int cpu
)
52 cpumask_t domain
= CPU_MASK_NONE
;
57 int uv_wakeup_secondary(int phys_apicid
, unsigned int start_rip
)
62 pnode
= uv_apicid_to_pnode(phys_apicid
);
63 val
= (1UL << UVH_IPI_INT_SEND_SHFT
) |
64 (phys_apicid
<< UVH_IPI_INT_APIC_ID_SHFT
) |
65 (((long)start_rip
<< UVH_IPI_INT_VECTOR_SHFT
) >> 12) |
67 uv_write_global_mmr64(pnode
, UVH_IPI_INT
, val
);
70 val
= (1UL << UVH_IPI_INT_SEND_SHFT
) |
71 (phys_apicid
<< UVH_IPI_INT_APIC_ID_SHFT
) |
72 (((long)start_rip
<< UVH_IPI_INT_VECTOR_SHFT
) >> 12) |
74 uv_write_global_mmr64(pnode
, UVH_IPI_INT
, val
);
78 static void uv_send_IPI_one(int cpu
, int vector
)
80 unsigned long val
, apicid
, lapicid
;
83 apicid
= per_cpu(x86_cpu_to_apicid
, cpu
); /* ZZZ - cache node-local ? */
84 lapicid
= apicid
& 0x3f; /* ZZZ macro needed */
85 pnode
= uv_apicid_to_pnode(apicid
);
87 (1UL << UVH_IPI_INT_SEND_SHFT
) | (lapicid
<<
88 UVH_IPI_INT_APIC_ID_SHFT
) |
89 (vector
<< UVH_IPI_INT_VECTOR_SHFT
);
90 uv_write_global_mmr64(pnode
, UVH_IPI_INT
, val
);
93 static void uv_send_IPI_mask(cpumask_t mask
, int vector
)
97 for (cpu
= 0; cpu
< NR_CPUS
; ++cpu
)
98 if (cpu_isset(cpu
, mask
))
99 uv_send_IPI_one(cpu
, vector
);
102 static void uv_send_IPI_allbutself(int vector
)
104 cpumask_t mask
= cpu_online_map
;
106 cpu_clear(smp_processor_id(), mask
);
108 if (!cpus_empty(mask
))
109 uv_send_IPI_mask(mask
, vector
);
112 static void uv_send_IPI_all(int vector
)
114 uv_send_IPI_mask(cpu_online_map
, vector
);
117 static int uv_apic_id_registered(void)
122 static unsigned int uv_cpu_mask_to_apicid(cpumask_t cpumask
)
127 * We're using fixed IRQ delivery, can only return one phys APIC ID.
128 * May as well be the first.
130 cpu
= first_cpu(cpumask
);
131 if ((unsigned)cpu
< NR_CPUS
)
132 return per_cpu(x86_cpu_to_apicid
, cpu
);
137 static unsigned int phys_pkg_id(int index_msb
)
139 return GET_APIC_ID(read_apic_id()) >> index_msb
;
142 #ifdef ZZZ /* Needs x2apic patch */
143 static void uv_send_IPI_self(int vector
)
145 apic_write(APIC_SELF_IPI
, vector
);
149 struct genapic apic_x2apic_uv_x
= {
150 .name
= "UV large system",
151 .int_delivery_mode
= dest_Fixed
,
152 .int_dest_mode
= (APIC_DEST_PHYSICAL
!= 0),
153 .target_cpus
= uv_target_cpus
,
154 .vector_allocation_domain
= uv_vector_allocation_domain
,/* Fixme ZZZ */
155 .apic_id_registered
= uv_apic_id_registered
,
156 .send_IPI_all
= uv_send_IPI_all
,
157 .send_IPI_allbutself
= uv_send_IPI_allbutself
,
158 .send_IPI_mask
= uv_send_IPI_mask
,
159 /* ZZZ.send_IPI_self = uv_send_IPI_self, */
160 .cpu_mask_to_apicid
= uv_cpu_mask_to_apicid
,
161 .phys_pkg_id
= phys_pkg_id
, /* Fixme ZZZ */
164 static __cpuinit
void set_x2apic_extra_bits(int pnode
)
166 __get_cpu_var(x2apic_extra_bits
) = (pnode
<< 6);
170 * Called on boot cpu.
172 static __init
int boot_pnode_to_blade(int pnode
)
176 for (blade
= 0; blade
< uv_num_possible_blades(); blade
++)
177 if (pnode
== uv_blade_info
[blade
].pnode
)
183 unsigned long redirect
;
187 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
189 static __initdata
struct redir_addr redir_addrs
[] = {
190 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR
, UVH_SI_ALIAS0_OVERLAY_CONFIG
},
191 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR
, UVH_SI_ALIAS1_OVERLAY_CONFIG
},
192 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR
, UVH_SI_ALIAS2_OVERLAY_CONFIG
},
195 static __init
void get_lowmem_redirect(unsigned long *base
, unsigned long *size
)
197 union uvh_si_alias0_overlay_config_u alias
;
198 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect
;
201 for (i
= 0; i
< ARRAY_SIZE(redir_addrs
); i
++) {
202 alias
.v
= uv_read_local_mmr(redir_addrs
[i
].alias
);
203 if (alias
.s
.base
== 0) {
204 *size
= (1UL << alias
.s
.m_alias
);
205 redirect
.v
= uv_read_local_mmr(redir_addrs
[i
].redirect
);
206 *base
= (unsigned long)redirect
.s
.dest_base
<< DEST_SHIFT
;
213 static __init
void map_low_mmrs(void)
215 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE
, UV_GLOBAL_MMR32_SIZE
);
216 init_extra_mapping_uc(UV_LOCAL_MMR_BASE
, UV_LOCAL_MMR_SIZE
);
219 enum map_type
{map_wb
, map_uc
};
221 static void map_high(char *id
, unsigned long base
, int shift
, enum map_type map_type
)
223 unsigned long bytes
, paddr
;
225 paddr
= base
<< shift
;
226 bytes
= (1UL << shift
);
227 printk(KERN_INFO
"UV: Map %s_HI 0x%lx - 0x%lx\n", id
, paddr
,
229 if (map_type
== map_uc
)
230 init_extra_mapping_uc(paddr
, bytes
);
232 init_extra_mapping_wb(paddr
, bytes
);
235 static __init
void map_gru_high(int max_pnode
)
237 union uvh_rh_gam_gru_overlay_config_mmr_u gru
;
238 int shift
= UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT
;
240 gru
.v
= uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR
);
242 map_high("GRU", gru
.s
.base
, shift
, map_wb
);
245 static __init
void map_config_high(int max_pnode
)
247 union uvh_rh_gam_cfg_overlay_config_mmr_u cfg
;
248 int shift
= UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT
;
250 cfg
.v
= uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR
);
252 map_high("CONFIG", cfg
.s
.base
, shift
, map_uc
);
255 static __init
void map_mmr_high(int max_pnode
)
257 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr
;
258 int shift
= UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT
;
260 mmr
.v
= uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR
);
262 map_high("MMR", mmr
.s
.base
, shift
, map_uc
);
265 static __init
void map_mmioh_high(int max_pnode
)
267 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh
;
268 int shift
= UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT
;
270 mmioh
.v
= uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR
);
272 map_high("MMIOH", mmioh
.s
.base
, shift
, map_uc
);
275 static __init
void uv_system_init(void)
277 union uvh_si_addr_map_config_u m_n_config
;
278 union uvh_node_id_u node_id
;
279 unsigned long gnode_upper
, lowmem_redir_base
, lowmem_redir_size
;
280 int bytes
, nid
, cpu
, lcpu
, pnode
, blade
, i
, j
, m_val
, n_val
;
282 unsigned long mmr_base
, present
;
286 m_n_config
.v
= uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG
);
287 m_val
= m_n_config
.s
.m_skt
;
288 n_val
= m_n_config
.s
.n_skt
;
290 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR
) &
292 printk(KERN_DEBUG
"UV: global MMR base 0x%lx\n", mmr_base
);
294 for(i
= 0; i
< UVH_NODE_PRESENT_TABLE_DEPTH
; i
++)
295 uv_possible_blades
+=
296 hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE
+ i
* 8));
297 printk(KERN_DEBUG
"UV: Found %d blades\n", uv_num_possible_blades());
299 bytes
= sizeof(struct uv_blade_info
) * uv_num_possible_blades();
300 uv_blade_info
= alloc_bootmem_pages(bytes
);
302 get_lowmem_redirect(&lowmem_redir_base
, &lowmem_redir_size
);
304 bytes
= sizeof(uv_node_to_blade
[0]) * num_possible_nodes();
305 uv_node_to_blade
= alloc_bootmem_pages(bytes
);
306 memset(uv_node_to_blade
, 255, bytes
);
308 bytes
= sizeof(uv_cpu_to_blade
[0]) * num_possible_cpus();
309 uv_cpu_to_blade
= alloc_bootmem_pages(bytes
);
310 memset(uv_cpu_to_blade
, 255, bytes
);
313 for (i
= 0; i
< UVH_NODE_PRESENT_TABLE_DEPTH
; i
++) {
314 present
= uv_read_local_mmr(UVH_NODE_PRESENT_TABLE
+ i
* 8);
315 for (j
= 0; j
< 64; j
++) {
316 if (!test_bit(j
, &present
))
318 uv_blade_info
[blade
].pnode
= (i
* 64 + j
);
319 uv_blade_info
[blade
].nr_possible_cpus
= 0;
320 uv_blade_info
[blade
].nr_online_cpus
= 0;
325 node_id
.v
= uv_read_local_mmr(UVH_NODE_ID
);
326 gnode_upper
= (((unsigned long)node_id
.s
.node_id
) &
327 ~((1 << n_val
) - 1)) << m_val
;
329 for_each_present_cpu(cpu
) {
330 nid
= cpu_to_node(cpu
);
331 pnode
= uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid
, cpu
));
332 blade
= boot_pnode_to_blade(pnode
);
333 lcpu
= uv_blade_info
[blade
].nr_possible_cpus
;
334 uv_blade_info
[blade
].nr_possible_cpus
++;
336 uv_cpu_hub_info(cpu
)->lowmem_remap_base
= lowmem_redir_base
;
337 uv_cpu_hub_info(cpu
)->lowmem_remap_top
=
338 lowmem_redir_base
+ lowmem_redir_size
;
339 uv_cpu_hub_info(cpu
)->m_val
= m_val
;
340 uv_cpu_hub_info(cpu
)->n_val
= m_val
;
341 uv_cpu_hub_info(cpu
)->numa_blade_id
= blade
;
342 uv_cpu_hub_info(cpu
)->blade_processor_id
= lcpu
;
343 uv_cpu_hub_info(cpu
)->pnode
= pnode
;
344 uv_cpu_hub_info(cpu
)->pnode_mask
= (1 << n_val
) - 1;
345 uv_cpu_hub_info(cpu
)->gpa_mask
= (1 << (m_val
+ n_val
)) - 1;
346 uv_cpu_hub_info(cpu
)->gnode_upper
= gnode_upper
;
347 uv_cpu_hub_info(cpu
)->global_mmr_base
= mmr_base
;
348 uv_cpu_hub_info(cpu
)->coherency_domain_number
= 0;/* ZZZ */
349 uv_node_to_blade
[nid
] = blade
;
350 uv_cpu_to_blade
[cpu
] = blade
;
351 max_pnode
= max(pnode
, max_pnode
);
353 printk(KERN_DEBUG
"UV: cpu %d, apicid 0x%x, pnode %d, nid %d, "
354 "lcpu %d, blade %d\n",
355 cpu
, per_cpu(x86_cpu_to_apicid
, cpu
), pnode
, nid
,
359 map_gru_high(max_pnode
);
360 map_mmr_high(max_pnode
);
361 map_config_high(max_pnode
);
362 map_mmioh_high(max_pnode
);
366 * Called on each cpu to initialize the per_cpu UV data area.
367 * ZZZ hotplug not supported yet
369 void __cpuinit
uv_cpu_init(void)
371 if (!uv_node_to_blade
)
374 uv_blade_info
[uv_numa_blade_id()].nr_online_cpus
++;
376 if (get_uv_system_type() == UV_NON_UNIQUE_APIC
)
377 set_x2apic_extra_bits(uv_hub_info
->pnode
);