include/asm-sparc64/pbm.h

   1 /* $Id: pbm.h,v 1.27 2001/08/12 13:18:23 davem Exp $
   2  * pbm.h: UltraSparc PCI controller software state.
   3  *
   4  * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
   5  */
   6
   7 #ifndef __SPARC64_PBM_H
   8 #define __SPARC64_PBM_H
   9
  10 #include <linux/types.h>
  11 #include <linux/pci.h>
  12 #include <linux/ioport.h>
  13 #include <linux/spinlock.h>
  14
  15 #include <asm/io.h>
  16 #include <asm/page.h>
  17 #include <asm/oplib.h>
  18 #include <asm/iommu.h>
  19
  20 /* The abstraction used here is that there are PCI controllers,
  21  * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
  22  * underneath.  Each PCI bus module uses an IOMMU (shared by both
  23  * PBMs of a controller, or per-PBM), and if a streaming buffer
  24  * is present, each PCI bus module has it's own. (ie. the IOMMU
  25  * might be shared between PBMs, the STC is never shared)
  26  * Furthermore, each PCI bus module controls it's own autonomous
  27  * PCI bus.
  28  */
  29
  30 #define PBM_LOGCLUSTERS 3
  31 #define PBM_NCLUSTERS (1 << PBM_LOGCLUSTERS)
  32
  33 struct pci_controller_info;
  34
  35 /* This contains the software state necessary to drive a PCI
  36  * controller's IOMMU.
  37  */
  38 struct pci_iommu {
  39         /* This protects the controller's IOMMU and all
  40          * streaming buffers underneath.
  41          */
  42         spinlock_t      lock;
  43
  44         /* IOMMU page table, a linear array of ioptes. */
  45         iopte_t         *page_table;            /* The page table itself. */
  46         int             page_table_sz_bits;     /* log2 of ow many pages does it map? */
  47
  48         /* Base PCI memory space address where IOMMU mappings
  49          * begin.
  50          */
  51         u32             page_table_map_base;
  52
  53         /* IOMMU Controller Registers */
  54         unsigned long   iommu_control;          /* IOMMU control register */
  55         unsigned long   iommu_tsbbase;          /* IOMMU page table base register */
  56         unsigned long   iommu_flush;            /* IOMMU page flush register */
  57         unsigned long   iommu_ctxflush;         /* IOMMU context flush register */
  58
  59         /* This is a register in the PCI controller, which if
  60          * read will have no side-effects but will guarantee
  61          * completion of all previous writes into IOMMU/STC.
  62          */
  63         unsigned long   write_complete_reg;
  64
  65         /* The lowest used consistent mapping entry.  Since
  66          * we allocate consistent maps out of cluster 0 this
  67          * is relative to the beginning of closter 0.
  68          */
  69         u32             lowest_consistent_map;
  70
  71         /* In order to deal with some buggy third-party PCI bridges that
  72          * do wrong prefetching, we never mark valid mappings as invalid.
  73          * Instead we point them at this dummy page.
  74          */
  75         unsigned long   dummy_page;
  76         unsigned long   dummy_page_pa;
  77
  78         /* If PBM_NCLUSTERS is ever decreased to 4 or lower,
  79          * or if largest supported page_table_sz * 8K goes above
  80          * 2GB, you must increase the size of the type of
  81          * these counters.  You have been duly warned. -DaveM
  82          */
  83         struct {
  84                 u16     next;
  85                 u16     flush;
  86         } alloc_info[PBM_NCLUSTERS];
  87
  88         /* CTX allocation. */
  89         unsigned long ctx_lowest_free;
  90         unsigned long ctx_bitmap[IOMMU_NUM_CTXS / (sizeof(unsigned long) * 8)];
  91
  92         /* Here a PCI controller driver describes the areas of
  93          * PCI memory space where DMA to/from physical memory
  94          * are addressed.  Drivers interrogate the PCI layer
  95          * if their device has addressing limitations.  They
  96          * do so via pci_dma_supported, and pass in a mask of
  97          * DMA address bits their device can actually drive.
  98          *
  99          * The test for being usable is:
 100          *      (device_mask & dma_addr_mask) == dma_addr_mask
 101          */
 102         u32 dma_addr_mask;
 103 };
 104
 105 extern void pci_iommu_table_init(struct pci_iommu *, int);
 106
 107 /* This describes a PCI bus module's streaming buffer. */
 108 struct pci_strbuf {
 109         int             strbuf_enabled;         /* Present and using it? */
 110
 111         /* Streaming Buffer Control Registers */
 112         unsigned long   strbuf_control;         /* STC control register */
 113         unsigned long   strbuf_pflush;          /* STC page flush register */
 114         unsigned long   strbuf_fsync;           /* STC flush synchronization reg */
 115         unsigned long   strbuf_ctxflush;        /* STC context flush register */
 116         unsigned long   strbuf_ctxmatch_base;   /* STC context flush match reg */
 117         unsigned long   strbuf_flushflag_pa;    /* Physical address of flush flag */
 118         volatile unsigned long *strbuf_flushflag; /* The flush flag itself */
 119
 120         /* And this is the actual flush flag area.
 121          * We allocate extra because the chips require
 122          * a 64-byte aligned area.
 123          */
 124         volatile unsigned long  __flushflag_buf[(64 + (64 - 1)) / sizeof(long)];
 125 };
 126
 127 #define PCI_STC_FLUSHFLAG_INIT(STC) \
 128         (*((STC)->strbuf_flushflag) = 0UL)
 129 #define PCI_STC_FLUSHFLAG_SET(STC) \
 130         (*((STC)->strbuf_flushflag) != 0UL)
 131
 132 /* There can be quite a few ranges and interrupt maps on a PCI
 133  * segment.  Thus...
 134  */
 135 #define PROM_PCIRNG_MAX         64
 136 #define PROM_PCIIMAP_MAX        64
 137
 138 struct pci_pbm_info {
 139         /* PCI controller we sit under. */
 140         struct pci_controller_info      *parent;
 141
 142         /* Physical address base of controller registers. */
 143         unsigned long                   controller_regs;
 144
 145         /* Physical address base of PBM registers. */
 146         unsigned long                   pbm_regs;
 147
 148         /* Physical address of DMA sync register, if any.  */
 149         unsigned long                   sync_reg;
 150
 151         /* Opaque 32-bit system bus Port ID. */
 152         u32                             portid;
 153
 154         /* Chipset version information. */
 155         int                             chip_type;
 156 #define PBM_CHIP_TYPE_SABRE             1
 157 #define PBM_CHIP_TYPE_PSYCHO            2
 158 #define PBM_CHIP_TYPE_SCHIZO            3
 159 #define PBM_CHIP_TYPE_SCHIZO_PLUS       4
 160 #define PBM_CHIP_TYPE_TOMATILLO         5
 161         int                             chip_version;
 162         int                             chip_revision;
 163
 164         /* Name used for top-level resources. */
 165         char                            name[64];
 166
 167         /* OBP specific information. */
 168         int                             prom_node;
 169         char                            prom_name[64];
 170         struct linux_prom_pci_ranges    pbm_ranges[PROM_PCIRNG_MAX];
 171         int                             num_pbm_ranges;
 172         struct linux_prom_pci_intmap    pbm_intmap[PROM_PCIIMAP_MAX];
 173         int                             num_pbm_intmap;
 174         struct linux_prom_pci_intmask   pbm_intmask;
 175         u64                             ino_bitmap;
 176
 177         /* PBM I/O and Memory space resources. */
 178         struct resource                 io_space;
 179         struct resource                 mem_space;
 180
 181         /* Base of PCI Config space, can be per-PBM or shared. */
 182         unsigned long                   config_space;
 183
 184         /* State of 66MHz capabilities on this PBM. */
 185         int                             is_66mhz_capable;
 186         int                             all_devs_66mhz;
 187
 188         /* This PBM's streaming buffer. */
 189         struct pci_strbuf               stc;
 190
 191         /* IOMMU state, potentially shared by both PBM segments. */
 192         struct pci_iommu                *iommu;
 193
 194         /* PCI slot mapping. */
 195         unsigned int                    pci_first_slot;
 196
 197         /* Now things for the actual PCI bus probes. */
 198         unsigned int                    pci_first_busno;
 199         unsigned int                    pci_last_busno;
 200         struct pci_bus                  *pci_bus;
 201 };
 202
 203 struct pci_controller_info {
 204         /* List of all PCI controllers. */
 205         struct pci_controller_info      *next;
 206
 207         /* Each controller gets a unique index, used mostly for
 208          * error logging purposes.
 209          */
 210         int                             index;
 211
 212         /* Do the PBMs both exist in the same PCI domain? */
 213         int                             pbms_same_domain;
 214
 215         /* The PCI bus modules controlled by us. */
 216         struct pci_pbm_info             pbm_A;
 217         struct pci_pbm_info             pbm_B;
 218
 219         /* Operations which are controller specific. */
 220         void (*scan_bus)(struct pci_controller_info *);
 221         unsigned int (*irq_build)(struct pci_pbm_info *, struct pci_dev *, unsigned int);
 222         void (*base_address_update)(struct pci_dev *, int);
 223         void (*resource_adjust)(struct pci_dev *, struct resource *, struct resource *);
 224
 225         /* Now things for the actual PCI bus probes. */
 226         struct pci_ops                  *pci_ops;
 227         unsigned int                    pci_first_busno;
 228         unsigned int                    pci_last_busno;
 229
 230         void                            *starfire_cookie;
 231 };
 232
 233 /* PCI devices which are not bridges have this placed in their pci_dev
 234  * sysdata member.  This makes OBP aware PCI device drivers easier to
 235  * code.
 236  */
 237 struct pcidev_cookie {
 238         struct pci_pbm_info             *pbm;
 239         char                            prom_name[64];
 240         int                             prom_node;
 241         struct linux_prom_pci_registers prom_regs[PROMREG_MAX];
 242         int num_prom_regs;
 243         struct linux_prom_pci_registers prom_assignments[PROMREG_MAX];
 244         int num_prom_assignments;
 245 };
 246
 247 /* Currently these are the same across all PCI controllers
 248  * we support.  Someday they may not be...
 249  */
 250 #define PCI_IRQ_IGN     0x000007c0      /* Interrupt Group Number */
 251 #define PCI_IRQ_INO     0x0000003f      /* Interrupt Number */
 252
 253 #endif /* !(__SPARC64_PBM_H) */