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ath5k: properly drop packets from ops->tx
[linux-2.6/mini2440.git] / drivers / net / wireless / ath5k / base.c
blob5d57d774e466b0308b47df24b5871005dcc4fc51
1 /*-
2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
7 *
8 * All rights reserved.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
23 *
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
27 *
28 * NO WARRANTY
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
40 *
41 */
42
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
46 #include <linux/if.h>
47 #include <linux/io.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
53
54 #include <net/ieee80211_radiotap.h>
55
56 #include <asm/unaligned.h>
57
58 #include "base.h"
59 #include "reg.h"
60 #include "debug.h"
61
62 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63 static int modparam_nohwcrypt;
64 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
66
67
68 /******************\
69 * Internal defines *
70 \******************/
71
72 /* Module info */
73 MODULE_AUTHOR("Jiri Slaby");
74 MODULE_AUTHOR("Nick Kossifidis");
75 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
76 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
77 MODULE_LICENSE("Dual BSD/GPL");
78 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
79
80
81 /* Known PCI ids */
82 static const struct pci_device_id ath5k_pci_id_table[] = {
83 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
84 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
85 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
86 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
87 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
88 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
89 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
90 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
91 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
95 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
98 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
99 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
100 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
101 { 0 }
102 };
103 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
104
105 /* Known SREVs */
106 static const struct ath5k_srev_name srev_names[] = {
107 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
108 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
109 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
110 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
111 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
112 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
113 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
114 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
115 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
116 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
117 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
118 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
119 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
120 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
121 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
122 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
123 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
124 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
125 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
126 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
127 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
128 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
129 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
130 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
131 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
132 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
133 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
134 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
135 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
136 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
137 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
138 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
139 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
140 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
141 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
142 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
143 };
144
145 static const struct ieee80211_rate ath5k_rates[] = {
146 { .bitrate = 10,
147 .hw_value = ATH5K_RATE_CODE_1M, },
148 { .bitrate = 20,
149 .hw_value = ATH5K_RATE_CODE_2M,
150 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
151 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
152 { .bitrate = 55,
153 .hw_value = ATH5K_RATE_CODE_5_5M,
154 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
156 { .bitrate = 110,
157 .hw_value = ATH5K_RATE_CODE_11M,
158 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
160 { .bitrate = 60,
161 .hw_value = ATH5K_RATE_CODE_6M,
162 .flags = 0 },
163 { .bitrate = 90,
164 .hw_value = ATH5K_RATE_CODE_9M,
165 .flags = 0 },
166 { .bitrate = 120,
167 .hw_value = ATH5K_RATE_CODE_12M,
168 .flags = 0 },
169 { .bitrate = 180,
170 .hw_value = ATH5K_RATE_CODE_18M,
171 .flags = 0 },
172 { .bitrate = 240,
173 .hw_value = ATH5K_RATE_CODE_24M,
174 .flags = 0 },
175 { .bitrate = 360,
176 .hw_value = ATH5K_RATE_CODE_36M,
177 .flags = 0 },
178 { .bitrate = 480,
179 .hw_value = ATH5K_RATE_CODE_48M,
180 .flags = 0 },
181 { .bitrate = 540,
182 .hw_value = ATH5K_RATE_CODE_54M,
183 .flags = 0 },
184 /* XR missing */
185 };
186
187 /*
188 * Prototypes - PCI stack related functions
189 */
190 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
191 const struct pci_device_id *id);
192 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
193 #ifdef CONFIG_PM
194 static int ath5k_pci_suspend(struct pci_dev *pdev,
195 pm_message_t state);
196 static int ath5k_pci_resume(struct pci_dev *pdev);
197 #else
198 #define ath5k_pci_suspend NULL
199 #define ath5k_pci_resume NULL
200 #endif /* CONFIG_PM */
201
202 static struct pci_driver ath5k_pci_driver = {
203 .name = KBUILD_MODNAME,
204 .id_table = ath5k_pci_id_table,
205 .probe = ath5k_pci_probe,
206 .remove = __devexit_p(ath5k_pci_remove),
207 .suspend = ath5k_pci_suspend,
208 .resume = ath5k_pci_resume,
209 };
210
211
212
213 /*
214 * Prototypes - MAC 802.11 stack related functions
215 */
216 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
217 static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
218 static int ath5k_reset_wake(struct ath5k_softc *sc);
219 static int ath5k_start(struct ieee80211_hw *hw);
220 static void ath5k_stop(struct ieee80211_hw *hw);
221 static int ath5k_add_interface(struct ieee80211_hw *hw,
222 struct ieee80211_if_init_conf *conf);
223 static void ath5k_remove_interface(struct ieee80211_hw *hw,
224 struct ieee80211_if_init_conf *conf);
225 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
226 static int ath5k_config_interface(struct ieee80211_hw *hw,
227 struct ieee80211_vif *vif,
228 struct ieee80211_if_conf *conf);
229 static void ath5k_configure_filter(struct ieee80211_hw *hw,
230 unsigned int changed_flags,
231 unsigned int *new_flags,
232 int mc_count, struct dev_mc_list *mclist);
233 static int ath5k_set_key(struct ieee80211_hw *hw,
234 enum set_key_cmd cmd,
235 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
236 struct ieee80211_key_conf *key);
237 static int ath5k_get_stats(struct ieee80211_hw *hw,
238 struct ieee80211_low_level_stats *stats);
239 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
240 struct ieee80211_tx_queue_stats *stats);
241 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
242 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
243 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
244 static int ath5k_beacon_update(struct ath5k_softc *sc,
245 struct sk_buff *skb);
246 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
247 struct ieee80211_vif *vif,
248 struct ieee80211_bss_conf *bss_conf,
249 u32 changes);
250
251 static const struct ieee80211_ops ath5k_hw_ops = {
252 .tx = ath5k_tx,
253 .start = ath5k_start,
254 .stop = ath5k_stop,
255 .add_interface = ath5k_add_interface,
256 .remove_interface = ath5k_remove_interface,
257 .config = ath5k_config,
258 .config_interface = ath5k_config_interface,
259 .configure_filter = ath5k_configure_filter,
260 .set_key = ath5k_set_key,
261 .get_stats = ath5k_get_stats,
262 .conf_tx = NULL,
263 .get_tx_stats = ath5k_get_tx_stats,
264 .get_tsf = ath5k_get_tsf,
265 .set_tsf = ath5k_set_tsf,
266 .reset_tsf = ath5k_reset_tsf,
267 .bss_info_changed = ath5k_bss_info_changed,
268 };
269
270 /*
271 * Prototypes - Internal functions
272 */
273 /* Attach detach */
274 static int ath5k_attach(struct pci_dev *pdev,
275 struct ieee80211_hw *hw);
276 static void ath5k_detach(struct pci_dev *pdev,
277 struct ieee80211_hw *hw);
278 /* Channel/mode setup */
279 static inline short ath5k_ieee2mhz(short chan);
280 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
281 struct ieee80211_channel *channels,
282 unsigned int mode,
283 unsigned int max);
284 static int ath5k_setup_bands(struct ieee80211_hw *hw);
285 static int ath5k_chan_set(struct ath5k_softc *sc,
286 struct ieee80211_channel *chan);
287 static void ath5k_setcurmode(struct ath5k_softc *sc,
288 unsigned int mode);
289 static void ath5k_mode_setup(struct ath5k_softc *sc);
290
291 /* Descriptor setup */
292 static int ath5k_desc_alloc(struct ath5k_softc *sc,
293 struct pci_dev *pdev);
294 static void ath5k_desc_free(struct ath5k_softc *sc,
295 struct pci_dev *pdev);
296 /* Buffers setup */
297 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
298 struct ath5k_buf *bf);
299 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
300 struct ath5k_buf *bf);
301 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
302 struct ath5k_buf *bf)
303 {
304 BUG_ON(!bf);
305 if (!bf->skb)
306 return;
307 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
308 PCI_DMA_TODEVICE);
309 dev_kfree_skb_any(bf->skb);
310 bf->skb = NULL;
311 }
312
313 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
314 struct ath5k_buf *bf)
315 {
316 BUG_ON(!bf);
317 if (!bf->skb)
318 return;
319 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
320 PCI_DMA_FROMDEVICE);
321 dev_kfree_skb_any(bf->skb);
322 bf->skb = NULL;
323 }
324
325
326 /* Queues setup */
327 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
328 int qtype, int subtype);
329 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
330 static int ath5k_beaconq_config(struct ath5k_softc *sc);
331 static void ath5k_txq_drainq(struct ath5k_softc *sc,
332 struct ath5k_txq *txq);
333 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
334 static void ath5k_txq_release(struct ath5k_softc *sc);
335 /* Rx handling */
336 static int ath5k_rx_start(struct ath5k_softc *sc);
337 static void ath5k_rx_stop(struct ath5k_softc *sc);
338 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
339 struct ath5k_desc *ds,
340 struct sk_buff *skb,
341 struct ath5k_rx_status *rs);
342 static void ath5k_tasklet_rx(unsigned long data);
343 /* Tx handling */
344 static void ath5k_tx_processq(struct ath5k_softc *sc,
345 struct ath5k_txq *txq);
346 static void ath5k_tasklet_tx(unsigned long data);
347 /* Beacon handling */
348 static int ath5k_beacon_setup(struct ath5k_softc *sc,
349 struct ath5k_buf *bf);
350 static void ath5k_beacon_send(struct ath5k_softc *sc);
351 static void ath5k_beacon_config(struct ath5k_softc *sc);
352 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
353 static void ath5k_tasklet_beacon(unsigned long data);
354
355 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
356 {
357 u64 tsf = ath5k_hw_get_tsf64(ah);
358
359 if ((tsf & 0x7fff) < rstamp)
360 tsf -= 0x8000;
361
362 return (tsf & ~0x7fff) | rstamp;
363 }
364
365 /* Interrupt handling */
366 static int ath5k_init(struct ath5k_softc *sc);
367 static int ath5k_stop_locked(struct ath5k_softc *sc);
368 static int ath5k_stop_hw(struct ath5k_softc *sc);
369 static irqreturn_t ath5k_intr(int irq, void *dev_id);
370 static void ath5k_tasklet_reset(unsigned long data);
371
372 static void ath5k_calibrate(unsigned long data);
373
374 /*
375 * Module init/exit functions
376 */
377 static int __init
378 init_ath5k_pci(void)
379 {
380 int ret;
381
382 ath5k_debug_init();
383
384 ret = pci_register_driver(&ath5k_pci_driver);
385 if (ret) {
386 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
387 return ret;
388 }
389
390 return 0;
391 }
392
393 static void __exit
394 exit_ath5k_pci(void)
395 {
396 pci_unregister_driver(&ath5k_pci_driver);
397
398 ath5k_debug_finish();
399 }
400
401 module_init(init_ath5k_pci);
402 module_exit(exit_ath5k_pci);
403
404
405 /********************\
406 * PCI Initialization *
407 \********************/
408
409 static const char *
410 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
411 {
412 const char *name = "xxxxx";
413 unsigned int i;
414
415 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
416 if (srev_names[i].sr_type != type)
417 continue;
418
419 if ((val & 0xf0) == srev_names[i].sr_val)
420 name = srev_names[i].sr_name;
421
422 if ((val & 0xff) == srev_names[i].sr_val) {
423 name = srev_names[i].sr_name;
424 break;
425 }
426 }
427
428 return name;
429 }
430
431 static int __devinit
432 ath5k_pci_probe(struct pci_dev *pdev,
433 const struct pci_device_id *id)
434 {
435 void __iomem *mem;
436 struct ath5k_softc *sc;
437 struct ieee80211_hw *hw;
438 int ret;
439 u8 csz;
440
441 ret = pci_enable_device(pdev);
442 if (ret) {
443 dev_err(&pdev->dev, "can't enable device\n");
444 goto err;
445 }
446
447 /* XXX 32-bit addressing only */
448 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
449 if (ret) {
450 dev_err(&pdev->dev, "32-bit DMA not available\n");
451 goto err_dis;
452 }
453
454 /*
455 * Cache line size is used to size and align various
456 * structures used to communicate with the hardware.
457 */
458 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
459 if (csz == 0) {
460 /*
461 * Linux 2.4.18 (at least) writes the cache line size
462 * register as a 16-bit wide register which is wrong.
463 * We must have this setup properly for rx buffer
464 * DMA to work so force a reasonable value here if it
465 * comes up zero.
466 */
467 csz = L1_CACHE_BYTES / sizeof(u32);
468 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
469 }
470 /*
471 * The default setting of latency timer yields poor results,
472 * set it to the value used by other systems. It may be worth
473 * tweaking this setting more.
474 */
475 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
476
477 /* Enable bus mastering */
478 pci_set_master(pdev);
479
480 /*
481 * Disable the RETRY_TIMEOUT register (0x41) to keep
482 * PCI Tx retries from interfering with C3 CPU state.
483 */
484 pci_write_config_byte(pdev, 0x41, 0);
485
486 ret = pci_request_region(pdev, 0, "ath5k");
487 if (ret) {
488 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
489 goto err_dis;
490 }
491
492 mem = pci_iomap(pdev, 0, 0);
493 if (!mem) {
494 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
495 ret = -EIO;
496 goto err_reg;
497 }
498
499 /*
500 * Allocate hw (mac80211 main struct)
501 * and hw->priv (driver private data)
502 */
503 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
504 if (hw == NULL) {
505 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
506 ret = -ENOMEM;
507 goto err_map;
508 }
509
510 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
511
512 /* Initialize driver private data */
513 SET_IEEE80211_DEV(hw, &pdev->dev);
514 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
515 IEEE80211_HW_SIGNAL_DBM |
516 IEEE80211_HW_NOISE_DBM;
517
518 hw->wiphy->interface_modes =
519 BIT(NL80211_IFTYPE_STATION) |
520 BIT(NL80211_IFTYPE_ADHOC) |
521 BIT(NL80211_IFTYPE_MESH_POINT);
522
523 hw->extra_tx_headroom = 2;
524 hw->channel_change_time = 5000;
525 sc = hw->priv;
526 sc->hw = hw;
527 sc->pdev = pdev;
528
529 ath5k_debug_init_device(sc);
530
531 /*
532 * Mark the device as detached to avoid processing
533 * interrupts until setup is complete.
534 */
535 __set_bit(ATH_STAT_INVALID, sc->status);
536
537 sc->iobase = mem; /* So we can unmap it on detach */
538 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
539 sc->opmode = NL80211_IFTYPE_STATION;
540 mutex_init(&sc->lock);
541 spin_lock_init(&sc->rxbuflock);
542 spin_lock_init(&sc->txbuflock);
543 spin_lock_init(&sc->block);
544
545 /* Set private data */
546 pci_set_drvdata(pdev, hw);
547
548 /* Setup interrupt handler */
549 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
550 if (ret) {
551 ATH5K_ERR(sc, "request_irq failed\n");
552 goto err_free;
553 }
554
555 /* Initialize device */
556 sc->ah = ath5k_hw_attach(sc, id->driver_data);
557 if (IS_ERR(sc->ah)) {
558 ret = PTR_ERR(sc->ah);
559 goto err_irq;
560 }
561
562 /* set up multi-rate retry capabilities */
563 if (sc->ah->ah_version == AR5K_AR5212) {
564 hw->max_rates = 4;
565 hw->max_rate_tries = 11;
566 }
567
568 /* Finish private driver data initialization */
569 ret = ath5k_attach(pdev, hw);
570 if (ret)
571 goto err_ah;
572
573 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
574 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
575 sc->ah->ah_mac_srev,
576 sc->ah->ah_phy_revision);
577
578 if (!sc->ah->ah_single_chip) {
579 /* Single chip radio (!RF5111) */
580 if (sc->ah->ah_radio_5ghz_revision &&
581 !sc->ah->ah_radio_2ghz_revision) {
582 /* No 5GHz support -> report 2GHz radio */
583 if (!test_bit(AR5K_MODE_11A,
584 sc->ah->ah_capabilities.cap_mode)) {
585 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
586 ath5k_chip_name(AR5K_VERSION_RAD,
587 sc->ah->ah_radio_5ghz_revision),
588 sc->ah->ah_radio_5ghz_revision);
589 /* No 2GHz support (5110 and some
590 * 5Ghz only cards) -> report 5Ghz radio */
591 } else if (!test_bit(AR5K_MODE_11B,
592 sc->ah->ah_capabilities.cap_mode)) {
593 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
594 ath5k_chip_name(AR5K_VERSION_RAD,
595 sc->ah->ah_radio_5ghz_revision),
596 sc->ah->ah_radio_5ghz_revision);
597 /* Multiband radio */
598 } else {
599 ATH5K_INFO(sc, "RF%s multiband radio found"
600 " (0x%x)\n",
601 ath5k_chip_name(AR5K_VERSION_RAD,
602 sc->ah->ah_radio_5ghz_revision),
603 sc->ah->ah_radio_5ghz_revision);
604 }
605 }
606 /* Multi chip radio (RF5111 - RF2111) ->
607 * report both 2GHz/5GHz radios */
608 else if (sc->ah->ah_radio_5ghz_revision &&
609 sc->ah->ah_radio_2ghz_revision){
610 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
611 ath5k_chip_name(AR5K_VERSION_RAD,
612 sc->ah->ah_radio_5ghz_revision),
613 sc->ah->ah_radio_5ghz_revision);
614 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
615 ath5k_chip_name(AR5K_VERSION_RAD,
616 sc->ah->ah_radio_2ghz_revision),
617 sc->ah->ah_radio_2ghz_revision);
618 }
619 }
620
621
622 /* ready to process interrupts */
623 __clear_bit(ATH_STAT_INVALID, sc->status);
624
625 return 0;
626 err_ah:
627 ath5k_hw_detach(sc->ah);
628 err_irq:
629 free_irq(pdev->irq, sc);
630 err_free:
631 ieee80211_free_hw(hw);
632 err_map:
633 pci_iounmap(pdev, mem);
634 err_reg:
635 pci_release_region(pdev, 0);
636 err_dis:
637 pci_disable_device(pdev);
638 err:
639 return ret;
640 }
641
642 static void __devexit
643 ath5k_pci_remove(struct pci_dev *pdev)
644 {
645 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
646 struct ath5k_softc *sc = hw->priv;
647
648 ath5k_debug_finish_device(sc);
649 ath5k_detach(pdev, hw);
650 ath5k_hw_detach(sc->ah);
651 free_irq(pdev->irq, sc);
652 pci_iounmap(pdev, sc->iobase);
653 pci_release_region(pdev, 0);
654 pci_disable_device(pdev);
655 ieee80211_free_hw(hw);
656 }
657
658 #ifdef CONFIG_PM
659 static int
660 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
661 {
662 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
663 struct ath5k_softc *sc = hw->priv;
664
665 ath5k_led_off(sc);
666
667 free_irq(pdev->irq, sc);
668 pci_save_state(pdev);
669 pci_disable_device(pdev);
670 pci_set_power_state(pdev, PCI_D3hot);
671
672 return 0;
673 }
674
675 static int
676 ath5k_pci_resume(struct pci_dev *pdev)
677 {
678 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
679 struct ath5k_softc *sc = hw->priv;
680 int err;
681
682 pci_restore_state(pdev);
683
684 err = pci_enable_device(pdev);
685 if (err)
686 return err;
687
688 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
689 if (err) {
690 ATH5K_ERR(sc, "request_irq failed\n");
691 goto err_no_irq;
692 }
693
694 ath5k_led_enable(sc);
695 return 0;
696
697 err_no_irq:
698 pci_disable_device(pdev);
699 return err;
700 }
701 #endif /* CONFIG_PM */
702
703
704 /***********************\
705 * Driver Initialization *
706 \***********************/
707
708 static int
709 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
710 {
711 struct ath5k_softc *sc = hw->priv;
712 struct ath5k_hw *ah = sc->ah;
713 u8 mac[ETH_ALEN] = {};
714 int ret;
715
716 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
717
718 /*
719 * Check if the MAC has multi-rate retry support.
720 * We do this by trying to setup a fake extended
721 * descriptor. MAC's that don't have support will
722 * return false w/o doing anything. MAC's that do
723 * support it will return true w/o doing anything.
724 */
725 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
726 if (ret < 0)
727 goto err;
728 if (ret > 0)
729 __set_bit(ATH_STAT_MRRETRY, sc->status);
730
731 /*
732 * Collect the channel list. The 802.11 layer
733 * is resposible for filtering this list based
734 * on settings like the phy mode and regulatory
735 * domain restrictions.
736 */
737 ret = ath5k_setup_bands(hw);
738 if (ret) {
739 ATH5K_ERR(sc, "can't get channels\n");
740 goto err;
741 }
742
743 /* NB: setup here so ath5k_rate_update is happy */
744 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
745 ath5k_setcurmode(sc, AR5K_MODE_11A);
746 else
747 ath5k_setcurmode(sc, AR5K_MODE_11B);
748
749 /*
750 * Allocate tx+rx descriptors and populate the lists.
751 */
752 ret = ath5k_desc_alloc(sc, pdev);
753 if (ret) {
754 ATH5K_ERR(sc, "can't allocate descriptors\n");
755 goto err;
756 }
757
758 /*
759 * Allocate hardware transmit queues: one queue for
760 * beacon frames and one data queue for each QoS
761 * priority. Note that hw functions handle reseting
762 * these queues at the needed time.
763 */
764 ret = ath5k_beaconq_setup(ah);
765 if (ret < 0) {
766 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
767 goto err_desc;
768 }
769 sc->bhalq = ret;
770
771 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
772 if (IS_ERR(sc->txq)) {
773 ATH5K_ERR(sc, "can't setup xmit queue\n");
774 ret = PTR_ERR(sc->txq);
775 goto err_bhal;
776 }
777
778 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
779 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
780 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
781 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
782 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
783
784 ret = ath5k_eeprom_read_mac(ah, mac);
785 if (ret) {
786 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
787 sc->pdev->device);
788 goto err_queues;
789 }
790
791 SET_IEEE80211_PERM_ADDR(hw, mac);
792 /* All MAC address bits matter for ACKs */
793 memset(sc->bssidmask, 0xff, ETH_ALEN);
794 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
795
796 ret = ieee80211_register_hw(hw);
797 if (ret) {
798 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
799 goto err_queues;
800 }
801
802 ath5k_init_leds(sc);
803
804 return 0;
805 err_queues:
806 ath5k_txq_release(sc);
807 err_bhal:
808 ath5k_hw_release_tx_queue(ah, sc->bhalq);
809 err_desc:
810 ath5k_desc_free(sc, pdev);
811 err:
812 return ret;
813 }
814
815 static void
816 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
817 {
818 struct ath5k_softc *sc = hw->priv;
819
820 /*
821 * NB: the order of these is important:
822 * o call the 802.11 layer before detaching ath5k_hw to
823 * insure callbacks into the driver to delete global
824 * key cache entries can be handled
825 * o reclaim the tx queue data structures after calling
826 * the 802.11 layer as we'll get called back to reclaim
827 * node state and potentially want to use them
828 * o to cleanup the tx queues the hal is called, so detach
829 * it last
830 * XXX: ??? detach ath5k_hw ???
831 * Other than that, it's straightforward...
832 */
833 ieee80211_unregister_hw(hw);
834 ath5k_desc_free(sc, pdev);
835 ath5k_txq_release(sc);
836 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
837 ath5k_unregister_leds(sc);
838
839 /*
840 * NB: can't reclaim these until after ieee80211_ifdetach
841 * returns because we'll get called back to reclaim node
842 * state and potentially want to use them.
843 */
844 }
845
846
847
848
849 /********************\
850 * Channel/mode setup *
851 \********************/
852
853 /*
854 * Convert IEEE channel number to MHz frequency.
855 */
856 static inline short
857 ath5k_ieee2mhz(short chan)
858 {
859 if (chan <= 14 || chan >= 27)
860 return ieee80211chan2mhz(chan);
861 else
862 return 2212 + chan * 20;
863 }
864
865 static unsigned int
866 ath5k_copy_channels(struct ath5k_hw *ah,
867 struct ieee80211_channel *channels,
868 unsigned int mode,
869 unsigned int max)
870 {
871 unsigned int i, count, size, chfreq, freq, ch;
872
873 if (!test_bit(mode, ah->ah_modes))
874 return 0;
875
876 switch (mode) {
877 case AR5K_MODE_11A:
878 case AR5K_MODE_11A_TURBO:
879 /* 1..220, but 2GHz frequencies are filtered by check_channel */
880 size = 220 ;
881 chfreq = CHANNEL_5GHZ;
882 break;
883 case AR5K_MODE_11B:
884 case AR5K_MODE_11G:
885 case AR5K_MODE_11G_TURBO:
886 size = 26;
887 chfreq = CHANNEL_2GHZ;
888 break;
889 default:
890 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
891 return 0;
892 }
893
894 for (i = 0, count = 0; i < size && max > 0; i++) {
895 ch = i + 1 ;
896 freq = ath5k_ieee2mhz(ch);
897
898 /* Check if channel is supported by the chipset */
899 if (!ath5k_channel_ok(ah, freq, chfreq))
900 continue;
901
902 /* Write channel info and increment counter */
903 channels[count].center_freq = freq;
904 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
905 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
906 switch (mode) {
907 case AR5K_MODE_11A:
908 case AR5K_MODE_11G:
909 channels[count].hw_value = chfreq | CHANNEL_OFDM;
910 break;
911 case AR5K_MODE_11A_TURBO:
912 case AR5K_MODE_11G_TURBO:
913 channels[count].hw_value = chfreq |
914 CHANNEL_OFDM | CHANNEL_TURBO;
915 break;
916 case AR5K_MODE_11B:
917 channels[count].hw_value = CHANNEL_B;
918 }
919
920 count++;
921 max--;
922 }
923
924 return count;
925 }
926
927 static void
928 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
929 {
930 u8 i;
931
932 for (i = 0; i < AR5K_MAX_RATES; i++)
933 sc->rate_idx[b->band][i] = -1;
934
935 for (i = 0; i < b->n_bitrates; i++) {
936 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
937 if (b->bitrates[i].hw_value_short)
938 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
939 }
940 }
941
942 static int
943 ath5k_setup_bands(struct ieee80211_hw *hw)
944 {
945 struct ath5k_softc *sc = hw->priv;
946 struct ath5k_hw *ah = sc->ah;
947 struct ieee80211_supported_band *sband;
948 int max_c, count_c = 0;
949 int i;
950
951 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
952 max_c = ARRAY_SIZE(sc->channels);
953
954 /* 2GHz band */
955 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
956 sband->band = IEEE80211_BAND_2GHZ;
957 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
958
959 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
960 /* G mode */
961 memcpy(sband->bitrates, &ath5k_rates[0],
962 sizeof(struct ieee80211_rate) * 12);
963 sband->n_bitrates = 12;
964
965 sband->channels = sc->channels;
966 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
967 AR5K_MODE_11G, max_c);
968
969 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
970 count_c = sband->n_channels;
971 max_c -= count_c;
972 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
973 /* B mode */
974 memcpy(sband->bitrates, &ath5k_rates[0],
975 sizeof(struct ieee80211_rate) * 4);
976 sband->n_bitrates = 4;
977
978 /* 5211 only supports B rates and uses 4bit rate codes
979 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
980 * fix them up here:
981 */
982 if (ah->ah_version == AR5K_AR5211) {
983 for (i = 0; i < 4; i++) {
984 sband->bitrates[i].hw_value =
985 sband->bitrates[i].hw_value & 0xF;
986 sband->bitrates[i].hw_value_short =
987 sband->bitrates[i].hw_value_short & 0xF;
988 }
989 }
990
991 sband->channels = sc->channels;
992 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
993 AR5K_MODE_11B, max_c);
994
995 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
996 count_c = sband->n_channels;
997 max_c -= count_c;
998 }
999 ath5k_setup_rate_idx(sc, sband);
1000
1001 /* 5GHz band, A mode */
1002 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1003 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1004 sband->band = IEEE80211_BAND_5GHZ;
1005 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1006
1007 memcpy(sband->bitrates, &ath5k_rates[4],
1008 sizeof(struct ieee80211_rate) * 8);
1009 sband->n_bitrates = 8;
1010
1011 sband->channels = &sc->channels[count_c];
1012 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1013 AR5K_MODE_11A, max_c);
1014
1015 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1016 }
1017 ath5k_setup_rate_idx(sc, sband);
1018
1019 ath5k_debug_dump_bands(sc);
1020
1021 return 0;
1022 }
1023
1024 /*
1025 * Set/change channels. If the channel is really being changed,
1026 * it's done by reseting the chip. To accomplish this we must
1027 * first cleanup any pending DMA, then restart stuff after a la
1028 * ath5k_init.
1029 *
1030 * Called with sc->lock.
1031 */
1032 static int
1033 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1034 {
1035 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1036 sc->curchan->center_freq, chan->center_freq);
1037
1038 if (chan->center_freq != sc->curchan->center_freq ||
1039 chan->hw_value != sc->curchan->hw_value) {
1040
1041 sc->curchan = chan;
1042 sc->curband = &sc->sbands[chan->band];
1043
1044 /*
1045 * To switch channels clear any pending DMA operations;
1046 * wait long enough for the RX fifo to drain, reset the
1047 * hardware at the new frequency, and then re-enable
1048 * the relevant bits of the h/w.
1049 */
1050 return ath5k_reset(sc, true, true);
1051 }
1052
1053 return 0;
1054 }
1055
1056 static void
1057 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1058 {
1059 sc->curmode = mode;
1060
1061 if (mode == AR5K_MODE_11A) {
1062 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1063 } else {
1064 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1065 }
1066 }
1067
1068 static void
1069 ath5k_mode_setup(struct ath5k_softc *sc)
1070 {
1071 struct ath5k_hw *ah = sc->ah;
1072 u32 rfilt;
1073
1074 /* configure rx filter */
1075 rfilt = sc->filter_flags;
1076 ath5k_hw_set_rx_filter(ah, rfilt);
1077
1078 if (ath5k_hw_hasbssidmask(ah))
1079 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1080
1081 /* configure operational mode */
1082 ath5k_hw_set_opmode(ah);
1083
1084 ath5k_hw_set_mcast_filter(ah, 0, 0);
1085 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1086 }
1087
1088 static inline int
1089 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1090 {
1091 int rix;
1092
1093 /* return base rate on errors */
1094 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1095 "hw_rix out of bounds: %x\n", hw_rix))
1096 return 0;
1097
1098 rix = sc->rate_idx[sc->curband->band][hw_rix];
1099 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1100 rix = 0;
1101
1102 return rix;
1103 }
1104
1105 /***************\
1106 * Buffers setup *
1107 \***************/
1108
1109 static
1110 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1111 {
1112 struct sk_buff *skb;
1113 unsigned int off;
1114
1115 /*
1116 * Allocate buffer with headroom_needed space for the
1117 * fake physical layer header at the start.
1118 */
1119 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1120
1121 if (!skb) {
1122 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1123 sc->rxbufsize + sc->cachelsz - 1);
1124 return NULL;
1125 }
1126 /*
1127 * Cache-line-align. This is important (for the
1128 * 5210 at least) as not doing so causes bogus data
1129 * in rx'd frames.
1130 */
1131 off = ((unsigned long)skb->data) % sc->cachelsz;
1132 if (off != 0)
1133 skb_reserve(skb, sc->cachelsz - off);
1134
1135 *skb_addr = pci_map_single(sc->pdev,
1136 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1137 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1138 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1139 dev_kfree_skb(skb);
1140 return NULL;
1141 }
1142 return skb;
1143 }
1144
1145 static int
1146 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1147 {
1148 struct ath5k_hw *ah = sc->ah;
1149 struct sk_buff *skb = bf->skb;
1150 struct ath5k_desc *ds;
1151
1152 if (!skb) {
1153 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1154 if (!skb)
1155 return -ENOMEM;
1156 bf->skb = skb;
1157 }
1158
1159 /*
1160 * Setup descriptors. For receive we always terminate
1161 * the descriptor list with a self-linked entry so we'll
1162 * not get overrun under high load (as can happen with a
1163 * 5212 when ANI processing enables PHY error frames).
1164 *
1165 * To insure the last descriptor is self-linked we create
1166 * each descriptor as self-linked and add it to the end. As
1167 * each additional descriptor is added the previous self-linked
1168 * entry is ``fixed'' naturally. This should be safe even
1169 * if DMA is happening. When processing RX interrupts we
1170 * never remove/process the last, self-linked, entry on the
1171 * descriptor list. This insures the hardware always has
1172 * someplace to write a new frame.
1173 */
1174 ds = bf->desc;
1175 ds->ds_link = bf->daddr; /* link to self */
1176 ds->ds_data = bf->skbaddr;
1177 ah->ah_setup_rx_desc(ah, ds,
1178 skb_tailroom(skb), /* buffer size */
1179 0);
1180
1181 if (sc->rxlink != NULL)
1182 *sc->rxlink = bf->daddr;
1183 sc->rxlink = &ds->ds_link;
1184 return 0;
1185 }
1186
1187 static int
1188 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1189 {
1190 struct ath5k_hw *ah = sc->ah;
1191 struct ath5k_txq *txq = sc->txq;
1192 struct ath5k_desc *ds = bf->desc;
1193 struct sk_buff *skb = bf->skb;
1194 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1195 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1196 struct ieee80211_rate *rate;
1197 unsigned int mrr_rate[3], mrr_tries[3];
1198 int i, ret;
1199 u16 hw_rate;
1200 u16 cts_rate = 0;
1201 u16 duration = 0;
1202 u8 rc_flags;
1203
1204 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1205
1206 /* XXX endianness */
1207 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1208 PCI_DMA_TODEVICE);
1209
1210 rate = ieee80211_get_tx_rate(sc->hw, info);
1211
1212 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1213 flags |= AR5K_TXDESC_NOACK;
1214
1215 rc_flags = info->control.rates[0].flags;
1216 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1217 rate->hw_value_short : rate->hw_value;
1218
1219 pktlen = skb->len;
1220
1221 /* FIXME: If we are in g mode and rate is a CCK rate
1222 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1223 * from tx power (value is in dB units already) */
1224 if (info->control.hw_key) {
1225 keyidx = info->control.hw_key->hw_key_idx;
1226 pktlen += info->control.hw_key->icv_len;
1227 }
1228 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1229 flags |= AR5K_TXDESC_RTSENA;
1230 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1231 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1232 sc->vif, pktlen, info));
1233 }
1234 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1235 flags |= AR5K_TXDESC_CTSENA;
1236 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1237 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1238 sc->vif, pktlen, info));
1239 }
1240 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1241 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1242 (sc->power_level * 2),
1243 hw_rate,
1244 info->control.rates[0].count, keyidx, 0, flags,
1245 cts_rate, duration);
1246 if (ret)
1247 goto err_unmap;
1248
1249 memset(mrr_rate, 0, sizeof(mrr_rate));
1250 memset(mrr_tries, 0, sizeof(mrr_tries));
1251 for (i = 0; i < 3; i++) {
1252 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1253 if (!rate)
1254 break;
1255
1256 mrr_rate[i] = rate->hw_value;
1257 mrr_tries[i] = info->control.rates[i + 1].count;
1258 }
1259
1260 ah->ah_setup_mrr_tx_desc(ah, ds,
1261 mrr_rate[0], mrr_tries[0],
1262 mrr_rate[1], mrr_tries[1],
1263 mrr_rate[2], mrr_tries[2]);
1264
1265 ds->ds_link = 0;
1266 ds->ds_data = bf->skbaddr;
1267
1268 spin_lock_bh(&txq->lock);
1269 list_add_tail(&bf->list, &txq->q);
1270 sc->tx_stats[txq->qnum].len++;
1271 if (txq->link == NULL) /* is this first packet? */
1272 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1273 else /* no, so only link it */
1274 *txq->link = bf->daddr;
1275
1276 txq->link = &ds->ds_link;
1277 ath5k_hw_start_tx_dma(ah, txq->qnum);
1278 mmiowb();
1279 spin_unlock_bh(&txq->lock);
1280
1281 return 0;
1282 err_unmap:
1283 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1284 return ret;
1285 }
1286
1287 /*******************\
1288 * Descriptors setup *
1289 \*******************/
1290
1291 static int
1292 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1293 {
1294 struct ath5k_desc *ds;
1295 struct ath5k_buf *bf;
1296 dma_addr_t da;
1297 unsigned int i;
1298 int ret;
1299
1300 /* allocate descriptors */
1301 sc->desc_len = sizeof(struct ath5k_desc) *
1302 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1303 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1304 if (sc->desc == NULL) {
1305 ATH5K_ERR(sc, "can't allocate descriptors\n");
1306 ret = -ENOMEM;
1307 goto err;
1308 }
1309 ds = sc->desc;
1310 da = sc->desc_daddr;
1311 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1312 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1313
1314 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1315 sizeof(struct ath5k_buf), GFP_KERNEL);
1316 if (bf == NULL) {
1317 ATH5K_ERR(sc, "can't allocate bufptr\n");
1318 ret = -ENOMEM;
1319 goto err_free;
1320 }
1321 sc->bufptr = bf;
1322
1323 INIT_LIST_HEAD(&sc->rxbuf);
1324 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1325 bf->desc = ds;
1326 bf->daddr = da;
1327 list_add_tail(&bf->list, &sc->rxbuf);
1328 }
1329
1330 INIT_LIST_HEAD(&sc->txbuf);
1331 sc->txbuf_len = ATH_TXBUF;
1332 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1333 da += sizeof(*ds)) {
1334 bf->desc = ds;
1335 bf->daddr = da;
1336 list_add_tail(&bf->list, &sc->txbuf);
1337 }
1338
1339 /* beacon buffer */
1340 bf->desc = ds;
1341 bf->daddr = da;
1342 sc->bbuf = bf;
1343
1344 return 0;
1345 err_free:
1346 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1347 err:
1348 sc->desc = NULL;
1349 return ret;
1350 }
1351
1352 static void
1353 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1354 {
1355 struct ath5k_buf *bf;
1356
1357 ath5k_txbuf_free(sc, sc->bbuf);
1358 list_for_each_entry(bf, &sc->txbuf, list)
1359 ath5k_txbuf_free(sc, bf);
1360 list_for_each_entry(bf, &sc->rxbuf, list)
1361 ath5k_rxbuf_free(sc, bf);
1362
1363 /* Free memory associated with all descriptors */
1364 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1365
1366 kfree(sc->bufptr);
1367 sc->bufptr = NULL;
1368 }
1369
1370
1371
1372
1373
1374 /**************\
1375 * Queues setup *
1376 \**************/
1377
1378 static struct ath5k_txq *
1379 ath5k_txq_setup(struct ath5k_softc *sc,
1380 int qtype, int subtype)
1381 {
1382 struct ath5k_hw *ah = sc->ah;
1383 struct ath5k_txq *txq;
1384 struct ath5k_txq_info qi = {
1385 .tqi_subtype = subtype,
1386 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1387 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1388 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1389 };
1390 int qnum;
1391
1392 /*
1393 * Enable interrupts only for EOL and DESC conditions.
1394 * We mark tx descriptors to receive a DESC interrupt
1395 * when a tx queue gets deep; otherwise waiting for the
1396 * EOL to reap descriptors. Note that this is done to
1397 * reduce interrupt load and this only defers reaping
1398 * descriptors, never transmitting frames. Aside from
1399 * reducing interrupts this also permits more concurrency.
1400 * The only potential downside is if the tx queue backs
1401 * up in which case the top half of the kernel may backup
1402 * due to a lack of tx descriptors.
1403 */
1404 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1405 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1406 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1407 if (qnum < 0) {
1408 /*
1409 * NB: don't print a message, this happens
1410 * normally on parts with too few tx queues
1411 */
1412 return ERR_PTR(qnum);
1413 }
1414 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1415 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1416 qnum, ARRAY_SIZE(sc->txqs));
1417 ath5k_hw_release_tx_queue(ah, qnum);
1418 return ERR_PTR(-EINVAL);
1419 }
1420 txq = &sc->txqs[qnum];
1421 if (!txq->setup) {
1422 txq->qnum = qnum;
1423 txq->link = NULL;
1424 INIT_LIST_HEAD(&txq->q);
1425 spin_lock_init(&txq->lock);
1426 txq->setup = true;
1427 }
1428 return &sc->txqs[qnum];
1429 }
1430
1431 static int
1432 ath5k_beaconq_setup(struct ath5k_hw *ah)
1433 {
1434 struct ath5k_txq_info qi = {
1435 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1436 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1437 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1438 /* NB: for dynamic turbo, don't enable any other interrupts */
1439 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1440 };
1441
1442 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1443 }
1444
1445 static int
1446 ath5k_beaconq_config(struct ath5k_softc *sc)
1447 {
1448 struct ath5k_hw *ah = sc->ah;
1449 struct ath5k_txq_info qi;
1450 int ret;
1451
1452 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1453 if (ret)
1454 return ret;
1455 if (sc->opmode == NL80211_IFTYPE_AP ||
1456 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1457 /*
1458 * Always burst out beacon and CAB traffic
1459 * (aifs = cwmin = cwmax = 0)
1460 */
1461 qi.tqi_aifs = 0;
1462 qi.tqi_cw_min = 0;
1463 qi.tqi_cw_max = 0;
1464 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1465 /*
1466 * Adhoc mode; backoff between 0 and (2 * cw_min).
1467 */
1468 qi.tqi_aifs = 0;
1469 qi.tqi_cw_min = 0;
1470 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1471 }
1472
1473 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1474 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1475 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1476
1477 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1478 if (ret) {
1479 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1480 "hardware queue!\n", __func__);
1481 return ret;
1482 }
1483
1484 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1485 }
1486
1487 static void
1488 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1489 {
1490 struct ath5k_buf *bf, *bf0;
1491
1492 /*
1493 * NB: this assumes output has been stopped and
1494 * we do not need to block ath5k_tx_tasklet
1495 */
1496 spin_lock_bh(&txq->lock);
1497 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1498 ath5k_debug_printtxbuf(sc, bf);
1499
1500 ath5k_txbuf_free(sc, bf);
1501
1502 spin_lock_bh(&sc->txbuflock);
1503 sc->tx_stats[txq->qnum].len--;
1504 list_move_tail(&bf->list, &sc->txbuf);
1505 sc->txbuf_len++;
1506 spin_unlock_bh(&sc->txbuflock);
1507 }
1508 txq->link = NULL;
1509 spin_unlock_bh(&txq->lock);
1510 }
1511
1512 /*
1513 * Drain the transmit queues and reclaim resources.
1514 */
1515 static void
1516 ath5k_txq_cleanup(struct ath5k_softc *sc)
1517 {
1518 struct ath5k_hw *ah = sc->ah;
1519 unsigned int i;
1520
1521 /* XXX return value */
1522 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1523 /* don't touch the hardware if marked invalid */
1524 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1525 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1526 ath5k_hw_get_txdp(ah, sc->bhalq));
1527 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1528 if (sc->txqs[i].setup) {
1529 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1530 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1531 "link %p\n",
1532 sc->txqs[i].qnum,
1533 ath5k_hw_get_txdp(ah,
1534 sc->txqs[i].qnum),
1535 sc->txqs[i].link);
1536 }
1537 }
1538 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1539
1540 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1541 if (sc->txqs[i].setup)
1542 ath5k_txq_drainq(sc, &sc->txqs[i]);
1543 }
1544
1545 static void
1546 ath5k_txq_release(struct ath5k_softc *sc)
1547 {
1548 struct ath5k_txq *txq = sc->txqs;
1549 unsigned int i;
1550
1551 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1552 if (txq->setup) {
1553 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1554 txq->setup = false;
1555 }
1556 }
1557
1558
1559
1560
1561 /*************\
1562 * RX Handling *
1563 \*************/
1564
1565 /*
1566 * Enable the receive h/w following a reset.
1567 */
1568 static int
1569 ath5k_rx_start(struct ath5k_softc *sc)
1570 {
1571 struct ath5k_hw *ah = sc->ah;
1572 struct ath5k_buf *bf;
1573 int ret;
1574
1575 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1576
1577 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1578 sc->cachelsz, sc->rxbufsize);
1579
1580 sc->rxlink = NULL;
1581
1582 spin_lock_bh(&sc->rxbuflock);
1583 list_for_each_entry(bf, &sc->rxbuf, list) {
1584 ret = ath5k_rxbuf_setup(sc, bf);
1585 if (ret != 0) {
1586 spin_unlock_bh(&sc->rxbuflock);
1587 goto err;
1588 }
1589 }
1590 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1591 spin_unlock_bh(&sc->rxbuflock);
1592
1593 ath5k_hw_set_rxdp(ah, bf->daddr);
1594 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1595 ath5k_mode_setup(sc); /* set filters, etc. */
1596 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1597
1598 return 0;
1599 err:
1600 return ret;
1601 }
1602
1603 /*
1604 * Disable the receive h/w in preparation for a reset.
1605 */
1606 static void
1607 ath5k_rx_stop(struct ath5k_softc *sc)
1608 {
1609 struct ath5k_hw *ah = sc->ah;
1610
1611 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1612 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1613 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1614
1615 ath5k_debug_printrxbuffs(sc, ah);
1616
1617 sc->rxlink = NULL; /* just in case */
1618 }
1619
1620 static unsigned int
1621 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1622 struct sk_buff *skb, struct ath5k_rx_status *rs)
1623 {
1624 struct ieee80211_hdr *hdr = (void *)skb->data;
1625 unsigned int keyix, hlen;
1626
1627 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1628 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1629 return RX_FLAG_DECRYPTED;
1630
1631 /* Apparently when a default key is used to decrypt the packet
1632 the hw does not set the index used to decrypt. In such cases
1633 get the index from the packet. */
1634 hlen = ieee80211_hdrlen(hdr->frame_control);
1635 if (ieee80211_has_protected(hdr->frame_control) &&
1636 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1637 skb->len >= hlen + 4) {
1638 keyix = skb->data[hlen + 3] >> 6;
1639
1640 if (test_bit(keyix, sc->keymap))
1641 return RX_FLAG_DECRYPTED;
1642 }
1643
1644 return 0;
1645 }
1646
1647
1648 static void
1649 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1650 struct ieee80211_rx_status *rxs)
1651 {
1652 u64 tsf, bc_tstamp;
1653 u32 hw_tu;
1654 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1655
1656 if (ieee80211_is_beacon(mgmt->frame_control) &&
1657 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1658 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1659 /*
1660 * Received an IBSS beacon with the same BSSID. Hardware *must*
1661 * have updated the local TSF. We have to work around various
1662 * hardware bugs, though...
1663 */
1664 tsf = ath5k_hw_get_tsf64(sc->ah);
1665 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1666 hw_tu = TSF_TO_TU(tsf);
1667
1668 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1669 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1670 (unsigned long long)bc_tstamp,
1671 (unsigned long long)rxs->mactime,
1672 (unsigned long long)(rxs->mactime - bc_tstamp),
1673 (unsigned long long)tsf);
1674
1675 /*
1676 * Sometimes the HW will give us a wrong tstamp in the rx
1677 * status, causing the timestamp extension to go wrong.
1678 * (This seems to happen especially with beacon frames bigger
1679 * than 78 byte (incl. FCS))
1680 * But we know that the receive timestamp must be later than the
1681 * timestamp of the beacon since HW must have synced to that.
1682 *
1683 * NOTE: here we assume mactime to be after the frame was
1684 * received, not like mac80211 which defines it at the start.
1685 */
1686 if (bc_tstamp > rxs->mactime) {
1687 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1688 "fixing mactime from %llx to %llx\n",
1689 (unsigned long long)rxs->mactime,
1690 (unsigned long long)tsf);
1691 rxs->mactime = tsf;
1692 }
1693
1694 /*
1695 * Local TSF might have moved higher than our beacon timers,
1696 * in that case we have to update them to continue sending
1697 * beacons. This also takes care of synchronizing beacon sending
1698 * times with other stations.
1699 */
1700 if (hw_tu >= sc->nexttbtt)
1701 ath5k_beacon_update_timers(sc, bc_tstamp);
1702 }
1703 }
1704
1705 static void ath5k_tasklet_beacon(unsigned long data)
1706 {
1707 struct ath5k_softc *sc = (struct ath5k_softc *) data;
1708
1709 /*
1710 * Software beacon alert--time to send a beacon.
1711 *
1712 * In IBSS mode we use this interrupt just to
1713 * keep track of the next TBTT (target beacon
1714 * transmission time) in order to detect wether
1715 * automatic TSF updates happened.
1716 */
1717 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1718 /* XXX: only if VEOL suppported */
1719 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
1720 sc->nexttbtt += sc->bintval;
1721 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1722 "SWBA nexttbtt: %x hw_tu: %x "
1723 "TSF: %llx\n",
1724 sc->nexttbtt,
1725 TSF_TO_TU(tsf),
1726 (unsigned long long) tsf);
1727 } else {
1728 spin_lock(&sc->block);
1729 ath5k_beacon_send(sc);
1730 spin_unlock(&sc->block);
1731 }
1732 }
1733
1734 static void
1735 ath5k_tasklet_rx(unsigned long data)
1736 {
1737 struct ieee80211_rx_status rxs = {};
1738 struct ath5k_rx_status rs = {};
1739 struct sk_buff *skb, *next_skb;
1740 dma_addr_t next_skb_addr;
1741 struct ath5k_softc *sc = (void *)data;
1742 struct ath5k_buf *bf, *bf_last;
1743 struct ath5k_desc *ds;
1744 int ret;
1745 int hdrlen;
1746 int padsize;
1747
1748 spin_lock(&sc->rxbuflock);
1749 if (list_empty(&sc->rxbuf)) {
1750 ATH5K_WARN(sc, "empty rx buf pool\n");
1751 goto unlock;
1752 }
1753 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
1754 do {
1755 rxs.flag = 0;
1756
1757 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1758 BUG_ON(bf->skb == NULL);
1759 skb = bf->skb;
1760 ds = bf->desc;
1761
1762 /*
1763 * last buffer must not be freed to ensure proper hardware
1764 * function. When the hardware finishes also a packet next to
1765 * it, we are sure, it doesn't use it anymore and we can go on.
1766 */
1767 if (bf_last == bf)
1768 bf->flags |= 1;
1769 if (bf->flags) {
1770 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1771 struct ath5k_buf, list);
1772 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1773 &rs);
1774 if (ret)
1775 break;
1776 bf->flags &= ~1;
1777 /* skip the overwritten one (even status is martian) */
1778 goto next;
1779 }
1780
1781 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1782 if (unlikely(ret == -EINPROGRESS))
1783 break;
1784 else if (unlikely(ret)) {
1785 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1786 spin_unlock(&sc->rxbuflock);
1787 return;
1788 }
1789
1790 if (unlikely(rs.rs_more)) {
1791 ATH5K_WARN(sc, "unsupported jumbo\n");
1792 goto next;
1793 }
1794
1795 if (unlikely(rs.rs_status)) {
1796 if (rs.rs_status & AR5K_RXERR_PHY)
1797 goto next;
1798 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1799 /*
1800 * Decrypt error. If the error occurred
1801 * because there was no hardware key, then
1802 * let the frame through so the upper layers
1803 * can process it. This is necessary for 5210
1804 * parts which have no way to setup a ``clear''
1805 * key cache entry.
1806 *
1807 * XXX do key cache faulting
1808 */
1809 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1810 !(rs.rs_status & AR5K_RXERR_CRC))
1811 goto accept;
1812 }
1813 if (rs.rs_status & AR5K_RXERR_MIC) {
1814 rxs.flag |= RX_FLAG_MMIC_ERROR;
1815 goto accept;
1816 }
1817
1818 /* let crypto-error packets fall through in MNTR */
1819 if ((rs.rs_status &
1820 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1821 sc->opmode != NL80211_IFTYPE_MONITOR)
1822 goto next;
1823 }
1824 accept:
1825 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1826
1827 /*
1828 * If we can't replace bf->skb with a new skb under memory
1829 * pressure, just skip this packet
1830 */
1831 if (!next_skb)
1832 goto next;
1833
1834 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1835 PCI_DMA_FROMDEVICE);
1836 skb_put(skb, rs.rs_datalen);
1837
1838 /* The MAC header is padded to have 32-bit boundary if the
1839 * packet payload is non-zero. The general calculation for
1840 * padsize would take into account odd header lengths:
1841 * padsize = (4 - hdrlen % 4) % 4; However, since only
1842 * even-length headers are used, padding can only be 0 or 2
1843 * bytes and we can optimize this a bit. In addition, we must
1844 * not try to remove padding from short control frames that do
1845 * not have payload. */
1846 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1847 padsize = ath5k_pad_size(hdrlen);
1848 if (padsize) {
1849 memmove(skb->data + padsize, skb->data, hdrlen);
1850 skb_pull(skb, padsize);
1851 }
1852
1853 /*
1854 * always extend the mac timestamp, since this information is
1855 * also needed for proper IBSS merging.
1856 *
1857 * XXX: it might be too late to do it here, since rs_tstamp is
1858 * 15bit only. that means TSF extension has to be done within
1859 * 32768usec (about 32ms). it might be necessary to move this to
1860 * the interrupt handler, like it is done in madwifi.
1861 *
1862 * Unfortunately we don't know when the hardware takes the rx
1863 * timestamp (beginning of phy frame, data frame, end of rx?).
1864 * The only thing we know is that it is hardware specific...
1865 * On AR5213 it seems the rx timestamp is at the end of the
1866 * frame, but i'm not sure.
1867 *
1868 * NOTE: mac80211 defines mactime at the beginning of the first
1869 * data symbol. Since we don't have any time references it's
1870 * impossible to comply to that. This affects IBSS merge only
1871 * right now, so it's not too bad...
1872 */
1873 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1874 rxs.flag |= RX_FLAG_TSFT;
1875
1876 rxs.freq = sc->curchan->center_freq;
1877 rxs.band = sc->curband->band;
1878
1879 rxs.noise = sc->ah->ah_noise_floor;
1880 rxs.signal = rxs.noise + rs.rs_rssi;
1881
1882 /* An rssi of 35 indicates you should be able use
1883 * 54 Mbps reliably. A more elaborate scheme can be used
1884 * here but it requires a map of SNR/throughput for each
1885 * possible mode used */
1886 rxs.qual = rs.rs_rssi * 100 / 35;
1887
1888 /* rssi can be more than 35 though, anything above that
1889 * should be considered at 100% */
1890 if (rxs.qual > 100)
1891 rxs.qual = 100;
1892
1893 rxs.antenna = rs.rs_antenna;
1894 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1895 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1896
1897 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1898 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
1899 rxs.flag |= RX_FLAG_SHORTPRE;
1900
1901 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1902
1903 /* check beacons in IBSS mode */
1904 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1905 ath5k_check_ibss_tsf(sc, skb, &rxs);
1906
1907 __ieee80211_rx(sc->hw, skb, &rxs);
1908
1909 bf->skb = next_skb;
1910 bf->skbaddr = next_skb_addr;
1911 next:
1912 list_move_tail(&bf->list, &sc->rxbuf);
1913 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1914 unlock:
1915 spin_unlock(&sc->rxbuflock);
1916 }
1917
1918
1919
1920
1921 /*************\
1922 * TX Handling *
1923 \*************/
1924
1925 static void
1926 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1927 {
1928 struct ath5k_tx_status ts = {};
1929 struct ath5k_buf *bf, *bf0;
1930 struct ath5k_desc *ds;
1931 struct sk_buff *skb;
1932 struct ieee80211_tx_info *info;
1933 int i, ret;
1934
1935 spin_lock(&txq->lock);
1936 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1937 ds = bf->desc;
1938
1939 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1940 if (unlikely(ret == -EINPROGRESS))
1941 break;
1942 else if (unlikely(ret)) {
1943 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1944 ret, txq->qnum);
1945 break;
1946 }
1947
1948 skb = bf->skb;
1949 info = IEEE80211_SKB_CB(skb);
1950 bf->skb = NULL;
1951
1952 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1953 PCI_DMA_TODEVICE);
1954
1955 ieee80211_tx_info_clear_status(info);
1956 for (i = 0; i < 4; i++) {
1957 struct ieee80211_tx_rate *r =
1958 &info->status.rates[i];
1959
1960 if (ts.ts_rate[i]) {
1961 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1962 r->count = ts.ts_retry[i];
1963 } else {
1964 r->idx = -1;
1965 r->count = 0;
1966 }
1967 }
1968
1969 /* count the successful attempt as well */
1970 info->status.rates[ts.ts_final_idx].count++;
1971
1972 if (unlikely(ts.ts_status)) {
1973 sc->ll_stats.dot11ACKFailureCount++;
1974 if (ts.ts_status & AR5K_TXERR_FILT)
1975 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1976 } else {
1977 info->flags |= IEEE80211_TX_STAT_ACK;
1978 info->status.ack_signal = ts.ts_rssi;
1979 }
1980
1981 ieee80211_tx_status(sc->hw, skb);
1982 sc->tx_stats[txq->qnum].count++;
1983
1984 spin_lock(&sc->txbuflock);
1985 sc->tx_stats[txq->qnum].len--;
1986 list_move_tail(&bf->list, &sc->txbuf);
1987 sc->txbuf_len++;
1988 spin_unlock(&sc->txbuflock);
1989 }
1990 if (likely(list_empty(&txq->q)))
1991 txq->link = NULL;
1992 spin_unlock(&txq->lock);
1993 if (sc->txbuf_len > ATH_TXBUF / 5)
1994 ieee80211_wake_queues(sc->hw);
1995 }
1996
1997 static void
1998 ath5k_tasklet_tx(unsigned long data)
1999 {
2000 struct ath5k_softc *sc = (void *)data;
2001
2002 ath5k_tx_processq(sc, sc->txq);
2003 }
2004
2005
2006 /*****************\
2007 * Beacon handling *
2008 \*****************/
2009
2010 /*
2011 * Setup the beacon frame for transmit.
2012 */
2013 static int
2014 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
2015 {
2016 struct sk_buff *skb = bf->skb;
2017 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2018 struct ath5k_hw *ah = sc->ah;
2019 struct ath5k_desc *ds;
2020 int ret, antenna = 0;
2021 u32 flags;
2022
2023 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2024 PCI_DMA_TODEVICE);
2025 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2026 "skbaddr %llx\n", skb, skb->data, skb->len,
2027 (unsigned long long)bf->skbaddr);
2028 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
2029 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2030 return -EIO;
2031 }
2032
2033 ds = bf->desc;
2034
2035 flags = AR5K_TXDESC_NOACK;
2036 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
2037 ds->ds_link = bf->daddr; /* self-linked */
2038 flags |= AR5K_TXDESC_VEOL;
2039 /*
2040 * Let hardware handle antenna switching if txantenna is not set
2041 */
2042 } else {
2043 ds->ds_link = 0;
2044 /*
2045 * Switch antenna every 4 beacons if txantenna is not set
2046 * XXX assumes two antennas
2047 */
2048 if (antenna == 0)
2049 antenna = sc->bsent & 4 ? 2 : 1;
2050 }
2051
2052 /* FIXME: If we are in g mode and rate is a CCK rate
2053 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2054 * from tx power (value is in dB units already) */
2055 ds->ds_data = bf->skbaddr;
2056 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2057 ieee80211_get_hdrlen_from_skb(skb),
2058 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2059 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2060 1, AR5K_TXKEYIX_INVALID,
2061 antenna, flags, 0, 0);
2062 if (ret)
2063 goto err_unmap;
2064
2065 return 0;
2066 err_unmap:
2067 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2068 return ret;
2069 }
2070
2071 /*
2072 * Transmit a beacon frame at SWBA. Dynamic updates to the
2073 * frame contents are done as needed and the slot time is
2074 * also adjusted based on current state.
2075 *
2076 * This is called from software irq context (beacontq or restq
2077 * tasklets) or user context from ath5k_beacon_config.
2078 */
2079 static void
2080 ath5k_beacon_send(struct ath5k_softc *sc)
2081 {
2082 struct ath5k_buf *bf = sc->bbuf;
2083 struct ath5k_hw *ah = sc->ah;
2084
2085 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2086
2087 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2088 sc->opmode == NL80211_IFTYPE_MONITOR)) {
2089 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2090 return;
2091 }
2092 /*
2093 * Check if the previous beacon has gone out. If
2094 * not don't don't try to post another, skip this
2095 * period and wait for the next. Missed beacons
2096 * indicate a problem and should not occur. If we
2097 * miss too many consecutive beacons reset the device.
2098 */
2099 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2100 sc->bmisscount++;
2101 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2102 "missed %u consecutive beacons\n", sc->bmisscount);
2103 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
2104 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2105 "stuck beacon time (%u missed)\n",
2106 sc->bmisscount);
2107 tasklet_schedule(&sc->restq);
2108 }
2109 return;
2110 }
2111 if (unlikely(sc->bmisscount != 0)) {
2112 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2113 "resume beacon xmit after %u misses\n",
2114 sc->bmisscount);
2115 sc->bmisscount = 0;
2116 }
2117
2118 /*
2119 * Stop any current dma and put the new frame on the queue.
2120 * This should never fail since we check above that no frames
2121 * are still pending on the queue.
2122 */
2123 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2124 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2125 /* NB: hw still stops DMA, so proceed */
2126 }
2127
2128 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2129 ath5k_hw_start_tx_dma(ah, sc->bhalq);
2130 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2131 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2132
2133 sc->bsent++;
2134 }
2135
2136
2137 /**
2138 * ath5k_beacon_update_timers - update beacon timers
2139 *
2140 * @sc: struct ath5k_softc pointer we are operating on
2141 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2142 * beacon timer update based on the current HW TSF.
2143 *
2144 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2145 * of a received beacon or the current local hardware TSF and write it to the
2146 * beacon timer registers.
2147 *
2148 * This is called in a variety of situations, e.g. when a beacon is received,
2149 * when a TSF update has been detected, but also when an new IBSS is created or
2150 * when we otherwise know we have to update the timers, but we keep it in this
2151 * function to have it all together in one place.
2152 */
2153 static void
2154 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2155 {
2156 struct ath5k_hw *ah = sc->ah;
2157 u32 nexttbtt, intval, hw_tu, bc_tu;
2158 u64 hw_tsf;
2159
2160 intval = sc->bintval & AR5K_BEACON_PERIOD;
2161 if (WARN_ON(!intval))
2162 return;
2163
2164 /* beacon TSF converted to TU */
2165 bc_tu = TSF_TO_TU(bc_tsf);
2166
2167 /* current TSF converted to TU */
2168 hw_tsf = ath5k_hw_get_tsf64(ah);
2169 hw_tu = TSF_TO_TU(hw_tsf);
2170
2171 #define FUDGE 3
2172 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2173 if (bc_tsf == -1) {
2174 /*
2175 * no beacons received, called internally.
2176 * just need to refresh timers based on HW TSF.
2177 */
2178 nexttbtt = roundup(hw_tu + FUDGE, intval);
2179 } else if (bc_tsf == 0) {
2180 /*
2181 * no beacon received, probably called by ath5k_reset_tsf().
2182 * reset TSF to start with 0.
2183 */
2184 nexttbtt = intval;
2185 intval |= AR5K_BEACON_RESET_TSF;
2186 } else if (bc_tsf > hw_tsf) {
2187 /*
2188 * beacon received, SW merge happend but HW TSF not yet updated.
2189 * not possible to reconfigure timers yet, but next time we
2190 * receive a beacon with the same BSSID, the hardware will
2191 * automatically update the TSF and then we need to reconfigure
2192 * the timers.
2193 */
2194 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2195 "need to wait for HW TSF sync\n");
2196 return;
2197 } else {
2198 /*
2199 * most important case for beacon synchronization between STA.
2200 *
2201 * beacon received and HW TSF has been already updated by HW.
2202 * update next TBTT based on the TSF of the beacon, but make
2203 * sure it is ahead of our local TSF timer.
2204 */
2205 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2206 }
2207 #undef FUDGE
2208
2209 sc->nexttbtt = nexttbtt;
2210
2211 intval |= AR5K_BEACON_ENA;
2212 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2213
2214 /*
2215 * debugging output last in order to preserve the time critical aspect
2216 * of this function
2217 */
2218 if (bc_tsf == -1)
2219 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2220 "reconfigured timers based on HW TSF\n");
2221 else if (bc_tsf == 0)
2222 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2223 "reset HW TSF and timers\n");
2224 else
2225 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2226 "updated timers based on beacon TSF\n");
2227
2228 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2229 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2230 (unsigned long long) bc_tsf,
2231 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2232 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2233 intval & AR5K_BEACON_PERIOD,
2234 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2235 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2236 }
2237
2238
2239 /**
2240 * ath5k_beacon_config - Configure the beacon queues and interrupts
2241 *
2242 * @sc: struct ath5k_softc pointer we are operating on
2243 *
2244 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2245 * interrupts to detect TSF updates only.
2246 */
2247 static void
2248 ath5k_beacon_config(struct ath5k_softc *sc)
2249 {
2250 struct ath5k_hw *ah = sc->ah;
2251 unsigned long flags;
2252
2253 ath5k_hw_set_imr(ah, 0);
2254 sc->bmisscount = 0;
2255 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2256
2257 if (sc->opmode == NL80211_IFTYPE_ADHOC ||
2258 sc->opmode == NL80211_IFTYPE_MESH_POINT ||
2259 sc->opmode == NL80211_IFTYPE_AP) {
2260 /*
2261 * In IBSS mode we use a self-linked tx descriptor and let the
2262 * hardware send the beacons automatically. We have to load it
2263 * only once here.
2264 * We use the SWBA interrupt only to keep track of the beacon
2265 * timers in order to detect automatic TSF updates.
2266 */
2267 ath5k_beaconq_config(sc);
2268
2269 sc->imask |= AR5K_INT_SWBA;
2270
2271 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2272 if (ath5k_hw_hasveol(ah)) {
2273 spin_lock_irqsave(&sc->block, flags);
2274 ath5k_beacon_send(sc);
2275 spin_unlock_irqrestore(&sc->block, flags);
2276 }
2277 } else
2278 ath5k_beacon_update_timers(sc, -1);
2279 }
2280
2281 ath5k_hw_set_imr(ah, sc->imask);
2282 }
2283
2284
2285 /********************\
2286 * Interrupt handling *
2287 \********************/
2288
2289 static int
2290 ath5k_init(struct ath5k_softc *sc)
2291 {
2292 struct ath5k_hw *ah = sc->ah;
2293 int ret, i;
2294
2295 mutex_lock(&sc->lock);
2296
2297 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2298
2299 /*
2300 * Stop anything previously setup. This is safe
2301 * no matter this is the first time through or not.
2302 */
2303 ath5k_stop_locked(sc);
2304
2305 /*
2306 * The basic interface to setting the hardware in a good
2307 * state is ``reset''. On return the hardware is known to
2308 * be powered up and with interrupts disabled. This must
2309 * be followed by initialization of the appropriate bits
2310 * and then setup of the interrupt mask.
2311 */
2312 sc->curchan = sc->hw->conf.channel;
2313 sc->curband = &sc->sbands[sc->curchan->band];
2314 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2315 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2316 AR5K_INT_FATAL | AR5K_INT_GLOBAL;
2317 ret = ath5k_reset(sc, false, false);
2318 if (ret)
2319 goto done;
2320
2321 /*
2322 * Reset the key cache since some parts do not reset the
2323 * contents on initial power up or resume from suspend.
2324 */
2325 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2326 ath5k_hw_reset_key(ah, i);
2327
2328 /* Set ack to be sent at low bit-rates */
2329 ath5k_hw_set_ack_bitrate_high(ah, false);
2330
2331 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2332 msecs_to_jiffies(ath5k_calinterval * 1000)));
2333
2334 ret = 0;
2335 done:
2336 mmiowb();
2337 mutex_unlock(&sc->lock);
2338 return ret;
2339 }
2340
2341 static int
2342 ath5k_stop_locked(struct ath5k_softc *sc)
2343 {
2344 struct ath5k_hw *ah = sc->ah;
2345
2346 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2347 test_bit(ATH_STAT_INVALID, sc->status));
2348
2349 /*
2350 * Shutdown the hardware and driver:
2351 * stop output from above
2352 * disable interrupts
2353 * turn off timers
2354 * turn off the radio
2355 * clear transmit machinery
2356 * clear receive machinery
2357 * drain and release tx queues
2358 * reclaim beacon resources
2359 * power down hardware
2360 *
2361 * Note that some of this work is not possible if the
2362 * hardware is gone (invalid).
2363 */
2364 ieee80211_stop_queues(sc->hw);
2365
2366 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2367 ath5k_led_off(sc);
2368 ath5k_hw_set_imr(ah, 0);
2369 synchronize_irq(sc->pdev->irq);
2370 }
2371 ath5k_txq_cleanup(sc);
2372 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2373 ath5k_rx_stop(sc);
2374 ath5k_hw_phy_disable(ah);
2375 } else
2376 sc->rxlink = NULL;
2377
2378 return 0;
2379 }
2380
2381 /*
2382 * Stop the device, grabbing the top-level lock to protect
2383 * against concurrent entry through ath5k_init (which can happen
2384 * if another thread does a system call and the thread doing the
2385 * stop is preempted).
2386 */
2387 static int
2388 ath5k_stop_hw(struct ath5k_softc *sc)
2389 {
2390 int ret;
2391
2392 mutex_lock(&sc->lock);
2393 ret = ath5k_stop_locked(sc);
2394 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2395 /*
2396 * Set the chip in full sleep mode. Note that we are
2397 * careful to do this only when bringing the interface
2398 * completely to a stop. When the chip is in this state
2399 * it must be carefully woken up or references to
2400 * registers in the PCI clock domain may freeze the bus
2401 * (and system). This varies by chip and is mostly an
2402 * issue with newer parts that go to sleep more quickly.
2403 */
2404 if (sc->ah->ah_mac_srev >= 0x78) {
2405 /*
2406 * XXX
2407 * don't put newer MAC revisions > 7.8 to sleep because
2408 * of the above mentioned problems
2409 */
2410 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2411 "not putting device to sleep\n");
2412 } else {
2413 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2414 "putting device to full sleep\n");
2415 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2416 }
2417 }
2418 ath5k_txbuf_free(sc, sc->bbuf);
2419
2420 mmiowb();
2421 mutex_unlock(&sc->lock);
2422
2423 del_timer_sync(&sc->calib_tim);
2424 tasklet_kill(&sc->rxtq);
2425 tasklet_kill(&sc->txtq);
2426 tasklet_kill(&sc->restq);
2427 tasklet_kill(&sc->beacontq);
2428
2429 return ret;
2430 }
2431
2432 static irqreturn_t
2433 ath5k_intr(int irq, void *dev_id)
2434 {
2435 struct ath5k_softc *sc = dev_id;
2436 struct ath5k_hw *ah = sc->ah;
2437 enum ath5k_int status;
2438 unsigned int counter = 1000;
2439
2440 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2441 !ath5k_hw_is_intr_pending(ah)))
2442 return IRQ_NONE;
2443
2444 do {
2445 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2446 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2447 status, sc->imask);
2448 if (unlikely(status & AR5K_INT_FATAL)) {
2449 /*
2450 * Fatal errors are unrecoverable.
2451 * Typically these are caused by DMA errors.
2452 */
2453 tasklet_schedule(&sc->restq);
2454 } else if (unlikely(status & AR5K_INT_RXORN)) {
2455 tasklet_schedule(&sc->restq);
2456 } else {
2457 if (status & AR5K_INT_SWBA) {
2458 tasklet_schedule(&sc->beacontq);
2459 }
2460 if (status & AR5K_INT_RXEOL) {
2461 /*
2462 * NB: the hardware should re-read the link when
2463 * RXE bit is written, but it doesn't work at
2464 * least on older hardware revs.
2465 */
2466 sc->rxlink = NULL;
2467 }
2468 if (status & AR5K_INT_TXURN) {
2469 /* bump tx trigger level */
2470 ath5k_hw_update_tx_triglevel(ah, true);
2471 }
2472 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2473 tasklet_schedule(&sc->rxtq);
2474 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2475 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2476 tasklet_schedule(&sc->txtq);
2477 if (status & AR5K_INT_BMISS) {
2478 /* TODO */
2479 }
2480 if (status & AR5K_INT_MIB) {
2481 /*
2482 * These stats are also used for ANI i think
2483 * so how about updating them more often ?
2484 */
2485 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2486 }
2487 }
2488 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2489
2490 if (unlikely(!counter))
2491 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2492
2493 return IRQ_HANDLED;
2494 }
2495
2496 static void
2497 ath5k_tasklet_reset(unsigned long data)
2498 {
2499 struct ath5k_softc *sc = (void *)data;
2500
2501 ath5k_reset_wake(sc);
2502 }
2503
2504 /*
2505 * Periodically recalibrate the PHY to account
2506 * for temperature/environment changes.
2507 */
2508 static void
2509 ath5k_calibrate(unsigned long data)
2510 {
2511 struct ath5k_softc *sc = (void *)data;
2512 struct ath5k_hw *ah = sc->ah;
2513
2514 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2515 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2516 sc->curchan->hw_value);
2517
2518 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2519 /*
2520 * Rfgain is out of bounds, reset the chip
2521 * to load new gain values.
2522 */
2523 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2524 ath5k_reset_wake(sc);
2525 }
2526 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2527 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2528 ieee80211_frequency_to_channel(
2529 sc->curchan->center_freq));
2530
2531 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2532 msecs_to_jiffies(ath5k_calinterval * 1000)));
2533 }
2534
2535
2536 /********************\
2537 * Mac80211 functions *
2538 \********************/
2539
2540 static int
2541 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2542 {
2543 struct ath5k_softc *sc = hw->priv;
2544 struct ath5k_buf *bf;
2545 unsigned long flags;
2546 int hdrlen;
2547 int padsize;
2548
2549 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2550
2551 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2552 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2553
2554 /*
2555 * the hardware expects the header padded to 4 byte boundaries
2556 * if this is not the case we add the padding after the header
2557 */
2558 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2559 padsize = ath5k_pad_size(hdrlen);
2560 if (padsize) {
2561
2562 if (skb_headroom(skb) < padsize) {
2563 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2564 " headroom to pad %d\n", hdrlen, padsize);
2565 goto drop_packet;
2566 }
2567 skb_push(skb, padsize);
2568 memmove(skb->data, skb->data+padsize, hdrlen);
2569 }
2570
2571 spin_lock_irqsave(&sc->txbuflock, flags);
2572 if (list_empty(&sc->txbuf)) {
2573 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2574 spin_unlock_irqrestore(&sc->txbuflock, flags);
2575 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2576 goto drop_packet;
2577 }
2578 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2579 list_del(&bf->list);
2580 sc->txbuf_len--;
2581 if (list_empty(&sc->txbuf))
2582 ieee80211_stop_queues(hw);
2583 spin_unlock_irqrestore(&sc->txbuflock, flags);
2584
2585 bf->skb = skb;
2586
2587 if (ath5k_txbuf_setup(sc, bf)) {
2588 bf->skb = NULL;
2589 spin_lock_irqsave(&sc->txbuflock, flags);
2590 list_add_tail(&bf->list, &sc->txbuf);
2591 sc->txbuf_len++;
2592 spin_unlock_irqrestore(&sc->txbuflock, flags);
2593 goto drop_packet;
2594 }
2595 return NETDEV_TX_OK;
2596
2597 drop_packet:
2598 dev_kfree_skb_any(skb);
2599 return NETDEV_TX_OK;
2600 }
2601
2602 static int
2603 ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
2604 {
2605 struct ath5k_hw *ah = sc->ah;
2606 int ret;
2607
2608 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2609
2610 if (stop) {
2611 ath5k_hw_set_imr(ah, 0);
2612 ath5k_txq_cleanup(sc);
2613 ath5k_rx_stop(sc);
2614 }
2615 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2616 if (ret) {
2617 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2618 goto err;
2619 }
2620
2621 ret = ath5k_rx_start(sc);
2622 if (ret) {
2623 ATH5K_ERR(sc, "can't start recv logic\n");
2624 goto err;
2625 }
2626
2627 /*
2628 * Change channels and update the h/w rate map if we're switching;
2629 * e.g. 11a to 11b/g.
2630 *
2631 * We may be doing a reset in response to an ioctl that changes the
2632 * channel so update any state that might change as a result.
2633 *
2634 * XXX needed?
2635 */
2636 /* ath5k_chan_change(sc, c); */
2637
2638 ath5k_beacon_config(sc);
2639 /* intrs are enabled by ath5k_beacon_config */
2640
2641 return 0;
2642 err:
2643 return ret;
2644 }
2645
2646 static int
2647 ath5k_reset_wake(struct ath5k_softc *sc)
2648 {
2649 int ret;
2650
2651 ret = ath5k_reset(sc, true, true);
2652 if (!ret)
2653 ieee80211_wake_queues(sc->hw);
2654
2655 return ret;
2656 }
2657
2658 static int ath5k_start(struct ieee80211_hw *hw)
2659 {
2660 return ath5k_init(hw->priv);
2661 }
2662
2663 static void ath5k_stop(struct ieee80211_hw *hw)
2664 {
2665 ath5k_stop_hw(hw->priv);
2666 }
2667
2668 static int ath5k_add_interface(struct ieee80211_hw *hw,
2669 struct ieee80211_if_init_conf *conf)
2670 {
2671 struct ath5k_softc *sc = hw->priv;
2672 int ret;
2673
2674 mutex_lock(&sc->lock);
2675 if (sc->vif) {
2676 ret = 0;
2677 goto end;
2678 }
2679
2680 sc->vif = conf->vif;
2681
2682 switch (conf->type) {
2683 case NL80211_IFTYPE_AP:
2684 case NL80211_IFTYPE_STATION:
2685 case NL80211_IFTYPE_ADHOC:
2686 case NL80211_IFTYPE_MESH_POINT:
2687 case NL80211_IFTYPE_MONITOR:
2688 sc->opmode = conf->type;
2689 break;
2690 default:
2691 ret = -EOPNOTSUPP;
2692 goto end;
2693 }
2694
2695 /* Set to a reasonable value. Note that this will
2696 * be set to mac80211's value at ath5k_config(). */
2697 sc->bintval = 1000;
2698 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
2699
2700 ret = 0;
2701 end:
2702 mutex_unlock(&sc->lock);
2703 return ret;
2704 }
2705
2706 static void
2707 ath5k_remove_interface(struct ieee80211_hw *hw,
2708 struct ieee80211_if_init_conf *conf)
2709 {
2710 struct ath5k_softc *sc = hw->priv;
2711 u8 mac[ETH_ALEN] = {};
2712
2713 mutex_lock(&sc->lock);
2714 if (sc->vif != conf->vif)
2715 goto end;
2716
2717 ath5k_hw_set_lladdr(sc->ah, mac);
2718 sc->vif = NULL;
2719 end:
2720 mutex_unlock(&sc->lock);
2721 }
2722
2723 /*
2724 * TODO: Phy disable/diversity etc
2725 */
2726 static int
2727 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2728 {
2729 struct ath5k_softc *sc = hw->priv;
2730 struct ieee80211_conf *conf = &hw->conf;
2731 int ret;
2732
2733 mutex_lock(&sc->lock);
2734
2735 sc->bintval = conf->beacon_int;
2736 sc->power_level = conf->power_level;
2737
2738 ret = ath5k_chan_set(sc, conf->channel);
2739
2740 mutex_unlock(&sc->lock);
2741 return ret;
2742 }
2743
2744 static int
2745 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2746 struct ieee80211_if_conf *conf)
2747 {
2748 struct ath5k_softc *sc = hw->priv;
2749 struct ath5k_hw *ah = sc->ah;
2750 int ret = 0;
2751
2752 mutex_lock(&sc->lock);
2753 if (sc->vif != vif) {
2754 ret = -EIO;
2755 goto unlock;
2756 }
2757 if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
2758 /* Cache for later use during resets */
2759 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2760 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2761 * a clean way of letting us retrieve this yet. */
2762 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2763 mmiowb();
2764 }
2765 if (conf->changed & IEEE80211_IFCC_BEACON &&
2766 (vif->type == NL80211_IFTYPE_ADHOC ||
2767 vif->type == NL80211_IFTYPE_MESH_POINT ||
2768 vif->type == NL80211_IFTYPE_AP)) {
2769 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2770 if (!beacon) {
2771 ret = -ENOMEM;
2772 goto unlock;
2773 }
2774 ath5k_beacon_update(sc, beacon);
2775 }
2776
2777 unlock:
2778 mutex_unlock(&sc->lock);
2779 return ret;
2780 }
2781
2782 #define SUPPORTED_FIF_FLAGS \
2783 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2784 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2785 FIF_BCN_PRBRESP_PROMISC
2786 /*
2787 * o always accept unicast, broadcast, and multicast traffic
2788 * o multicast traffic for all BSSIDs will be enabled if mac80211
2789 * says it should be
2790 * o maintain current state of phy ofdm or phy cck error reception.
2791 * If the hardware detects any of these type of errors then
2792 * ath5k_hw_get_rx_filter() will pass to us the respective
2793 * hardware filters to be able to receive these type of frames.
2794 * o probe request frames are accepted only when operating in
2795 * hostap, adhoc, or monitor modes
2796 * o enable promiscuous mode according to the interface state
2797 * o accept beacons:
2798 * - when operating in adhoc mode so the 802.11 layer creates
2799 * node table entries for peers,
2800 * - when operating in station mode for collecting rssi data when
2801 * the station is otherwise quiet, or
2802 * - when scanning
2803 */
2804 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2805 unsigned int changed_flags,
2806 unsigned int *new_flags,
2807 int mc_count, struct dev_mc_list *mclist)
2808 {
2809 struct ath5k_softc *sc = hw->priv;
2810 struct ath5k_hw *ah = sc->ah;
2811 u32 mfilt[2], val, rfilt;
2812 u8 pos;
2813 int i;
2814
2815 mfilt[0] = 0;
2816 mfilt[1] = 0;
2817
2818 /* Only deal with supported flags */
2819 changed_flags &= SUPPORTED_FIF_FLAGS;
2820 *new_flags &= SUPPORTED_FIF_FLAGS;
2821
2822 /* If HW detects any phy or radar errors, leave those filters on.
2823 * Also, always enable Unicast, Broadcasts and Multicast
2824 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2825 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2826 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2827 AR5K_RX_FILTER_MCAST);
2828
2829 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2830 if (*new_flags & FIF_PROMISC_IN_BSS) {
2831 rfilt |= AR5K_RX_FILTER_PROM;
2832 __set_bit(ATH_STAT_PROMISC, sc->status);
2833 } else {
2834 __clear_bit(ATH_STAT_PROMISC, sc->status);
2835 }
2836 }
2837
2838 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2839 if (*new_flags & FIF_ALLMULTI) {
2840 mfilt[0] = ~0;
2841 mfilt[1] = ~0;
2842 } else {
2843 for (i = 0; i < mc_count; i++) {
2844 if (!mclist)
2845 break;
2846 /* calculate XOR of eight 6-bit values */
2847 val = get_unaligned_le32(mclist->dmi_addr + 0);
2848 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2849 val = get_unaligned_le32(mclist->dmi_addr + 3);
2850 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2851 pos &= 0x3f;
2852 mfilt[pos / 32] |= (1 << (pos % 32));
2853 /* XXX: we might be able to just do this instead,
2854 * but not sure, needs testing, if we do use this we'd
2855 * neet to inform below to not reset the mcast */
2856 /* ath5k_hw_set_mcast_filterindex(ah,
2857 * mclist->dmi_addr[5]); */
2858 mclist = mclist->next;
2859 }
2860 }
2861
2862 /* This is the best we can do */
2863 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2864 rfilt |= AR5K_RX_FILTER_PHYERR;
2865
2866 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2867 * and probes for any BSSID, this needs testing */
2868 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2869 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2870
2871 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2872 * set we should only pass on control frames for this
2873 * station. This needs testing. I believe right now this
2874 * enables *all* control frames, which is OK.. but
2875 * but we should see if we can improve on granularity */
2876 if (*new_flags & FIF_CONTROL)
2877 rfilt |= AR5K_RX_FILTER_CONTROL;
2878
2879 /* Additional settings per mode -- this is per ath5k */
2880
2881 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2882
2883 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2884 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2885 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2886 if (sc->opmode != NL80211_IFTYPE_STATION)
2887 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2888 if (sc->opmode != NL80211_IFTYPE_AP &&
2889 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
2890 test_bit(ATH_STAT_PROMISC, sc->status))
2891 rfilt |= AR5K_RX_FILTER_PROM;
2892 if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
2893 sc->opmode == NL80211_IFTYPE_ADHOC ||
2894 sc->opmode == NL80211_IFTYPE_AP)
2895 rfilt |= AR5K_RX_FILTER_BEACON;
2896 if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
2897 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2898 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2899
2900 /* Set filters */
2901 ath5k_hw_set_rx_filter(ah, rfilt);
2902
2903 /* Set multicast bits */
2904 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2905 /* Set the cached hw filter flags, this will alter actually
2906 * be set in HW */
2907 sc->filter_flags = rfilt;
2908 }
2909
2910 static int
2911 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2912 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
2913 struct ieee80211_key_conf *key)
2914 {
2915 struct ath5k_softc *sc = hw->priv;
2916 int ret = 0;
2917
2918 if (modparam_nohwcrypt)
2919 return -EOPNOTSUPP;
2920
2921 switch (key->alg) {
2922 case ALG_WEP:
2923 case ALG_TKIP:
2924 break;
2925 case ALG_CCMP:
2926 return -EOPNOTSUPP;
2927 default:
2928 WARN_ON(1);
2929 return -EINVAL;
2930 }
2931
2932 mutex_lock(&sc->lock);
2933
2934 switch (cmd) {
2935 case SET_KEY:
2936 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
2937 sta ? sta->addr : NULL);
2938 if (ret) {
2939 ATH5K_ERR(sc, "can't set the key\n");
2940 goto unlock;
2941 }
2942 __set_bit(key->keyidx, sc->keymap);
2943 key->hw_key_idx = key->keyidx;
2944 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
2945 IEEE80211_KEY_FLAG_GENERATE_MMIC);
2946 break;
2947 case DISABLE_KEY:
2948 ath5k_hw_reset_key(sc->ah, key->keyidx);
2949 __clear_bit(key->keyidx, sc->keymap);
2950 break;
2951 default:
2952 ret = -EINVAL;
2953 goto unlock;
2954 }
2955
2956 unlock:
2957 mmiowb();
2958 mutex_unlock(&sc->lock);
2959 return ret;
2960 }
2961
2962 static int
2963 ath5k_get_stats(struct ieee80211_hw *hw,
2964 struct ieee80211_low_level_stats *stats)
2965 {
2966 struct ath5k_softc *sc = hw->priv;
2967 struct ath5k_hw *ah = sc->ah;
2968
2969 /* Force update */
2970 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2971
2972 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
2973
2974 return 0;
2975 }
2976
2977 static int
2978 ath5k_get_tx_stats(struct ieee80211_hw *hw,
2979 struct ieee80211_tx_queue_stats *stats)
2980 {
2981 struct ath5k_softc *sc = hw->priv;
2982
2983 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
2984
2985 return 0;
2986 }
2987
2988 static u64
2989 ath5k_get_tsf(struct ieee80211_hw *hw)
2990 {
2991 struct ath5k_softc *sc = hw->priv;
2992
2993 return ath5k_hw_get_tsf64(sc->ah);
2994 }
2995
2996 static void
2997 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2998 {
2999 struct ath5k_softc *sc = hw->priv;
3000
3001 ath5k_hw_set_tsf64(sc->ah, tsf);
3002 }
3003
3004 static void
3005 ath5k_reset_tsf(struct ieee80211_hw *hw)
3006 {
3007 struct ath5k_softc *sc = hw->priv;
3008
3009 /*
3010 * in IBSS mode we need to update the beacon timers too.
3011 * this will also reset the TSF if we call it with 0
3012 */
3013 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3014 ath5k_beacon_update_timers(sc, 0);
3015 else
3016 ath5k_hw_reset_tsf(sc->ah);
3017 }
3018
3019 static int
3020 ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb)
3021 {
3022 unsigned long flags;
3023 int ret;
3024
3025 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3026
3027 spin_lock_irqsave(&sc->block, flags);
3028 ath5k_txbuf_free(sc, sc->bbuf);
3029 sc->bbuf->skb = skb;
3030 ret = ath5k_beacon_setup(sc, sc->bbuf);
3031 if (ret)
3032 sc->bbuf->skb = NULL;
3033 spin_unlock_irqrestore(&sc->block, flags);
3034 if (!ret) {
3035 ath5k_beacon_config(sc);
3036 mmiowb();
3037 }
3038
3039 return ret;
3040 }
3041 static void
3042 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3043 {
3044 struct ath5k_softc *sc = hw->priv;
3045 struct ath5k_hw *ah = sc->ah;
3046 u32 rfilt;
3047 rfilt = ath5k_hw_get_rx_filter(ah);
3048 if (enable)
3049 rfilt |= AR5K_RX_FILTER_BEACON;
3050 else
3051 rfilt &= ~AR5K_RX_FILTER_BEACON;
3052 ath5k_hw_set_rx_filter(ah, rfilt);
3053 sc->filter_flags = rfilt;
3054 }
3055
3056 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3057 struct ieee80211_vif *vif,
3058 struct ieee80211_bss_conf *bss_conf,
3059 u32 changes)
3060 {
3061 struct ath5k_softc *sc = hw->priv;
3062 if (changes & BSS_CHANGED_ASSOC) {
3063 mutex_lock(&sc->lock);
3064 sc->assoc = bss_conf->assoc;
3065 if (sc->opmode == NL80211_IFTYPE_STATION)
3066 set_beacon_filter(hw, sc->assoc);
3067 mutex_unlock(&sc->lock);
3068 }
3069 }
Support for the Chinese Samsung S3C2440 based development boards