1 /* spinlock.h: 32-bit Sparc spinlock support.
3 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
6 #ifndef __SPARC_SPINLOCK_H
7 #define __SPARC_SPINLOCK_H
9 #include <linux/threads.h> /* For NR_CPUS */
15 #define __raw_spin_is_locked(lock) (*((volatile unsigned char *)(lock)) != 0)
17 #define __raw_spin_unlock_wait(lock) \
18 do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
20 static inline void __raw_spin_lock(raw_spinlock_t
*lock
)
24 "ldstub [%0], %%g2\n\t"
25 "orcc %%g2, 0x0, %%g0\n\t"
27 " ldub [%0], %%g2\n\t"
30 "orcc %%g2, 0x0, %%g0\n\t"
32 " ldub [%0], %%g2\n\t"
37 : "g2", "memory", "cc");
40 static inline int __raw_spin_trylock(raw_spinlock_t
*lock
)
43 __asm__
__volatile__("ldstub [%1], %0"
50 static inline void __raw_spin_unlock(raw_spinlock_t
*lock
)
52 __asm__
__volatile__("stb %%g0, [%0]" : : "r" (lock
) : "memory");
55 /* Read-write spinlocks, allowing multiple readers
56 * but only one writer.
58 * NOTE! it is quite common to have readers in interrupts
59 * but no interrupt writers. For those circumstances we
60 * can "mix" irq-safe locks - any writer needs to get a
61 * irq-safe write-lock, but readers can get non-irqsafe
64 * XXX This might create some problems with my dual spinlock
65 * XXX scheme, deadlocks etc. -DaveM
67 * Sort of like atomic_t's on Sparc, but even more clever.
69 * ------------------------------------
70 * | 24-bit counter | wlock | raw_rwlock_t
71 * ------------------------------------
74 * wlock signifies the one writer is in or somebody is updating
75 * counter. For a writer, if he successfully acquires the wlock,
76 * but counter is non-zero, he has to release the lock and wait,
77 * till both counter and wlock are zero.
79 * Unfortunately this scheme limits us to ~16,000,000 cpus.
81 static inline void __read_lock(raw_rwlock_t
*rw
)
83 register raw_rwlock_t
*lp
asm("g1");
87 "call ___rw_read_enter\n\t"
88 " ldstub [%%g1 + 3], %%g2\n"
91 : "g2", "g4", "memory", "cc");
94 #define __raw_read_lock(lock) \
95 do { unsigned long flags; \
96 local_irq_save(flags); \
98 local_irq_restore(flags); \
101 static inline void __read_unlock(raw_rwlock_t
*rw
)
103 register raw_rwlock_t
*lp
asm("g1");
105 __asm__
__volatile__(
107 "call ___rw_read_exit\n\t"
108 " ldstub [%%g1 + 3], %%g2\n"
111 : "g2", "g4", "memory", "cc");
114 #define __raw_read_unlock(lock) \
115 do { unsigned long flags; \
116 local_irq_save(flags); \
117 __read_unlock(lock); \
118 local_irq_restore(flags); \
121 static inline void __raw_write_lock(raw_rwlock_t
*rw
)
123 register raw_rwlock_t
*lp
asm("g1");
125 __asm__
__volatile__(
127 "call ___rw_write_enter\n\t"
128 " ldstub [%%g1 + 3], %%g2\n"
131 : "g2", "g4", "memory", "cc");
132 *(volatile __u32
*)&lp
->lock
= ~0U;
135 static inline int __raw_write_trylock(raw_rwlock_t
*rw
)
139 __asm__
__volatile__("ldstub [%1 + 3], %0"
145 val
= rw
->lock
& ~0xff;
147 ((volatile u8
*)&rw
->lock
)[3] = 0;
149 *(volatile u32
*)&rw
->lock
= ~0U;
155 static inline int __read_trylock(raw_rwlock_t
*rw
)
157 register raw_rwlock_t
*lp
asm("g1");
158 register int res
asm("o0");
160 __asm__
__volatile__(
162 "call ___rw_read_try\n\t"
163 " ldstub [%%g1 + 3], %%g2\n"
166 : "g2", "g4", "memory", "cc");
170 #define __raw_read_trylock(lock) \
171 ({ unsigned long flags; \
173 local_irq_save(flags); \
174 res = __read_trylock(lock); \
175 local_irq_restore(flags); \
179 #define __raw_write_unlock(rw) do { (rw)->lock = 0; } while(0)
181 #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
183 #define _raw_spin_relax(lock) cpu_relax()
184 #define _raw_read_relax(lock) cpu_relax()
185 #define _raw_write_relax(lock) cpu_relax()
187 #define __raw_read_can_lock(rw) (!((rw)->lock & 0xff))
188 #define __raw_write_can_lock(rw) (!(rw)->lock)
190 #endif /* !(__ASSEMBLY__) */
192 #endif /* __SPARC_SPINLOCK_H */