| blob | 5a1aa0b55044426d2391d47e4105e362a24924c6 |
1 /* bnx2x_reg.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2008 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * The registers description starts with the regsister Access type followed
10 * by size in bits. For example [RW 32]. The access types are:
11 * R - Read only
12 * RC - Clear on read
13 * RW - Read/Write
14 * ST - Statistics register (clear on read)
15 * W - Write only
16 * WB - Wide bus register - the size is over 32 bits and it should be
17 * read/write in consecutive 32 bits accesses
18 * WR - Write Clear (write 1 to clear the bit)
19 *
20 */
23 /* [R 19] Interrupt register #0 read */
24 #define BRB1_REG_BRB1_INT_STS 0x6011c
25 /* [RW 4] Parity mask register #0 read/write */
26 #define BRB1_REG_BRB1_PRTY_MASK 0x60138
27 /* [R 4] Parity register #0 read */
28 #define BRB1_REG_BRB1_PRTY_STS 0x6012c
29 /* [RW 10] At address BRB1_IND_FREE_LIST_PRS_CRDT initialize free head. At
30 address BRB1_IND_FREE_LIST_PRS_CRDT+1 initialize free tail. At address
31 BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. */
32 #define BRB1_REG_FREE_LIST_PRS_CRDT 0x60200
33 /* [RW 23] LL RAM data. */
34 #define BRB1_REG_LL_RAM 0x61000
35 /* [R 24] The number of full blocks. */
36 #define BRB1_REG_NUM_OF_FULL_BLOCKS 0x60090
37 /* [ST 32] The number of cycles that the write_full signal towards MAC #0
38 was asserted. */
39 #define BRB1_REG_NUM_OF_FULL_CYCLES_0 0x600c8
40 #define BRB1_REG_NUM_OF_FULL_CYCLES_1 0x600cc
41 #define BRB1_REG_NUM_OF_FULL_CYCLES_2 0x600d0
42 #define BRB1_REG_NUM_OF_FULL_CYCLES_3 0x600d4
43 #define BRB1_REG_NUM_OF_FULL_CYCLES_4 0x600d8
44 /* [ST 32] The number of cycles that the pause signal towards MAC #0 was
45 asserted. */
46 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_0 0x600b8
47 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_1 0x600bc
48 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_2 0x600c0
49 #define BRB1_REG_NUM_OF_PAUSE_CYCLES_3 0x600c4
50 /* [RW 10] Write client 0: De-assert pause threshold. */
51 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_0 0x60078
52 #define BRB1_REG_PAUSE_HIGH_THRESHOLD_1 0x6007c
53 /* [RW 10] Write client 0: Assert pause threshold. */
54 #define BRB1_REG_PAUSE_LOW_THRESHOLD_0 0x60068
55 #define BRB1_REG_PAUSE_LOW_THRESHOLD_1 0x6006c
56 /* [RW 1] Reset the design by software. */
57 #define BRB1_REG_SOFT_RESET 0x600dc
58 /* [R 5] Used to read the value of the XX protection CAM occupancy counter. */
59 #define CCM_REG_CAM_OCCUP 0xd0188
60 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
61 acknowledge output is deasserted; all other signals are treated as usual;
62 if 1 - normal activity. */
63 #define CCM_REG_CCM_CFC_IFEN 0xd003c
64 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
65 disregarded; valid is deasserted; all other signals are treated as usual;
66 if 1 - normal activity. */
67 #define CCM_REG_CCM_CQM_IFEN 0xd000c
68 /* [RW 1] If set the Q index; received from the QM is inserted to event ID.
69 Otherwise 0 is inserted. */
70 #define CCM_REG_CCM_CQM_USE_Q 0xd00c0
71 /* [RW 11] Interrupt mask register #0 read/write */
72 #define CCM_REG_CCM_INT_MASK 0xd01e4
73 /* [R 11] Interrupt register #0 read */
74 #define CCM_REG_CCM_INT_STS 0xd01d8
75 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
76 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
77 Is used to determine the number of the AG context REG-pairs written back;
78 when the input message Reg1WbFlg isn't set. */
79 #define CCM_REG_CCM_REG0_SZ 0xd00c4
80 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
81 disregarded; valid is deasserted; all other signals are treated as usual;
82 if 1 - normal activity. */
83 #define CCM_REG_CCM_STORM0_IFEN 0xd0004
84 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
85 disregarded; valid is deasserted; all other signals are treated as usual;
86 if 1 - normal activity. */
87 #define CCM_REG_CCM_STORM1_IFEN 0xd0008
88 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
89 disregarded; valid output is deasserted; all other signals are treated as
90 usual; if 1 - normal activity. */
91 #define CCM_REG_CDU_AG_RD_IFEN 0xd0030
92 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
93 are disregarded; all other signals are treated as usual; if 1 - normal
94 activity. */
95 #define CCM_REG_CDU_AG_WR_IFEN 0xd002c
96 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
97 disregarded; valid output is deasserted; all other signals are treated as
98 usual; if 1 - normal activity. */
99 #define CCM_REG_CDU_SM_RD_IFEN 0xd0038
100 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
101 input is disregarded; all other signals are treated as usual; if 1 -
102 normal activity. */
103 #define CCM_REG_CDU_SM_WR_IFEN 0xd0034
104 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
105 the initial credit value; read returns the current value of the credit
106 counter. Must be initialized to 1 at start-up. */
107 #define CCM_REG_CFC_INIT_CRD 0xd0204
108 /* [RW 2] Auxillary counter flag Q number 1. */
109 #define CCM_REG_CNT_AUX1_Q 0xd00c8
110 /* [RW 2] Auxillary counter flag Q number 2. */
111 #define CCM_REG_CNT_AUX2_Q 0xd00cc
112 /* [RW 28] The CM header value for QM request (primary). */
113 #define CCM_REG_CQM_CCM_HDR_P 0xd008c
114 /* [RW 28] The CM header value for QM request (secondary). */
115 #define CCM_REG_CQM_CCM_HDR_S 0xd0090
116 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
117 acknowledge output is deasserted; all other signals are treated as usual;
118 if 1 - normal activity. */
119 #define CCM_REG_CQM_CCM_IFEN 0xd0014
120 /* [RW 6] QM output initial credit. Max credit available - 32. Write writes
121 the initial credit value; read returns the current value of the credit
122 counter. Must be initialized to 32 at start-up. */
123 #define CCM_REG_CQM_INIT_CRD 0xd020c
124 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
125 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
126 prioritised); 2 stands for weight 2; tc. */
127 #define CCM_REG_CQM_P_WEIGHT 0xd00b8
128 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
129 acknowledge output is deasserted; all other signals are treated as usual;
130 if 1 - normal activity. */
131 #define CCM_REG_CSDM_IFEN 0xd0018
132 /* [RC 1] Set when the message length mismatch (relative to last indication)
133 at the SDM interface is detected. */
134 #define CCM_REG_CSDM_LENGTH_MIS 0xd0170
135 /* [RW 28] The CM header for QM formatting in case of an error in the QM
136 inputs. */
137 #define CCM_REG_ERR_CCM_HDR 0xd0094
138 /* [RW 8] The Event ID in case the input message ErrorFlg is set. */
139 #define CCM_REG_ERR_EVNT_ID 0xd0098
140 /* [RW 8] FIC0 output initial credit. Max credit available - 255. Write
141 writes the initial credit value; read returns the current value of the
142 credit counter. Must be initialized to 64 at start-up. */
143 #define CCM_REG_FIC0_INIT_CRD 0xd0210
144 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
145 writes the initial credit value; read returns the current value of the
146 credit counter. Must be initialized to 64 at start-up. */
147 #define CCM_REG_FIC1_INIT_CRD 0xd0214
148 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
149 - strict priority defined by ~ccm_registers_gr_ag_pr.gr_ag_pr;
150 ~ccm_registers_gr_ld0_pr.gr_ld0_pr and
151 ~ccm_registers_gr_ld1_pr.gr_ld1_pr. Groups are according to channels and
152 outputs to STORM: aggregation; load FIC0; load FIC1 and store. */
153 #define CCM_REG_GR_ARB_TYPE 0xd015c
154 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
155 highest priority is 3. It is supposed; that the Store channel priority is
156 the compliment to 4 of the rest priorities - Aggregation channel; Load
157 (FIC0) channel and Load (FIC1). */
158 #define CCM_REG_GR_LD0_PR 0xd0164
159 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
160 highest priority is 3. It is supposed; that the Store channel priority is
161 the compliment to 4 of the rest priorities - Aggregation channel; Load
162 (FIC0) channel and Load (FIC1). */
163 #define CCM_REG_GR_LD1_PR 0xd0168
164 /* [RW 2] General flags index. */
165 #define CCM_REG_INV_DONE_Q 0xd0108
166 /* [RW 4] The number of double REG-pairs(128 bits); loaded from the STORM
167 context and sent to STORM; for a specific connection type. The double
168 REG-pairs are used in order to align to STORM context row size of 128
169 bits. The offset of these data in the STORM context is always 0. Index
170 _(0..15) stands for the connection type (one of 16). */
171 #define CCM_REG_N_SM_CTX_LD_0 0xd004c
172 #define CCM_REG_N_SM_CTX_LD_1 0xd0050
173 #define CCM_REG_N_SM_CTX_LD_10 0xd0074
174 #define CCM_REG_N_SM_CTX_LD_11 0xd0078
175 #define CCM_REG_N_SM_CTX_LD_12 0xd007c
176 #define CCM_REG_N_SM_CTX_LD_13 0xd0080
177 #define CCM_REG_N_SM_CTX_LD_14 0xd0084
178 #define CCM_REG_N_SM_CTX_LD_15 0xd0088
179 #define CCM_REG_N_SM_CTX_LD_2 0xd0054
180 #define CCM_REG_N_SM_CTX_LD_3 0xd0058
181 #define CCM_REG_N_SM_CTX_LD_4 0xd005c
182 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
183 acknowledge output is deasserted; all other signals are treated as usual;
184 if 1 - normal activity. */
185 #define CCM_REG_PBF_IFEN 0xd0028
186 /* [RC 1] Set when the message length mismatch (relative to last indication)
187 at the pbf interface is detected. */
188 #define CCM_REG_PBF_LENGTH_MIS 0xd0180
189 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
190 weight 8 (the most prioritised); 1 stands for weight 1(least
191 prioritised); 2 stands for weight 2; tc. */
192 #define CCM_REG_PBF_WEIGHT 0xd00ac
193 /* [RW 6] The physical queue number of queue number 1 per port index. */
194 #define CCM_REG_PHYS_QNUM1_0 0xd0134
195 #define CCM_REG_PHYS_QNUM1_1 0xd0138
196 /* [RW 6] The physical queue number of queue number 2 per port index. */
197 #define CCM_REG_PHYS_QNUM2_0 0xd013c
198 #define CCM_REG_PHYS_QNUM2_1 0xd0140
199 /* [RW 6] The physical queue number of queue number 3 per port index. */
200 #define CCM_REG_PHYS_QNUM3_0 0xd0144
201 /* [RW 6] The physical queue number of queue number 0 with QOS equal 0 port
202 index 0. */
203 #define CCM_REG_QOS_PHYS_QNUM0_0 0xd0114
204 #define CCM_REG_QOS_PHYS_QNUM0_1 0xd0118
205 /* [RW 6] The physical queue number of queue number 0 with QOS equal 1 port
206 index 0. */
207 #define CCM_REG_QOS_PHYS_QNUM1_0 0xd011c
208 #define CCM_REG_QOS_PHYS_QNUM1_1 0xd0120
209 /* [RW 6] The physical queue number of queue number 0 with QOS equal 2 port
210 index 0. */
211 #define CCM_REG_QOS_PHYS_QNUM2_0 0xd0124
212 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
213 disregarded; acknowledge output is deasserted; all other signals are
214 treated as usual; if 1 - normal activity. */
215 #define CCM_REG_STORM_CCM_IFEN 0xd0010
216 /* [RC 1] Set when the message length mismatch (relative to last indication)
217 at the STORM interface is detected. */
218 #define CCM_REG_STORM_LENGTH_MIS 0xd016c
219 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
220 disregarded; acknowledge output is deasserted; all other signals are
221 treated as usual; if 1 - normal activity. */
222 #define CCM_REG_TSEM_IFEN 0xd001c
223 /* [RC 1] Set when the message length mismatch (relative to last indication)
224 at the tsem interface is detected. */
225 #define CCM_REG_TSEM_LENGTH_MIS 0xd0174
226 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
227 weight 8 (the most prioritised); 1 stands for weight 1(least
228 prioritised); 2 stands for weight 2; tc. */
229 #define CCM_REG_TSEM_WEIGHT 0xd00a0
230 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
231 disregarded; acknowledge output is deasserted; all other signals are
232 treated as usual; if 1 - normal activity. */
233 #define CCM_REG_USEM_IFEN 0xd0024
234 /* [RC 1] Set when message length mismatch (relative to last indication) at
235 the usem interface is detected. */
236 #define CCM_REG_USEM_LENGTH_MIS 0xd017c
237 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
238 weight 8 (the most prioritised); 1 stands for weight 1(least
239 prioritised); 2 stands for weight 2; tc. */
240 #define CCM_REG_USEM_WEIGHT 0xd00a8
241 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
242 disregarded; acknowledge output is deasserted; all other signals are
243 treated as usual; if 1 - normal activity. */
244 #define CCM_REG_XSEM_IFEN 0xd0020
245 /* [RC 1] Set when the message length mismatch (relative to last indication)
246 at the xsem interface is detected. */
247 #define CCM_REG_XSEM_LENGTH_MIS 0xd0178
248 /* [RW 3] The weight of the input xsem in the WRR mechanism. 0 stands for
249 weight 8 (the most prioritised); 1 stands for weight 1(least
250 prioritised); 2 stands for weight 2; tc. */
251 #define CCM_REG_XSEM_WEIGHT 0xd00a4
252 /* [RW 19] Indirect access to the descriptor table of the XX protection
253 mechanism. The fields are: [5:0] - message length; [12:6] - message
254 pointer; 18:13] - next pointer. */
255 #define CCM_REG_XX_DESCR_TABLE 0xd0300
256 /* [R 7] Used to read the value of XX protection Free counter. */
257 #define CCM_REG_XX_FREE 0xd0184
258 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
259 of the Input Stage XX protection buffer by the XX protection pending
260 messages. Max credit available - 127. Write writes the initial credit
261 value; read returns the current value of the credit counter. Must be
262 initialized to maximum XX protected message size - 2 at start-up. */
263 #define CCM_REG_XX_INIT_CRD 0xd0220
264 /* [RW 7] The maximum number of pending messages; which may be stored in XX
265 protection. At read the ~ccm_registers_xx_free.xx_free counter is read.
266 At write comprises the start value of the ~ccm_registers_xx_free.xx_free
267 counter. */
268 #define CCM_REG_XX_MSG_NUM 0xd0224
269 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
270 #define CCM_REG_XX_OVFL_EVNT_ID 0xd0044
271 /* [RW 18] Indirect access to the XX table of the XX protection mechanism.
272 The fields are: [5:0] - tail pointer; 11:6] - Link List size; 17:12] -
273 header pointer. */
274 #define CCM_REG_XX_TABLE 0xd0280
275 #define CDU_REG_CDU_CHK_MASK0 0x101000
276 #define CDU_REG_CDU_CHK_MASK1 0x101004
277 #define CDU_REG_CDU_CONTROL0 0x101008
278 #define CDU_REG_CDU_DEBUG 0x101010
279 #define CDU_REG_CDU_GLOBAL_PARAMS 0x101020
280 /* [RW 7] Interrupt mask register #0 read/write */
281 #define CDU_REG_CDU_INT_MASK 0x10103c
282 /* [R 7] Interrupt register #0 read */
283 #define CDU_REG_CDU_INT_STS 0x101030
284 /* [RW 5] Parity mask register #0 read/write */
285 #define CDU_REG_CDU_PRTY_MASK 0x10104c
286 /* [R 5] Parity register #0 read */
287 #define CDU_REG_CDU_PRTY_STS 0x101040
288 /* [RC 32] logging of error data in case of a CDU load error:
289 {expected_cid[15:0]; xpected_type[2:0]; xpected_region[2:0]; ctive_error;
290 ype_error; ctual_active; ctual_compressed_context}; */
291 #define CDU_REG_ERROR_DATA 0x101014
292 /* [WB 216] L1TT ram access. each entry has the following format :
293 {mrege_regions[7:0]; ffset12[5:0]...offset0[5:0];
294 ength12[5:0]...length0[5:0]; d12[3:0]...id0[3:0]} */
295 #define CDU_REG_L1TT 0x101800
296 /* [WB 24] MATT ram access. each entry has the following
297 format:{RegionLength[11:0]; egionOffset[11:0]} */
298 #define CDU_REG_MATT 0x101100
299 /* [R 1] indication the initializing the activity counter by the hardware
300 was done. */
301 #define CFC_REG_AC_INIT_DONE 0x104078
302 /* [RW 13] activity counter ram access */
303 #define CFC_REG_ACTIVITY_COUNTER 0x104400
304 #define CFC_REG_ACTIVITY_COUNTER_SIZE 256
305 /* [R 1] indication the initializing the cams by the hardware was done. */
306 #define CFC_REG_CAM_INIT_DONE 0x10407c
307 /* [RW 2] Interrupt mask register #0 read/write */
308 #define CFC_REG_CFC_INT_MASK 0x104108
309 /* [R 2] Interrupt register #0 read */
310 #define CFC_REG_CFC_INT_STS 0x1040fc
311 /* [RC 2] Interrupt register #0 read clear */
312 #define CFC_REG_CFC_INT_STS_CLR 0x104100
313 /* [RW 4] Parity mask register #0 read/write */
314 #define CFC_REG_CFC_PRTY_MASK 0x104118
315 /* [R 4] Parity register #0 read */
316 #define CFC_REG_CFC_PRTY_STS 0x10410c
317 /* [RW 21] CID cam access (21:1 - Data; alid - 0) */
318 #define CFC_REG_CID_CAM 0x104800
319 #define CFC_REG_CONTROL0 0x104028
320 #define CFC_REG_DEBUG0 0x104050
321 /* [RW 14] indicates per error (in #cfc_registers_cfc_error_vector.cfc_error
322 vector) whether the cfc should be disabled upon it */
323 #define CFC_REG_DISABLE_ON_ERROR 0x104044
324 /* [RC 14] CFC error vector. when the CFC detects an internal error it will
325 set one of these bits. the bit description can be found in CFC
326 specifications */
327 #define CFC_REG_ERROR_VECTOR 0x10403c
328 #define CFC_REG_INIT_REG 0x10404c
329 /* [RW 24] {weight_load_client7[2:0] to weight_load_client0[2:0]}. this
330 field allows changing the priorities of the weighted-round-robin arbiter
331 which selects which CFC load client should be served next */
332 #define CFC_REG_LCREQ_WEIGHTS 0x104084
333 /* [R 1] indication the initializing the link list by the hardware was done. */
334 #define CFC_REG_LL_INIT_DONE 0x104074
335 /* [R 9] Number of allocated LCIDs which are at empty state */
336 #define CFC_REG_NUM_LCIDS_ALLOC 0x104020
337 /* [R 9] Number of Arriving LCIDs in Link List Block */
338 #define CFC_REG_NUM_LCIDS_ARRIVING 0x104004
339 /* [R 9] Number of Inside LCIDs in Link List Block */
340 #define CFC_REG_NUM_LCIDS_INSIDE 0x104008
341 /* [R 9] Number of Leaving LCIDs in Link List Block */
342 #define CFC_REG_NUM_LCIDS_LEAVING 0x104018
343 /* [RW 8] The event id for aggregated interrupt 0 */
344 #define CSDM_REG_AGG_INT_EVENT_0 0xc2038
345 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
346 #define CSDM_REG_CFC_RSP_START_ADDR 0xc2008
347 /* [RW 16] The maximum value of the competion counter #0 */
348 #define CSDM_REG_CMP_COUNTER_MAX0 0xc201c
349 /* [RW 16] The maximum value of the competion counter #1 */
350 #define CSDM_REG_CMP_COUNTER_MAX1 0xc2020
351 /* [RW 16] The maximum value of the competion counter #2 */
352 #define CSDM_REG_CMP_COUNTER_MAX2 0xc2024
353 /* [RW 16] The maximum value of the competion counter #3 */
354 #define CSDM_REG_CMP_COUNTER_MAX3 0xc2028
355 /* [RW 13] The start address in the internal RAM for the completion
356 counters. */
357 #define CSDM_REG_CMP_COUNTER_START_ADDR 0xc200c
358 /* [RW 32] Interrupt mask register #0 read/write */
359 #define CSDM_REG_CSDM_INT_MASK_0 0xc229c
360 #define CSDM_REG_CSDM_INT_MASK_1 0xc22ac
361 /* [RW 11] Parity mask register #0 read/write */
362 #define CSDM_REG_CSDM_PRTY_MASK 0xc22bc
363 /* [R 11] Parity register #0 read */
364 #define CSDM_REG_CSDM_PRTY_STS 0xc22b0
365 #define CSDM_REG_ENABLE_IN1 0xc2238
366 #define CSDM_REG_ENABLE_IN2 0xc223c
367 #define CSDM_REG_ENABLE_OUT1 0xc2240
368 #define CSDM_REG_ENABLE_OUT2 0xc2244
369 /* [RW 4] The initial number of messages that can be sent to the pxp control
370 interface without receiving any ACK. */
371 #define CSDM_REG_INIT_CREDIT_PXP_CTRL 0xc24bc
372 /* [ST 32] The number of ACK after placement messages received */
373 #define CSDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc227c
374 /* [ST 32] The number of packet end messages received from the parser */
375 #define CSDM_REG_NUM_OF_PKT_END_MSG 0xc2274
376 /* [ST 32] The number of requests received from the pxp async if */
377 #define CSDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc2278
378 /* [ST 32] The number of commands received in queue 0 */
379 #define CSDM_REG_NUM_OF_Q0_CMD 0xc2248
380 /* [ST 32] The number of commands received in queue 10 */
381 #define CSDM_REG_NUM_OF_Q10_CMD 0xc226c
382 /* [ST 32] The number of commands received in queue 11 */
383 #define CSDM_REG_NUM_OF_Q11_CMD 0xc2270
384 /* [ST 32] The number of commands received in queue 1 */
385 #define CSDM_REG_NUM_OF_Q1_CMD 0xc224c
386 /* [ST 32] The number of commands received in queue 3 */
387 #define CSDM_REG_NUM_OF_Q3_CMD 0xc2250
388 /* [ST 32] The number of commands received in queue 4 */
389 #define CSDM_REG_NUM_OF_Q4_CMD 0xc2254
390 /* [ST 32] The number of commands received in queue 5 */
391 #define CSDM_REG_NUM_OF_Q5_CMD 0xc2258
392 /* [ST 32] The number of commands received in queue 6 */
393 #define CSDM_REG_NUM_OF_Q6_CMD 0xc225c
394 /* [ST 32] The number of commands received in queue 7 */
395 #define CSDM_REG_NUM_OF_Q7_CMD 0xc2260
396 /* [ST 32] The number of commands received in queue 8 */
397 #define CSDM_REG_NUM_OF_Q8_CMD 0xc2264
398 /* [ST 32] The number of commands received in queue 9 */
399 #define CSDM_REG_NUM_OF_Q9_CMD 0xc2268
400 /* [RW 13] The start address in the internal RAM for queue counters */
401 #define CSDM_REG_Q_COUNTER_START_ADDR 0xc2010
402 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
403 #define CSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc2548
404 /* [R 1] parser fifo empty in sdm_sync block */
405 #define CSDM_REG_SYNC_PARSER_EMPTY 0xc2550
406 /* [R 1] parser serial fifo empty in sdm_sync block */
407 #define CSDM_REG_SYNC_SYNC_EMPTY 0xc2558
408 /* [RW 32] Tick for timer counter. Applicable only when
409 ~csdm_registers_timer_tick_enable.timer_tick_enable =1 */
410 #define CSDM_REG_TIMER_TICK 0xc2000
411 /* [RW 5] The number of time_slots in the arbitration cycle */
412 #define CSEM_REG_ARB_CYCLE_SIZE 0x200034
413 /* [RW 3] The source that is associated with arbitration element 0. Source
414 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
415 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
416 #define CSEM_REG_ARB_ELEMENT0 0x200020
417 /* [RW 3] The source that is associated with arbitration element 1. Source
418 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
419 sleeping thread with priority 1; 4- sleeping thread with priority 2.
420 Could not be equal to register ~csem_registers_arb_element0.arb_element0 */
421 #define CSEM_REG_ARB_ELEMENT1 0x200024
422 /* [RW 3] The source that is associated with arbitration element 2. Source
423 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
424 sleeping thread with priority 1; 4- sleeping thread with priority 2.
425 Could not be equal to register ~csem_registers_arb_element0.arb_element0
426 and ~csem_registers_arb_element1.arb_element1 */
427 #define CSEM_REG_ARB_ELEMENT2 0x200028
428 /* [RW 3] The source that is associated with arbitration element 3. Source
429 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
430 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
431 not be equal to register ~csem_registers_arb_element0.arb_element0 and
432 ~csem_registers_arb_element1.arb_element1 and
433 ~csem_registers_arb_element2.arb_element2 */
434 #define CSEM_REG_ARB_ELEMENT3 0x20002c
435 /* [RW 3] The source that is associated with arbitration element 4. Source
436 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
437 sleeping thread with priority 1; 4- sleeping thread with priority 2.
438 Could not be equal to register ~csem_registers_arb_element0.arb_element0
439 and ~csem_registers_arb_element1.arb_element1 and
440 ~csem_registers_arb_element2.arb_element2 and
441 ~csem_registers_arb_element3.arb_element3 */
442 #define CSEM_REG_ARB_ELEMENT4 0x200030
443 /* [RW 32] Interrupt mask register #0 read/write */
444 #define CSEM_REG_CSEM_INT_MASK_0 0x200110
445 #define CSEM_REG_CSEM_INT_MASK_1 0x200120
446 /* [RW 32] Parity mask register #0 read/write */
447 #define CSEM_REG_CSEM_PRTY_MASK_0 0x200130
448 #define CSEM_REG_CSEM_PRTY_MASK_1 0x200140
449 /* [R 32] Parity register #0 read */
450 #define CSEM_REG_CSEM_PRTY_STS_0 0x200124
451 #define CSEM_REG_CSEM_PRTY_STS_1 0x200134
452 #define CSEM_REG_ENABLE_IN 0x2000a4
453 #define CSEM_REG_ENABLE_OUT 0x2000a8
454 /* [RW 32] This address space contains all registers and memories that are
455 placed in SEM_FAST block. The SEM_FAST registers are described in
456 appendix B. In order to access the SEM_FAST registers the base address
457 CSEM_REGISTERS_FAST_MEMORY (Offset: 0x220000) should be added to each
458 SEM_FAST register offset. */
459 #define CSEM_REG_FAST_MEMORY 0x220000
460 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
461 by the microcode */
462 #define CSEM_REG_FIC0_DISABLE 0x200224
463 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
464 by the microcode */
465 #define CSEM_REG_FIC1_DISABLE 0x200234
466 /* [RW 15] Interrupt table Read and write access to it is not possible in
467 the middle of the work */
468 #define CSEM_REG_INT_TABLE 0x200400
469 /* [ST 24] Statistics register. The number of messages that entered through
470 FIC0 */
471 #define CSEM_REG_MSG_NUM_FIC0 0x200000
472 /* [ST 24] Statistics register. The number of messages that entered through
473 FIC1 */
474 #define CSEM_REG_MSG_NUM_FIC1 0x200004
475 /* [ST 24] Statistics register. The number of messages that were sent to
476 FOC0 */
477 #define CSEM_REG_MSG_NUM_FOC0 0x200008
478 /* [ST 24] Statistics register. The number of messages that were sent to
479 FOC1 */
480 #define CSEM_REG_MSG_NUM_FOC1 0x20000c
481 /* [ST 24] Statistics register. The number of messages that were sent to
482 FOC2 */
483 #define CSEM_REG_MSG_NUM_FOC2 0x200010
484 /* [ST 24] Statistics register. The number of messages that were sent to
485 FOC3 */
486 #define CSEM_REG_MSG_NUM_FOC3 0x200014
487 /* [RW 1] Disables input messages from the passive buffer May be updated
488 during run_time by the microcode */
489 #define CSEM_REG_PAS_DISABLE 0x20024c
490 /* [WB 128] Debug only. Passive buffer memory */
491 #define CSEM_REG_PASSIVE_BUFFER 0x202000
492 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
493 #define CSEM_REG_PRAM 0x240000
494 /* [R 16] Valid sleeping threads indication have bit per thread */
495 #define CSEM_REG_SLEEP_THREADS_VALID 0x20026c
496 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
497 #define CSEM_REG_SLOW_EXT_STORE_EMPTY 0x2002a0
498 /* [RW 16] List of free threads . There is a bit per thread. */
499 #define CSEM_REG_THREADS_LIST 0x2002e4
500 /* [RW 3] The arbitration scheme of time_slot 0 */
501 #define CSEM_REG_TS_0_AS 0x200038
502 /* [RW 3] The arbitration scheme of time_slot 10 */
503 #define CSEM_REG_TS_10_AS 0x200060
504 /* [RW 3] The arbitration scheme of time_slot 11 */
505 #define CSEM_REG_TS_11_AS 0x200064
506 /* [RW 3] The arbitration scheme of time_slot 12 */
507 #define CSEM_REG_TS_12_AS 0x200068
508 /* [RW 3] The arbitration scheme of time_slot 13 */
509 #define CSEM_REG_TS_13_AS 0x20006c
510 /* [RW 3] The arbitration scheme of time_slot 14 */
511 #define CSEM_REG_TS_14_AS 0x200070
512 /* [RW 3] The arbitration scheme of time_slot 15 */
513 #define CSEM_REG_TS_15_AS 0x200074
514 /* [RW 3] The arbitration scheme of time_slot 16 */
515 #define CSEM_REG_TS_16_AS 0x200078
516 /* [RW 3] The arbitration scheme of time_slot 17 */
517 #define CSEM_REG_TS_17_AS 0x20007c
518 /* [RW 3] The arbitration scheme of time_slot 18 */
519 #define CSEM_REG_TS_18_AS 0x200080
520 /* [RW 3] The arbitration scheme of time_slot 1 */
521 #define CSEM_REG_TS_1_AS 0x20003c
522 /* [RW 3] The arbitration scheme of time_slot 2 */
523 #define CSEM_REG_TS_2_AS 0x200040
524 /* [RW 3] The arbitration scheme of time_slot 3 */
525 #define CSEM_REG_TS_3_AS 0x200044
526 /* [RW 3] The arbitration scheme of time_slot 4 */
527 #define CSEM_REG_TS_4_AS 0x200048
528 /* [RW 3] The arbitration scheme of time_slot 5 */
529 #define CSEM_REG_TS_5_AS 0x20004c
530 /* [RW 3] The arbitration scheme of time_slot 6 */
531 #define CSEM_REG_TS_6_AS 0x200050
532 /* [RW 3] The arbitration scheme of time_slot 7 */
533 #define CSEM_REG_TS_7_AS 0x200054
534 /* [RW 3] The arbitration scheme of time_slot 8 */
535 #define CSEM_REG_TS_8_AS 0x200058
536 /* [RW 3] The arbitration scheme of time_slot 9 */
537 #define CSEM_REG_TS_9_AS 0x20005c
538 /* [RW 1] Parity mask register #0 read/write */
539 #define DBG_REG_DBG_PRTY_MASK 0xc0a8
540 /* [R 1] Parity register #0 read */
541 #define DBG_REG_DBG_PRTY_STS 0xc09c
542 /* [RW 2] debug only: These bits indicate the credit for PCI request type 4
543 interface; MUST be configured AFTER pci_ext_buffer_strt_addr_lsb/msb are
544 configured */
545 #define DBG_REG_PCI_REQ_CREDIT 0xc120
546 /* [RW 32] Commands memory. The address to command X; row Y is to calculated
547 as 14*X+Y. */
548 #define DMAE_REG_CMD_MEM 0x102400
549 /* [RW 1] If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c
550 initial value is all ones. */
551 #define DMAE_REG_CRC16C_INIT 0x10201c
552 /* [RW 1] If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the
553 CRC-16 T10 initial value is all ones. */
554 #define DMAE_REG_CRC16T10_INIT 0x102020
555 /* [RW 2] Interrupt mask register #0 read/write */
556 #define DMAE_REG_DMAE_INT_MASK 0x102054
557 /* [RW 4] Parity mask register #0 read/write */
558 #define DMAE_REG_DMAE_PRTY_MASK 0x102064
559 /* [R 4] Parity register #0 read */
560 #define DMAE_REG_DMAE_PRTY_STS 0x102058
561 /* [RW 1] Command 0 go. */
562 #define DMAE_REG_GO_C0 0x102080
563 /* [RW 1] Command 1 go. */
564 #define DMAE_REG_GO_C1 0x102084
565 /* [RW 1] Command 10 go. */
566 #define DMAE_REG_GO_C10 0x102088
567 #define DMAE_REG_GO_C10_SIZE 1
568 /* [RW 1] Command 11 go. */
569 #define DMAE_REG_GO_C11 0x10208c
570 #define DMAE_REG_GO_C11_SIZE 1
571 /* [RW 1] Command 12 go. */
572 #define DMAE_REG_GO_C12 0x102090
573 #define DMAE_REG_GO_C12_SIZE 1
574 /* [RW 1] Command 13 go. */
575 #define DMAE_REG_GO_C13 0x102094
576 #define DMAE_REG_GO_C13_SIZE 1
577 /* [RW 1] Command 14 go. */
578 #define DMAE_REG_GO_C14 0x102098
579 #define DMAE_REG_GO_C14_SIZE 1
580 /* [RW 1] Command 15 go. */
581 #define DMAE_REG_GO_C15 0x10209c
582 #define DMAE_REG_GO_C15_SIZE 1
583 /* [RW 1] Command 10 go. */
584 #define DMAE_REG_GO_C10 0x102088
585 /* [RW 1] Command 11 go. */
586 #define DMAE_REG_GO_C11 0x10208c
587 /* [RW 1] Command 12 go. */
588 #define DMAE_REG_GO_C12 0x102090
589 /* [RW 1] Command 13 go. */
590 #define DMAE_REG_GO_C13 0x102094
591 /* [RW 1] Command 14 go. */
592 #define DMAE_REG_GO_C14 0x102098
593 /* [RW 1] Command 15 go. */
594 #define DMAE_REG_GO_C15 0x10209c
595 /* [RW 1] Command 2 go. */
596 #define DMAE_REG_GO_C2 0x1020a0
597 /* [RW 1] Command 3 go. */
598 #define DMAE_REG_GO_C3 0x1020a4
599 /* [RW 1] Command 4 go. */
600 #define DMAE_REG_GO_C4 0x1020a8
601 /* [RW 1] Command 5 go. */
602 #define DMAE_REG_GO_C5 0x1020ac
603 /* [RW 1] Command 6 go. */
604 #define DMAE_REG_GO_C6 0x1020b0
605 /* [RW 1] Command 7 go. */
606 #define DMAE_REG_GO_C7 0x1020b4
607 /* [RW 1] Command 8 go. */
608 #define DMAE_REG_GO_C8 0x1020b8
609 /* [RW 1] Command 9 go. */
610 #define DMAE_REG_GO_C9 0x1020bc
611 /* [RW 1] DMAE GRC Interface (Target; aster) enable. If 0 - the acknowledge
612 input is disregarded; valid is deasserted; all other signals are treated
613 as usual; if 1 - normal activity. */
614 #define DMAE_REG_GRC_IFEN 0x102008
615 /* [RW 1] DMAE PCI Interface (Request; ead; rite) enable. If 0 - the
616 acknowledge input is disregarded; valid is deasserted; full is asserted;
617 all other signals are treated as usual; if 1 - normal activity. */
618 #define DMAE_REG_PCI_IFEN 0x102004
619 /* [RW 4] DMAE- PCI Request Interface initial credit. Write writes the
620 initial value to the credit counter; related to the address. Read returns
621 the current value of the counter. */
622 #define DMAE_REG_PXP_REQ_INIT_CRD 0x1020c0
623 /* [RW 8] Aggregation command. */
624 #define DORQ_REG_AGG_CMD0 0x170060
625 /* [RW 8] Aggregation command. */
626 #define DORQ_REG_AGG_CMD1 0x170064
627 /* [RW 8] Aggregation command. */
628 #define DORQ_REG_AGG_CMD2 0x170068
629 /* [RW 8] Aggregation command. */
630 #define DORQ_REG_AGG_CMD3 0x17006c
631 /* [RW 28] UCM Header. */
632 #define DORQ_REG_CMHEAD_RX 0x170050
633 /* [RW 5] Interrupt mask register #0 read/write */
634 #define DORQ_REG_DORQ_INT_MASK 0x170180
635 /* [R 5] Interrupt register #0 read */
636 #define DORQ_REG_DORQ_INT_STS 0x170174
637 /* [RC 5] Interrupt register #0 read clear */
638 #define DORQ_REG_DORQ_INT_STS_CLR 0x170178
639 /* [RW 2] Parity mask register #0 read/write */
640 #define DORQ_REG_DORQ_PRTY_MASK 0x170190
641 /* [R 2] Parity register #0 read */
642 #define DORQ_REG_DORQ_PRTY_STS 0x170184
643 /* [RW 8] The address to write the DPM CID to STORM. */
644 #define DORQ_REG_DPM_CID_ADDR 0x170044
645 /* [RW 5] The DPM mode CID extraction offset. */
646 #define DORQ_REG_DPM_CID_OFST 0x170030
647 /* [RW 12] The threshold of the DQ FIFO to send the almost full interrupt. */
648 #define DORQ_REG_DQ_FIFO_AFULL_TH 0x17007c
649 /* [RW 12] The threshold of the DQ FIFO to send the full interrupt. */
650 #define DORQ_REG_DQ_FIFO_FULL_TH 0x170078
651 /* [R 13] Current value of the DQ FIFO fill level according to following
652 pointer. The range is 0 - 256 FIFO rows; where each row stands for the
653 doorbell. */
654 #define DORQ_REG_DQ_FILL_LVLF 0x1700a4
655 /* [R 1] DQ FIFO full status. Is set; when FIFO filling level is more or
656 equal to full threshold; reset on full clear. */
657 #define DORQ_REG_DQ_FULL_ST 0x1700c0
658 /* [RW 28] The value sent to CM header in the case of CFC load error. */
659 #define DORQ_REG_ERR_CMHEAD 0x170058
660 #define DORQ_REG_IF_EN 0x170004
661 #define DORQ_REG_MODE_ACT 0x170008
662 /* [RW 5] The normal mode CID extraction offset. */
663 #define DORQ_REG_NORM_CID_OFST 0x17002c
664 /* [RW 28] TCM Header when only TCP context is loaded. */
665 #define DORQ_REG_NORM_CMHEAD_TX 0x17004c
666 /* [RW 3] The number of simultaneous outstanding requests to Context Fetch
667 Interface. */
668 #define DORQ_REG_OUTST_REQ 0x17003c
669 #define DORQ_REG_REGN 0x170038
670 /* [R 4] Current value of response A counter credit. Initial credit is
671 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
672 register. */
673 #define DORQ_REG_RSPA_CRD_CNT 0x1700ac
674 /* [R 4] Current value of response B counter credit. Initial credit is
675 configured through write to ~dorq_registers_rsp_init_crd.rsp_init_crd
676 register. */
677 #define DORQ_REG_RSPB_CRD_CNT 0x1700b0
678 /* [RW 4] The initial credit at the Doorbell Response Interface. The write
679 writes the same initial credit to the rspa_crd_cnt and rspb_crd_cnt. The
680 read reads this written value. */
681 #define DORQ_REG_RSP_INIT_CRD 0x170048
682 /* [RW 4] Initial activity counter value on the load request; when the
683 shortcut is done. */
684 #define DORQ_REG_SHRT_ACT_CNT 0x170070
685 /* [RW 28] TCM Header when both ULP and TCP context is loaded. */
686 #define DORQ_REG_SHRT_CMHEAD 0x170054
687 #define HC_CONFIG_0_REG_ATTN_BIT_EN_0 (0x1<<4)
688 #define HC_CONFIG_0_REG_INT_LINE_EN_0 (0x1<<3)
689 #define HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 (0x1<<2)
690 #define HC_CONFIG_0_REG_SINGLE_ISR_EN_0 (0x1<<1)
691 #define HC_REG_AGG_INT_0 0x108050
692 #define HC_REG_AGG_INT_1 0x108054
693 /* [RW 16] attention bit and attention acknowledge bits status for port 0
694 and 1 according to the following address map: addr 0 - attn_bit_0; addr 1
695 - attn_ack_bit_0; addr 2 - attn_bit_1; addr 3 - attn_ack_bit_1; */
696 #define HC_REG_ATTN_BIT 0x108120
697 /* [RW 16] attn bits status index for attn bit msg; addr 0 - function 0;
698 addr 1 - functin 1 */
699 #define HC_REG_ATTN_IDX 0x108100
700 /* [RW 32] port 0 lower 32 bits address field for attn messag. */
701 #define HC_REG_ATTN_MSG0_ADDR_L 0x108018
702 /* [RW 32] port 1 lower 32 bits address field for attn messag. */
703 #define HC_REG_ATTN_MSG1_ADDR_L 0x108020
704 /* [RW 8] status block number for attn bit msg - function 0; */
705 #define HC_REG_ATTN_NUM_P0 0x108038
706 /* [RW 8] status block number for attn bit msg - function 1 */
707 #define HC_REG_ATTN_NUM_P1 0x10803c
708 #define HC_REG_CONFIG_0 0x108000
709 #define HC_REG_CONFIG_1 0x108004
710 /* [RW 3] Parity mask register #0 read/write */
711 #define HC_REG_HC_PRTY_MASK 0x1080a0
712 /* [R 3] Parity register #0 read */
713 #define HC_REG_HC_PRTY_STS 0x108094
714 /* [RW 17] status block interrupt mask; one in each bit means unmask; zerow
715 in each bit means mask; bit 0 - default SB; bit 1 - SB_0; bit 2 - SB_1...
716 bit 16- SB_15; addr 0 - port 0; addr 1 - port 1 */
717 #define HC_REG_INT_MASK 0x108108
718 /* [RW 16] port 0 attn bit condition monitoring; each bit that is set will
719 lock a change fron 0 to 1 in the corresponding attention signals that
720 comes from the AEU */
721 #define HC_REG_LEADING_EDGE_0 0x108040
722 #define HC_REG_LEADING_EDGE_1 0x108048
723 /* [RW 16] all producer and consumer of port 0 according to the following
724 addresses; U_prod: 0-15; C_prod: 16-31; U_cons: 32-47; C_cons:48-63;
725 Defoult_prod: U/C/X/T/Attn-64/65/66/67/68; Defoult_cons:
726 U/C/X/T/Attn-69/70/71/72/73 */
727 #define HC_REG_P0_PROD_CONS 0x108200
728 /* [RW 16] all producer and consumer of port 1according to the following
729 addresses; U_prod: 0-15; C_prod: 16-31; U_cons: 32-47; C_cons:48-63;
730 Defoult_prod: U/C/X/T/Attn-64/65/66/67/68; Defoult_cons:
731 U/C/X/T/Attn-69/70/71/72/73 */
732 #define HC_REG_P1_PROD_CONS 0x108400
733 /* [W 1] This register is write only and has 4 addresses as follow: 0 =
734 clear all PBA bits port 0; 1 = clear all pending interrupts request
735 port0; 2 = clear all PBA bits port 1; 3 = clear all pending interrupts
736 request port1; here is no meaning for the data in this register */
737 #define HC_REG_PBA_COMMAND 0x108140
738 #define HC_REG_PCI_CONFIG_0 0x108010
739 #define HC_REG_PCI_CONFIG_1 0x108014
740 /* [RW 24] all counters acording to the following address: LSB: 0=read; 1=
741 read_clear; 0-71 = HW counters (the inside order is the same as the
742 interrupt table in the spec); 72-219 = SW counters 1 (stops after first
743 consumer upd) the inside order is: 72-103 - U_non_default_p0; 104-135
744 C_non_defaul_p0; 36-145 U/C/X/T/Attn_default_p0; 146-177
745 U_non_default_p1; 178-209 C_non_defaul_p1; 10-219 U/C/X/T/Attn_default_p1
746 ; 220-367 = SW counters 2 (stops when prod=cons) the inside order is:
747 220-251 - U_non_default_p0; 252-283 C_non_defaul_p0; 84-293
748 U/C/X/T/Attn_default_p0; 294-325 U_non_default_p1; 326-357
749 C_non_defaul_p1; 58-367 U/C/X/T/Attn_default_p1 ; 368-515 = mailbox
750 counters; (the inside order of the mailbox counter is 368-431 U and C
751 non_default_p0; 432-441 U/C/X/T/Attn_default_p0; 442-505 U and C
752 non_default_p1; 506-515 U/C/X/T/Attn_default_p1) */
753 #define HC_REG_STATISTIC_COUNTERS 0x109000
754 /* [RW 16] port 0 attn bit condition monitoring; each bit that is set will
755 lock a change fron 1 to 0 in the corresponding attention signals that
756 comes from the AEU */
757 #define HC_REG_TRAILING_EDGE_0 0x108044
758 #define HC_REG_TRAILING_EDGE_1 0x10804c
759 #define HC_REG_UC_RAM_ADDR_0 0x108028
760 #define HC_REG_UC_RAM_ADDR_1 0x108030
761 /* [RW 16] ustorm address for coalesc now message */
762 #define HC_REG_USTORM_ADDR_FOR_COALESCE 0x108068
763 #define HC_REG_VQID_0 0x108008
764 #define HC_REG_VQID_1 0x10800c
765 #define MCP_REG_MCPR_NVM_ACCESS_ENABLE 0x86424
766 #define MCP_REG_MCPR_NVM_ADDR 0x8640c
767 #define MCP_REG_MCPR_NVM_CFG4 0x8642c
768 #define MCP_REG_MCPR_NVM_COMMAND 0x86400
769 #define MCP_REG_MCPR_NVM_READ 0x86410
770 #define MCP_REG_MCPR_NVM_SW_ARB 0x86420
771 #define MCP_REG_MCPR_NVM_WRITE 0x86408
772 #define MCP_REG_MCPR_NVM_WRITE1 0x86428
773 #define MCP_REG_MCPR_SCRATCH 0xa0000
774 /* [R 32] read first 32 bit after inversion of function 0. mapped as
775 follows: [0] NIG attention for function0; [1] NIG attention for
776 function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp;
777 [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9]
778 GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE
779 glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0;
780 [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16]
781 MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB
782 Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw
783 interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity
784 error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] TCM Hw
785 interrupt; [28] TSEMI Parity error; [29] TSEMI Hw interrupt; [30] PBF
786 Parity error; [31] PBF Hw interrupt; */
787 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 0xa42c
788 #define MISC_REG_AEU_AFTER_INVERT_1_FUNC_1 0xa430
789 /* [R 32] read first 32 bit after inversion of mcp. mapped as follows: [0]
790 NIG attention for function0; [1] NIG attention for function1; [2] GPIO1
791 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1;
792 [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10]
793 PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event
794 function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP
795 Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for
796 mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19]
797 BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC
798 Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw
799 interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI
800 Parity error; [29] TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw
801 interrupt; */
802 #define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434
803 /* [R 32] read second 32 bit after inversion of function 0. mapped as
804 follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
805 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
806 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
807 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
808 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
809 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
810 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
811 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
812 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
813 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
814 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
815 interrupt; */
816 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 0xa438
817 #define MISC_REG_AEU_AFTER_INVERT_2_FUNC_1 0xa43c
818 /* [R 32] read second 32 bit after inversion of mcp. mapped as follows: [0]
819 PBClient Parity error; [1] PBClient Hw interrupt; [2] QM Parity error;
820 [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt;
821 [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9]
822 XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
823 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
824 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
825 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
826 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
827 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
828 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
829 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
830 #define MISC_REG_AEU_AFTER_INVERT_2_MCP 0xa440
831 /* [R 32] read third 32 bit after inversion of function 0. mapped as
832 follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity
833 error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5]
834 PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
835 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
836 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
837 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
838 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
839 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
840 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
841 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
842 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
843 attn1; */
844 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 0xa444
845 #define MISC_REG_AEU_AFTER_INVERT_3_FUNC_1 0xa448
846 /* [R 32] read third 32 bit after inversion of mcp. mapped as follows: [0]
847 CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP
848 Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient
849 Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity
850 error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw
851 interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14]
852 MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17]
853 Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW
854 timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3
855 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW timers attn_1
856 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3 func1; [29] SW
857 timers attn_4 func1; [30] General attn0; [31] General attn1; */
858 #define MISC_REG_AEU_AFTER_INVERT_3_MCP 0xa44c
859 /* [R 32] read fourth 32 bit after inversion of function 0. mapped as
860 follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
861 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
862 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
863 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
864 [14] General attn16; [15] General attn17; [16] General attn18; [17]
865 General attn19; [18] General attn20; [19] General attn21; [20] Main power
866 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
867 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
868 Latched timeout attention; [27] GRC Latched reserved access attention;
869 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
870 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
871 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 0xa450
872 #define MISC_REG_AEU_AFTER_INVERT_4_FUNC_1 0xa454
873 /* [R 32] read fourth 32 bit after inversion of mcp. mapped as follows: [0]
874 General attn2; [1] General attn3; [2] General attn4; [3] General attn5;
875 [4] General attn6; [5] General attn7; [6] General attn8; [7] General
876 attn9; [8] General attn10; [9] General attn11; [10] General attn12; [11]
877 General attn13; [12] General attn14; [13] General attn15; [14] General
878 attn16; [15] General attn17; [16] General attn18; [17] General attn19;
879 [18] General attn20; [19] General attn21; [20] Main power interrupt; [21]
880 RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN Latched attn; [24]
881 RBCU Latched attn; [25] RBCP Latched attn; [26] GRC Latched timeout
882 attention; [27] GRC Latched reserved access attention; [28] MCP Latched
883 rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP Latched
884 ump_tx_parity; [31] MCP Latched scpad_parity; */
885 #define MISC_REG_AEU_AFTER_INVERT_4_MCP 0xa458
886 /* [W 11] write to this register results with the clear of the latched
887 signals; one in d0 clears RBCR latch; one in d1 clears RBCT latch; one in
888 d2 clears RBCN latch; one in d3 clears RBCU latch; one in d4 clears RBCP
889 latch; one in d5 clears GRC Latched timeout attention; one in d6 clears
890 GRC Latched reserved access attention; one in d7 clears Latched
891 rom_parity; one in d8 clears Latched ump_rx_parity; one in d9 clears
892 Latched ump_tx_parity; one in d10 clears Latched scpad_parity; read from
893 this register return zero */
894 #define MISC_REG_AEU_CLR_LATCH_SIGNAL 0xa45c
895 /* [RW 32] first 32b for enabling the output for function 0 output0. mapped
896 as follows: [0] NIG attention for function0; [1] NIG attention for
897 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
898 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
899 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
900 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
901 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
902 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
903 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
904 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
905 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
906 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
907 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
908 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0 0xa06c
909 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1 0xa07c
910 #define MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3 0xa09c
911 /* [RW 32] first 32b for enabling the output for function 1 output0. mapped
912 as follows: [0] NIG attention for function0; [1] NIG attention for
913 function1; [2] GPIO1 function 1; [3] GPIO2 function 1; [4] GPIO3 function
914 1; [5] GPIO4 function 1; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
915 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
916 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
917 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
918 SPIO4; [15] SPIO5; [16] MSI/X indication for function 1; [17] MSI/X
919 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
920 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
921 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
922 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
923 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
924 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 0xa10c
925 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 0xa11c
926 #define MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3 0xa13c
927 /* [RW 32] first 32b for enabling the output for close the gate nig 0.
928 mapped as follows: [0] NIG attention for function0; [1] NIG attention for
929 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
930 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
931 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
932 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
933 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
934 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
935 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
936 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
937 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
938 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
939 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
940 #define MISC_REG_AEU_ENABLE1_NIG_0 0xa0ec
941 #define MISC_REG_AEU_ENABLE1_NIG_1 0xa18c
942 /* [RW 32] first 32b for enabling the output for close the gate pxp 0.
943 mapped as follows: [0] NIG attention for function0; [1] NIG attention for
944 function1; [2] GPIO1 function 0; [3] GPIO2 function 0; [4] GPIO3 function
945 0; [5] GPIO4 function 0; [6] GPIO1 function 1; [7] GPIO2 function 1; [8]
946 GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
947 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
948 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
949 SPIO4; [15] SPIO5; [16] MSI/X indication for function 0; [17] MSI/X
950 indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt;
951 [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23]
952 SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26]
953 TCM Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29]
954 TSEMI Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
955 #define MISC_REG_AEU_ENABLE1_PXP_0 0xa0fc
956 #define MISC_REG_AEU_ENABLE1_PXP_1 0xa19c
957 /* [RW 32] second 32b for enabling the output for function 0 output0. mapped
958 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
959 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
960 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
961 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
962 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
963 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
964 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
965 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
966 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
967 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
968 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
969 interrupt; */
970 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0 0xa070
971 #define MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1 0xa080
972 /* [RW 32] second 32b for enabling the output for function 1 output0. mapped
973 as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt; [2] QM
974 Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw
975 interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity
976 error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw
977 interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14]
978 NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error;
979 [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw
980 interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM
981 Parity error; [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI
982 Hw interrupt; [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM
983 Parity error; [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw
984 interrupt; */
985 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0 0xa110
986 #define MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1 0xa120
987 /* [RW 32] second 32b for enabling the output for close the gate nig 0.
988 mapped as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt;
989 [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5]
990 Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8]
991 XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11]
992 XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw
993 interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI
994 core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity
995 error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw
996 interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI
997 Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw
998 interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM
999 Parity error; [31] CCM Hw interrupt; */
1000 #define MISC_REG_AEU_ENABLE2_NIG_0 0xa0f0
1001 #define MISC_REG_AEU_ENABLE2_NIG_1 0xa190
1002 /* [RW 32] second 32b for enabling the output for close the gate pxp 0.
1003 mapped as follows: [0] PBClient Parity error; [1] PBClient Hw interrupt;
1004 [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5]
1005 Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8]
1006 XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11]
1007 XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw
1008 interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI
1009 core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity
1010 error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw
1011 interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI
1012 Parity error; [25] USEMI Hw interrupt; [26] UPB Parity error; [27] UPB Hw
1013 interrupt; [28] CSDM Parity error; [29] CSDM Hw interrupt; [30] CCM
1014 Parity error; [31] CCM Hw interrupt; */
1015 #define MISC_REG_AEU_ENABLE2_PXP_0 0xa100
1016 #define MISC_REG_AEU_ENABLE2_PXP_1 0xa1a0
1017 /* [RW 32] third 32b for enabling the output for function 0 output0. mapped
1018 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1019 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1020 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1021 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1022 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1023 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1024 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1025 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1026 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1027 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1028 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1029 attn1; */
1030 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0 0xa074
1031 #define MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1 0xa084
1032 /* [RW 32] third 32b for enabling the output for function 1 output0. mapped
1033 as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP
1034 Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error;
1035 [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw
1036 interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity
1037 error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC)
1038 Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16]
1039 pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20]
1040 MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23]
1041 SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST; [26] SW
1042 timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers attn_3
1043 func1; [29] SW timers attn_4 func1; [30] General attn0; [31] General
1044 attn1; */
1045 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0 0xa114
1046 #define MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1 0xa124
1047 /* [RW 32] third 32b for enabling the output for close the gate nig 0.
1048 mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2]
1049 PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity
1050 error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC
1051 Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE
1052 Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13]
1053 IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt;
1054 [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0;
1055 [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0;
1056 [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST;
1057 [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers
1058 attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31]
1059 General attn1; */
1060 #define MISC_REG_AEU_ENABLE3_NIG_0 0xa0f4
1061 #define MISC_REG_AEU_ENABLE3_NIG_1 0xa194
1062 /* [RW 32] third 32b for enabling the output for close the gate pxp 0.
1063 mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2]
1064 PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity
1065 error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC
1066 Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE
1067 Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13]
1068 IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt;
1069 [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0;
1070 [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0;
1071 [23] SW timers attn_3 func0; [24] SW timers attn_4 func0; [25] PERST;
1072 [26] SW timers attn_1 func1; [27] SW timers attn_2 func1; [28] SW timers
1073 attn_3 func1; [29] SW timers attn_4 func1; [30] General attn0; [31]
1074 General attn1; */
1075 #define MISC_REG_AEU_ENABLE3_PXP_0 0xa104
1076 #define MISC_REG_AEU_ENABLE3_PXP_1 0xa1a4
1077 /* [RW 32] fourth 32b for enabling the output for function 0 output0.mapped
1078 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1079 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1080 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1081 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1082 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1083 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1084 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1085 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1086 Latched timeout attention; [27] GRC Latched reserved access attention;
1087 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1088 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1089 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 0xa078
1090 #define MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2 0xa098
1091 /* [RW 32] fourth 32b for enabling the output for function 1 output0.mapped
1092 as follows: [0] General attn2; [1] General attn3; [2] General attn4; [3]
1093 General attn5; [4] General attn6; [5] General attn7; [6] General attn8;
1094 [7] General attn9; [8] General attn10; [9] General attn11; [10] General
1095 attn12; [11] General attn13; [12] General attn14; [13] General attn15;
1096 [14] General attn16; [15] General attn17; [16] General attn18; [17]
1097 General attn19; [18] General attn20; [19] General attn21; [20] Main power
1098 interrupt; [21] RBCR Latched attn; [22] RBCT Latched attn; [23] RBCN
1099 Latched attn; [24] RBCU Latched attn; [25] RBCP Latched attn; [26] GRC
1100 Latched timeout attention; [27] GRC Latched reserved access attention;
1101 [28] MCP Latched rom_parity; [29] MCP Latched ump_rx_parity; [30] MCP
1102 Latched ump_tx_parity; [31] MCP Latched scpad_parity; */
1103 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0 0xa118
1104 #define MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2 0xa138
1105 /* [RW 32] fourth 32b for enabling the output for close the gate nig
1106 0.mapped as follows: [0] General attn2; [1] General attn3; [2] General
1107 attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6]
1108 General attn8; [7] General attn9; [8] General attn10; [9] General attn11;
1109 [10] General attn12; [11] General attn13; [12] General attn14; [13]
1110 General attn15; [14] General attn16; [15] General attn17; [16] General
1111 attn18; [17] General attn19; [18] General attn20; [19] General attn21;
1112 [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched
1113 attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched
1114 attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved
1115 access attention; [28] MCP Latched rom_parity; [29] MCP Latched
1116 ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched
1117 scpad_parity; */
1118 #define MISC_REG_AEU_ENABLE4_NIG_0 0xa0f8
1119 #define MISC_REG_AEU_ENABLE4_NIG_1 0xa198
1120 /* [RW 32] fourth 32b for enabling the output for close the gate pxp
1121 0.mapped as follows: [0] General attn2; [1] General attn3; [2] General
1122 attn4; [3] General attn5; [4] General attn6; [5] General attn7; [6]
1123 General attn8; [7] General attn9; [8] General attn10; [9] General attn11;
1124 [10] General attn12; [11] General attn13; [12] General attn14; [13]
1125 General attn15; [14] General attn16; [15] General attn17; [16] General
1126 attn18; [17] General attn19; [18] General attn20; [19] General attn21;
1127 [20] Main power interrupt; [21] RBCR Latched attn; [22] RBCT Latched
1128 attn; [23] RBCN Latched attn; [24] RBCU Latched attn; [25] RBCP Latched
1129 attn; [26] GRC Latched timeout attention; [27] GRC Latched reserved
1130 access attention; [28] MCP Latched rom_parity; [29] MCP Latched
1131 ump_rx_parity; [30] MCP Latched ump_tx_parity; [31] MCP Latched
1132 scpad_parity; */
1133 #define MISC_REG_AEU_ENABLE4_PXP_0 0xa108
1134 #define MISC_REG_AEU_ENABLE4_PXP_1 0xa1a8
1135 /* [RW 1] set/clr general attention 0; this will set/clr bit 94 in the aeu
1136 128 bit vector */
1137 #define MISC_REG_AEU_GENERAL_ATTN_0 0xa000
1138 #define MISC_REG_AEU_GENERAL_ATTN_1 0xa004
1139 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1140 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1141 #define MISC_REG_AEU_GENERAL_ATTN_12 0xa030
1142 #define MISC_REG_AEU_GENERAL_ATTN_13 0xa034
1143 #define MISC_REG_AEU_GENERAL_ATTN_14 0xa038
1144 #define MISC_REG_AEU_GENERAL_ATTN_15 0xa03c
1145 #define MISC_REG_AEU_GENERAL_ATTN_16 0xa040
1146 #define MISC_REG_AEU_GENERAL_ATTN_17 0xa044
1147 #define MISC_REG_AEU_GENERAL_ATTN_18 0xa048
1148 #define MISC_REG_AEU_GENERAL_ATTN_19 0xa04c
1149 #define MISC_REG_AEU_GENERAL_ATTN_10 0xa028
1150 #define MISC_REG_AEU_GENERAL_ATTN_11 0xa02c
1151 #define MISC_REG_AEU_GENERAL_ATTN_2 0xa008
1152 #define MISC_REG_AEU_GENERAL_ATTN_20 0xa050
1153 #define MISC_REG_AEU_GENERAL_ATTN_21 0xa054
1154 #define MISC_REG_AEU_GENERAL_ATTN_3 0xa00c
1155 #define MISC_REG_AEU_GENERAL_ATTN_4 0xa010
1156 #define MISC_REG_AEU_GENERAL_ATTN_5 0xa014
1157 #define MISC_REG_AEU_GENERAL_ATTN_6 0xa018
1158 #define MISC_REG_AEU_GENERAL_ATTN_7 0xa01c
1159 #define MISC_REG_AEU_GENERAL_ATTN_8 0xa020
1160 #define MISC_REG_AEU_GENERAL_ATTN_9 0xa024
1161 /* [RW 32] first 32b for inverting the input for function 0; for each bit:
1162 0= do not invert; 1= invert; mapped as follows: [0] NIG attention for
1163 function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp;
1164 [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1;
1165 [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event
1166 function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP
1167 Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14]
1168 SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication
1169 for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS
1170 Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw
1171 interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM
1172 Parity error; [27] TCM Hw interrupt; [28] TSEMI Parity error; [29] TSEMI
1173 Hw interrupt; [30] PBF Parity error; [31] PBF Hw interrupt; */
1174 #define MISC_REG_AEU_INVERTER_1_FUNC_0 0xa22c
1175 #define MISC_REG_AEU_INVERTER_1_FUNC_1 0xa23c
1176 /* [RW 32] second 32b for inverting the input for function 0; for each bit:
1177 0= do not invert; 1= invert. mapped as follows: [0] PBClient Parity
1178 error; [1] PBClient Hw interrupt; [2] QM Parity error; [3] QM Hw
1179 interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM
1180 Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw
1181 interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12]
1182 DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity
1183 error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux
1184 PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt;
1185 [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error;
1186 [23] UCM Hw interrupt; [24] USEMI Parity error; [25] USEMI Hw interrupt;
1187 [26] UPB Parity error; [27] UPB Hw interrupt; [28] CSDM Parity error;
1188 [29] CSDM Hw interrupt; [30] CCM Parity error; [31] CCM Hw interrupt; */
1189 #define MISC_REG_AEU_INVERTER_2_FUNC_0 0xa230
1190 #define MISC_REG_AEU_INVERTER_2_FUNC_1 0xa240
1191 /* [RW 10] [7:0] = mask 8 attention output signals toward IGU function0;
1192 [9:8] = mask close the gates signals of function 0 toward PXP [8] and NIG
1193 [9]. Zero = mask; one = unmask */
1194 #define MISC_REG_AEU_MASK_ATTN_FUNC_0 0xa060
1195 #define MISC_REG_AEU_MASK_ATTN_FUNC_1 0xa064
1196 /* [R 4] This field indicates the type of the device. '0' - 2 Ports; '1' - 1
1197 Port. */
1198 #define MISC_REG_BOND_ID 0xa400
1199 /* [R 8] These bits indicate the metal revision of the chip. This value
1200 starts at 0x00 for each all-layer tape-out and increments by one for each
1201 tape-out. */
1202 #define MISC_REG_CHIP_METAL 0xa404
1203 /* [R 16] These bits indicate the part number for the chip. */
1204 #define MISC_REG_CHIP_NUM 0xa408
1205 /* [R 4] These bits indicate the base revision of the chip. This value
1206 starts at 0x0 for the A0 tape-out and increments by one for each
1207 all-layer tape-out. */
1208 #define MISC_REG_CHIP_REV 0xa40c
1209 /* [RW 32] The following driver registers(1..6) represent 6 drivers and 32
1210 clients. Each client can be controlled by one driver only. One in each
1211 bit represent that this driver control the appropriate client (Ex: bit 5
1212 is set means this driver control client number 5). addr1 = set; addr0 =
1213 clear; read from both addresses will give the same result = status. write
1214 to address 1 will set a request to control all the clients that their
1215 appropriate bit (in the write command) is set. if the client is free (the
1216 appropriate bit in all the other drivers is clear) one will be written to
1217 that driver register; if the client isn't free the bit will remain zero.
1218 if the appropriate bit is set (the driver request to gain control on a
1219 client it already controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW
1220 interrupt will be asserted). write to address 0 will set a request to
1221 free all the clients that their appropriate bit (in the write command) is
1222 set. if the appropriate bit is clear (the driver request to free a client
1223 it doesn't controls the ~MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will
1224 be asserted). */
1225 #define MISC_REG_DRIVER_CONTROL_1 0xa510
1226 /* [RW 32] GPIO. [31-28] FLOAT port 0; [27-24] FLOAT port 0; When any of
1227 these bits is written as a '1'; the corresponding SPIO bit will turn off
1228 it's drivers and become an input. This is the reset state of all GPIO
1229 pins. The read value of these bits will be a '1' if that last command
1230 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
1231 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
1232 as a '1'; the corresponding GPIO bit will drive low. The read value of
1233 these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
1234 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
1235 SET When any of these bits is written as a '1'; the corresponding GPIO
1236 bit will drive high (if it has that capability). The read value of these
1237 bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
1238 bit was a #SET. (reset value 0). [7-4] VALUE port 1; [3-0] VALUE port 0;
1239 RO; These bits indicate the read value of each of the eight GPIO pins.
1240 This is the result value of the pin; not the drive value. Writing these
1241 bits will have not effect. */
1242 #define MISC_REG_GPIO 0xa490
1243 /* [RW 1] Setting this bit enables a timer in the GRC block to timeout any
1244 access that does not finish within
1245 ~misc_registers_grc_timout_val.grc_timeout_val cycles. When this bit is
1246 cleared; this timeout is disabled. If this timeout occurs; the GRC shall
1247 assert it attention output. */
1248 #define MISC_REG_GRC_TIMEOUT_EN 0xa280
1249 /* [RW 28] 28 LSB of LCPLL first register; reset val = 521. inside order of
1250 the bits is: [2:0] OAC reset value 001) CML output buffer bias control;
1251 111 for +40%; 011 for +20%; 001 for 0%; 000 for -20%. [5:3] Icp_ctrl
1252 (reset value 001) Charge pump current control; 111 for 720u; 011 for
1253 600u; 001 for 480u and 000 for 360u. [7:6] Bias_ctrl (reset value 00)
1254 Global bias control; When bit 7 is high bias current will be 10 0gh; When
1255 bit 6 is high bias will be 100w; Valid values are 00; 10; 01. [10:8]
1256 Pll_observe (reset value 010) Bits to control observability. bit 10 is
1257 for test bias; bit 9 is for test CK; bit 8 is test Vc. [12:11] Vth_ctrl
1258 (reset value 00) Comparator threshold control. 00 for 0.6V; 01 for 0.54V
1259 and 10 for 0.66V. [13] pllSeqStart (reset value 0) Enables VCO tuning
1260 sequencer: 1= sequencer disabled; 0= sequencer enabled (inverted
1261 internally). [14] reserved (reset value 0) Reset for VCO sequencer is
1262 connected to RESET input directly. [15] capRetry_en (reset value 0)
1263 enable retry on cap search failure (inverted). [16] freqMonitor_e (reset
1264 value 0) bit to continuously monitor vco freq (inverted). [17]
1265 freqDetRestart_en (reset value 0) bit to enable restart when not freq
1266 locked (inverted). [18] freqDetRetry_en (reset value 0) bit to enable
1267 retry on freq det failure(inverted). [19] pllForceFdone_en (reset value
1268 0) bit to enable pllForceFdone & pllForceFpass into pllSeq. [20]
1269 pllForceFdone (reset value 0) bit to force freqDone. [21] pllForceFpass
1270 (reset value 0) bit to force freqPass. [22] pllForceDone_en (reset value
1271 0) bit to enable pllForceCapDone. [23] pllForceCapDone (reset value 0)
1272 bit to force capDone. [24] pllForceCapPass_en (reset value 0) bit to
1273 enable pllForceCapPass. [25] pllForceCapPass (reset value 0) bit to force
1274 capPass. [26] capRestart (reset value 0) bit to force cap sequencer to
1275 restart. [27] capSelectM_en (reset value 0) bit to enable cap select
1276 register bits. */
1277 #define MISC_REG_LCPLL_CTRL_1 0xa2a4
1278 #define MISC_REG_LCPLL_CTRL_REG_2 0xa2a8
1279 /* [RW 4] Interrupt mask register #0 read/write */
1280 #define MISC_REG_MISC_INT_MASK 0xa388
1281 /* [RW 1] Parity mask register #0 read/write */
1282 #define MISC_REG_MISC_PRTY_MASK 0xa398
1283 /* [R 1] Parity register #0 read */
1284 #define MISC_REG_MISC_PRTY_STS 0xa38c
1285 /* [RW 32] 32 LSB of storm PLL first register; reset val = 0x 071d2911.
1286 inside order of the bits is: [0] P1 divider[0] (reset value 1); [1] P1
1287 divider[1] (reset value 0); [2] P1 divider[2] (reset value 0); [3] P1
1288 divider[3] (reset value 0); [4] P2 divider[0] (reset value 1); [5] P2
1289 divider[1] (reset value 0); [6] P2 divider[2] (reset value 0); [7] P2
1290 divider[3] (reset value 0); [8] ph_det_dis (reset value 1); [9]
1291 freq_det_dis (reset value 0); [10] Icpx[0] (reset value 0); [11] Icpx[1]
1292 (reset value 1); [12] Icpx[2] (reset value 0); [13] Icpx[3] (reset value
1293 1); [14] Icpx[4] (reset value 0); [15] Icpx[5] (reset value 0); [16]
1294 Rx[0] (reset value 1); [17] Rx[1] (reset value 0); [18] vc_en (reset
1295 value 1); [19] vco_rng[0] (reset value 1); [20] vco_rng[1] (reset value
1296 1); [21] Kvco_xf[0] (reset value 0); [22] Kvco_xf[1] (reset value 0);
1297 [23] Kvco_xf[2] (reset value 0); [24] Kvco_xs[0] (reset value 1); [25]
1298 Kvco_xs[1] (reset value 1); [26] Kvco_xs[2] (reset value 1); [27]
1299 testd_en (reset value 0); [28] testd_sel[0] (reset value 0); [29]
1300 testd_sel[1] (reset value 0); [30] testd_sel[2] (reset value 0); [31]
1301 testa_en (reset value 0); */
1302 #define MISC_REG_PLL_STORM_CTRL_1 0xa294
1303 #define MISC_REG_PLL_STORM_CTRL_2 0xa298
1304 #define MISC_REG_PLL_STORM_CTRL_3 0xa29c
1305 #define MISC_REG_PLL_STORM_CTRL_4 0xa2a0
1306 /* [RW 32] reset reg#1; rite/read one = the specific block is out of reset;
1307 write/read zero = the specific block is in reset; addr 0-wr- the write
1308 value will be written to the register; addr 1-set - one will be written
1309 to all the bits that have the value of one in the data written (bits that
1310 have the value of zero will not be change) ; addr 2-clear - zero will be
1311 written to all the bits that have the value of one in the data written
1312 (bits that have the value of zero will not be change); addr 3-ignore;
1313 read ignore from all addr except addr 00; inside order of the bits is:
1314 [0] rst_brb1; [1] rst_prs; [2] rst_src; [3] rst_tsdm; [4] rst_tsem; [5]
1315 rst_tcm; [6] rst_rbcr; [7] rst_nig; [8] rst_usdm; [9] rst_ucm; [10]
1316 rst_usem; [11] rst_upb; [12] rst_ccm; [13] rst_csem; [14] rst_csdm; [15]
1317 rst_rbcu; [16] rst_pbf; [17] rst_qm; [18] rst_tm; [19] rst_dorq; [20]
1318 rst_xcm; [21] rst_xsdm; [22] rst_xsem; [23] rst_rbct; [24] rst_cdu; [25]
1319 rst_cfc; [26] rst_pxp; [27] rst_pxpv; [28] rst_rbcp; [29] rst_hc; [30]
1320 rst_dmae; [31] rst_semi_rtc; */
1321 #define MISC_REG_RESET_REG_1 0xa580
1322 #define MISC_REG_RESET_REG_2 0xa590
1323 /* [RW 20] 20 bit GRC address where the scratch-pad of the MCP that is
1324 shared with the driver resides */
1325 #define MISC_REG_SHARED_MEM_ADDR 0xa2b4
1326 /* [RW 32] SPIO. [31-24] FLOAT When any of these bits is written as a '1';
1327 the corresponding SPIO bit will turn off it's drivers and become an
1328 input. This is the reset state of all SPIO pins. The read value of these
1329 bits will be a '1' if that last command (#SET; #CL; or #FLOAT) for this
1330 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
1331 is written as a '1'; the corresponding SPIO bit will drive low. The read
1332 value of these bits will be a '1' if that last command (#SET; #CLR; or
1333 #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
1334 these bits is written as a '1'; the corresponding SPIO bit will drive
1335 high (if it has that capability). The read value of these bits will be a
1336 '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
1337 (reset value 0). [7-0] VALUE RO; These bits indicate the read value of
1338 each of the eight SPIO pins. This is the result value of the pin; not the
1339 drive value. Writing these bits will have not effect. Each 8 bits field
1340 is divided as follows: [0] VAUX Enable; when pulsed low; enables supply
1341 from VAUX. (This is an output pin only; the FLOAT field is not applicable
1342 for this pin); [1] VAUX Disable; when pulsed low; disables supply form
1343 VAUX. (This is an output pin only; FLOAT field is not applicable for this
1344 pin); [2] SEL_VAUX_B - Control to power switching logic. Drive low to
1345 select VAUX supply. (This is an output pin only; it is not controlled by
1346 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
1347 field is not applicable for this pin; only the VALUE fields is relevant -
1348 it reflects the output value); [3] reserved; [4] spio_4; [5] spio_5; [6]
1349 Bit 0 of UMP device ID select; read by UMP firmware; [7] Bit 1 of UMP
1350 device ID select; read by UMP firmware. */
1351 #define MISC_REG_SPIO 0xa4fc
1352 /* [RW 8] These bits enable the SPIO_INTs to signals event to the IGU/MC.
1353 according to the following map: [3:0] reserved; [4] spio_4 [5] spio_5;
1354 [7:0] reserved */
1355 #define MISC_REG_SPIO_EVENT_EN 0xa2b8
1356 /* [RW 32] SPIO INT. [31-24] OLD_CLR Writing a '1' to these bit clears the
1357 corresponding bit in the #OLD_VALUE register. This will acknowledge an
1358 interrupt on the falling edge of corresponding SPIO input (reset value
1359 0). [23-16] OLD_SET Writing a '1' to these bit sets the corresponding bit
1360 in the #OLD_VALUE register. This will acknowledge an interrupt on the
1361 rising edge of corresponding SPIO input (reset value 0). [15-8] OLD_VALUE
1362 RO; These bits indicate the old value of the SPIO input value. When the
1363 ~INT_STATE bit is set; this bit indicates the OLD value of the pin such
1364 that if ~INT_STATE is set and this bit is '0'; then the interrupt is due
1365 to a low to high edge. If ~INT_STATE is set and this bit is '1'; then the
1366 interrupt is due to a high to low edge (reset value 0). [7-0] INT_STATE
1367 RO; These bits indicate the current SPIO interrupt state for each SPIO
1368 pin. This bit is cleared when the appropriate #OLD_SET or #OLD_CLR
1369 command bit is written. This bit is set when the SPIO input does not
1370 match the current value in #OLD_VALUE (reset value 0). */
1371 #define MISC_REG_SPIO_INT 0xa500
1372 /* [RW 1] Set by the MCP to remember if one or more of the drivers is/are
1373 loaded; 0-prepare; -unprepare */
1374 #define MISC_REG_UNPREPARED 0xa424
1375 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT (0x1<<0)
1376 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS (0x1<<9)
1377 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G (0x1<<15)
1378 #define NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS (0xf<<18)
1379 /* [RW 1] Input enable for RX_BMAC0 IF */
1380 #define NIG_REG_BMAC0_IN_EN 0x100ac
1381 /* [RW 1] output enable for TX_BMAC0 IF */
1382 #define NIG_REG_BMAC0_OUT_EN 0x100e0
1383 /* [RW 1] output enable for TX BMAC pause port 0 IF */
1384 #define NIG_REG_BMAC0_PAUSE_OUT_EN 0x10110
1385 /* [RW 1] output enable for RX_BMAC0_REGS IF */
1386 #define NIG_REG_BMAC0_REGS_OUT_EN 0x100e8
1387 /* [RW 1] output enable for RX BRB1 port0 IF */
1388 #define NIG_REG_BRB0_OUT_EN 0x100f8
1389 /* [RW 1] Input enable for TX BRB1 pause port 0 IF */
1390 #define NIG_REG_BRB0_PAUSE_IN_EN 0x100c4
1391 /* [RW 1] output enable for RX BRB1 port1 IF */
1392 #define NIG_REG_BRB1_OUT_EN 0x100fc
1393 /* [RW 1] Input enable for TX BRB1 pause port 1 IF */
1394 #define NIG_REG_BRB1_PAUSE_IN_EN 0x100c8
1395 /* [RW 1] output enable for RX BRB1 LP IF */
1396 #define NIG_REG_BRB_LB_OUT_EN 0x10100
1397 /* [WB_W 72] Debug packet to LP from RBC; Data spelling:[63:0] data; 64]
1398 error; [67:65]eop_bvalid; [68]eop; [69]sop; [70]port_id; 71]flush */
1399 #define NIG_REG_DEBUG_PACKET_LB 0x10800
1400 /* [RW 1] Input enable for TX Debug packet */
1401 #define NIG_REG_EGRESS_DEBUG_IN_EN 0x100dc
1402 /* [RW 1] If 1 - egress drain mode for port0 is active. In this mode all
1403 packets from PBFare not forwarded to the MAC and just deleted from FIFO.
1404 First packet may be deleted from the middle. And last packet will be
1405 always deleted till the end. */
1406 #define NIG_REG_EGRESS_DRAIN0_MODE 0x10060
1407 /* [RW 1] Output enable to EMAC0 */
1408 #define NIG_REG_EGRESS_EMAC0_OUT_EN 0x10120
1409 /* [RW 1] MAC configuration for packets of port0. If 1 - all packet outputs
1410 to emac for port0; other way to bmac for port0 */
1411 #define NIG_REG_EGRESS_EMAC0_PORT 0x10058
1412 /* [RW 1] Input enable for TX PBF user packet port0 IF */
1413 #define NIG_REG_EGRESS_PBF0_IN_EN 0x100cc
1414 /* [RW 1] Input enable for TX PBF user packet port1 IF */
1415 #define NIG_REG_EGRESS_PBF1_IN_EN 0x100d0
1416 /* [RW 1] Input enable for RX_EMAC0 IF */
1417 #define NIG_REG_EMAC0_IN_EN 0x100a4
1418 /* [RW 1] output enable for TX EMAC pause port 0 IF */
1419 #define NIG_REG_EMAC0_PAUSE_OUT_EN 0x10118
1420 /* [R 1] status from emac0. This bit is set when MDINT from either the
1421 EXT_MDINT pin or from the Copper PHY is driven low. This condition must
1422 be cleared in the attached PHY device that is driving the MINT pin. */
1423 #define NIG_REG_EMAC0_STATUS_MISC_MI_INT 0x10494
1424 /* [WB 48] This address space contains BMAC0 registers. The BMAC registers
1425 are described in appendix A. In order to access the BMAC0 registers; the
1426 base address; NIG_REGISTERS_INGRESS_BMAC0_MEM; Offset: 0x10c00; should be
1427 added to each BMAC register offset */
1428 #define NIG_REG_INGRESS_BMAC0_MEM 0x10c00
1429 /* [WB 48] This address space contains BMAC1 registers. The BMAC registers
1430 are described in appendix A. In order to access the BMAC0 registers; the
1431 base address; NIG_REGISTERS_INGRESS_BMAC1_MEM; Offset: 0x11000; should be
1432 added to each BMAC register offset */
1433 #define NIG_REG_INGRESS_BMAC1_MEM 0x11000
1434 /* [R 1] FIFO empty in EOP descriptor FIFO of LP in NIG_RX_EOP */
1435 #define NIG_REG_INGRESS_EOP_LB_EMPTY 0x104e0
1436 /* [RW 17] Debug only. RX_EOP_DSCR_lb_FIFO in NIG_RX_EOP. Data
1437 packet_length[13:0]; mac_error[14]; trunc_error[15]; parity[16] */
1438 #define NIG_REG_INGRESS_EOP_LB_FIFO 0x104e4
1439 /* [RW 1] led 10g for port 0 */
1440 #define NIG_REG_LED_10G_P0 0x10320
1441 /* [RW 1] Port0: This bit is set to enable the use of the
1442 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 field
1443 defined below. If this bit is cleared; then the blink rate will be about
1444 8Hz. */
1445 #define NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 0x10318
1446 /* [RW 12] Port0: Specifies the period of each blink cycle (on + off) for
1447 Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field
1448 is reset to 0x080; giving a default blink period of approximately 8Hz. */
1449 #define NIG_REG_LED_CONTROL_BLINK_RATE_P0 0x10310
1450 /* [RW 1] Port0: If set along with the
1451 nig_registers_led_control_override_traffic_p0.led_control_override_traffic_p0
1452 bit and ~nig_registers_led_control_traffic_p0.led_control_traffic_p0 LED
1453 bit; the Traffic LED will blink with the blink rate specified in
1454 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1455 ~nig_registers_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1456 fields. */
1457 #define NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 0x10308
1458 /* [RW 1] Port0: If set overrides hardware control of the Traffic LED. The
1459 Traffic LED will then be controlled via bit ~nig_registers_
1460 led_control_traffic_p0.led_control_traffic_p0 and bit
1461 ~nig_registers_led_control_blink_traffic_p0.led_control_blink_traffic_p0 */
1462 #define NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 0x102f8
1463 /* [RW 1] Port0: If set along with the led_control_override_trafic_p0 bit;
1464 turns on the Traffic LED. If the led_control_blink_traffic_p0 bit is also
1465 set; the LED will blink with blink rate specified in
1466 ~nig_registers_led_control_blink_rate_p0.led_control_blink_rate_p0 and
1467 ~nig_regsters_led_control_blink_rate_ena_p0.led_control_blink_rate_ena_p0
1468 fields. */
1469 #define NIG_REG_LED_CONTROL_TRAFFIC_P0 0x10300
1470 /* [RW 4] led mode for port0: 0 MAC; 1-3 PHY1; 4 MAC2; 5-7 PHY4; 8-MAC3;
1471 9-11PHY7; 12 MAC4; 13-15 PHY10; */
1472 #define NIG_REG_LED_MODE_P0 0x102f0
1473 #define NIG_REG_LLH0_BRB1_DRV_MASK 0x10244
1474 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
1475 #define NIG_REG_LLH0_BRB1_NOT_MCP 0x1025c
1476 /* [RW 32] cm header for llh0 */
1477 #define NIG_REG_LLH0_CM_HEADER 0x1007c
1478 #define NIG_REG_LLH0_ERROR_MASK 0x1008c
1479 /* [RW 8] event id for llh0 */
1480 #define NIG_REG_LLH0_EVENT_ID 0x10084
1481 /* [RW 8] init credit counter for port0 in LLH */
1482 #define NIG_REG_LLH0_XCM_INIT_CREDIT 0x10554
1483 #define NIG_REG_LLH0_XCM_MASK 0x10130
1484 /* [RW 1] send to BRB1 if no match on any of RMP rules. */
1485 #define NIG_REG_LLH1_BRB1_NOT_MCP 0x102dc
1486 /* [RW 32] cm header for llh1 */
1487 #define NIG_REG_LLH1_CM_HEADER 0x10080
1488 #define NIG_REG_LLH1_ERROR_MASK 0x10090
1489 /* [RW 8] event id for llh1 */
1490 #define NIG_REG_LLH1_EVENT_ID 0x10088
1491 /* [RW 8] init credit counter for port1 in LLH */
1492 #define NIG_REG_LLH1_XCM_INIT_CREDIT 0x10564
1493 #define NIG_REG_LLH1_XCM_MASK 0x10134
1494 #define NIG_REG_MASK_INTERRUPT_PORT0 0x10330
1495 #define NIG_REG_MASK_INTERRUPT_PORT1 0x10334
1496 /* [RW 1] Output signal from NIG to EMAC0. When set enables the EMAC0 block. */
1497 #define NIG_REG_NIG_EMAC0_EN 0x1003c
1498 /* [RW 1] Output signal from NIG to TX_EMAC0. When set indicates to the
1499 EMAC0 to strip the CRC from the ingress packets. */
1500 #define NIG_REG_NIG_INGRESS_EMAC0_NO_CRC 0x10044
1501 /* [RW 1] Input enable for RX PBF LP IF */
1502 #define NIG_REG_PBF_LB_IN_EN 0x100b4
1503 /* [RW 1] Value of this register will be transmitted to port swap when
1504 ~nig_registers_strap_override.strap_override =1 */
1505 #define NIG_REG_PORT_SWAP 0x10394
1506 /* [RW 1] output enable for RX parser descriptor IF */
1507 #define NIG_REG_PRS_EOP_OUT_EN 0x10104
1508 /* [RW 1] Input enable for RX parser request IF */
1509 #define NIG_REG_PRS_REQ_IN_EN 0x100b8
1510 /* [RW 5] control to serdes - CL22 PHY_ADD and CL45 PRTAD */
1511 #define NIG_REG_SERDES0_CTRL_PHY_ADDR 0x10374
1512 /* [R 1] status from serdes0 that inputs to interrupt logic of link status */
1513 #define NIG_REG_SERDES0_STATUS_LINK_STATUS 0x10578
1514 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1515 for port0 */
1516 #define NIG_REG_STAT0_BRB_DISCARD 0x105f0
1517 /* [R 32] Rx statistics : In user packets discarded due to BRB backpressure
1518 for port1 */
1519 #define NIG_REG_STAT1_BRB_DISCARD 0x10628
1520 /* [WB_R 64] Rx statistics : User octets received for LP */
1521 #define NIG_REG_STAT2_BRB_OCTET 0x107e0
1522 #define NIG_REG_STATUS_INTERRUPT_PORT0 0x10328
1523 #define NIG_REG_STATUS_INTERRUPT_PORT1 0x1032c
1524 /* [RW 1] port swap mux selection. If this register equal to 0 then port
1525 swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
1526 ort swap is equal to ~nig_registers_port_swap.port_swap */
1527 #define NIG_REG_STRAP_OVERRIDE 0x10398
1528 /* [RW 1] output enable for RX_XCM0 IF */
1529 #define NIG_REG_XCM0_OUT_EN 0x100f0
1530 /* [RW 1] output enable for RX_XCM1 IF */
1531 #define NIG_REG_XCM1_OUT_EN 0x100f4
1532 /* [RW 5] control to xgxs - CL45 DEVAD */
1533 #define NIG_REG_XGXS0_CTRL_MD_DEVAD 0x1033c
1534 /* [RW 5] control to xgxs - CL22 PHY_ADD and CL45 PRTAD */
1535 #define NIG_REG_XGXS0_CTRL_PHY_ADDR 0x10340
1536 /* [R 1] status from xgxs0 that inputs to interrupt logic of link10g. */
1537 #define NIG_REG_XGXS0_STATUS_LINK10G 0x10680
1538 /* [R 4] status from xgxs0 that inputs to interrupt logic of link status */
1539 #define NIG_REG_XGXS0_STATUS_LINK_STATUS 0x10684
1540 /* [RW 2] selection for XGXS lane of port 0 in NIG_MUX block */
1541 #define NIG_REG_XGXS_LANE_SEL_P0 0x102e8
1542 /* [RW 1] selection for port0 for NIG_MUX block : 0 = SerDes; 1 = XGXS */
1543 #define NIG_REG_XGXS_SERDES0_MODE_SEL 0x102e0
1544 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS (0x1<<9)
1545 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G (0x1<<15)
1546 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS (0xf<<18)
1547 #define NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 18
1548 /* [RW 1] Disable processing further tasks from port 0 (after ending the
1549 current task in process). */
1550 #define PBF_REG_DISABLE_NEW_TASK_PROC_P0 0x14005c
1551 /* [RW 1] Disable processing further tasks from port 1 (after ending the
1552 current task in process). */
1553 #define PBF_REG_DISABLE_NEW_TASK_PROC_P1 0x140060
1554 /* [RW 1] Disable processing further tasks from port 4 (after ending the
1555 current task in process). */
1556 #define PBF_REG_DISABLE_NEW_TASK_PROC_P4 0x14006c
1557 #define PBF_REG_IF_ENABLE_REG 0x140044
1558 /* [RW 1] Init bit. When set the initial credits are copied to the credit
1559 registers (except the port credits). Should be set and then reset after
1560 the configuration of the block has ended. */
1561 #define PBF_REG_INIT 0x140000
1562 /* [RW 1] Init bit for port 0. When set the initial credit of port 0 is
1563 copied to the credit register. Should be set and then reset after the
1564 configuration of the port has ended. */
1565 #define PBF_REG_INIT_P0 0x140004
1566 /* [RW 1] Init bit for port 1. When set the initial credit of port 1 is
1567 copied to the credit register. Should be set and then reset after the
1568 configuration of the port has ended. */
1569 #define PBF_REG_INIT_P1 0x140008
1570 /* [RW 1] Init bit for port 4. When set the initial credit of port 4 is
1571 copied to the credit register. Should be set and then reset after the
1572 configuration of the port has ended. */
1573 #define PBF_REG_INIT_P4 0x14000c
1574 /* [RW 1] Enable for mac interface 0. */
1575 #define PBF_REG_MAC_IF0_ENABLE 0x140030
1576 /* [RW 1] Enable for mac interface 1. */
1577 #define PBF_REG_MAC_IF1_ENABLE 0x140034
1578 /* [RW 1] Enable for the loopback interface. */
1579 #define PBF_REG_MAC_LB_ENABLE 0x140040
1580 /* [RW 10] Port 0 threshold used by arbiter in 16 byte lines used when pause
1581 not suppoterd. */
1582 #define PBF_REG_P0_ARB_THRSH 0x1400e4
1583 /* [R 11] Current credit for port 0 in the tx port buffers in 16 byte lines. */
1584 #define PBF_REG_P0_CREDIT 0x140200
1585 /* [RW 11] Initial credit for port 0 in the tx port buffers in 16 byte
1586 lines. */
1587 #define PBF_REG_P0_INIT_CRD 0x1400d0
1588 /* [RW 1] Indication that pause is enabled for port 0. */
1589 #define PBF_REG_P0_PAUSE_ENABLE 0x140014
1590 /* [R 8] Number of tasks in port 0 task queue. */
1591 #define PBF_REG_P0_TASK_CNT 0x140204
1592 /* [R 11] Current credit for port 1 in the tx port buffers in 16 byte lines. */
1593 #define PBF_REG_P1_CREDIT 0x140208
1594 /* [RW 11] Initial credit for port 1 in the tx port buffers in 16 byte
1595 lines. */
1596 #define PBF_REG_P1_INIT_CRD 0x1400d4
1597 /* [R 8] Number of tasks in port 1 task queue. */
1598 #define PBF_REG_P1_TASK_CNT 0x14020c
1599 /* [R 11] Current credit for port 4 in the tx port buffers in 16 byte lines. */
1600 #define PBF_REG_P4_CREDIT 0x140210
1601 /* [RW 11] Initial credit for port 4 in the tx port buffers in 16 byte
1602 lines. */
1603 #define PBF_REG_P4_INIT_CRD 0x1400e0
1604 /* [R 8] Number of tasks in port 4 task queue. */
1605 #define PBF_REG_P4_TASK_CNT 0x140214
1606 /* [RW 5] Interrupt mask register #0 read/write */
1607 #define PBF_REG_PBF_INT_MASK 0x1401d4
1608 /* [R 5] Interrupt register #0 read */
1609 #define PBF_REG_PBF_INT_STS 0x1401c8
1610 #define PB_REG_CONTROL 0
1611 /* [RW 2] Interrupt mask register #0 read/write */
1612 #define PB_REG_PB_INT_MASK 0x28
1613 /* [R 2] Interrupt register #0 read */
1614 #define PB_REG_PB_INT_STS 0x1c
1615 /* [RW 4] Parity mask register #0 read/write */
1616 #define PB_REG_PB_PRTY_MASK 0x38
1617 /* [R 4] Parity register #0 read */
1618 #define PB_REG_PB_PRTY_STS 0x2c
1619 #define PRS_REG_A_PRSU_20 0x40134
1620 /* [R 8] debug only: CFC load request current credit. Transaction based. */
1621 #define PRS_REG_CFC_LD_CURRENT_CREDIT 0x40164
1622 /* [R 8] debug only: CFC search request current credit. Transaction based. */
1623 #define PRS_REG_CFC_SEARCH_CURRENT_CREDIT 0x40168
1624 /* [RW 6] The initial credit for the search message to the CFC interface.
1625 Credit is transaction based. */
1626 #define PRS_REG_CFC_SEARCH_INITIAL_CREDIT 0x4011c
1627 /* [RW 24] CID for port 0 if no match */
1628 #define PRS_REG_CID_PORT_0 0x400fc
1629 #define PRS_REG_CID_PORT_1 0x40100
1630 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
1631 load response is reset and packet type is 0. Used in packet start message
1632 to TCM. */
1633 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0 0x400dc
1634 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1 0x400e0
1635 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2 0x400e4
1636 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3 0x400e8
1637 #define PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4 0x400ec
1638 /* [RW 32] The CM header for flush message where 'load existed' bit in CFC
1639 load response is set and packet type is 0. Used in packet start message
1640 to TCM. */
1641 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0 0x400bc
1642 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1 0x400c0
1643 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2 0x400c4
1644 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3 0x400c8
1645 #define PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4 0x400cc
1646 /* [RW 32] The CM header for a match and packet type 1 for loopback port.
1647 Used in packet start message to TCM. */
1648 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_1 0x4009c
1649 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_2 0x400a0
1650 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_3 0x400a4
1651 #define PRS_REG_CM_HDR_LOOPBACK_TYPE_4 0x400a8
1652 /* [RW 32] The CM header for a match and packet type 0. Used in packet start
1653 message to TCM. */
1654 #define PRS_REG_CM_HDR_TYPE_0 0x40078
1655 #define PRS_REG_CM_HDR_TYPE_1 0x4007c
1656 #define PRS_REG_CM_HDR_TYPE_2 0x40080
1657 #define PRS_REG_CM_HDR_TYPE_3 0x40084
1658 #define PRS_REG_CM_HDR_TYPE_4 0x40088
1659 /* [RW 32] The CM header in case there was not a match on the connection */
1660 #define PRS_REG_CM_NO_MATCH_HDR 0x400b8
1661 /* [RW 8] The 8-bit event ID for a match and packet type 1. Used in packet
1662 start message to TCM. */
1663 #define PRS_REG_EVENT_ID_1 0x40054
1664 #define PRS_REG_EVENT_ID_2 0x40058
1665 #define PRS_REG_EVENT_ID_3 0x4005c
1666 /* [RW 8] Context region for flush packet with packet type 0. Used in CFC
1667 load request message. */
1668 #define PRS_REG_FLUSH_REGIONS_TYPE_0 0x40004
1669 #define PRS_REG_FLUSH_REGIONS_TYPE_1 0x40008
1670 #define PRS_REG_FLUSH_REGIONS_TYPE_2 0x4000c
1671 #define PRS_REG_FLUSH_REGIONS_TYPE_3 0x40010
1672 #define PRS_REG_FLUSH_REGIONS_TYPE_4 0x40014
1673 #define PRS_REG_FLUSH_REGIONS_TYPE_5 0x40018
1674 #define PRS_REG_FLUSH_REGIONS_TYPE_6 0x4001c
1675 #define PRS_REG_FLUSH_REGIONS_TYPE_7 0x40020
1676 /* [RW 4] The increment value to send in the CFC load request message */
1677 #define PRS_REG_INC_VALUE 0x40048
1678 /* [RW 1] If set indicates not to send messages to CFC on received packets */
1679 #define PRS_REG_NIC_MODE 0x40138
1680 /* [RW 8] The 8-bit event ID for cases where there is no match on the
1681 connection. Used in packet start message to TCM. */
1682 #define PRS_REG_NO_MATCH_EVENT_ID 0x40070
1683 /* [ST 24] The number of input CFC flush packets */
1684 #define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES 0x40128
1685 /* [ST 32] The number of cycles the Parser halted its operation since it
1686 could not allocate the next serial number */
1687 #define PRS_REG_NUM_OF_DEAD_CYCLES 0x40130
1688 /* [ST 24] The number of input packets */
1689 #define PRS_REG_NUM_OF_PACKETS 0x40124
1690 /* [ST 24] The number of input transparent flush packets */
1691 #define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES 0x4012c
1692 /* [RW 8] Context region for received Ethernet packet with a match and
1693 packet type 0. Used in CFC load request message */
1694 #define PRS_REG_PACKET_REGIONS_TYPE_0 0x40028
1695 #define PRS_REG_PACKET_REGIONS_TYPE_1 0x4002c
1696 #define PRS_REG_PACKET_REGIONS_TYPE_2 0x40030
1697 #define PRS_REG_PACKET_REGIONS_TYPE_3 0x40034
1698 #define PRS_REG_PACKET_REGIONS_TYPE_4 0x40038
1699 #define PRS_REG_PACKET_REGIONS_TYPE_5 0x4003c
1700 #define PRS_REG_PACKET_REGIONS_TYPE_6 0x40040
1701 #define PRS_REG_PACKET_REGIONS_TYPE_7 0x40044
1702 /* [R 2] debug only: Number of pending requests for CAC on port 0. */
1703 #define PRS_REG_PENDING_BRB_CAC0_RQ 0x40174
1704 /* [R 2] debug only: Number of pending requests for header parsing. */
1705 #define PRS_REG_PENDING_BRB_PRS_RQ 0x40170
1706 /* [R 1] Interrupt register #0 read */
1707 #define PRS_REG_PRS_INT_STS 0x40188
1708 /* [RW 8] Parity mask register #0 read/write */
1709 #define PRS_REG_PRS_PRTY_MASK 0x401a4
1710 /* [R 8] Parity register #0 read */
1711 #define PRS_REG_PRS_PRTY_STS 0x40198
1712 /* [RW 8] Context region for pure acknowledge packets. Used in CFC load
1713 request message */
1714 #define PRS_REG_PURE_REGIONS 0x40024
1715 /* [R 32] debug only: Serial number status lsb 32 bits. '1' indicates this
1716 serail number was released by SDM but cannot be used because a previous
1717 serial number was not released. */
1718 #define PRS_REG_SERIAL_NUM_STATUS_LSB 0x40154
1719 /* [R 32] debug only: Serial number status msb 32 bits. '1' indicates this
1720 serail number was released by SDM but cannot be used because a previous
1721 serial number was not released. */
1722 #define PRS_REG_SERIAL_NUM_STATUS_MSB 0x40158
1723 /* [R 4] debug only: SRC current credit. Transaction based. */
1724 #define PRS_REG_SRC_CURRENT_CREDIT 0x4016c
1725 /* [R 8] debug only: TCM current credit. Cycle based. */
1726 #define PRS_REG_TCM_CURRENT_CREDIT 0x40160
1727 /* [R 8] debug only: TSDM current credit. Transaction based. */
1728 #define PRS_REG_TSDM_CURRENT_CREDIT 0x4015c
1729 /* [R 6] Debug only: Number of used entries in the data FIFO */
1730 #define PXP2_REG_HST_DATA_FIFO_STATUS 0x12047c
1731 /* [R 7] Debug only: Number of used entries in the header FIFO */
1732 #define PXP2_REG_HST_HEADER_FIFO_STATUS 0x120478
1733 #define PXP2_REG_PGL_CONTROL0 0x120490
1734 #define PXP2_REG_PGL_CONTROL1 0x120514
1735 /* [RW 32] Inbound interrupt table for CSDM: bits[31:16]-mask;
1736 its[15:0]-address */
1737 #define PXP2_REG_PGL_INT_CSDM_0 0x1204f4
1738 #define PXP2_REG_PGL_INT_CSDM_1 0x1204f8
1739 #define PXP2_REG_PGL_INT_CSDM_2 0x1204fc
1740 #define PXP2_REG_PGL_INT_CSDM_3 0x120500
1741 #define PXP2_REG_PGL_INT_CSDM_4 0x120504
1742 #define PXP2_REG_PGL_INT_CSDM_5 0x120508
1743 #define PXP2_REG_PGL_INT_CSDM_6 0x12050c
1744 #define PXP2_REG_PGL_INT_CSDM_7 0x120510
1745 /* [RW 32] Inbound interrupt table for TSDM: bits[31:16]-mask;
1746 its[15:0]-address */
1747 #define PXP2_REG_PGL_INT_TSDM_0 0x120494
1748 #define PXP2_REG_PGL_INT_TSDM_1 0x120498
1749 #define PXP2_REG_PGL_INT_TSDM_2 0x12049c
1750 #define PXP2_REG_PGL_INT_TSDM_3 0x1204a0
1751 #define PXP2_REG_PGL_INT_TSDM_4 0x1204a4
1752 #define PXP2_REG_PGL_INT_TSDM_5 0x1204a8
1753 #define PXP2_REG_PGL_INT_TSDM_6 0x1204ac
1754 #define PXP2_REG_PGL_INT_TSDM_7 0x1204b0
1755 /* [RW 32] Inbound interrupt table for USDM: bits[31:16]-mask;
1756 its[15:0]-address */
1757 #define PXP2_REG_PGL_INT_USDM_0 0x1204b4
1758 #define PXP2_REG_PGL_INT_USDM_1 0x1204b8
1759 #define PXP2_REG_PGL_INT_USDM_2 0x1204bc
1760 #define PXP2_REG_PGL_INT_USDM_3 0x1204c0
1761 #define PXP2_REG_PGL_INT_USDM_4 0x1204c4
1762 #define PXP2_REG_PGL_INT_USDM_5 0x1204c8
1763 #define PXP2_REG_PGL_INT_USDM_6 0x1204cc
1764 #define PXP2_REG_PGL_INT_USDM_7 0x1204d0
1765 /* [RW 32] Inbound interrupt table for XSDM: bits[31:16]-mask;
1766 its[15:0]-address */
1767 #define PXP2_REG_PGL_INT_XSDM_0 0x1204d4
1768 #define PXP2_REG_PGL_INT_XSDM_1 0x1204d8
1769 #define PXP2_REG_PGL_INT_XSDM_2 0x1204dc
1770 #define PXP2_REG_PGL_INT_XSDM_3 0x1204e0
1771 #define PXP2_REG_PGL_INT_XSDM_4 0x1204e4
1772 #define PXP2_REG_PGL_INT_XSDM_5 0x1204e8
1773 #define PXP2_REG_PGL_INT_XSDM_6 0x1204ec
1774 #define PXP2_REG_PGL_INT_XSDM_7 0x1204f0
1775 /* [R 1] this bit indicates that a read request was blocked because of
1776 bus_master_en was deasserted */
1777 #define PXP2_REG_PGL_READ_BLOCKED 0x120568
1778 /* [R 6] debug only */
1779 #define PXP2_REG_PGL_TXR_CDTS 0x120528
1780 /* [R 18] debug only */
1781 #define PXP2_REG_PGL_TXW_CDTS 0x12052c
1782 /* [R 1] this bit indicates that a write request was blocked because of
1783 bus_master_en was deasserted */
1784 #define PXP2_REG_PGL_WRITE_BLOCKED 0x120564
1785 #define PXP2_REG_PSWRQ_BW_ADD1 0x1201c0
1786 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
1787 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
1788 #define PXP2_REG_PSWRQ_BW_ADD10 0x1201e4
1789 #define PXP2_REG_PSWRQ_BW_ADD11 0x1201e8
1790 #define PXP2_REG_PSWRQ_BW_ADD2 0x1201c4
1791 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228
1792 #define PXP2_REG_PSWRQ_BW_ADD28 0x120228
1793 #define PXP2_REG_PSWRQ_BW_ADD3 0x1201c8
1794 #define PXP2_REG_PSWRQ_BW_ADD6 0x1201d4
1795 #define PXP2_REG_PSWRQ_BW_ADD7 0x1201d8
1796 #define PXP2_REG_PSWRQ_BW_ADD8 0x1201dc
1797 #define PXP2_REG_PSWRQ_BW_ADD9 0x1201e0
1798 #define PXP2_REG_PSWRQ_BW_CREDIT 0x12032c
1799 #define PXP2_REG_PSWRQ_BW_L1 0x1202b0
1800 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4
1801 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8
1802 #define PXP2_REG_PSWRQ_BW_L10 0x1202d4
1803 #define PXP2_REG_PSWRQ_BW_L11 0x1202d8
1804 #define PXP2_REG_PSWRQ_BW_L2 0x1202b4
1805 #define PXP2_REG_PSWRQ_BW_L28 0x120318
1806 #define PXP2_REG_PSWRQ_BW_L28 0x120318
1807 #define PXP2_REG_PSWRQ_BW_L3 0x1202b8
1808 #define PXP2_REG_PSWRQ_BW_L6 0x1202c4
1809 #define PXP2_REG_PSWRQ_BW_L7 0x1202c8
1810 #define PXP2_REG_PSWRQ_BW_L8 0x1202cc
1811 #define PXP2_REG_PSWRQ_BW_L9 0x1202d0
1812 #define PXP2_REG_PSWRQ_BW_RD 0x120324
1813 #define PXP2_REG_PSWRQ_BW_UB1 0x120238
1814 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c
1815 #define PXP2_REG_PSWRQ_BW_UB11 0x120260
1816 #define PXP2_REG_PSWRQ_BW_UB10 0x12025c
1817 #define PXP2_REG_PSWRQ_BW_UB11 0x120260
1818 #define PXP2_REG_PSWRQ_BW_UB2 0x12023c
1819 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
1820 #define PXP2_REG_PSWRQ_BW_UB28 0x1202a0
1821 #define PXP2_REG_PSWRQ_BW_UB3 0x120240
1822 #define PXP2_REG_PSWRQ_BW_UB6 0x12024c
1823 #define PXP2_REG_PSWRQ_BW_UB7 0x120250
1824 #define PXP2_REG_PSWRQ_BW_UB8 0x120254
1825 #define PXP2_REG_PSWRQ_BW_UB9 0x120258
1826 #define PXP2_REG_PSWRQ_BW_WR 0x120328
1827 #define PXP2_REG_PSWRQ_CDU0_L2P 0x120000
1828 #define PXP2_REG_PSWRQ_QM0_L2P 0x120038
1829 #define PXP2_REG_PSWRQ_SRC0_L2P 0x120054
1830 #define PXP2_REG_PSWRQ_TM0_L2P 0x12001c
1831 /* [RW 25] Interrupt mask register #0 read/write */
1832 #define PXP2_REG_PXP2_INT_MASK 0x120578
1833 /* [R 25] Interrupt register #0 read */
1834 #define PXP2_REG_PXP2_INT_STS 0x12056c
1835 /* [RC 25] Interrupt register #0 read clear */
1836 #define PXP2_REG_PXP2_INT_STS_CLR 0x120570
1837 /* [RW 32] Parity mask register #0 read/write */
1838 #define PXP2_REG_PXP2_PRTY_MASK_0 0x120588
1839 #define PXP2_REG_PXP2_PRTY_MASK_1 0x120598
1840 /* [R 32] Parity register #0 read */
1841 #define PXP2_REG_PXP2_PRTY_STS_0 0x12057c
1842 #define PXP2_REG_PXP2_PRTY_STS_1 0x12058c
1843 /* [R 1] Debug only: The 'almost full' indication from each fifo (gives
1844 indication about backpressure) */
1845 #define PXP2_REG_RD_ALMOST_FULL_0 0x120424
1846 /* [R 8] Debug only: The blocks counter - number of unused block ids */
1847 #define PXP2_REG_RD_BLK_CNT 0x120418
1848 /* [RW 8] Debug only: Total number of available blocks in Tetris Buffer.
1849 Must be bigger than 6. Normally should not be changed. */
1850 #define PXP2_REG_RD_BLK_NUM_CFG 0x12040c
1851 /* [RW 2] CDU byte swapping mode configuration for master read requests */
1852 #define PXP2_REG_RD_CDURD_SWAP_MODE 0x120404
1853 /* [RW 1] When '1'; inputs to the PSWRD block are ignored */
1854 #define PXP2_REG_RD_DISABLE_INPUTS 0x120374
1855 /* [R 1] PSWRD internal memories initialization is done */
1856 #define PXP2_REG_RD_INIT_DONE 0x120370
1857 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1858 allocated for vq10 */
1859 #define PXP2_REG_RD_MAX_BLKS_VQ10 0x1203a0
1860 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1861 allocated for vq11 */
1862 #define PXP2_REG_RD_MAX_BLKS_VQ11 0x1203a4
1863 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1864 allocated for vq17 */
1865 #define PXP2_REG_RD_MAX_BLKS_VQ17 0x1203bc
1866 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1867 allocated for vq18 */
1868 #define PXP2_REG_RD_MAX_BLKS_VQ18 0x1203c0
1869 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1870 allocated for vq19 */
1871 #define PXP2_REG_RD_MAX_BLKS_VQ19 0x1203c4
1872 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1873 allocated for vq22 */
1874 #define PXP2_REG_RD_MAX_BLKS_VQ22 0x1203d0
1875 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1876 allocated for vq6 */
1877 #define PXP2_REG_RD_MAX_BLKS_VQ6 0x120390
1878 /* [RW 8] The maximum number of blocks in Tetris Buffer that can be
1879 allocated for vq9 */
1880 #define PXP2_REG_RD_MAX_BLKS_VQ9 0x12039c
1881 /* [RW 2] PBF byte swapping mode configuration for master read requests */
1882 #define PXP2_REG_RD_PBF_SWAP_MODE 0x1203f4
1883 /* [R 1] Debug only: Indication if delivery ports are idle */
1884 #define PXP2_REG_RD_PORT_IS_IDLE_0 0x12041c
1885 #define PXP2_REG_RD_PORT_IS_IDLE_1 0x120420
1886 /* [RW 2] QM byte swapping mode configuration for master read requests */
1887 #define PXP2_REG_RD_QM_SWAP_MODE 0x1203f8
1888 /* [R 7] Debug only: The SR counter - number of unused sub request ids */
1889 #define PXP2_REG_RD_SR_CNT 0x120414
1890 /* [RW 2] SRC byte swapping mode configuration for master read requests */
1891 #define PXP2_REG_RD_SRC_SWAP_MODE 0x120400
1892 /* [RW 7] Debug only: Total number of available PCI read sub-requests. Must
1893 be bigger than 1. Normally should not be changed. */
1894 #define PXP2_REG_RD_SR_NUM_CFG 0x120408
1895 /* [RW 1] Signals the PSWRD block to start initializing internal memories */
1896 #define PXP2_REG_RD_START_INIT 0x12036c
1897 /* [RW 2] TM byte swapping mode configuration for master read requests */
1898 #define PXP2_REG_RD_TM_SWAP_MODE 0x1203fc
1899 /* [RW 10] Bandwidth addition to VQ0 write requests */
1900 #define PXP2_REG_RQ_BW_RD_ADD0 0x1201bc
1901 /* [RW 10] Bandwidth addition to VQ12 read requests */
1902 #define PXP2_REG_RQ_BW_RD_ADD12 0x1201ec
1903 /* [RW 10] Bandwidth addition to VQ13 read requests */
1904 #define PXP2_REG_RQ_BW_RD_ADD13 0x1201f0
1905 /* [RW 10] Bandwidth addition to VQ14 read requests */
1906 #define PXP2_REG_RQ_BW_RD_ADD14 0x1201f4
1907 /* [RW 10] Bandwidth addition to VQ15 read requests */
1908 #define PXP2_REG_RQ_BW_RD_ADD15 0x1201f8
1909 /* [RW 10] Bandwidth addition to VQ16 read requests */
1910 #define PXP2_REG_RQ_BW_RD_ADD16 0x1201fc
1911 /* [RW 10] Bandwidth addition to VQ17 read requests */
1912 #define PXP2_REG_RQ_BW_RD_ADD17 0x120200
1913 /* [RW 10] Bandwidth addition to VQ18 read requests */
1914 #define PXP2_REG_RQ_BW_RD_ADD18 0x120204
1915 /* [RW 10] Bandwidth addition to VQ19 read requests */
1916 #define PXP2_REG_RQ_BW_RD_ADD19 0x120208
1917 /* [RW 10] Bandwidth addition to VQ20 read requests */
1918 #define PXP2_REG_RQ_BW_RD_ADD20 0x12020c
1919 /* [RW 10] Bandwidth addition to VQ22 read requests */
1920 #define PXP2_REG_RQ_BW_RD_ADD22 0x120210
1921 /* [RW 10] Bandwidth addition to VQ23 read requests */
1922 #define PXP2_REG_RQ_BW_RD_ADD23 0x120214
1923 /* [RW 10] Bandwidth addition to VQ24 read requests */
1924 #define PXP2_REG_RQ_BW_RD_ADD24 0x120218
1925 /* [RW 10] Bandwidth addition to VQ25 read requests */
1926 #define PXP2_REG_RQ_BW_RD_ADD25 0x12021c
1927 /* [RW 10] Bandwidth addition to VQ26 read requests */
1928 #define PXP2_REG_RQ_BW_RD_ADD26 0x120220
1929 /* [RW 10] Bandwidth addition to VQ27 read requests */
1930 #define PXP2_REG_RQ_BW_RD_ADD27 0x120224
1931 /* [RW 10] Bandwidth addition to VQ4 read requests */
1932 #define PXP2_REG_RQ_BW_RD_ADD4 0x1201cc
1933 /* [RW 10] Bandwidth addition to VQ5 read requests */
1934 #define PXP2_REG_RQ_BW_RD_ADD5 0x1201d0
1935 /* [RW 10] Bandwidth Typical L for VQ0 Read requests */
1936 #define PXP2_REG_RQ_BW_RD_L0 0x1202ac
1937 /* [RW 10] Bandwidth Typical L for VQ12 Read requests */
1938 #define PXP2_REG_RQ_BW_RD_L12 0x1202dc
1939 /* [RW 10] Bandwidth Typical L for VQ13 Read requests */
1940 #define PXP2_REG_RQ_BW_RD_L13 0x1202e0
1941 /* [RW 10] Bandwidth Typical L for VQ14 Read requests */
1942 #define PXP2_REG_RQ_BW_RD_L14 0x1202e4
1943 /* [RW 10] Bandwidth Typical L for VQ15 Read requests */
1944 #define PXP2_REG_RQ_BW_RD_L15 0x1202e8
1945 /* [RW 10] Bandwidth Typical L for VQ16 Read requests */
1946 #define PXP2_REG_RQ_BW_RD_L16 0x1202ec
1947 /* [RW 10] Bandwidth Typical L for VQ17 Read requests */
1948 #define PXP2_REG_RQ_BW_RD_L17 0x1202f0
1949 /* [RW 10] Bandwidth Typical L for VQ18 Read requests */
1950 #define PXP2_REG_RQ_BW_RD_L18 0x1202f4
1951 /* [RW 10] Bandwidth Typical L for VQ19 Read requests */
1952 #define PXP2_REG_RQ_BW_RD_L19 0x1202f8
1953 /* [RW 10] Bandwidth Typical L for VQ20 Read requests */
1954 #define PXP2_REG_RQ_BW_RD_L20 0x1202fc
1955 /* [RW 10] Bandwidth Typical L for VQ22 Read requests */
1956 #define PXP2_REG_RQ_BW_RD_L22 0x120300
1957 /* [RW 10] Bandwidth Typical L for VQ23 Read requests */
1958 #define PXP2_REG_RQ_BW_RD_L23 0x120304
1959 /* [RW 10] Bandwidth Typical L for VQ24 Read requests */
1960 #define PXP2_REG_RQ_BW_RD_L24 0x120308
1961 /* [RW 10] Bandwidth Typical L for VQ25 Read requests */
1962 #define PXP2_REG_RQ_BW_RD_L25 0x12030c
1963 /* [RW 10] Bandwidth Typical L for VQ26 Read requests */
1964 #define PXP2_REG_RQ_BW_RD_L26 0x120310
1965 /* [RW 10] Bandwidth Typical L for VQ27 Read requests */
1966 #define PXP2_REG_RQ_BW_RD_L27 0x120314
1967 /* [RW 10] Bandwidth Typical L for VQ4 Read requests */
1968 #define PXP2_REG_RQ_BW_RD_L4 0x1202bc
1969 /* [RW 10] Bandwidth Typical L for VQ5 Read- currently not used */
1970 #define PXP2_REG_RQ_BW_RD_L5 0x1202c0
1971 /* [RW 7] Bandwidth upper bound for VQ0 read requests */
1972 #define PXP2_REG_RQ_BW_RD_UBOUND0 0x120234
1973 /* [RW 7] Bandwidth upper bound for VQ12 read requests */
1974 #define PXP2_REG_RQ_BW_RD_UBOUND12 0x120264
1975 /* [RW 7] Bandwidth upper bound for VQ13 read requests */
1976 #define PXP2_REG_RQ_BW_RD_UBOUND13 0x120268
1977 /* [RW 7] Bandwidth upper bound for VQ14 read requests */
1978 #define PXP2_REG_RQ_BW_RD_UBOUND14 0x12026c
1979 /* [RW 7] Bandwidth upper bound for VQ15 read requests */
1980 #define PXP2_REG_RQ_BW_RD_UBOUND15 0x120270
1981 /* [RW 7] Bandwidth upper bound for VQ16 read requests */
1982 #define PXP2_REG_RQ_BW_RD_UBOUND16 0x120274
1983 /* [RW 7] Bandwidth upper bound for VQ17 read requests */
1984 #define PXP2_REG_RQ_BW_RD_UBOUND17 0x120278
1985 /* [RW 7] Bandwidth upper bound for VQ18 read requests */
1986 #define PXP2_REG_RQ_BW_RD_UBOUND18 0x12027c
1987 /* [RW 7] Bandwidth upper bound for VQ19 read requests */
1988 #define PXP2_REG_RQ_BW_RD_UBOUND19 0x120280
1989 /* [RW 7] Bandwidth upper bound for VQ20 read requests */
1990 #define PXP2_REG_RQ_BW_RD_UBOUND20 0x120284
1991 /* [RW 7] Bandwidth upper bound for VQ22 read requests */
1992 #define PXP2_REG_RQ_BW_RD_UBOUND22 0x120288
1993 /* [RW 7] Bandwidth upper bound for VQ23 read requests */
1994 #define PXP2_REG_RQ_BW_RD_UBOUND23 0x12028c
1995 /* [RW 7] Bandwidth upper bound for VQ24 read requests */
1996 #define PXP2_REG_RQ_BW_RD_UBOUND24 0x120290
1997 /* [RW 7] Bandwidth upper bound for VQ25 read requests */
1998 #define PXP2_REG_RQ_BW_RD_UBOUND25 0x120294
1999 /* [RW 7] Bandwidth upper bound for VQ26 read requests */
2000 #define PXP2_REG_RQ_BW_RD_UBOUND26 0x120298
2001 /* [RW 7] Bandwidth upper bound for VQ27 read requests */
2002 #define PXP2_REG_RQ_BW_RD_UBOUND27 0x12029c
2003 /* [RW 7] Bandwidth upper bound for VQ4 read requests */
2004 #define PXP2_REG_RQ_BW_RD_UBOUND4 0x120244
2005 /* [RW 7] Bandwidth upper bound for VQ5 read requests */
2006 #define PXP2_REG_RQ_BW_RD_UBOUND5 0x120248
2007 /* [RW 10] Bandwidth addition to VQ29 write requests */
2008 #define PXP2_REG_RQ_BW_WR_ADD29 0x12022c
2009 /* [RW 10] Bandwidth addition to VQ30 write requests */
2010 #define PXP2_REG_RQ_BW_WR_ADD30 0x120230
2011 /* [RW 10] Bandwidth Typical L for VQ29 Write requests */
2012 #define PXP2_REG_RQ_BW_WR_L29 0x12031c
2013 /* [RW 10] Bandwidth Typical L for VQ30 Write requests */
2014 #define PXP2_REG_RQ_BW_WR_L30 0x120320
2015 /* [RW 7] Bandwidth upper bound for VQ29 */
2016 #define PXP2_REG_RQ_BW_WR_UBOUND29 0x1202a4
2017 /* [RW 7] Bandwidth upper bound for VQ30 */
2018 #define PXP2_REG_RQ_BW_WR_UBOUND30 0x1202a8
2019 /* [RW 2] Endian mode for cdu */
2020 #define PXP2_REG_RQ_CDU_ENDIAN_M 0x1201a0
2021 /* [RW 3] page size in L2P table for CDU module; -4k; -8k; -16k; -32k; -64k;
2022 -128k */
2023 #define PXP2_REG_RQ_CDU_P_SIZE 0x120018
2024 /* [R 1] 1' indicates that the requester has finished its internal
2025 configuration */
2026 #define PXP2_REG_RQ_CFG_DONE 0x1201b4
2027 /* [RW 2] Endian mode for debug */
2028 #define PXP2_REG_RQ_DBG_ENDIAN_M 0x1201a4
2029 /* [RW 1] When '1'; requests will enter input buffers but wont get out
2030 towards the glue */
2031 #define PXP2_REG_RQ_DISABLE_INPUTS 0x120330
2032 /* [RW 2] Endian mode for hc */
2033 #define PXP2_REG_RQ_HC_ENDIAN_M 0x1201a8
2034 /* [WB 53] Onchip address table */
2035 #define PXP2_REG_RQ_ONCHIP_AT 0x122000
2036 /* [RW 13] Pending read limiter threshold; in Dwords */
2037 #define PXP2_REG_RQ_PDR_LIMIT 0x12033c
2038 /* [RW 2] Endian mode for qm */
2039 #define PXP2_REG_RQ_QM_ENDIAN_M 0x120194
2040 /* [RW 3] page size in L2P table for QM module; -4k; -8k; -16k; -32k; -64k;
2041 -128k */
2042 #define PXP2_REG_RQ_QM_P_SIZE 0x120050
2043 /* [RW 1] 1' indicates that the RBC has finished configurating the PSWRQ */
2044 #define PXP2_REG_RQ_RBC_DONE 0x1201b0
2045 /* [RW 3] Max burst size filed for read requests port 0; 000 - 128B;
2046 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
2047 #define PXP2_REG_RQ_RD_MBS0 0x120160
2048 /* [RW 3] Max burst size filed for read requests port 1; 000 - 128B;
2049 001:256B; 010: 512B; 11:1K:100:2K; 01:4K */
2050 #define PXP2_REG_RQ_RD_MBS1 0x120168
2051 /* [RW 2] Endian mode for src */
2052 #define PXP2_REG_RQ_SRC_ENDIAN_M 0x12019c
2053 /* [RW 3] page size in L2P table for SRC module; -4k; -8k; -16k; -32k; -64k;
2054 -128k */
2055 #define PXP2_REG_RQ_SRC_P_SIZE 0x12006c
2056 /* [RW 2] Endian mode for tm */
2057 #define PXP2_REG_RQ_TM_ENDIAN_M 0x120198
2058 /* [RW 3] page size in L2P table for TM module; -4k; -8k; -16k; -32k; -64k;
2059 -128k */
2060 #define PXP2_REG_RQ_TM_P_SIZE 0x120034
2061 /* [R 5] Number of entries in the ufifo; his fifo has l2p completions */
2062 #define PXP2_REG_RQ_UFIFO_NUM_OF_ENTRY 0x12080c
2063 /* [R 8] Number of entries occupied by vq 0 in pswrq memory */
2064 #define PXP2_REG_RQ_VQ0_ENTRY_CNT 0x120810
2065 /* [R 8] Number of entries occupied by vq 10 in pswrq memory */
2066 #define PXP2_REG_RQ_VQ10_ENTRY_CNT 0x120818
2067 /* [R 8] Number of entries occupied by vq 11 in pswrq memory */
2068 #define PXP2_REG_RQ_VQ11_ENTRY_CNT 0x120820
2069 /* [R 8] Number of entries occupied by vq 12 in pswrq memory */
2070 #define PXP2_REG_RQ_VQ12_ENTRY_CNT 0x120828
2071 /* [R 8] Number of entries occupied by vq 13 in pswrq memory */
2072 #define PXP2_REG_RQ_VQ13_ENTRY_CNT 0x120830
2073 /* [R 8] Number of entries occupied by vq 14 in pswrq memory */
2074 #define PXP2_REG_RQ_VQ14_ENTRY_CNT 0x120838
2075 /* [R 8] Number of entries occupied by vq 15 in pswrq memory */
2076 #define PXP2_REG_RQ_VQ15_ENTRY_CNT 0x120840
2077 /* [R 8] Number of entries occupied by vq 16 in pswrq memory */
2078 #define PXP2_REG_RQ_VQ16_ENTRY_CNT 0x120848
2079 /* [R 8] Number of entries occupied by vq 17 in pswrq memory */
2080 #define PXP2_REG_RQ_VQ17_ENTRY_CNT 0x120850
2081 /* [R 8] Number of entries occupied by vq 18 in pswrq memory */
2082 #define PXP2_REG_RQ_VQ18_ENTRY_CNT 0x120858
2083 /* [R 8] Number of entries occupied by vq 19 in pswrq memory */
2084 #define PXP2_REG_RQ_VQ19_ENTRY_CNT 0x120860
2085 /* [R 8] Number of entries occupied by vq 1 in pswrq memory */
2086 #define PXP2_REG_RQ_VQ1_ENTRY_CNT 0x120868
2087 /* [R 8] Number of entries occupied by vq 20 in pswrq memory */
2088 #define PXP2_REG_RQ_VQ20_ENTRY_CNT 0x120870
2089 /* [R 8] Number of entries occupied by vq 21 in pswrq memory */
2090 #define PXP2_REG_RQ_VQ21_ENTRY_CNT 0x120878
2091 /* [R 8] Number of entries occupied by vq 22 in pswrq memory */
2092 #define PXP2_REG_RQ_VQ22_ENTRY_CNT 0x120880
2093 /* [R 8] Number of entries occupied by vq 23 in pswrq memory */
2094 #define PXP2_REG_RQ_VQ23_ENTRY_CNT 0x120888
2095 /* [R 8] Number of entries occupied by vq 24 in pswrq memory */
2096 #define PXP2_REG_RQ_VQ24_ENTRY_CNT 0x120890
2097 /* [R 8] Number of entries occupied by vq 25 in pswrq memory */
2098 #define PXP2_REG_RQ_VQ25_ENTRY_CNT 0x120898
2099 /* [R 8] Number of entries occupied by vq 26 in pswrq memory */
2100 #define PXP2_REG_RQ_VQ26_ENTRY_CNT 0x1208a0
2101 /* [R 8] Number of entries occupied by vq 27 in pswrq memory */
2102 #define PXP2_REG_RQ_VQ27_ENTRY_CNT 0x1208a8
2103 /* [R 8] Number of entries occupied by vq 28 in pswrq memory */
2104 #define PXP2_REG_RQ_VQ28_ENTRY_CNT 0x1208b0
2105 /* [R 8] Number of entries occupied by vq 29 in pswrq memory */
2106 #define PXP2_REG_RQ_VQ29_ENTRY_CNT 0x1208b8
2107 /* [R 8] Number of entries occupied by vq 2 in pswrq memory */
2108 #define PXP2_REG_RQ_VQ2_ENTRY_CNT 0x1208c0
2109 /* [R 8] Number of entries occupied by vq 30 in pswrq memory */
2110 #define PXP2_REG_RQ_VQ30_ENTRY_CNT 0x1208c8
2111 /* [R 8] Number of entries occupied by vq 31 in pswrq memory */
2112 #define PXP2_REG_RQ_VQ31_ENTRY_CNT 0x1208d0
2113 /* [R 8] Number of entries occupied by vq 3 in pswrq memory */
2114 #define PXP2_REG_RQ_VQ3_ENTRY_CNT 0x1208d8
2115 /* [R 8] Number of entries occupied by vq 4 in pswrq memory */
2116 #define PXP2_REG_RQ_VQ4_ENTRY_CNT 0x1208e0
2117 /* [R 8] Number of entries occupied by vq 5 in pswrq memory */
2118 #define PXP2_REG_RQ_VQ5_ENTRY_CNT 0x1208e8
2119 /* [R 8] Number of entries occupied by vq 6 in pswrq memory */
2120 #define PXP2_REG_RQ_VQ6_ENTRY_CNT 0x1208f0
2121 /* [R 8] Number of entries occupied by vq 7 in pswrq memory */
2122 #define PXP2_REG_RQ_VQ7_ENTRY_CNT 0x1208f8
2123 /* [R 8] Number of entries occupied by vq 8 in pswrq memory */
2124 #define PXP2_REG_RQ_VQ8_ENTRY_CNT 0x120900
2125 /* [R 8] Number of entries occupied by vq 9 in pswrq memory */
2126 #define PXP2_REG_RQ_VQ9_ENTRY_CNT 0x120908
2127 /* [RW 3] Max burst size filed for write requests port 0; 000 - 128B;
2128 001:256B; 010: 512B; */
2129 #define PXP2_REG_RQ_WR_MBS0 0x12015c
2130 /* [RW 3] Max burst size filed for write requests port 1; 000 - 128B;
2131 001:256B; 010: 512B; */
2132 #define PXP2_REG_RQ_WR_MBS1 0x120164
2133 /* [RW 10] if Number of entries in dmae fifo will be higer than this
2134 threshold then has_payload indication will be asserted; the default value
2135 should be equal to > write MBS size! */
2136 #define PXP2_REG_WR_DMAE_TH 0x120368
2137 /* [RW 10] if Number of entries in usdmdp fifo will be higer than this
2138 threshold then has_payload indication will be asserted; the default value
2139 should be equal to > write MBS size! */
2140 #define PXP2_REG_WR_USDMDP_TH 0x120348
2141 /* [R 1] debug only: Indication if PSWHST arbiter is idle */
2142 #define PXP_REG_HST_ARB_IS_IDLE 0x103004
2143 /* [R 8] debug only: A bit mask for all PSWHST arbiter clients. '1' means
2144 this client is waiting for the arbiter. */
2145 #define PXP_REG_HST_CLIENTS_WAITING_TO_ARB 0x103008
2146 /* [WB 160] Used for initialization of the inbound interrupts memory */
2147 #define PXP_REG_HST_INBOUND_INT 0x103800
2148 /* [RW 32] Interrupt mask register #0 read/write */
2149 #define PXP_REG_PXP_INT_MASK_0 0x103074
2150 #define PXP_REG_PXP_INT_MASK_1 0x103084
2151 /* [R 32] Interrupt register #0 read */
2152 #define PXP_REG_PXP_INT_STS_0 0x103068
2153 #define PXP_REG_PXP_INT_STS_1 0x103078
2154 /* [RC 32] Interrupt register #0 read clear */
2155 #define PXP_REG_PXP_INT_STS_CLR_0 0x10306c
2156 /* [RW 26] Parity mask register #0 read/write */
2157 #define PXP_REG_PXP_PRTY_MASK 0x103094
2158 /* [R 26] Parity register #0 read */
2159 #define PXP_REG_PXP_PRTY_STS 0x103088
2160 /* [RW 4] The activity counter initial increment value sent in the load
2161 request */
2162 #define QM_REG_ACTCTRINITVAL_0 0x168040
2163 #define QM_REG_ACTCTRINITVAL_1 0x168044
2164 #define QM_REG_ACTCTRINITVAL_2 0x168048
2165 #define QM_REG_ACTCTRINITVAL_3 0x16804c
2166 /* [RW 32] The base logical address (in bytes) of each physical queue. The
2167 index I represents the physical queue number. The 12 lsbs are ignore and
2168 considered zero so practically there are only 20 bits in this register. */
2169 #define QM_REG_BASEADDR 0x168900
2170 /* [RW 16] The byte credit cost for each task. This value is for both ports */
2171 #define QM_REG_BYTECRDCOST 0x168234
2172 /* [RW 16] The initial byte credit value for both ports. */
2173 #define QM_REG_BYTECRDINITVAL 0x168238
2174 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2175 queue uses port 0 else it uses port 1. */
2176 #define QM_REG_BYTECRDPORT_LSB 0x168228
2177 /* [RW 32] A bit per physical queue. If the bit is cleared then the physical
2178 queue uses port 0 else it uses port 1. */
2179 #define QM_REG_BYTECRDPORT_MSB 0x168224
2180 /* [RW 16] The byte credit value that if above the QM is considered almost
2181 full */
2182 #define QM_REG_BYTECREDITAFULLTHR 0x168094
2183 /* [RW 4] The initial credit for interface */
2184 #define QM_REG_CMINITCRD_0 0x1680cc
2185 #define QM_REG_CMINITCRD_1 0x1680d0
2186 #define QM_REG_CMINITCRD_2 0x1680d4
2187 #define QM_REG_CMINITCRD_3 0x1680d8
2188 #define QM_REG_CMINITCRD_4 0x1680dc
2189 #define QM_REG_CMINITCRD_5 0x1680e0
2190 #define QM_REG_CMINITCRD_6 0x1680e4
2191 #define QM_REG_CMINITCRD_7 0x1680e8
2192 /* [RW 8] A mask bit per CM interface. If this bit is 0 then this interface
2193 is masked */
2194 #define QM_REG_CMINTEN 0x1680ec
2195 /* [RW 12] A bit vector which indicates which one of the queues are tied to
2196 interface 0 */
2197 #define QM_REG_CMINTVOQMASK_0 0x1681f4
2198 #define QM_REG_CMINTVOQMASK_1 0x1681f8
2199 #define QM_REG_CMINTVOQMASK_2 0x1681fc
2200 #define QM_REG_CMINTVOQMASK_3 0x168200
2201 #define QM_REG_CMINTVOQMASK_4 0x168204
2202 #define QM_REG_CMINTVOQMASK_5 0x168208
2203 #define QM_REG_CMINTVOQMASK_6 0x16820c
2204 #define QM_REG_CMINTVOQMASK_7 0x168210
2205 /* [RW 20] The number of connections divided by 16 which dictates the size
2206 of each queue per port 0 */
2207 #define QM_REG_CONNNUM_0 0x168020
2208 /* [R 6] Keep the fill level of the fifo from write client 4 */
2209 #define QM_REG_CQM_WRC_FIFOLVL 0x168018
2210 /* [RW 8] The context regions sent in the CFC load request */
2211 #define QM_REG_CTXREG_0 0x168030
2212 #define QM_REG_CTXREG_1 0x168034
2213 #define QM_REG_CTXREG_2 0x168038
2214 #define QM_REG_CTXREG_3 0x16803c
2215 /* [RW 12] The VOQ mask used to select the VOQs which needs to be full for
2216 bypass enable */
2217 #define QM_REG_ENBYPVOQMASK 0x16823c
2218 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
2219 physical queue uses the byte credit */
2220 #define QM_REG_ENBYTECRD_LSB 0x168220
2221 /* [RW 32] A bit mask per each physical queue. If a bit is set then the
2222 physical queue uses the byte credit */
2223 #define QM_REG_ENBYTECRD_MSB 0x16821c
2224 /* [RW 4] If cleared then the secondary interface will not be served by the
2225 RR arbiter */
2226 #define QM_REG_ENSEC 0x1680f0
2227 /* [RW 32] A bit vector per each physical queue which selects which function
2228 number to use on PCI access for that queue. */
2229 #define QM_REG_FUNCNUMSEL_LSB 0x168230
2230 /* [RW 32] A bit vector per each physical queue which selects which function
2231 number to use on PCI access for that queue. */
2232 #define QM_REG_FUNCNUMSEL_MSB 0x16822c
2233 /* [RW 32] A mask register to mask the Almost empty signals which will not
2234 be use for the almost empty indication to the HW block */
2235 #define QM_REG_HWAEMPTYMASK_LSB 0x168218
2236 /* [RW 32] A mask register to mask the Almost empty signals which will not
2237 be use for the almost empty indication to the HW block */
2238 #define QM_REG_HWAEMPTYMASK_MSB 0x168214
2239 /* [RW 4] The number of outstanding request to CFC */
2240 #define QM_REG_OUTLDREQ 0x168804
2241 /* [RC 1] A flag to indicate that overflow error occurred in one of the
2242 queues. */
2243 #define QM_REG_OVFERROR 0x16805c
2244 /* [RC 6] the Q were the qverflow occurs */
2245 #define QM_REG_OVFQNUM 0x168058
2246 /* [R 32] Pause state for physical queues 31-0 */
2247 #define QM_REG_PAUSESTATE0 0x168410
2248 /* [R 32] Pause state for physical queues 64-32 */
2249 #define QM_REG_PAUSESTATE1 0x168414
2250 /* [RW 2] The PCI attributes field used in the PCI request. */
2251 #define QM_REG_PCIREQAT 0x168054
2252 /* [R 16] The byte credit of port 0 */
2253 #define QM_REG_PORT0BYTECRD 0x168300
2254 /* [R 16] The byte credit of port 1 */
2255 #define QM_REG_PORT1BYTECRD 0x168304
2256 /* [WB 54] Pointer Table Memory; The mapping is as follow: ptrtbl[53:30]
2257 read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read bank0;
2258 ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank; */
2259 #define QM_REG_PTRTBL 0x168a00
2260 /* [RW 2] Interrupt mask register #0 read/write */
2261 #define QM_REG_QM_INT_MASK 0x168444
2262 /* [R 2] Interrupt register #0 read */
2263 #define QM_REG_QM_INT_STS 0x168438
2264 /* [RW 9] Parity mask register #0 read/write */
2265 #define QM_REG_QM_PRTY_MASK 0x168454
2266 /* [R 9] Parity register #0 read */
2267 #define QM_REG_QM_PRTY_STS 0x168448
2268 /* [R 32] Current queues in pipeline: Queues from 32 to 63 */
2269 #define QM_REG_QSTATUS_HIGH 0x16802c
2270 /* [R 32] Current queues in pipeline: Queues from 0 to 31 */
2271 #define QM_REG_QSTATUS_LOW 0x168028
2272 /* [R 24] The number of tasks queued for each queue */
2273 #define QM_REG_QTASKCTR_0 0x168308
2274 /* [RW 4] Queue tied to VOQ */
2275 #define QM_REG_QVOQIDX_0 0x1680f4
2276 #define QM_REG_QVOQIDX_10 0x16811c
2277 #define QM_REG_QVOQIDX_11 0x168120
2278 #define QM_REG_QVOQIDX_12 0x168124
2279 #define QM_REG_QVOQIDX_13 0x168128
2280 #define QM_REG_QVOQIDX_14 0x16812c
2281 #define QM_REG_QVOQIDX_15 0x168130
2282 #define QM_REG_QVOQIDX_16 0x168134
2283 #define QM_REG_QVOQIDX_17 0x168138
2284 #define QM_REG_QVOQIDX_21 0x168148
2285 #define QM_REG_QVOQIDX_25 0x168158
2286 #define QM_REG_QVOQIDX_29 0x168168
2287 #define QM_REG_QVOQIDX_32 0x168174
2288 #define QM_REG_QVOQIDX_33 0x168178
2289 #define QM_REG_QVOQIDX_34 0x16817c
2290 #define QM_REG_QVOQIDX_35 0x168180
2291 #define QM_REG_QVOQIDX_36 0x168184
2292 #define QM_REG_QVOQIDX_37 0x168188
2293 #define QM_REG_QVOQIDX_38 0x16818c
2294 #define QM_REG_QVOQIDX_39 0x168190
2295 #define QM_REG_QVOQIDX_40 0x168194
2296 #define QM_REG_QVOQIDX_41 0x168198
2297 #define QM_REG_QVOQIDX_42 0x16819c
2298 #define QM_REG_QVOQIDX_43 0x1681a0
2299 #define QM_REG_QVOQIDX_44 0x1681a4
2300 #define QM_REG_QVOQIDX_45 0x1681a8
2301 #define QM_REG_QVOQIDX_46 0x1681ac
2302 #define QM_REG_QVOQIDX_47 0x1681b0
2303 #define QM_REG_QVOQIDX_48 0x1681b4
2304 #define QM_REG_QVOQIDX_49 0x1681b8
2305 #define QM_REG_QVOQIDX_5 0x168108
2306 #define QM_REG_QVOQIDX_50 0x1681bc
2307 #define QM_REG_QVOQIDX_51 0x1681c0
2308 #define QM_REG_QVOQIDX_52 0x1681c4
2309 #define QM_REG_QVOQIDX_53 0x1681c8
2310 #define QM_REG_QVOQIDX_54 0x1681cc
2311 #define QM_REG_QVOQIDX_55 0x1681d0
2312 #define QM_REG_QVOQIDX_56 0x1681d4
2313 #define QM_REG_QVOQIDX_57 0x1681d8
2314 #define QM_REG_QVOQIDX_58 0x1681dc
2315 #define QM_REG_QVOQIDX_59 0x1681e0
2316 #define QM_REG_QVOQIDX_50 0x1681bc
2317 #define QM_REG_QVOQIDX_51 0x1681c0
2318 #define QM_REG_QVOQIDX_52 0x1681c4
2319 #define QM_REG_QVOQIDX_53 0x1681c8
2320 #define QM_REG_QVOQIDX_54 0x1681cc
2321 #define QM_REG_QVOQIDX_55 0x1681d0
2322 #define QM_REG_QVOQIDX_56 0x1681d4
2323 #define QM_REG_QVOQIDX_57 0x1681d8
2324 #define QM_REG_QVOQIDX_58 0x1681dc
2325 #define QM_REG_QVOQIDX_59 0x1681e0
2326 #define QM_REG_QVOQIDX_6 0x16810c
2327 #define QM_REG_QVOQIDX_60 0x1681e4
2328 #define QM_REG_QVOQIDX_61 0x1681e8
2329 #define QM_REG_QVOQIDX_62 0x1681ec
2330 #define QM_REG_QVOQIDX_63 0x1681f0
2331 #define QM_REG_QVOQIDX_60 0x1681e4
2332 #define QM_REG_QVOQIDX_61 0x1681e8
2333 #define QM_REG_QVOQIDX_62 0x1681ec
2334 #define QM_REG_QVOQIDX_63 0x1681f0
2335 #define QM_REG_QVOQIDX_7 0x168110
2336 #define QM_REG_QVOQIDX_8 0x168114
2337 #define QM_REG_QVOQIDX_9 0x168118
2338 /* [R 24] Remaining pause timeout for port 0 */
2339 #define QM_REG_REMAINPAUSETM0 0x168418
2340 /* [R 24] Remaining pause timeout for port 1 */
2341 #define QM_REG_REMAINPAUSETM1 0x16841c
2342 /* [RW 1] Initialization bit command */
2343 #define QM_REG_SOFT_RESET 0x168428
2344 /* [RW 8] The credit cost per every task in the QM. A value per each VOQ */
2345 #define QM_REG_TASKCRDCOST_0 0x16809c
2346 #define QM_REG_TASKCRDCOST_1 0x1680a0
2347 #define QM_REG_TASKCRDCOST_10 0x1680c4
2348 #define QM_REG_TASKCRDCOST_11 0x1680c8
2349 #define QM_REG_TASKCRDCOST_2 0x1680a4
2350 #define QM_REG_TASKCRDCOST_4 0x1680ac
2351 #define QM_REG_TASKCRDCOST_5 0x1680b0
2352 /* [R 6] Keep the fill level of the fifo from write client 3 */
2353 #define QM_REG_TQM_WRC_FIFOLVL 0x168010
2354 /* [R 6] Keep the fill level of the fifo from write client 2 */
2355 #define QM_REG_UQM_WRC_FIFOLVL 0x168008
2356 /* [RC 32] Credit update error register */
2357 #define QM_REG_VOQCRDERRREG 0x168408
2358 /* [R 16] The credit value for each VOQ */
2359 #define QM_REG_VOQCREDIT_0 0x1682d0
2360 #define QM_REG_VOQCREDIT_1 0x1682d4
2361 #define QM_REG_VOQCREDIT_10 0x1682f8
2362 #define QM_REG_VOQCREDIT_11 0x1682fc
2363 #define QM_REG_VOQCREDIT_4 0x1682e0
2364 /* [RW 16] The credit value that if above the QM is considered almost full */
2365 #define QM_REG_VOQCREDITAFULLTHR 0x168090
2366 /* [RW 16] The init and maximum credit for each VoQ */
2367 #define QM_REG_VOQINITCREDIT_0 0x168060
2368 #define QM_REG_VOQINITCREDIT_1 0x168064
2369 #define QM_REG_VOQINITCREDIT_10 0x168088
2370 #define QM_REG_VOQINITCREDIT_11 0x16808c
2371 #define QM_REG_VOQINITCREDIT_2 0x168068
2372 #define QM_REG_VOQINITCREDIT_4 0x168070
2373 #define QM_REG_VOQINITCREDIT_5 0x168074
2374 /* [RW 1] The port of which VOQ belongs */
2375 #define QM_REG_VOQPORT_1 0x1682a4
2376 #define QM_REG_VOQPORT_10 0x1682c8
2377 #define QM_REG_VOQPORT_11 0x1682cc
2378 #define QM_REG_VOQPORT_2 0x1682a8
2379 /* [RW 32] The physical queue number associated with each VOQ */
2380 #define QM_REG_VOQQMASK_0_LSB 0x168240
2381 /* [RW 32] The physical queue number associated with each VOQ */
2382 #define QM_REG_VOQQMASK_0_MSB 0x168244
2383 /* [RW 32] The physical queue number associated with each VOQ */
2384 #define QM_REG_VOQQMASK_1_MSB 0x16824c
2385 /* [RW 32] The physical queue number associated with each VOQ */
2386 #define QM_REG_VOQQMASK_2_LSB 0x168250
2387 /* [RW 32] The physical queue number associated with each VOQ */
2388 #define QM_REG_VOQQMASK_2_MSB 0x168254
2389 /* [RW 32] The physical queue number associated with each VOQ */
2390 #define QM_REG_VOQQMASK_3_LSB 0x168258
2391 /* [RW 32] The physical queue number associated with each VOQ */
2392 #define QM_REG_VOQQMASK_4_LSB 0x168260
2393 /* [RW 32] The physical queue number associated with each VOQ */
2394 #define QM_REG_VOQQMASK_4_MSB 0x168264
2395 /* [RW 32] The physical queue number associated with each VOQ */
2396 #define QM_REG_VOQQMASK_5_LSB 0x168268
2397 /* [RW 32] The physical queue number associated with each VOQ */
2398 #define QM_REG_VOQQMASK_5_MSB 0x16826c
2399 /* [RW 32] The physical queue number associated with each VOQ */
2400 #define QM_REG_VOQQMASK_6_LSB 0x168270
2401 /* [RW 32] The physical queue number associated with each VOQ */
2402 #define QM_REG_VOQQMASK_6_MSB 0x168274
2403 /* [RW 32] The physical queue number associated with each VOQ */
2404 #define QM_REG_VOQQMASK_7_LSB 0x168278
2405 /* [RW 32] The physical queue number associated with each VOQ */
2406 #define QM_REG_VOQQMASK_7_MSB 0x16827c
2407 /* [RW 32] The physical queue number associated with each VOQ */
2408 #define QM_REG_VOQQMASK_8_LSB 0x168280
2409 /* [RW 32] The physical queue number associated with each VOQ */
2410 #define QM_REG_VOQQMASK_8_MSB 0x168284
2411 /* [RW 32] The physical queue number associated with each VOQ */
2412 #define QM_REG_VOQQMASK_9_LSB 0x168288
2413 /* [RW 32] Wrr weights */
2414 #define QM_REG_WRRWEIGHTS_0 0x16880c
2415 #define QM_REG_WRRWEIGHTS_1 0x168810
2416 #define QM_REG_WRRWEIGHTS_10 0x168814
2417 #define QM_REG_WRRWEIGHTS_10_SIZE 1
2418 /* [RW 32] Wrr weights */
2419 #define QM_REG_WRRWEIGHTS_11 0x168818
2420 #define QM_REG_WRRWEIGHTS_11_SIZE 1
2421 /* [RW 32] Wrr weights */
2422 #define QM_REG_WRRWEIGHTS_12 0x16881c
2423 #define QM_REG_WRRWEIGHTS_12_SIZE 1
2424 /* [RW 32] Wrr weights */
2425 #define QM_REG_WRRWEIGHTS_13 0x168820
2426 #define QM_REG_WRRWEIGHTS_13_SIZE 1
2427 /* [RW 32] Wrr weights */
2428 #define QM_REG_WRRWEIGHTS_14 0x168824
2429 #define QM_REG_WRRWEIGHTS_14_SIZE 1
2430 /* [RW 32] Wrr weights */
2431 #define QM_REG_WRRWEIGHTS_15 0x168828
2432 #define QM_REG_WRRWEIGHTS_15_SIZE 1
2433 /* [RW 32] Wrr weights */
2434 #define QM_REG_WRRWEIGHTS_10 0x168814
2435 #define QM_REG_WRRWEIGHTS_11 0x168818
2436 #define QM_REG_WRRWEIGHTS_12 0x16881c
2437 #define QM_REG_WRRWEIGHTS_13 0x168820
2438 #define QM_REG_WRRWEIGHTS_14 0x168824
2439 #define QM_REG_WRRWEIGHTS_15 0x168828
2440 #define QM_REG_WRRWEIGHTS_2 0x16882c
2441 #define QM_REG_WRRWEIGHTS_3 0x168830
2442 #define QM_REG_WRRWEIGHTS_4 0x168834
2443 #define QM_REG_WRRWEIGHTS_5 0x168838
2444 #define QM_REG_WRRWEIGHTS_6 0x16883c
2445 #define QM_REG_WRRWEIGHTS_7 0x168840
2446 #define QM_REG_WRRWEIGHTS_8 0x168844
2447 #define QM_REG_WRRWEIGHTS_9 0x168848
2448 /* [R 6] Keep the fill level of the fifo from write client 1 */
2449 #define QM_REG_XQM_WRC_FIFOLVL 0x168000
2450 #define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
2451 #define DORQ_DORQ_INT_STS_REG_ADDRESS_ERROR_SIZE 0
2452 #define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
2453 #define DORQ_DORQ_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
2454 #define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
2455 #define DORQ_DORQ_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
2456 #define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
2457 #define DORQ_DORQ_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
2458 #define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR (0x1<<0)
2459 #define NIG_NIG_INT_STS_0_REG_ADDRESS_ERROR_SIZE 0
2460 #define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR (0x1<<0)
2461 #define NIG_NIG_INT_STS_CLR_0_REG_ADDRESS_ERROR_SIZE 0
2462 #define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR (0x1<<0)
2463 #define NIG_NIG_INT_STS_WR_0_REG_ADDRESS_ERROR_SIZE 0
2464 #define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR (0x1<<0)
2465 #define NIG_NIG_INT_MASK_0_REG_ADDRESS_ERROR_SIZE 0
2466 #define TCM_TCM_INT_STS_REG_ADDRESS_ERROR (0x1<<0)
2467 #define TCM_TCM_INT_STS_REG_ADDRESS_ERROR_SIZE 0
2468 #define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR (0x1<<0)
2469 #define TCM_TCM_INT_STS_CLR_REG_ADDRESS_ERROR_SIZE 0
2470 #define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR (0x1<<0)
2471 #define TCM_TCM_INT_STS_WR_REG_ADDRESS_ERROR_SIZE 0
2472 #define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR (0x1<<0)
2473 #define TCM_TCM_INT_MASK_REG_ADDRESS_ERROR_SIZE 0
2474 #define CFC_DEBUG1_REG_WRITE_AC (0x1<<4)
2475 #define CFC_DEBUG1_REG_WRITE_AC_SIZE 4
2476 /* [R 1] debug only: This bit indicates wheter indicates that external
2477 buffer was wrapped (oldest data was thrown); Relevant only when
2478 ~dbg_registers_debug_target=2 (PCI) & ~dbg_registers_full_mode=1 (wrap); */
2479 #define DBG_REG_WRAP_ON_EXT_BUFFER 0xc124
2480 #define DBG_REG_WRAP_ON_EXT_BUFFER_SIZE 1
2481 /* [R 1] debug only: This bit indicates wheter the internal buffer was
2482 wrapped (oldest data was thrown) Relevant only when
2483 ~dbg_registers_debug_target=0 (internal buffer) */
2484 #define DBG_REG_WRAP_ON_INT_BUFFER 0xc128
2485 #define DBG_REG_WRAP_ON_INT_BUFFER_SIZE 1
2486 /* [RW 32] Wrr weights */
2487 #define QM_REG_WRRWEIGHTS_0 0x16880c
2488 #define QM_REG_WRRWEIGHTS_0_SIZE 1
2489 /* [RW 32] Wrr weights */
2490 #define QM_REG_WRRWEIGHTS_1 0x168810
2491 #define QM_REG_WRRWEIGHTS_1_SIZE 1
2492 /* [RW 32] Wrr weights */
2493 #define QM_REG_WRRWEIGHTS_10 0x168814
2494 #define QM_REG_WRRWEIGHTS_10_SIZE 1
2495 /* [RW 32] Wrr weights */
2496 #define QM_REG_WRRWEIGHTS_11 0x168818
2497 #define QM_REG_WRRWEIGHTS_11_SIZE 1
2498 /* [RW 32] Wrr weights */
2499 #define QM_REG_WRRWEIGHTS_12 0x16881c
2500 #define QM_REG_WRRWEIGHTS_12_SIZE 1
2501 /* [RW 32] Wrr weights */
2502 #define QM_REG_WRRWEIGHTS_13 0x168820
2503 #define QM_REG_WRRWEIGHTS_13_SIZE 1
2504 /* [RW 32] Wrr weights */
2505 #define QM_REG_WRRWEIGHTS_14 0x168824
2506 #define QM_REG_WRRWEIGHTS_14_SIZE 1
2507 /* [RW 32] Wrr weights */
2508 #define QM_REG_WRRWEIGHTS_15 0x168828
2509 #define QM_REG_WRRWEIGHTS_15_SIZE 1
2510 /* [RW 32] Wrr weights */
2511 #define QM_REG_WRRWEIGHTS_2 0x16882c
2512 #define QM_REG_WRRWEIGHTS_2_SIZE 1
2513 /* [RW 32] Wrr weights */
2514 #define QM_REG_WRRWEIGHTS_3 0x168830
2515 #define QM_REG_WRRWEIGHTS_3_SIZE 1
2516 /* [RW 32] Wrr weights */
2517 #define QM_REG_WRRWEIGHTS_4 0x168834
2518 #define QM_REG_WRRWEIGHTS_4_SIZE 1
2519 /* [RW 32] Wrr weights */
2520 #define QM_REG_WRRWEIGHTS_5 0x168838
2521 #define QM_REG_WRRWEIGHTS_5_SIZE 1
2522 /* [RW 32] Wrr weights */
2523 #define QM_REG_WRRWEIGHTS_6 0x16883c
2524 #define QM_REG_WRRWEIGHTS_6_SIZE 1
2525 /* [RW 32] Wrr weights */
2526 #define QM_REG_WRRWEIGHTS_7 0x168840
2527 #define QM_REG_WRRWEIGHTS_7_SIZE 1
2528 /* [RW 32] Wrr weights */
2529 #define QM_REG_WRRWEIGHTS_8 0x168844
2530 #define QM_REG_WRRWEIGHTS_8_SIZE 1
2531 /* [RW 32] Wrr weights */
2532 #define QM_REG_WRRWEIGHTS_9 0x168848
2533 #define QM_REG_WRRWEIGHTS_9_SIZE 1
2534 /* [RW 22] Number of free element in the free list of T2 entries - port 0. */
2535 #define SRC_REG_COUNTFREE0 0x40500
2536 /* [WB 64] First free element in the free list of T2 entries - port 0. */
2537 #define SRC_REG_FIRSTFREE0 0x40510
2538 #define SRC_REG_KEYRSS0_0 0x40408
2539 #define SRC_REG_KEYRSS1_9 0x40454
2540 /* [WB 64] Last free element in the free list of T2 entries - port 0. */
2541 #define SRC_REG_LASTFREE0 0x40530
2542 /* [RW 5] The number of hash bits used for the search (h); Values can be 8
2543 to 24. */
2544 #define SRC_REG_NUMBER_HASH_BITS0 0x40400
2545 /* [RW 1] Reset internal state machines. */
2546 #define SRC_REG_SOFT_RST 0x4049c
2547 /* [R 1] Interrupt register #0 read */
2548 #define SRC_REG_SRC_INT_STS 0x404ac
2549 /* [RW 3] Parity mask register #0 read/write */
2550 #define SRC_REG_SRC_PRTY_MASK 0x404c8
2551 /* [R 3] Parity register #0 read */
2552 #define SRC_REG_SRC_PRTY_STS 0x404bc
2553 /* [R 4] Used to read the value of the XX protection CAM occupancy counter. */
2554 #define TCM_REG_CAM_OCCUP 0x5017c
2555 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
2556 disregarded; valid output is deasserted; all other signals are treated as
2557 usual; if 1 - normal activity. */
2558 #define TCM_REG_CDU_AG_RD_IFEN 0x50034
2559 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
2560 are disregarded; all other signals are treated as usual; if 1 - normal
2561 activity. */
2562 #define TCM_REG_CDU_AG_WR_IFEN 0x50030
2563 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
2564 disregarded; valid output is deasserted; all other signals are treated as
2565 usual; if 1 - normal activity. */
2566 #define TCM_REG_CDU_SM_RD_IFEN 0x5003c
2567 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
2568 input is disregarded; all other signals are treated as usual; if 1 -
2569 normal activity. */
2570 #define TCM_REG_CDU_SM_WR_IFEN 0x50038
2571 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
2572 the initial credit value; read returns the current value of the credit
2573 counter. Must be initialized to 1 at start-up. */
2574 #define TCM_REG_CFC_INIT_CRD 0x50204
2575 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
2576 weight 8 (the most prioritised); 1 stands for weight 1(least
2577 prioritised); 2 stands for weight 2; tc. */
2578 #define TCM_REG_CP_WEIGHT 0x500c0
2579 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
2580 disregarded; acknowledge output is deasserted; all other signals are
2581 treated as usual; if 1 - normal activity. */
2582 #define TCM_REG_CSEM_IFEN 0x5002c
2583 /* [RC 1] Message length mismatch (relative to last indication) at the In#9
2584 interface. */
2585 #define TCM_REG_CSEM_LENGTH_MIS 0x50174
2586 /* [RW 8] The Event ID in case of ErrorFlg is set in the input message. */
2587 #define TCM_REG_ERR_EVNT_ID 0x500a0
2588 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
2589 #define TCM_REG_ERR_TCM_HDR 0x5009c
2590 /* [RW 8] The Event ID for Timers expiration. */
2591 #define TCM_REG_EXPR_EVNT_ID 0x500a4
2592 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
2593 writes the initial credit value; read returns the current value of the
2594 credit counter. Must be initialized to 64 at start-up. */
2595 #define TCM_REG_FIC0_INIT_CRD 0x5020c
2596 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
2597 writes the initial credit value; read returns the current value of the
2598 credit counter. Must be initialized to 64 at start-up. */
2599 #define TCM_REG_FIC1_INIT_CRD 0x50210
2600 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
2601 - strict priority defined by ~tcm_registers_gr_ag_pr.gr_ag_pr;
2602 ~tcm_registers_gr_ld0_pr.gr_ld0_pr and
2603 ~tcm_registers_gr_ld1_pr.gr_ld1_pr. */
2604 #define TCM_REG_GR_ARB_TYPE 0x50114
2605 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
2606 highest priority is 3. It is supposed that the Store channel is the
2607 compliment of the other 3 groups. */
2608 #define TCM_REG_GR_LD0_PR 0x5011c
2609 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
2610 highest priority is 3. It is supposed that the Store channel is the
2611 compliment of the other 3 groups. */
2612 #define TCM_REG_GR_LD1_PR 0x50120
2613 /* [RW 4] The number of double REG-pairs; loaded from the STORM context and
2614 sent to STORM; for a specific connection type. The double REG-pairs are
2615 used to align to STORM context row size of 128 bits. The offset of these
2616 data in the STORM context is always 0. Index _i stands for the connection
2617 type (one of 16). */
2618 #define TCM_REG_N_SM_CTX_LD_0 0x50050
2619 #define TCM_REG_N_SM_CTX_LD_1 0x50054
2620 #define TCM_REG_N_SM_CTX_LD_10 0x50078
2621 #define TCM_REG_N_SM_CTX_LD_11 0x5007c
2622 #define TCM_REG_N_SM_CTX_LD_12 0x50080
2623 #define TCM_REG_N_SM_CTX_LD_13 0x50084
2624 #define TCM_REG_N_SM_CTX_LD_14 0x50088
2625 #define TCM_REG_N_SM_CTX_LD_15 0x5008c
2626 #define TCM_REG_N_SM_CTX_LD_2 0x50058
2627 #define TCM_REG_N_SM_CTX_LD_3 0x5005c
2628 #define TCM_REG_N_SM_CTX_LD_4 0x50060
2629 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
2630 acknowledge output is deasserted; all other signals are treated as usual;
2631 if 1 - normal activity. */
2632 #define TCM_REG_PBF_IFEN 0x50024
2633 /* [RC 1] Message length mismatch (relative to last indication) at the In#7
2634 interface. */
2635 #define TCM_REG_PBF_LENGTH_MIS 0x5016c
2636 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
2637 weight 8 (the most prioritised); 1 stands for weight 1(least
2638 prioritised); 2 stands for weight 2; tc. */
2639 #define TCM_REG_PBF_WEIGHT 0x500b4
2640 /* [RW 6] The physical queue number 0 per port index. */
2641 #define TCM_REG_PHYS_QNUM0_0 0x500e0
2642 #define TCM_REG_PHYS_QNUM0_1 0x500e4
2643 /* [RW 6] The physical queue number 1 per port index. */
2644 #define TCM_REG_PHYS_QNUM1_0 0x500e8
2645 /* [RW 1] Input prs Interface enable. If 0 - the valid input is disregarded;
2646 acknowledge output is deasserted; all other signals are treated as usual;
2647 if 1 - normal activity. */
2648 #define TCM_REG_PRS_IFEN 0x50020
2649 /* [RC 1] Message length mismatch (relative to last indication) at the In#6
2650 interface. */
2651 #define TCM_REG_PRS_LENGTH_MIS 0x50168
2652 /* [RW 3] The weight of the input prs in the WRR mechanism. 0 stands for
2653 weight 8 (the most prioritised); 1 stands for weight 1(least
2654 prioritised); 2 stands for weight 2; tc. */
2655 #define TCM_REG_PRS_WEIGHT 0x500b0
2656 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
2657 #define TCM_REG_STOP_EVNT_ID 0x500a8
2658 /* [RC 1] Message length mismatch (relative to last indication) at the STORM
2659 interface. */
2660 #define TCM_REG_STORM_LENGTH_MIS 0x50160
2661 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
2662 disregarded; acknowledge output is deasserted; all other signals are
2663 treated as usual; if 1 - normal activity. */
2664 #define TCM_REG_STORM_TCM_IFEN 0x50010
2665 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
2666 acknowledge output is deasserted; all other signals are treated as usual;
2667 if 1 - normal activity. */
2668 #define TCM_REG_TCM_CFC_IFEN 0x50040
2669 /* [RW 11] Interrupt mask register #0 read/write */
2670 #define TCM_REG_TCM_INT_MASK 0x501dc
2671 /* [R 11] Interrupt register #0 read */
2672 #define TCM_REG_TCM_INT_STS 0x501d0
2673 /* [RW 3] The size of AG context region 0 in REG-pairs. Designates the MS
2674 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
2675 Is used to determine the number of the AG context REG-pairs written back;
2676 when the input message Reg1WbFlg isn't set. */
2677 #define TCM_REG_TCM_REG0_SZ 0x500d8
2678 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
2679 disregarded; valid is deasserted; all other signals are treated as usual;
2680 if 1 - normal activity. */
2681 #define TCM_REG_TCM_STORM0_IFEN 0x50004
2682 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
2683 disregarded; valid is deasserted; all other signals are treated as usual;
2684 if 1 - normal activity. */
2685 #define TCM_REG_TCM_STORM1_IFEN 0x50008
2686 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
2687 disregarded; valid is deasserted; all other signals are treated as usual;
2688 if 1 - normal activity. */
2689 #define TCM_REG_TCM_TQM_IFEN 0x5000c
2690 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
2691 #define TCM_REG_TCM_TQM_USE_Q 0x500d4
2692 /* [RW 28] The CM header for Timers expiration command. */
2693 #define TCM_REG_TM_TCM_HDR 0x50098
2694 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
2695 disregarded; acknowledge output is deasserted; all other signals are
2696 treated as usual; if 1 - normal activity. */
2697 #define TCM_REG_TM_TCM_IFEN 0x5001c
2698 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
2699 the initial credit value; read returns the current value of the credit
2700 counter. Must be initialized to 32 at start-up. */
2701 #define TCM_REG_TQM_INIT_CRD 0x5021c
2702 /* [RW 28] The CM header value for QM request (primary). */
2703 #define TCM_REG_TQM_TCM_HDR_P 0x50090
2704 /* [RW 28] The CM header value for QM request (secondary). */
2705 #define TCM_REG_TQM_TCM_HDR_S 0x50094
2706 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
2707 acknowledge output is deasserted; all other signals are treated as usual;
2708 if 1 - normal activity. */
2709 #define TCM_REG_TQM_TCM_IFEN 0x50014
2710 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
2711 acknowledge output is deasserted; all other signals are treated as usual;
2712 if 1 - normal activity. */
2713 #define TCM_REG_TSDM_IFEN 0x50018
2714 /* [RC 1] Message length mismatch (relative to last indication) at the SDM
2715 interface. */
2716 #define TCM_REG_TSDM_LENGTH_MIS 0x50164
2717 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
2718 weight 8 (the most prioritised); 1 stands for weight 1(least
2719 prioritised); 2 stands for weight 2; tc. */
2720 #define TCM_REG_TSDM_WEIGHT 0x500c4
2721 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
2722 disregarded; acknowledge output is deasserted; all other signals are
2723 treated as usual; if 1 - normal activity. */
2724 #define TCM_REG_USEM_IFEN 0x50028
2725 /* [RC 1] Message length mismatch (relative to last indication) at the In#8
2726 interface. */
2727 #define TCM_REG_USEM_LENGTH_MIS 0x50170
2728 /* [RW 21] Indirect access to the descriptor table of the XX protection
2729 mechanism. The fields are: [5:0] - length of the message; 15:6] - message
2730 pointer; 20:16] - next pointer. */
2731 #define TCM_REG_XX_DESCR_TABLE 0x50280
2732 /* [R 6] Use to read the value of XX protection Free counter. */
2733 #define TCM_REG_XX_FREE 0x50178
2734 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
2735 of the Input Stage XX protection buffer by the XX protection pending
2736 messages. Max credit available - 127.Write writes the initial credit
2737 value; read returns the current value of the credit counter. Must be
2738 initialized to 19 at start-up. */
2739 #define TCM_REG_XX_INIT_CRD 0x50220
2740 /* [RW 6] Maximum link list size (messages locked) per connection in the XX
2741 protection. */
2742 #define TCM_REG_XX_MAX_LL_SZ 0x50044
2743 /* [RW 6] The maximum number of pending messages; which may be stored in XX
2744 protection. ~tcm_registers_xx_free.xx_free is read on read. */
2745 #define TCM_REG_XX_MSG_NUM 0x50224
2746 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
2747 #define TCM_REG_XX_OVFL_EVNT_ID 0x50048
2748 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
2749 The fields are:[4:0] - tail pointer; [10:5] - Link List size; 15:11] -
2750 header pointer. */
2751 #define TCM_REG_XX_TABLE 0x50240
2752 /* [RW 4] Load value for for cfc ac credit cnt. */
2753 #define TM_REG_CFC_AC_CRDCNT_VAL 0x164208
2754 /* [RW 4] Load value for cfc cld credit cnt. */
2755 #define TM_REG_CFC_CLD_CRDCNT_VAL 0x164210
2756 /* [RW 8] Client0 context region. */
2757 #define TM_REG_CL0_CONT_REGION 0x164030
2758 /* [RW 8] Client1 context region. */
2759 #define TM_REG_CL1_CONT_REGION 0x164034
2760 /* [RW 8] Client2 context region. */
2761 #define TM_REG_CL2_CONT_REGION 0x164038
2762 /* [RW 2] Client in High priority client number. */
2763 #define TM_REG_CLIN_PRIOR0_CLIENT 0x164024
2764 /* [RW 4] Load value for clout0 cred cnt. */
2765 #define TM_REG_CLOUT_CRDCNT0_VAL 0x164220
2766 /* [RW 4] Load value for clout1 cred cnt. */
2767 #define TM_REG_CLOUT_CRDCNT1_VAL 0x164228
2768 /* [RW 4] Load value for clout2 cred cnt. */
2769 #define TM_REG_CLOUT_CRDCNT2_VAL 0x164230
2770 /* [RW 1] Enable client0 input. */
2771 #define TM_REG_EN_CL0_INPUT 0x164008
2772 /* [RW 1] Enable client1 input. */
2773 #define TM_REG_EN_CL1_INPUT 0x16400c
2774 /* [RW 1] Enable client2 input. */
2775 #define TM_REG_EN_CL2_INPUT 0x164010
2776 /* [RW 1] Enable real time counter. */
2777 #define TM_REG_EN_REAL_TIME_CNT 0x1640d8
2778 /* [RW 1] Enable for Timers state machines. */
2779 #define TM_REG_EN_TIMERS 0x164000
2780 /* [RW 4] Load value for expiration credit cnt. CFC max number of
2781 outstanding load requests for timers (expiration) context loading. */
2782 #define TM_REG_EXP_CRDCNT_VAL 0x164238
2783 /* [RW 18] Linear0 Max active cid. */
2784 #define TM_REG_LIN0_MAX_ACTIVE_CID 0x164048
2785 /* [WB 64] Linear0 phy address. */
2786 #define TM_REG_LIN0_PHY_ADDR 0x164270
2787 /* [RW 24] Linear0 array scan timeout. */
2788 #define TM_REG_LIN0_SCAN_TIME 0x16403c
2789 /* [WB 64] Linear1 phy address. */
2790 #define TM_REG_LIN1_PHY_ADDR 0x164280
2791 /* [RW 6] Linear timer set_clear fifo threshold. */
2792 #define TM_REG_LIN_SETCLR_FIFO_ALFULL_THR 0x164070
2793 /* [RW 2] Load value for pci arbiter credit cnt. */
2794 #define TM_REG_PCIARB_CRDCNT_VAL 0x164260
2795 /* [RW 1] Timer software reset - active high. */
2796 #define TM_REG_TIMER_SOFT_RST 0x164004
2797 /* [RW 20] The amount of hardware cycles for each timer tick. */
2798 #define TM_REG_TIMER_TICK_SIZE 0x16401c
2799 /* [RW 8] Timers Context region. */
2800 #define TM_REG_TM_CONTEXT_REGION 0x164044
2801 /* [RW 1] Interrupt mask register #0 read/write */
2802 #define TM_REG_TM_INT_MASK 0x1640fc
2803 /* [R 1] Interrupt register #0 read */
2804 #define TM_REG_TM_INT_STS 0x1640f0
2805 /* [RW 8] The event id for aggregated interrupt 0 */
2806 #define TSDM_REG_AGG_INT_EVENT_0 0x42038
2807 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
2808 #define TSDM_REG_CFC_RSP_START_ADDR 0x42008
2809 /* [RW 16] The maximum value of the competion counter #0 */
2810 #define TSDM_REG_CMP_COUNTER_MAX0 0x4201c
2811 /* [RW 16] The maximum value of the competion counter #1 */
2812 #define TSDM_REG_CMP_COUNTER_MAX1 0x42020
2813 /* [RW 16] The maximum value of the competion counter #2 */
2814 #define TSDM_REG_CMP_COUNTER_MAX2 0x42024
2815 /* [RW 16] The maximum value of the competion counter #3 */
2816 #define TSDM_REG_CMP_COUNTER_MAX3 0x42028
2817 /* [RW 13] The start address in the internal RAM for the completion
2818 counters. */
2819 #define TSDM_REG_CMP_COUNTER_START_ADDR 0x4200c
2820 #define TSDM_REG_ENABLE_IN1 0x42238
2821 #define TSDM_REG_ENABLE_IN2 0x4223c
2822 #define TSDM_REG_ENABLE_OUT1 0x42240
2823 #define TSDM_REG_ENABLE_OUT2 0x42244
2824 /* [RW 4] The initial number of messages that can be sent to the pxp control
2825 interface without receiving any ACK. */
2826 #define TSDM_REG_INIT_CREDIT_PXP_CTRL 0x424bc
2827 /* [ST 32] The number of ACK after placement messages received */
2828 #define TSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x4227c
2829 /* [ST 32] The number of packet end messages received from the parser */
2830 #define TSDM_REG_NUM_OF_PKT_END_MSG 0x42274
2831 /* [ST 32] The number of requests received from the pxp async if */
2832 #define TSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x42278
2833 /* [ST 32] The number of commands received in queue 0 */
2834 #define TSDM_REG_NUM_OF_Q0_CMD 0x42248
2835 /* [ST 32] The number of commands received in queue 10 */
2836 #define TSDM_REG_NUM_OF_Q10_CMD 0x4226c
2837 /* [ST 32] The number of commands received in queue 11 */
2838 #define TSDM_REG_NUM_OF_Q11_CMD 0x42270
2839 /* [ST 32] The number of commands received in queue 1 */
2840 #define TSDM_REG_NUM_OF_Q1_CMD 0x4224c
2841 /* [ST 32] The number of commands received in queue 3 */
2842 #define TSDM_REG_NUM_OF_Q3_CMD 0x42250
2843 /* [ST 32] The number of commands received in queue 4 */
2844 #define TSDM_REG_NUM_OF_Q4_CMD 0x42254
2845 /* [ST 32] The number of commands received in queue 5 */
2846 #define TSDM_REG_NUM_OF_Q5_CMD 0x42258
2847 /* [ST 32] The number of commands received in queue 6 */
2848 #define TSDM_REG_NUM_OF_Q6_CMD 0x4225c
2849 /* [ST 32] The number of commands received in queue 7 */
2850 #define TSDM_REG_NUM_OF_Q7_CMD 0x42260
2851 /* [ST 32] The number of commands received in queue 8 */
2852 #define TSDM_REG_NUM_OF_Q8_CMD 0x42264
2853 /* [ST 32] The number of commands received in queue 9 */
2854 #define TSDM_REG_NUM_OF_Q9_CMD 0x42268
2855 /* [RW 13] The start address in the internal RAM for the packet end message */
2856 #define TSDM_REG_PCK_END_MSG_START_ADDR 0x42014
2857 /* [RW 13] The start address in the internal RAM for queue counters */
2858 #define TSDM_REG_Q_COUNTER_START_ADDR 0x42010
2859 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
2860 #define TSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x42548
2861 /* [R 1] parser fifo empty in sdm_sync block */
2862 #define TSDM_REG_SYNC_PARSER_EMPTY 0x42550
2863 /* [R 1] parser serial fifo empty in sdm_sync block */
2864 #define TSDM_REG_SYNC_SYNC_EMPTY 0x42558
2865 /* [RW 32] Tick for timer counter. Applicable only when
2866 ~tsdm_registers_timer_tick_enable.timer_tick_enable =1 */
2867 #define TSDM_REG_TIMER_TICK 0x42000
2868 /* [RW 32] Interrupt mask register #0 read/write */
2869 #define TSDM_REG_TSDM_INT_MASK_0 0x4229c
2870 #define TSDM_REG_TSDM_INT_MASK_1 0x422ac
2871 /* [RW 11] Parity mask register #0 read/write */
2872 #define TSDM_REG_TSDM_PRTY_MASK 0x422bc
2873 /* [R 11] Parity register #0 read */
2874 #define TSDM_REG_TSDM_PRTY_STS 0x422b0
2875 /* [RW 5] The number of time_slots in the arbitration cycle */
2876 #define TSEM_REG_ARB_CYCLE_SIZE 0x180034
2877 /* [RW 3] The source that is associated with arbitration element 0. Source
2878 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
2879 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
2880 #define TSEM_REG_ARB_ELEMENT0 0x180020
2881 /* [RW 3] The source that is associated with arbitration element 1. Source
2882 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
2883 sleeping thread with priority 1; 4- sleeping thread with priority 2.
2884 Could not be equal to register ~tsem_registers_arb_element0.arb_element0 */
2885 #define TSEM_REG_ARB_ELEMENT1 0x180024
2886 /* [RW 3] The source that is associated with arbitration element 2. Source
2887 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
2888 sleeping thread with priority 1; 4- sleeping thread with priority 2.
2889 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
2890 and ~tsem_registers_arb_element1.arb_element1 */
2891 #define TSEM_REG_ARB_ELEMENT2 0x180028
2892 /* [RW 3] The source that is associated with arbitration element 3. Source
2893 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
2894 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
2895 not be equal to register ~tsem_registers_arb_element0.arb_element0 and
2896 ~tsem_registers_arb_element1.arb_element1 and
2897 ~tsem_registers_arb_element2.arb_element2 */
2898 #define TSEM_REG_ARB_ELEMENT3 0x18002c
2899 /* [RW 3] The source that is associated with arbitration element 4. Source
2900 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
2901 sleeping thread with priority 1; 4- sleeping thread with priority 2.
2902 Could not be equal to register ~tsem_registers_arb_element0.arb_element0
2903 and ~tsem_registers_arb_element1.arb_element1 and
2904 ~tsem_registers_arb_element2.arb_element2 and
2905 ~tsem_registers_arb_element3.arb_element3 */
2906 #define TSEM_REG_ARB_ELEMENT4 0x180030
2907 #define TSEM_REG_ENABLE_IN 0x1800a4
2908 #define TSEM_REG_ENABLE_OUT 0x1800a8
2909 /* [RW 32] This address space contains all registers and memories that are
2910 placed in SEM_FAST block. The SEM_FAST registers are described in
2911 appendix B. In order to access the SEM_FAST registers the base address
2912 TSEM_REGISTERS_FAST_MEMORY (Offset: 0x1a0000) should be added to each
2913 SEM_FAST register offset. */
2914 #define TSEM_REG_FAST_MEMORY 0x1a0000
2915 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
2916 by the microcode */
2917 #define TSEM_REG_FIC0_DISABLE 0x180224
2918 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
2919 by the microcode */
2920 #define TSEM_REG_FIC1_DISABLE 0x180234
2921 /* [RW 15] Interrupt table Read and write access to it is not possible in
2922 the middle of the work */
2923 #define TSEM_REG_INT_TABLE 0x180400
2924 /* [ST 24] Statistics register. The number of messages that entered through
2925 FIC0 */
2926 #define TSEM_REG_MSG_NUM_FIC0 0x180000
2927 /* [ST 24] Statistics register. The number of messages that entered through
2928 FIC1 */
2929 #define TSEM_REG_MSG_NUM_FIC1 0x180004
2930 /* [ST 24] Statistics register. The number of messages that were sent to
2931 FOC0 */
2932 #define TSEM_REG_MSG_NUM_FOC0 0x180008
2933 /* [ST 24] Statistics register. The number of messages that were sent to
2934 FOC1 */
2935 #define TSEM_REG_MSG_NUM_FOC1 0x18000c
2936 /* [ST 24] Statistics register. The number of messages that were sent to
2937 FOC2 */
2938 #define TSEM_REG_MSG_NUM_FOC2 0x180010
2939 /* [ST 24] Statistics register. The number of messages that were sent to
2940 FOC3 */
2941 #define TSEM_REG_MSG_NUM_FOC3 0x180014
2942 /* [RW 1] Disables input messages from the passive buffer May be updated
2943 during run_time by the microcode */
2944 #define TSEM_REG_PAS_DISABLE 0x18024c
2945 /* [WB 128] Debug only. Passive buffer memory */
2946 #define TSEM_REG_PASSIVE_BUFFER 0x181000
2947 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
2948 #define TSEM_REG_PRAM 0x1c0000
2949 /* [R 8] Valid sleeping threads indication have bit per thread */
2950 #define TSEM_REG_SLEEP_THREADS_VALID 0x18026c
2951 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
2952 #define TSEM_REG_SLOW_EXT_STORE_EMPTY 0x1802a0
2953 /* [RW 8] List of free threads . There is a bit per thread. */
2954 #define TSEM_REG_THREADS_LIST 0x1802e4
2955 /* [RW 3] The arbitration scheme of time_slot 0 */
2956 #define TSEM_REG_TS_0_AS 0x180038
2957 /* [RW 3] The arbitration scheme of time_slot 10 */
2958 #define TSEM_REG_TS_10_AS 0x180060
2959 /* [RW 3] The arbitration scheme of time_slot 11 */
2960 #define TSEM_REG_TS_11_AS 0x180064
2961 /* [RW 3] The arbitration scheme of time_slot 12 */
2962 #define TSEM_REG_TS_12_AS 0x180068
2963 /* [RW 3] The arbitration scheme of time_slot 13 */
2964 #define TSEM_REG_TS_13_AS 0x18006c
2965 /* [RW 3] The arbitration scheme of time_slot 14 */
2966 #define TSEM_REG_TS_14_AS 0x180070
2967 /* [RW 3] The arbitration scheme of time_slot 15 */
2968 #define TSEM_REG_TS_15_AS 0x180074
2969 /* [RW 3] The arbitration scheme of time_slot 16 */
2970 #define TSEM_REG_TS_16_AS 0x180078
2971 /* [RW 3] The arbitration scheme of time_slot 17 */
2972 #define TSEM_REG_TS_17_AS 0x18007c
2973 /* [RW 3] The arbitration scheme of time_slot 18 */
2974 #define TSEM_REG_TS_18_AS 0x180080
2975 /* [RW 3] The arbitration scheme of time_slot 1 */
2976 #define TSEM_REG_TS_1_AS 0x18003c
2977 /* [RW 3] The arbitration scheme of time_slot 2 */
2978 #define TSEM_REG_TS_2_AS 0x180040
2979 /* [RW 3] The arbitration scheme of time_slot 3 */
2980 #define TSEM_REG_TS_3_AS 0x180044
2981 /* [RW 3] The arbitration scheme of time_slot 4 */
2982 #define TSEM_REG_TS_4_AS 0x180048
2983 /* [RW 3] The arbitration scheme of time_slot 5 */
2984 #define TSEM_REG_TS_5_AS 0x18004c
2985 /* [RW 3] The arbitration scheme of time_slot 6 */
2986 #define TSEM_REG_TS_6_AS 0x180050
2987 /* [RW 3] The arbitration scheme of time_slot 7 */
2988 #define TSEM_REG_TS_7_AS 0x180054
2989 /* [RW 3] The arbitration scheme of time_slot 8 */
2990 #define TSEM_REG_TS_8_AS 0x180058
2991 /* [RW 3] The arbitration scheme of time_slot 9 */
2992 #define TSEM_REG_TS_9_AS 0x18005c
2993 /* [RW 32] Interrupt mask register #0 read/write */
2994 #define TSEM_REG_TSEM_INT_MASK_0 0x180100
2995 #define TSEM_REG_TSEM_INT_MASK_1 0x180110
2996 /* [RW 32] Parity mask register #0 read/write */
2997 #define TSEM_REG_TSEM_PRTY_MASK_0 0x180120
2998 #define TSEM_REG_TSEM_PRTY_MASK_1 0x180130
2999 /* [R 32] Parity register #0 read */
3000 #define TSEM_REG_TSEM_PRTY_STS_0 0x180114
3001 #define TSEM_REG_TSEM_PRTY_STS_1 0x180124
3002 /* [R 5] Used to read the XX protection CAM occupancy counter. */
3003 #define UCM_REG_CAM_OCCUP 0xe0170
3004 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
3005 disregarded; valid output is deasserted; all other signals are treated as
3006 usual; if 1 - normal activity. */
3007 #define UCM_REG_CDU_AG_RD_IFEN 0xe0038
3008 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
3009 are disregarded; all other signals are treated as usual; if 1 - normal
3010 activity. */
3011 #define UCM_REG_CDU_AG_WR_IFEN 0xe0034
3012 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
3013 disregarded; valid output is deasserted; all other signals are treated as
3014 usual; if 1 - normal activity. */
3015 #define UCM_REG_CDU_SM_RD_IFEN 0xe0040
3016 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
3017 input is disregarded; all other signals are treated as usual; if 1 -
3018 normal activity. */
3019 #define UCM_REG_CDU_SM_WR_IFEN 0xe003c
3020 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
3021 the initial credit value; read returns the current value of the credit
3022 counter. Must be initialized to 1 at start-up. */
3023 #define UCM_REG_CFC_INIT_CRD 0xe0204
3024 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
3025 weight 8 (the most prioritised); 1 stands for weight 1(least
3026 prioritised); 2 stands for weight 2; tc. */
3027 #define UCM_REG_CP_WEIGHT 0xe00c4
3028 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
3029 disregarded; acknowledge output is deasserted; all other signals are
3030 treated as usual; if 1 - normal activity. */
3031 #define UCM_REG_CSEM_IFEN 0xe0028
3032 /* [RC 1] Set when the message length mismatch (relative to last indication)
3033 at the csem interface is detected. */
3034 #define UCM_REG_CSEM_LENGTH_MIS 0xe0160
3035 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
3036 weight 8 (the most prioritised); 1 stands for weight 1(least
3037 prioritised); 2 stands for weight 2; tc. */
3038 #define UCM_REG_CSEM_WEIGHT 0xe00b8
3039 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
3040 disregarded; acknowledge output is deasserted; all other signals are
3041 treated as usual; if 1 - normal activity. */
3042 #define UCM_REG_DORQ_IFEN 0xe0030
3043 /* [RC 1] Set when the message length mismatch (relative to last indication)
3044 at the dorq interface is detected. */
3045 #define UCM_REG_DORQ_LENGTH_MIS 0xe0168
3046 /* [RW 8] The Event ID in case ErrorFlg input message bit is set. */
3047 #define UCM_REG_ERR_EVNT_ID 0xe00a4
3048 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
3049 #define UCM_REG_ERR_UCM_HDR 0xe00a0
3050 /* [RW 8] The Event ID for Timers expiration. */
3051 #define UCM_REG_EXPR_EVNT_ID 0xe00a8
3052 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
3053 writes the initial credit value; read returns the current value of the
3054 credit counter. Must be initialized to 64 at start-up. */
3055 #define UCM_REG_FIC0_INIT_CRD 0xe020c
3056 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
3057 writes the initial credit value; read returns the current value of the
3058 credit counter. Must be initialized to 64 at start-up. */
3059 #define UCM_REG_FIC1_INIT_CRD 0xe0210
3060 /* [RW 1] Arbitration between Input Arbiter groups: 0 - fair Round-Robin; 1
3061 - strict priority defined by ~ucm_registers_gr_ag_pr.gr_ag_pr;
3062 ~ucm_registers_gr_ld0_pr.gr_ld0_pr and
3063 ~ucm_registers_gr_ld1_pr.gr_ld1_pr. */
3064 #define UCM_REG_GR_ARB_TYPE 0xe0144
3065 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
3066 highest priority is 3. It is supposed that the Store channel group is
3067 compliment to the others. */
3068 #define UCM_REG_GR_LD0_PR 0xe014c
3069 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
3070 highest priority is 3. It is supposed that the Store channel group is
3071 compliment to the others. */
3072 #define UCM_REG_GR_LD1_PR 0xe0150
3073 /* [RW 2] The queue index for invalidate counter flag decision. */
3074 #define UCM_REG_INV_CFLG_Q 0xe00e4
3075 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
3076 sent to STORM; for a specific connection type. the double REG-pairs are
3077 used in order to align to STORM context row size of 128 bits. The offset
3078 of these data in the STORM context is always 0. Index _i stands for the
3079 connection type (one of 16). */
3080 #define UCM_REG_N_SM_CTX_LD_0 0xe0054
3081 #define UCM_REG_N_SM_CTX_LD_1 0xe0058
3082 #define UCM_REG_N_SM_CTX_LD_10 0xe007c
3083 #define UCM_REG_N_SM_CTX_LD_11 0xe0080
3084 #define UCM_REG_N_SM_CTX_LD_12 0xe0084
3085 #define UCM_REG_N_SM_CTX_LD_13 0xe0088
3086 #define UCM_REG_N_SM_CTX_LD_14 0xe008c
3087 #define UCM_REG_N_SM_CTX_LD_15 0xe0090
3088 #define UCM_REG_N_SM_CTX_LD_2 0xe005c
3089 #define UCM_REG_N_SM_CTX_LD_3 0xe0060
3090 #define UCM_REG_N_SM_CTX_LD_4 0xe0064
3091 /* [RW 6] The physical queue number 0 per port index (CID[23]) */
3092 #define UCM_REG_PHYS_QNUM0_0 0xe0110
3093 #define UCM_REG_PHYS_QNUM0_1 0xe0114
3094 /* [RW 6] The physical queue number 1 per port index (CID[23]) */
3095 #define UCM_REG_PHYS_QNUM1_0 0xe0118
3096 #define UCM_REG_PHYS_QNUM1_1 0xe011c
3097 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
3098 #define UCM_REG_STOP_EVNT_ID 0xe00ac
3099 /* [RC 1] Set when the message length mismatch (relative to last indication)
3100 at the STORM interface is detected. */
3101 #define UCM_REG_STORM_LENGTH_MIS 0xe0154
3102 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
3103 disregarded; acknowledge output is deasserted; all other signals are
3104 treated as usual; if 1 - normal activity. */
3105 #define UCM_REG_STORM_UCM_IFEN 0xe0010
3106 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
3107 writes the initial credit value; read returns the current value of the
3108 credit counter. Must be initialized to 4 at start-up. */
3109 #define UCM_REG_TM_INIT_CRD 0xe021c
3110 /* [RW 28] The CM header for Timers expiration command. */
3111 #define UCM_REG_TM_UCM_HDR 0xe009c
3112 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
3113 disregarded; acknowledge output is deasserted; all other signals are
3114 treated as usual; if 1 - normal activity. */
3115 #define UCM_REG_TM_UCM_IFEN 0xe001c
3116 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
3117 disregarded; acknowledge output is deasserted; all other signals are
3118 treated as usual; if 1 - normal activity. */
3119 #define UCM_REG_TSEM_IFEN 0xe0024
3120 /* [RC 1] Set when the message length mismatch (relative to last indication)
3121 at the tsem interface is detected. */
3122 #define UCM_REG_TSEM_LENGTH_MIS 0xe015c
3123 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
3124 weight 8 (the most prioritised); 1 stands for weight 1(least
3125 prioritised); 2 stands for weight 2; tc. */
3126 #define UCM_REG_TSEM_WEIGHT 0xe00b4
3127 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
3128 acknowledge output is deasserted; all other signals are treated as usual;
3129 if 1 - normal activity. */
3130 #define UCM_REG_UCM_CFC_IFEN 0xe0044
3131 /* [RW 11] Interrupt mask register #0 read/write */
3132 #define UCM_REG_UCM_INT_MASK 0xe01d4
3133 /* [R 11] Interrupt register #0 read */
3134 #define UCM_REG_UCM_INT_STS 0xe01c8
3135 /* [RW 2] The size of AG context region 0 in REG-pairs. Designates the MS
3136 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
3137 Is used to determine the number of the AG context REG-pairs written back;
3138 when the Reg1WbFlg isn't set. */
3139 #define UCM_REG_UCM_REG0_SZ 0xe00dc
3140 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
3141 disregarded; valid is deasserted; all other signals are treated as usual;
3142 if 1 - normal activity. */
3143 #define UCM_REG_UCM_STORM0_IFEN 0xe0004
3144 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
3145 disregarded; valid is deasserted; all other signals are treated as usual;
3146 if 1 - normal activity. */
3147 #define UCM_REG_UCM_STORM1_IFEN 0xe0008
3148 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
3149 disregarded; acknowledge output is deasserted; all other signals are
3150 treated as usual; if 1 - normal activity. */
3151 #define UCM_REG_UCM_TM_IFEN 0xe0020
3152 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
3153 disregarded; valid is deasserted; all other signals are treated as usual;
3154 if 1 - normal activity. */
3155 #define UCM_REG_UCM_UQM_IFEN 0xe000c
3156 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
3157 #define UCM_REG_UCM_UQM_USE_Q 0xe00d8
3158 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
3159 the initial credit value; read returns the current value of the credit
3160 counter. Must be initialized to 32 at start-up. */
3161 #define UCM_REG_UQM_INIT_CRD 0xe0220
3162 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
3163 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3164 prioritised); 2 stands for weight 2; tc. */
3165 #define UCM_REG_UQM_P_WEIGHT 0xe00cc
3166 /* [RW 28] The CM header value for QM request (primary). */
3167 #define UCM_REG_UQM_UCM_HDR_P 0xe0094
3168 /* [RW 28] The CM header value for QM request (secondary). */
3169 #define UCM_REG_UQM_UCM_HDR_S 0xe0098
3170 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
3171 acknowledge output is deasserted; all other signals are treated as usual;
3172 if 1 - normal activity. */
3173 #define UCM_REG_UQM_UCM_IFEN 0xe0014
3174 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
3175 acknowledge output is deasserted; all other signals are treated as usual;
3176 if 1 - normal activity. */
3177 #define UCM_REG_USDM_IFEN 0xe0018
3178 /* [RC 1] Set when the message length mismatch (relative to last indication)
3179 at the SDM interface is detected. */
3180 #define UCM_REG_USDM_LENGTH_MIS 0xe0158
3181 /* [RW 1] Input xsem Interface enable. If 0 - the valid input is
3182 disregarded; acknowledge output is deasserted; all other signals are
3183 treated as usual; if 1 - normal activity. */
3184 #define UCM_REG_XSEM_IFEN 0xe002c
3185 /* [RC 1] Set when the message length mismatch (relative to last indication)
3186 at the xsem interface isdetected. */
3187 #define UCM_REG_XSEM_LENGTH_MIS 0xe0164
3188 /* [RW 20] Indirect access to the descriptor table of the XX protection
3189 mechanism. The fields are:[5:0] - message length; 14:6] - message
3190 pointer; 19:15] - next pointer. */
3191 #define UCM_REG_XX_DESCR_TABLE 0xe0280
3192 /* [R 6] Use to read the XX protection Free counter. */
3193 #define UCM_REG_XX_FREE 0xe016c
3194 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
3195 of the Input Stage XX protection buffer by the XX protection pending
3196 messages. Write writes the initial credit value; read returns the current
3197 value of the credit counter. Must be initialized to 12 at start-up. */
3198 #define UCM_REG_XX_INIT_CRD 0xe0224
3199 /* [RW 6] The maximum number of pending messages; which may be stored in XX
3200 protection. ~ucm_registers_xx_free.xx_free read on read. */
3201 #define UCM_REG_XX_MSG_NUM 0xe0228
3202 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
3203 #define UCM_REG_XX_OVFL_EVNT_ID 0xe004c
3204 /* [RW 16] Indirect access to the XX table of the XX protection mechanism.
3205 The fields are: [4:0] - tail pointer; 10:5] - Link List size; 15:11] -
3206 header pointer. */
3207 #define UCM_REG_XX_TABLE 0xe0300
3208 /* [RW 8] The event id for aggregated interrupt 0 */
3209 #define USDM_REG_AGG_INT_EVENT_0 0xc4038
3210 #define USDM_REG_AGG_INT_EVENT_1 0xc403c
3211 #define USDM_REG_AGG_INT_EVENT_10 0xc4060
3212 #define USDM_REG_AGG_INT_EVENT_11 0xc4064
3213 #define USDM_REG_AGG_INT_EVENT_12 0xc4068
3214 #define USDM_REG_AGG_INT_EVENT_13 0xc406c
3215 #define USDM_REG_AGG_INT_EVENT_14 0xc4070
3216 #define USDM_REG_AGG_INT_EVENT_15 0xc4074
3217 #define USDM_REG_AGG_INT_EVENT_16 0xc4078
3218 #define USDM_REG_AGG_INT_EVENT_17 0xc407c
3219 #define USDM_REG_AGG_INT_EVENT_18 0xc4080
3220 #define USDM_REG_AGG_INT_EVENT_19 0xc4084
3221 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
3222 or auto-mask-mode (1) */
3223 #define USDM_REG_AGG_INT_MODE_0 0xc41b8
3224 #define USDM_REG_AGG_INT_MODE_1 0xc41bc
3225 #define USDM_REG_AGG_INT_MODE_10 0xc41e0
3226 #define USDM_REG_AGG_INT_MODE_11 0xc41e4
3227 #define USDM_REG_AGG_INT_MODE_12 0xc41e8
3228 #define USDM_REG_AGG_INT_MODE_13 0xc41ec
3229 #define USDM_REG_AGG_INT_MODE_14 0xc41f0
3230 #define USDM_REG_AGG_INT_MODE_15 0xc41f4
3231 #define USDM_REG_AGG_INT_MODE_16 0xc41f8
3232 #define USDM_REG_AGG_INT_MODE_17 0xc41fc
3233 #define USDM_REG_AGG_INT_MODE_18 0xc4200
3234 #define USDM_REG_AGG_INT_MODE_19 0xc4204
3235 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
3236 #define USDM_REG_CFC_RSP_START_ADDR 0xc4008
3237 /* [RW 16] The maximum value of the competion counter #0 */
3238 #define USDM_REG_CMP_COUNTER_MAX0 0xc401c
3239 /* [RW 16] The maximum value of the competion counter #1 */
3240 #define USDM_REG_CMP_COUNTER_MAX1 0xc4020
3241 /* [RW 16] The maximum value of the competion counter #2 */
3242 #define USDM_REG_CMP_COUNTER_MAX2 0xc4024
3243 /* [RW 16] The maximum value of the competion counter #3 */
3244 #define USDM_REG_CMP_COUNTER_MAX3 0xc4028
3245 /* [RW 13] The start address in the internal RAM for the completion
3246 counters. */
3247 #define USDM_REG_CMP_COUNTER_START_ADDR 0xc400c
3248 #define USDM_REG_ENABLE_IN1 0xc4238
3249 #define USDM_REG_ENABLE_IN2 0xc423c
3250 #define USDM_REG_ENABLE_OUT1 0xc4240
3251 #define USDM_REG_ENABLE_OUT2 0xc4244
3252 /* [RW 4] The initial number of messages that can be sent to the pxp control
3253 interface without receiving any ACK. */
3254 #define USDM_REG_INIT_CREDIT_PXP_CTRL 0xc44c0
3255 /* [ST 32] The number of ACK after placement messages received */
3256 #define USDM_REG_NUM_OF_ACK_AFTER_PLACE 0xc4280
3257 /* [ST 32] The number of packet end messages received from the parser */
3258 #define USDM_REG_NUM_OF_PKT_END_MSG 0xc4278
3259 /* [ST 32] The number of requests received from the pxp async if */
3260 #define USDM_REG_NUM_OF_PXP_ASYNC_REQ 0xc427c
3261 /* [ST 32] The number of commands received in queue 0 */
3262 #define USDM_REG_NUM_OF_Q0_CMD 0xc4248
3263 /* [ST 32] The number of commands received in queue 10 */
3264 #define USDM_REG_NUM_OF_Q10_CMD 0xc4270
3265 /* [ST 32] The number of commands received in queue 11 */
3266 #define USDM_REG_NUM_OF_Q11_CMD 0xc4274
3267 /* [ST 32] The number of commands received in queue 1 */
3268 #define USDM_REG_NUM_OF_Q1_CMD 0xc424c
3269 /* [ST 32] The number of commands received in queue 2 */
3270 #define USDM_REG_NUM_OF_Q2_CMD 0xc4250
3271 /* [ST 32] The number of commands received in queue 3 */
3272 #define USDM_REG_NUM_OF_Q3_CMD 0xc4254
3273 /* [ST 32] The number of commands received in queue 4 */
3274 #define USDM_REG_NUM_OF_Q4_CMD 0xc4258
3275 /* [ST 32] The number of commands received in queue 5 */
3276 #define USDM_REG_NUM_OF_Q5_CMD 0xc425c
3277 /* [ST 32] The number of commands received in queue 6 */
3278 #define USDM_REG_NUM_OF_Q6_CMD 0xc4260
3279 /* [ST 32] The number of commands received in queue 7 */
3280 #define USDM_REG_NUM_OF_Q7_CMD 0xc4264
3281 /* [ST 32] The number of commands received in queue 8 */
3282 #define USDM_REG_NUM_OF_Q8_CMD 0xc4268
3283 /* [ST 32] The number of commands received in queue 9 */
3284 #define USDM_REG_NUM_OF_Q9_CMD 0xc426c
3285 /* [RW 13] The start address in the internal RAM for the packet end message */
3286 #define USDM_REG_PCK_END_MSG_START_ADDR 0xc4014
3287 /* [RW 13] The start address in the internal RAM for queue counters */
3288 #define USDM_REG_Q_COUNTER_START_ADDR 0xc4010
3289 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
3290 #define USDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0xc4550
3291 /* [R 1] parser fifo empty in sdm_sync block */
3292 #define USDM_REG_SYNC_PARSER_EMPTY 0xc4558
3293 /* [R 1] parser serial fifo empty in sdm_sync block */
3294 #define USDM_REG_SYNC_SYNC_EMPTY 0xc4560
3295 /* [RW 32] Tick for timer counter. Applicable only when
3296 ~usdm_registers_timer_tick_enable.timer_tick_enable =1 */
3297 #define USDM_REG_TIMER_TICK 0xc4000
3298 /* [RW 32] Interrupt mask register #0 read/write */
3299 #define USDM_REG_USDM_INT_MASK_0 0xc42a0
3300 #define USDM_REG_USDM_INT_MASK_1 0xc42b0
3301 /* [RW 11] Parity mask register #0 read/write */
3302 #define USDM_REG_USDM_PRTY_MASK 0xc42c0
3303 /* [R 11] Parity register #0 read */
3304 #define USDM_REG_USDM_PRTY_STS 0xc42b4
3305 /* [RW 5] The number of time_slots in the arbitration cycle */
3306 #define USEM_REG_ARB_CYCLE_SIZE 0x300034
3307 /* [RW 3] The source that is associated with arbitration element 0. Source
3308 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3309 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
3310 #define USEM_REG_ARB_ELEMENT0 0x300020
3311 /* [RW 3] The source that is associated with arbitration element 1. Source
3312 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3313 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3314 Could not be equal to register ~usem_registers_arb_element0.arb_element0 */
3315 #define USEM_REG_ARB_ELEMENT1 0x300024
3316 /* [RW 3] The source that is associated with arbitration element 2. Source
3317 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3318 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3319 Could not be equal to register ~usem_registers_arb_element0.arb_element0
3320 and ~usem_registers_arb_element1.arb_element1 */
3321 #define USEM_REG_ARB_ELEMENT2 0x300028
3322 /* [RW 3] The source that is associated with arbitration element 3. Source
3323 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3324 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
3325 not be equal to register ~usem_registers_arb_element0.arb_element0 and
3326 ~usem_registers_arb_element1.arb_element1 and
3327 ~usem_registers_arb_element2.arb_element2 */
3328 #define USEM_REG_ARB_ELEMENT3 0x30002c
3329 /* [RW 3] The source that is associated with arbitration element 4. Source
3330 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3331 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3332 Could not be equal to register ~usem_registers_arb_element0.arb_element0
3333 and ~usem_registers_arb_element1.arb_element1 and
3334 ~usem_registers_arb_element2.arb_element2 and
3335 ~usem_registers_arb_element3.arb_element3 */
3336 #define USEM_REG_ARB_ELEMENT4 0x300030
3337 #define USEM_REG_ENABLE_IN 0x3000a4
3338 #define USEM_REG_ENABLE_OUT 0x3000a8
3339 /* [RW 32] This address space contains all registers and memories that are
3340 placed in SEM_FAST block. The SEM_FAST registers are described in
3341 appendix B. In order to access the SEM_FAST registers... the base address
3342 USEM_REGISTERS_FAST_MEMORY (Offset: 0x320000) should be added to each
3343 SEM_FAST register offset. */
3344 #define USEM_REG_FAST_MEMORY 0x320000
3345 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
3346 by the microcode */
3347 #define USEM_REG_FIC0_DISABLE 0x300224
3348 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
3349 by the microcode */
3350 #define USEM_REG_FIC1_DISABLE 0x300234
3351 /* [RW 15] Interrupt table Read and write access to it is not possible in
3352 the middle of the work */
3353 #define USEM_REG_INT_TABLE 0x300400
3354 /* [ST 24] Statistics register. The number of messages that entered through
3355 FIC0 */
3356 #define USEM_REG_MSG_NUM_FIC0 0x300000
3357 /* [ST 24] Statistics register. The number of messages that entered through
3358 FIC1 */
3359 #define USEM_REG_MSG_NUM_FIC1 0x300004
3360 /* [ST 24] Statistics register. The number of messages that were sent to
3361 FOC0 */
3362 #define USEM_REG_MSG_NUM_FOC0 0x300008
3363 /* [ST 24] Statistics register. The number of messages that were sent to
3364 FOC1 */
3365 #define USEM_REG_MSG_NUM_FOC1 0x30000c
3366 /* [ST 24] Statistics register. The number of messages that were sent to
3367 FOC2 */
3368 #define USEM_REG_MSG_NUM_FOC2 0x300010
3369 /* [ST 24] Statistics register. The number of messages that were sent to
3370 FOC3 */
3371 #define USEM_REG_MSG_NUM_FOC3 0x300014
3372 /* [RW 1] Disables input messages from the passive buffer May be updated
3373 during run_time by the microcode */
3374 #define USEM_REG_PAS_DISABLE 0x30024c
3375 /* [WB 128] Debug only. Passive buffer memory */
3376 #define USEM_REG_PASSIVE_BUFFER 0x302000
3377 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
3378 #define USEM_REG_PRAM 0x340000
3379 /* [R 16] Valid sleeping threads indication have bit per thread */
3380 #define USEM_REG_SLEEP_THREADS_VALID 0x30026c
3381 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
3382 #define USEM_REG_SLOW_EXT_STORE_EMPTY 0x3002a0
3383 /* [RW 16] List of free threads . There is a bit per thread. */
3384 #define USEM_REG_THREADS_LIST 0x3002e4
3385 /* [RW 3] The arbitration scheme of time_slot 0 */
3386 #define USEM_REG_TS_0_AS 0x300038
3387 /* [RW 3] The arbitration scheme of time_slot 10 */
3388 #define USEM_REG_TS_10_AS 0x300060
3389 /* [RW 3] The arbitration scheme of time_slot 11 */
3390 #define USEM_REG_TS_11_AS 0x300064
3391 /* [RW 3] The arbitration scheme of time_slot 12 */
3392 #define USEM_REG_TS_12_AS 0x300068
3393 /* [RW 3] The arbitration scheme of time_slot 13 */
3394 #define USEM_REG_TS_13_AS 0x30006c
3395 /* [RW 3] The arbitration scheme of time_slot 14 */
3396 #define USEM_REG_TS_14_AS 0x300070
3397 /* [RW 3] The arbitration scheme of time_slot 15 */
3398 #define USEM_REG_TS_15_AS 0x300074
3399 /* [RW 3] The arbitration scheme of time_slot 16 */
3400 #define USEM_REG_TS_16_AS 0x300078
3401 /* [RW 3] The arbitration scheme of time_slot 17 */
3402 #define USEM_REG_TS_17_AS 0x30007c
3403 /* [RW 3] The arbitration scheme of time_slot 18 */
3404 #define USEM_REG_TS_18_AS 0x300080
3405 /* [RW 3] The arbitration scheme of time_slot 1 */
3406 #define USEM_REG_TS_1_AS 0x30003c
3407 /* [RW 3] The arbitration scheme of time_slot 2 */
3408 #define USEM_REG_TS_2_AS 0x300040
3409 /* [RW 3] The arbitration scheme of time_slot 3 */
3410 #define USEM_REG_TS_3_AS 0x300044
3411 /* [RW 3] The arbitration scheme of time_slot 4 */
3412 #define USEM_REG_TS_4_AS 0x300048
3413 /* [RW 3] The arbitration scheme of time_slot 5 */
3414 #define USEM_REG_TS_5_AS 0x30004c
3415 /* [RW 3] The arbitration scheme of time_slot 6 */
3416 #define USEM_REG_TS_6_AS 0x300050
3417 /* [RW 3] The arbitration scheme of time_slot 7 */
3418 #define USEM_REG_TS_7_AS 0x300054
3419 /* [RW 3] The arbitration scheme of time_slot 8 */
3420 #define USEM_REG_TS_8_AS 0x300058
3421 /* [RW 3] The arbitration scheme of time_slot 9 */
3422 #define USEM_REG_TS_9_AS 0x30005c
3423 /* [RW 32] Interrupt mask register #0 read/write */
3424 #define USEM_REG_USEM_INT_MASK_0 0x300110
3425 #define USEM_REG_USEM_INT_MASK_1 0x300120
3426 /* [RW 32] Parity mask register #0 read/write */
3427 #define USEM_REG_USEM_PRTY_MASK_0 0x300130
3428 #define USEM_REG_USEM_PRTY_MASK_1 0x300140
3429 /* [R 32] Parity register #0 read */
3430 #define USEM_REG_USEM_PRTY_STS_0 0x300124
3431 #define USEM_REG_USEM_PRTY_STS_1 0x300134
3432 /* [RW 2] The queue index for registration on Aux1 counter flag. */
3433 #define XCM_REG_AUX1_Q 0x20134
3434 /* [RW 2] Per each decision rule the queue index to register to. */
3435 #define XCM_REG_AUX_CNT_FLG_Q_19 0x201b0
3436 /* [R 5] Used to read the XX protection CAM occupancy counter. */
3437 #define XCM_REG_CAM_OCCUP 0x20244
3438 /* [RW 1] CDU AG read Interface enable. If 0 - the request input is
3439 disregarded; valid output is deasserted; all other signals are treated as
3440 usual; if 1 - normal activity. */
3441 #define XCM_REG_CDU_AG_RD_IFEN 0x20044
3442 /* [RW 1] CDU AG write Interface enable. If 0 - the request and valid input
3443 are disregarded; all other signals are treated as usual; if 1 - normal
3444 activity. */
3445 #define XCM_REG_CDU_AG_WR_IFEN 0x20040
3446 /* [RW 1] CDU STORM read Interface enable. If 0 - the request input is
3447 disregarded; valid output is deasserted; all other signals are treated as
3448 usual; if 1 - normal activity. */
3449 #define XCM_REG_CDU_SM_RD_IFEN 0x2004c
3450 /* [RW 1] CDU STORM write Interface enable. If 0 - the request and valid
3451 input is disregarded; all other signals are treated as usual; if 1 -
3452 normal activity. */
3453 #define XCM_REG_CDU_SM_WR_IFEN 0x20048
3454 /* [RW 4] CFC output initial credit. Max credit available - 15.Write writes
3455 the initial credit value; read returns the current value of the credit
3456 counter. Must be initialized to 1 at start-up. */
3457 #define XCM_REG_CFC_INIT_CRD 0x20404
3458 /* [RW 3] The weight of the CP input in the WRR mechanism. 0 stands for
3459 weight 8 (the most prioritised); 1 stands for weight 1(least
3460 prioritised); 2 stands for weight 2; tc. */
3461 #define XCM_REG_CP_WEIGHT 0x200dc
3462 /* [RW 1] Input csem Interface enable. If 0 - the valid input is
3463 disregarded; acknowledge output is deasserted; all other signals are
3464 treated as usual; if 1 - normal activity. */
3465 #define XCM_REG_CSEM_IFEN 0x20028
3466 /* [RC 1] Set at message length mismatch (relative to last indication) at
3467 the csem interface. */
3468 #define XCM_REG_CSEM_LENGTH_MIS 0x20228
3469 /* [RW 3] The weight of the input csem in the WRR mechanism. 0 stands for
3470 weight 8 (the most prioritised); 1 stands for weight 1(least
3471 prioritised); 2 stands for weight 2; tc. */
3472 #define XCM_REG_CSEM_WEIGHT 0x200c4
3473 /* [RW 1] Input dorq Interface enable. If 0 - the valid input is
3474 disregarded; acknowledge output is deasserted; all other signals are
3475 treated as usual; if 1 - normal activity. */
3476 #define XCM_REG_DORQ_IFEN 0x20030
3477 /* [RC 1] Set at message length mismatch (relative to last indication) at
3478 the dorq interface. */
3479 #define XCM_REG_DORQ_LENGTH_MIS 0x20230
3480 /* [RW 8] The Event ID in case the ErrorFlg input message bit is set. */
3481 #define XCM_REG_ERR_EVNT_ID 0x200b0
3482 /* [RW 28] The CM erroneous header for QM and Timers formatting. */
3483 #define XCM_REG_ERR_XCM_HDR 0x200ac
3484 /* [RW 8] The Event ID for Timers expiration. */
3485 #define XCM_REG_EXPR_EVNT_ID 0x200b4
3486 /* [RW 8] FIC0 output initial credit. Max credit available - 255.Write
3487 writes the initial credit value; read returns the current value of the
3488 credit counter. Must be initialized to 64 at start-up. */
3489 #define XCM_REG_FIC0_INIT_CRD 0x2040c
3490 /* [RW 8] FIC1 output initial credit. Max credit available - 255.Write
3491 writes the initial credit value; read returns the current value of the
3492 credit counter. Must be initialized to 64 at start-up. */
3493 #define XCM_REG_FIC1_INIT_CRD 0x20410
3494 /* [RW 8] The maximum delayed ACK counter value.Must be at least 2. Per port
3495 value. */
3496 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_0 0x20118
3497 #define XCM_REG_GLB_DEL_ACK_MAX_CNT_1 0x2011c
3498 /* [RW 28] The delayed ACK timeout in ticks. Per port value. */
3499 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_0 0x20108
3500 #define XCM_REG_GLB_DEL_ACK_TMR_VAL_1 0x2010c
3501 /* [RW 1] Arbitratiojn between Input Arbiter groups: 0 - fair Round-Robin; 1
3502 - strict priority defined by ~xcm_registers_gr_ag_pr.gr_ag_pr;
3503 ~xcm_registers_gr_ld0_pr.gr_ld0_pr and
3504 ~xcm_registers_gr_ld1_pr.gr_ld1_pr. */
3505 #define XCM_REG_GR_ARB_TYPE 0x2020c
3506 /* [RW 2] Load (FIC0) channel group priority. The lowest priority is 0; the
3507 highest priority is 3. It is supposed that the Channel group is the
3508 compliment of the other 3 groups. */
3509 #define XCM_REG_GR_LD0_PR 0x20214
3510 /* [RW 2] Load (FIC1) channel group priority. The lowest priority is 0; the
3511 highest priority is 3. It is supposed that the Channel group is the
3512 compliment of the other 3 groups. */
3513 #define XCM_REG_GR_LD1_PR 0x20218
3514 /* [RW 1] Input nig0 Interface enable. If 0 - the valid input is
3515 disregarded; acknowledge output is deasserted; all other signals are
3516 treated as usual; if 1 - normal activity. */
3517 #define XCM_REG_NIG0_IFEN 0x20038
3518 /* [RC 1] Set at message length mismatch (relative to last indication) at
3519 the nig0 interface. */
3520 #define XCM_REG_NIG0_LENGTH_MIS 0x20238
3521 /* [RW 1] Input nig1 Interface enable. If 0 - the valid input is
3522 disregarded; acknowledge output is deasserted; all other signals are
3523 treated as usual; if 1 - normal activity. */
3524 #define XCM_REG_NIG1_IFEN 0x2003c
3525 /* [RC 1] Set at message length mismatch (relative to last indication) at
3526 the nig1 interface. */
3527 #define XCM_REG_NIG1_LENGTH_MIS 0x2023c
3528 /* [RW 3] The weight of the input nig1 in the WRR mechanism. 0 stands for
3529 weight 8 (the most prioritised); 1 stands for weight 1(least
3530 prioritised); 2 stands for weight 2; tc. */
3531 #define XCM_REG_NIG1_WEIGHT 0x200d8
3532 /* [RW 5] The number of double REG-pairs; loaded from the STORM context and
3533 sent to STORM; for a specific connection type. The double REG-pairs are
3534 used in order to align to STORM context row size of 128 bits. The offset
3535 of these data in the STORM context is always 0. Index _i stands for the
3536 connection type (one of 16). */
3537 #define XCM_REG_N_SM_CTX_LD_0 0x20060
3538 #define XCM_REG_N_SM_CTX_LD_1 0x20064
3539 #define XCM_REG_N_SM_CTX_LD_10 0x20088
3540 #define XCM_REG_N_SM_CTX_LD_11 0x2008c
3541 #define XCM_REG_N_SM_CTX_LD_12 0x20090
3542 #define XCM_REG_N_SM_CTX_LD_13 0x20094
3543 #define XCM_REG_N_SM_CTX_LD_14 0x20098
3544 #define XCM_REG_N_SM_CTX_LD_15 0x2009c
3545 #define XCM_REG_N_SM_CTX_LD_2 0x20068
3546 #define XCM_REG_N_SM_CTX_LD_3 0x2006c
3547 #define XCM_REG_N_SM_CTX_LD_4 0x20070
3548 /* [RW 1] Input pbf Interface enable. If 0 - the valid input is disregarded;
3549 acknowledge output is deasserted; all other signals are treated as usual;
3550 if 1 - normal activity. */
3551 #define XCM_REG_PBF_IFEN 0x20034
3552 /* [RC 1] Set at message length mismatch (relative to last indication) at
3553 the pbf interface. */
3554 #define XCM_REG_PBF_LENGTH_MIS 0x20234
3555 /* [RW 3] The weight of the input pbf in the WRR mechanism. 0 stands for
3556 weight 8 (the most prioritised); 1 stands for weight 1(least
3557 prioritised); 2 stands for weight 2; tc. */
3558 #define XCM_REG_PBF_WEIGHT 0x200d0
3559 /* [RW 8] The Event ID for Timers formatting in case of stop done. */
3560 #define XCM_REG_STOP_EVNT_ID 0x200b8
3561 /* [RC 1] Set at message length mismatch (relative to last indication) at
3562 the STORM interface. */
3563 #define XCM_REG_STORM_LENGTH_MIS 0x2021c
3564 /* [RW 3] The weight of the STORM input in the WRR mechanism. 0 stands for
3565 weight 8 (the most prioritised); 1 stands for weight 1(least
3566 prioritised); 2 stands for weight 2; tc. */
3567 #define XCM_REG_STORM_WEIGHT 0x200bc
3568 /* [RW 1] STORM - CM Interface enable. If 0 - the valid input is
3569 disregarded; acknowledge output is deasserted; all other signals are
3570 treated as usual; if 1 - normal activity. */
3571 #define XCM_REG_STORM_XCM_IFEN 0x20010
3572 /* [RW 4] Timers output initial credit. Max credit available - 15.Write
3573 writes the initial credit value; read returns the current value of the
3574 credit counter. Must be initialized to 4 at start-up. */
3575 #define XCM_REG_TM_INIT_CRD 0x2041c
3576 /* [RW 28] The CM header for Timers expiration command. */
3577 #define XCM_REG_TM_XCM_HDR 0x200a8
3578 /* [RW 1] Timers - CM Interface enable. If 0 - the valid input is
3579 disregarded; acknowledge output is deasserted; all other signals are
3580 treated as usual; if 1 - normal activity. */
3581 #define XCM_REG_TM_XCM_IFEN 0x2001c
3582 /* [RW 1] Input tsem Interface enable. If 0 - the valid input is
3583 disregarded; acknowledge output is deasserted; all other signals are
3584 treated as usual; if 1 - normal activity. */
3585 #define XCM_REG_TSEM_IFEN 0x20024
3586 /* [RC 1] Set at message length mismatch (relative to last indication) at
3587 the tsem interface. */
3588 #define XCM_REG_TSEM_LENGTH_MIS 0x20224
3589 /* [RW 3] The weight of the input tsem in the WRR mechanism. 0 stands for
3590 weight 8 (the most prioritised); 1 stands for weight 1(least
3591 prioritised); 2 stands for weight 2; tc. */
3592 #define XCM_REG_TSEM_WEIGHT 0x200c0
3593 /* [RW 2] The queue index for registration on UNA greater NXT decision rule. */
3594 #define XCM_REG_UNA_GT_NXT_Q 0x20120
3595 /* [RW 1] Input usem Interface enable. If 0 - the valid input is
3596 disregarded; acknowledge output is deasserted; all other signals are
3597 treated as usual; if 1 - normal activity. */
3598 #define XCM_REG_USEM_IFEN 0x2002c
3599 /* [RC 1] Message length mismatch (relative to last indication) at the usem
3600 interface. */
3601 #define XCM_REG_USEM_LENGTH_MIS 0x2022c
3602 /* [RW 3] The weight of the input usem in the WRR mechanism. 0 stands for
3603 weight 8 (the most prioritised); 1 stands for weight 1(least
3604 prioritised); 2 stands for weight 2; tc. */
3605 #define XCM_REG_USEM_WEIGHT 0x200c8
3606 /* [RW 2] DA counter command; used in case of window update doorbell.The
3607 first index stands for the value DaEnable of that connection. The second
3608 index stands for port number. */
3609 #define XCM_REG_WU_DA_CNT_CMD00 0x201d4
3610 /* [RW 2] DA counter command; used in case of window update doorbell.The
3611 first index stands for the value DaEnable of that connection. The second
3612 index stands for port number. */
3613 #define XCM_REG_WU_DA_CNT_CMD01 0x201d8
3614 /* [RW 2] DA counter command; used in case of window update doorbell.The
3615 first index stands for the value DaEnable of that connection. The second
3616 index stands for port number. */
3617 #define XCM_REG_WU_DA_CNT_CMD10 0x201dc
3618 /* [RW 2] DA counter command; used in case of window update doorbell.The
3619 first index stands for the value DaEnable of that connection. The second
3620 index stands for port number. */
3621 #define XCM_REG_WU_DA_CNT_CMD11 0x201e0
3622 /* [RW 8] DA counter update value used in case of window update doorbell.The
3623 first index stands for the value DaEnable of that connection. The second
3624 index stands for port number. */
3625 #define XCM_REG_WU_DA_CNT_UPD_VAL00 0x201e4
3626 /* [RW 8] DA counter update value; used in case of window update
3627 doorbell.The first index stands for the value DaEnable of that
3628 connection. The second index stands for port number. */
3629 #define XCM_REG_WU_DA_CNT_UPD_VAL01 0x201e8
3630 /* [RW 8] DA counter update value; used in case of window update
3631 doorbell.The first index stands for the value DaEnable of that
3632 connection. The second index stands for port number. */
3633 #define XCM_REG_WU_DA_CNT_UPD_VAL10 0x201ec
3634 /* [RW 8] DA counter update value; used in case of window update
3635 doorbell.The first index stands for the value DaEnable of that
3636 connection. The second index stands for port number. */
3637 #define XCM_REG_WU_DA_CNT_UPD_VAL11 0x201f0
3638 /* [RW 1] DA timer command; used in case of window update doorbell.The first
3639 index stands for the value DaEnable of that connection. The second index
3640 stands for port number. */
3641 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00 0x201c4
3642 /* [RW 1] DA timer command; used in case of window update doorbell.The first
3643 index stands for the value DaEnable of that connection. The second index
3644 stands for port number. */
3645 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01 0x201c8
3646 /* [RW 1] DA timer command; used in case of window update doorbell.The first
3647 index stands for the value DaEnable of that connection. The second index
3648 stands for port number. */
3649 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10 0x201cc
3650 /* [RW 1] DA timer command; used in case of window update doorbell.The first
3651 index stands for the value DaEnable of that connection. The second index
3652 stands for port number. */
3653 #define XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11 0x201d0
3654 /* [RW 1] CM - CFC Interface enable. If 0 - the valid input is disregarded;
3655 acknowledge output is deasserted; all other signals are treated as usual;
3656 if 1 - normal activity. */
3657 #define XCM_REG_XCM_CFC_IFEN 0x20050
3658 /* [RW 14] Interrupt mask register #0 read/write */
3659 #define XCM_REG_XCM_INT_MASK 0x202b4
3660 /* [R 14] Interrupt register #0 read */
3661 #define XCM_REG_XCM_INT_STS 0x202a8
3662 /* [RW 4] The size of AG context region 0 in REG-pairs. Designates the MS
3663 REG-pair number (e.g. if region 0 is 6 REG-pairs; the value should be 5).
3664 Is used to determine the number of the AG context REG-pairs written back;
3665 when the Reg1WbFlg isn't set. */
3666 #define XCM_REG_XCM_REG0_SZ 0x200f4
3667 /* [RW 1] CM - STORM 0 Interface enable. If 0 - the acknowledge input is
3668 disregarded; valid is deasserted; all other signals are treated as usual;
3669 if 1 - normal activity. */
3670 #define XCM_REG_XCM_STORM0_IFEN 0x20004
3671 /* [RW 1] CM - STORM 1 Interface enable. If 0 - the acknowledge input is
3672 disregarded; valid is deasserted; all other signals are treated as usual;
3673 if 1 - normal activity. */
3674 #define XCM_REG_XCM_STORM1_IFEN 0x20008
3675 /* [RW 1] CM - Timers Interface enable. If 0 - the valid input is
3676 disregarded; acknowledge output is deasserted; all other signals are
3677 treated as usual; if 1 - normal activity. */
3678 #define XCM_REG_XCM_TM_IFEN 0x20020
3679 /* [RW 1] CM - QM Interface enable. If 0 - the acknowledge input is
3680 disregarded; valid is deasserted; all other signals are treated as usual;
3681 if 1 - normal activity. */
3682 #define XCM_REG_XCM_XQM_IFEN 0x2000c
3683 /* [RW 1] If set the Q index; received from the QM is inserted to event ID. */
3684 #define XCM_REG_XCM_XQM_USE_Q 0x200f0
3685 /* [RW 4] The value by which CFC updates the activity counter at QM bypass. */
3686 #define XCM_REG_XQM_BYP_ACT_UPD 0x200fc
3687 /* [RW 6] QM output initial credit. Max credit available - 32.Write writes
3688 the initial credit value; read returns the current value of the credit
3689 counter. Must be initialized to 32 at start-up. */
3690 #define XCM_REG_XQM_INIT_CRD 0x20420
3691 /* [RW 3] The weight of the QM (primary) input in the WRR mechanism. 0
3692 stands for weight 8 (the most prioritised); 1 stands for weight 1(least
3693 prioritised); 2 stands for weight 2; tc. */
3694 #define XCM_REG_XQM_P_WEIGHT 0x200e4
3695 /* [RW 28] The CM header value for QM request (primary). */
3696 #define XCM_REG_XQM_XCM_HDR_P 0x200a0
3697 /* [RW 28] The CM header value for QM request (secondary). */
3698 #define XCM_REG_XQM_XCM_HDR_S 0x200a4
3699 /* [RW 1] QM - CM Interface enable. If 0 - the valid input is disregarded;
3700 acknowledge output is deasserted; all other signals are treated as usual;
3701 if 1 - normal activity. */
3702 #define XCM_REG_XQM_XCM_IFEN 0x20014
3703 /* [RW 1] Input SDM Interface enable. If 0 - the valid input is disregarded;
3704 acknowledge output is deasserted; all other signals are treated as usual;
3705 if 1 - normal activity. */
3706 #define XCM_REG_XSDM_IFEN 0x20018
3707 /* [RC 1] Set at message length mismatch (relative to last indication) at
3708 the SDM interface. */
3709 #define XCM_REG_XSDM_LENGTH_MIS 0x20220
3710 /* [RW 3] The weight of the SDM input in the WRR mechanism. 0 stands for
3711 weight 8 (the most prioritised); 1 stands for weight 1(least
3712 prioritised); 2 stands for weight 2; tc. */
3713 #define XCM_REG_XSDM_WEIGHT 0x200e0
3714 /* [RW 17] Indirect access to the descriptor table of the XX protection
3715 mechanism. The fields are: [5:0] - message length; 11:6] - message
3716 pointer; 16:12] - next pointer. */
3717 #define XCM_REG_XX_DESCR_TABLE 0x20480
3718 /* [R 6] Used to read the XX protection Free counter. */
3719 #define XCM_REG_XX_FREE 0x20240
3720 /* [RW 6] Initial value for the credit counter; responsible for fulfilling
3721 of the Input Stage XX protection buffer by the XX protection pending
3722 messages. Max credit available - 3.Write writes the initial credit value;
3723 read returns the current value of the credit counter. Must be initialized
3724 to 2 at start-up. */
3725 #define XCM_REG_XX_INIT_CRD 0x20424
3726 /* [RW 6] The maximum number of pending messages; which may be stored in XX
3727 protection. ~xcm_registers_xx_free.xx_free read on read. */
3728 #define XCM_REG_XX_MSG_NUM 0x20428
3729 /* [RW 8] The Event ID; sent to the STORM in case of XX overflow. */
3730 #define XCM_REG_XX_OVFL_EVNT_ID 0x20058
3731 /* [RW 15] Indirect access to the XX table of the XX protection mechanism.
3732 The fields are:[4:0] - tail pointer; 9:5] - Link List size; 14:10] -
3733 header pointer. */
3734 #define XCM_REG_XX_TABLE 0x20500
3735 /* [RW 8] The event id for aggregated interrupt 0 */
3736 #define XSDM_REG_AGG_INT_EVENT_0 0x166038
3737 #define XSDM_REG_AGG_INT_EVENT_1 0x16603c
3738 #define XSDM_REG_AGG_INT_EVENT_10 0x166060
3739 #define XSDM_REG_AGG_INT_EVENT_11 0x166064
3740 #define XSDM_REG_AGG_INT_EVENT_12 0x166068
3741 #define XSDM_REG_AGG_INT_EVENT_13 0x16606c
3742 #define XSDM_REG_AGG_INT_EVENT_14 0x166070
3743 #define XSDM_REG_AGG_INT_EVENT_15 0x166074
3744 #define XSDM_REG_AGG_INT_EVENT_16 0x166078
3745 #define XSDM_REG_AGG_INT_EVENT_17 0x16607c
3746 #define XSDM_REG_AGG_INT_EVENT_18 0x166080
3747 #define XSDM_REG_AGG_INT_EVENT_19 0x166084
3748 #define XSDM_REG_AGG_INT_EVENT_2 0x166040
3749 #define XSDM_REG_AGG_INT_EVENT_20 0x166088
3750 #define XSDM_REG_AGG_INT_EVENT_21 0x16608c
3751 #define XSDM_REG_AGG_INT_EVENT_22 0x166090
3752 #define XSDM_REG_AGG_INT_EVENT_23 0x166094
3753 #define XSDM_REG_AGG_INT_EVENT_24 0x166098
3754 #define XSDM_REG_AGG_INT_EVENT_25 0x16609c
3755 #define XSDM_REG_AGG_INT_EVENT_26 0x1660a0
3756 #define XSDM_REG_AGG_INT_EVENT_27 0x1660a4
3757 #define XSDM_REG_AGG_INT_EVENT_28 0x1660a8
3758 #define XSDM_REG_AGG_INT_EVENT_29 0x1660ac
3759 /* [RW 1] For each aggregated interrupt index whether the mode is normal (0)
3760 or auto-mask-mode (1) */
3761 #define XSDM_REG_AGG_INT_MODE_0 0x1661b8
3762 #define XSDM_REG_AGG_INT_MODE_1 0x1661bc
3763 #define XSDM_REG_AGG_INT_MODE_10 0x1661e0
3764 #define XSDM_REG_AGG_INT_MODE_11 0x1661e4
3765 #define XSDM_REG_AGG_INT_MODE_12 0x1661e8
3766 #define XSDM_REG_AGG_INT_MODE_13 0x1661ec
3767 #define XSDM_REG_AGG_INT_MODE_14 0x1661f0
3768 #define XSDM_REG_AGG_INT_MODE_15 0x1661f4
3769 #define XSDM_REG_AGG_INT_MODE_16 0x1661f8
3770 #define XSDM_REG_AGG_INT_MODE_17 0x1661fc
3771 #define XSDM_REG_AGG_INT_MODE_18 0x166200
3772 #define XSDM_REG_AGG_INT_MODE_19 0x166204
3773 /* [RW 13] The start address in the internal RAM for the cfc_rsp lcid */
3774 #define XSDM_REG_CFC_RSP_START_ADDR 0x166008
3775 /* [RW 16] The maximum value of the competion counter #0 */
3776 #define XSDM_REG_CMP_COUNTER_MAX0 0x16601c
3777 /* [RW 16] The maximum value of the competion counter #1 */
3778 #define XSDM_REG_CMP_COUNTER_MAX1 0x166020
3779 /* [RW 16] The maximum value of the competion counter #2 */
3780 #define XSDM_REG_CMP_COUNTER_MAX2 0x166024
3781 /* [RW 16] The maximum value of the competion counter #3 */
3782 #define XSDM_REG_CMP_COUNTER_MAX3 0x166028
3783 /* [RW 13] The start address in the internal RAM for the completion
3784 counters. */
3785 #define XSDM_REG_CMP_COUNTER_START_ADDR 0x16600c
3786 #define XSDM_REG_ENABLE_IN1 0x166238
3787 #define XSDM_REG_ENABLE_IN2 0x16623c
3788 #define XSDM_REG_ENABLE_OUT1 0x166240
3789 #define XSDM_REG_ENABLE_OUT2 0x166244
3790 /* [RW 4] The initial number of messages that can be sent to the pxp control
3791 interface without receiving any ACK. */
3792 #define XSDM_REG_INIT_CREDIT_PXP_CTRL 0x1664bc
3793 /* [ST 32] The number of ACK after placement messages received */
3794 #define XSDM_REG_NUM_OF_ACK_AFTER_PLACE 0x16627c
3795 /* [ST 32] The number of packet end messages received from the parser */
3796 #define XSDM_REG_NUM_OF_PKT_END_MSG 0x166274
3797 /* [ST 32] The number of requests received from the pxp async if */
3798 #define XSDM_REG_NUM_OF_PXP_ASYNC_REQ 0x166278
3799 /* [ST 32] The number of commands received in queue 0 */
3800 #define XSDM_REG_NUM_OF_Q0_CMD 0x166248
3801 /* [ST 32] The number of commands received in queue 10 */
3802 #define XSDM_REG_NUM_OF_Q10_CMD 0x16626c
3803 /* [ST 32] The number of commands received in queue 11 */
3804 #define XSDM_REG_NUM_OF_Q11_CMD 0x166270
3805 /* [ST 32] The number of commands received in queue 1 */
3806 #define XSDM_REG_NUM_OF_Q1_CMD 0x16624c
3807 /* [ST 32] The number of commands received in queue 3 */
3808 #define XSDM_REG_NUM_OF_Q3_CMD 0x166250
3809 /* [ST 32] The number of commands received in queue 4 */
3810 #define XSDM_REG_NUM_OF_Q4_CMD 0x166254
3811 /* [ST 32] The number of commands received in queue 5 */
3812 #define XSDM_REG_NUM_OF_Q5_CMD 0x166258
3813 /* [ST 32] The number of commands received in queue 6 */
3814 #define XSDM_REG_NUM_OF_Q6_CMD 0x16625c
3815 /* [ST 32] The number of commands received in queue 7 */
3816 #define XSDM_REG_NUM_OF_Q7_CMD 0x166260
3817 /* [ST 32] The number of commands received in queue 8 */
3818 #define XSDM_REG_NUM_OF_Q8_CMD 0x166264
3819 /* [ST 32] The number of commands received in queue 9 */
3820 #define XSDM_REG_NUM_OF_Q9_CMD 0x166268
3821 /* [RW 13] The start address in the internal RAM for queue counters */
3822 #define XSDM_REG_Q_COUNTER_START_ADDR 0x166010
3823 /* [R 1] pxp_ctrl rd_data fifo empty in sdm_dma_rsp block */
3824 #define XSDM_REG_RSP_PXP_CTRL_RDATA_EMPTY 0x166548
3825 /* [R 1] parser fifo empty in sdm_sync block */
3826 #define XSDM_REG_SYNC_PARSER_EMPTY 0x166550
3827 /* [R 1] parser serial fifo empty in sdm_sync block */
3828 #define XSDM_REG_SYNC_SYNC_EMPTY 0x166558
3829 /* [RW 32] Tick for timer counter. Applicable only when
3830 ~xsdm_registers_timer_tick_enable.timer_tick_enable =1 */
3831 #define XSDM_REG_TIMER_TICK 0x166000
3832 /* [RW 32] Interrupt mask register #0 read/write */
3833 #define XSDM_REG_XSDM_INT_MASK_0 0x16629c
3834 #define XSDM_REG_XSDM_INT_MASK_1 0x1662ac
3835 /* [RW 11] Parity mask register #0 read/write */
3836 #define XSDM_REG_XSDM_PRTY_MASK 0x1662bc
3837 /* [R 11] Parity register #0 read */
3838 #define XSDM_REG_XSDM_PRTY_STS 0x1662b0
3839 /* [RW 5] The number of time_slots in the arbitration cycle */
3840 #define XSEM_REG_ARB_CYCLE_SIZE 0x280034
3841 /* [RW 3] The source that is associated with arbitration element 0. Source
3842 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3843 sleeping thread with priority 1; 4- sleeping thread with priority 2 */
3844 #define XSEM_REG_ARB_ELEMENT0 0x280020
3845 /* [RW 3] The source that is associated with arbitration element 1. Source
3846 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3847 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3848 Could not be equal to register ~xsem_registers_arb_element0.arb_element0 */
3849 #define XSEM_REG_ARB_ELEMENT1 0x280024
3850 /* [RW 3] The source that is associated with arbitration element 2. Source
3851 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3852 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3853 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
3854 and ~xsem_registers_arb_element1.arb_element1 */
3855 #define XSEM_REG_ARB_ELEMENT2 0x280028
3856 /* [RW 3] The source that is associated with arbitration element 3. Source
3857 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3858 sleeping thread with priority 1; 4- sleeping thread with priority 2.Could
3859 not be equal to register ~xsem_registers_arb_element0.arb_element0 and
3860 ~xsem_registers_arb_element1.arb_element1 and
3861 ~xsem_registers_arb_element2.arb_element2 */
3862 #define XSEM_REG_ARB_ELEMENT3 0x28002c
3863 /* [RW 3] The source that is associated with arbitration element 4. Source
3864 decoding is: 0- foc0; 1-fic1; 2-sleeping thread with priority 0; 3-
3865 sleeping thread with priority 1; 4- sleeping thread with priority 2.
3866 Could not be equal to register ~xsem_registers_arb_element0.arb_element0
3867 and ~xsem_registers_arb_element1.arb_element1 and
3868 ~xsem_registers_arb_element2.arb_element2 and
3869 ~xsem_registers_arb_element3.arb_element3 */
3870 #define XSEM_REG_ARB_ELEMENT4 0x280030
3871 #define XSEM_REG_ENABLE_IN 0x2800a4
3872 #define XSEM_REG_ENABLE_OUT 0x2800a8
3873 /* [RW 32] This address space contains all registers and memories that are
3874 placed in SEM_FAST block. The SEM_FAST registers are described in
3875 appendix B. In order to access the SEM_FAST registers the base address
3876 XSEM_REGISTERS_FAST_MEMORY (Offset: 0x2a0000) should be added to each
3877 SEM_FAST register offset. */
3878 #define XSEM_REG_FAST_MEMORY 0x2a0000
3879 /* [RW 1] Disables input messages from FIC0 May be updated during run_time
3880 by the microcode */
3881 #define XSEM_REG_FIC0_DISABLE 0x280224
3882 /* [RW 1] Disables input messages from FIC1 May be updated during run_time
3883 by the microcode */
3884 #define XSEM_REG_FIC1_DISABLE 0x280234
3885 /* [RW 15] Interrupt table Read and write access to it is not possible in
3886 the middle of the work */
3887 #define XSEM_REG_INT_TABLE 0x280400
3888 /* [ST 24] Statistics register. The number of messages that entered through
3889 FIC0 */
3890 #define XSEM_REG_MSG_NUM_FIC0 0x280000
3891 /* [ST 24] Statistics register. The number of messages that entered through
3892 FIC1 */
3893 #define XSEM_REG_MSG_NUM_FIC1 0x280004
3894 /* [ST 24] Statistics register. The number of messages that were sent to
3895 FOC0 */
3896 #define XSEM_REG_MSG_NUM_FOC0 0x280008
3897 /* [ST 24] Statistics register. The number of messages that were sent to
3898 FOC1 */
3899 #define XSEM_REG_MSG_NUM_FOC1 0x28000c
3900 /* [ST 24] Statistics register. The number of messages that were sent to
3901 FOC2 */
3902 #define XSEM_REG_MSG_NUM_FOC2 0x280010
3903 /* [ST 24] Statistics register. The number of messages that were sent to
3904 FOC3 */
3905 #define XSEM_REG_MSG_NUM_FOC3 0x280014
3906 /* [RW 1] Disables input messages from the passive buffer May be updated
3907 during run_time by the microcode */
3908 #define XSEM_REG_PAS_DISABLE 0x28024c
3909 /* [WB 128] Debug only. Passive buffer memory */
3910 #define XSEM_REG_PASSIVE_BUFFER 0x282000
3911 /* [WB 46] pram memory. B45 is parity; b[44:0] - data. */
3912 #define XSEM_REG_PRAM 0x2c0000
3913 /* [R 16] Valid sleeping threads indication have bit per thread */
3914 #define XSEM_REG_SLEEP_THREADS_VALID 0x28026c
3915 /* [R 1] EXT_STORE FIFO is empty in sem_slow_ls_ext */
3916 #define XSEM_REG_SLOW_EXT_STORE_EMPTY 0x2802a0
3917 /* [RW 16] List of free threads . There is a bit per thread. */
3918 #define XSEM_REG_THREADS_LIST 0x2802e4
3919 /* [RW 3] The arbitration scheme of time_slot 0 */
3920 #define XSEM_REG_TS_0_AS 0x280038
3921 /* [RW 3] The arbitration scheme of time_slot 10 */
3922 #define XSEM_REG_TS_10_AS 0x280060
3923 /* [RW 3] The arbitration scheme of time_slot 11 */
3924 #define XSEM_REG_TS_11_AS 0x280064
3925 /* [RW 3] The arbitration scheme of time_slot 12 */
3926 #define XSEM_REG_TS_12_AS 0x280068
3927 /* [RW 3] The arbitration scheme of time_slot 13 */
3928 #define XSEM_REG_TS_13_AS 0x28006c
3929 /* [RW 3] The arbitration scheme of time_slot 14 */
3930 #define XSEM_REG_TS_14_AS 0x280070
3931 /* [RW 3] The arbitration scheme of time_slot 15 */
3932 #define XSEM_REG_TS_15_AS 0x280074
3933 /* [RW 3] The arbitration scheme of time_slot 16 */
3934 #define XSEM_REG_TS_16_AS 0x280078
3935 /* [RW 3] The arbitration scheme of time_slot 17 */
3936 #define XSEM_REG_TS_17_AS 0x28007c
3937 /* [RW 3] The arbitration scheme of time_slot 18 */
3938 #define XSEM_REG_TS_18_AS 0x280080
3939 /* [RW 3] The arbitration scheme of time_slot 1 */
3940 #define XSEM_REG_TS_1_AS 0x28003c
3941 /* [RW 3] The arbitration scheme of time_slot 2 */
3942 #define XSEM_REG_TS_2_AS 0x280040
3943 /* [RW 3] The arbitration scheme of time_slot 3 */
3944 #define XSEM_REG_TS_3_AS 0x280044
3945 /* [RW 3] The arbitration scheme of time_slot 4 */
3946 #define XSEM_REG_TS_4_AS 0x280048
3947 /* [RW 3] The arbitration scheme of time_slot 5 */
3948 #define XSEM_REG_TS_5_AS 0x28004c
3949 /* [RW 3] The arbitration scheme of time_slot 6 */
3950 #define XSEM_REG_TS_6_AS 0x280050
3951 /* [RW 3] The arbitration scheme of time_slot 7 */
3952 #define XSEM_REG_TS_7_AS 0x280054
3953 /* [RW 3] The arbitration scheme of time_slot 8 */
3954 #define XSEM_REG_TS_8_AS 0x280058
3955 /* [RW 3] The arbitration scheme of time_slot 9 */
3956 #define XSEM_REG_TS_9_AS 0x28005c
3957 /* [RW 32] Interrupt mask register #0 read/write */
3958 #define XSEM_REG_XSEM_INT_MASK_0 0x280110
3959 #define XSEM_REG_XSEM_INT_MASK_1 0x280120
3960 /* [RW 32] Parity mask register #0 read/write */
3961 #define XSEM_REG_XSEM_PRTY_MASK_0 0x280130
3962 #define XSEM_REG_XSEM_PRTY_MASK_1 0x280140
3963 /* [R 32] Parity register #0 read */
3964 #define XSEM_REG_XSEM_PRTY_STS_0 0x280124
3965 #define XSEM_REG_XSEM_PRTY_STS_1 0x280134
3966 #define MCPR_NVM_ACCESS_ENABLE_EN (1L<<0)
3967 #define MCPR_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
3968 #define MCPR_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
3969 #define MCPR_NVM_CFG4_FLASH_SIZE (0x7L<<0)
3970 #define MCPR_NVM_COMMAND_DOIT (1L<<4)
3971 #define MCPR_NVM_COMMAND_DONE (1L<<3)
3972 #define MCPR_NVM_COMMAND_FIRST (1L<<7)
3973 #define MCPR_NVM_COMMAND_LAST (1L<<8)
3974 #define MCPR_NVM_COMMAND_WR (1L<<5)
3975 #define MCPR_NVM_COMMAND_WREN (1L<<16)
3976 #define MCPR_NVM_COMMAND_WREN_BITSHIFT 16
3977 #define MCPR_NVM_COMMAND_WRDI (1L<<17)
3978 #define MCPR_NVM_COMMAND_WRDI_BITSHIFT 17
3979 #define MCPR_NVM_SW_ARB_ARB_ARB1 (1L<<9)
3980 #define MCPR_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
3981 #define MCPR_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
3982 #define BIGMAC_REGISTER_BMAC_CONTROL (0x00<<3)
3983 #define BIGMAC_REGISTER_BMAC_XGXS_CONTROL (0x01<<3)
3984 #define BIGMAC_REGISTER_CNT_MAX_SIZE (0x05<<3)
3985 #define BIGMAC_REGISTER_RX_CONTROL (0x21<<3)
3986 #define BIGMAC_REGISTER_RX_LLFC_MSG_FLDS (0x46<<3)
3987 #define BIGMAC_REGISTER_RX_MAX_SIZE (0x23<<3)
3988 #define BIGMAC_REGISTER_RX_STAT_GR64 (0x26<<3)
3989 #define BIGMAC_REGISTER_RX_STAT_GRIPJ (0x42<<3)
3990 #define BIGMAC_REGISTER_TX_CONTROL (0x07<<3)
3991 #define BIGMAC_REGISTER_TX_MAX_SIZE (0x09<<3)
3992 #define BIGMAC_REGISTER_TX_PAUSE_THRESHOLD (0x0A<<3)
3993 #define BIGMAC_REGISTER_TX_SOURCE_ADDR (0x08<<3)
3994 #define BIGMAC_REGISTER_TX_STAT_GTBYT (0x20<<3)
3995 #define BIGMAC_REGISTER_TX_STAT_GTPKT (0x0C<<3)
3996 #define EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
3997 #define EMAC_MDIO_COMM_COMMAND_READ_22 (2L<<26)
3998 #define EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
3999 #define EMAC_MDIO_COMM_COMMAND_WRITE_22 (1L<<26)
4000 #define EMAC_MDIO_COMM_COMMAND_WRITE_45 (1L<<26)
4001 #define EMAC_MDIO_COMM_DATA (0xffffL<<0)
4002 #define EMAC_MDIO_COMM_START_BUSY (1L<<29)
4003 #define EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
4004 #define EMAC_MDIO_MODE_CLAUSE_45 (1L<<31)
4005 #define EMAC_MDIO_MODE_CLOCK_CNT (0x3fL<<16)
4006 #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT 16
4007 #define EMAC_MODE_25G_MODE (1L<<5)
4008 #define EMAC_MODE_ACPI_RCVD (1L<<20)
4009 #define EMAC_MODE_HALF_DUPLEX (1L<<1)
4010 #define EMAC_MODE_MPKT (1L<<18)
4011 #define EMAC_MODE_MPKT_RCVD (1L<<19)
4012 #define EMAC_MODE_PORT_GMII (2L<<2)
4013 #define EMAC_MODE_PORT_MII (1L<<2)
4014 #define EMAC_MODE_PORT_MII_10M (3L<<2)
4015 #define EMAC_MODE_RESET (1L<<0)
4016 #define EMAC_REG_EMAC_MAC_MATCH 0x10
4017 #define EMAC_REG_EMAC_MDIO_COMM 0xac
4018 #define EMAC_REG_EMAC_MDIO_MODE 0xb4
4019 #define EMAC_REG_EMAC_MODE 0x0
4020 #define EMAC_REG_EMAC_RX_MODE 0xc8
4021 #define EMAC_REG_EMAC_RX_MTU_SIZE 0x9c
4022 #define EMAC_REG_EMAC_RX_STAT_AC 0x180
4023 #define EMAC_REG_EMAC_RX_STAT_AC_28 0x1f4
4024 #define EMAC_REG_EMAC_RX_STAT_AC_COUNT 23
4025 #define EMAC_REG_EMAC_TX_MODE 0xbc
4026 #define EMAC_REG_EMAC_TX_STAT_AC 0x280
4027 #define EMAC_REG_EMAC_TX_STAT_AC_COUNT 22
4028 #define EMAC_RX_MODE_FLOW_EN (1L<<2)
4029 #define EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
4030 #define EMAC_RX_MODE_PROMISCUOUS (1L<<8)
4031 #define EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
4032 #define EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
4033 #define EMAC_TX_MODE_RESET (1L<<0)
4034 #define MISC_REGISTERS_GPIO_1 1
4035 #define MISC_REGISTERS_GPIO_2 2
4036 #define MISC_REGISTERS_GPIO_3 3
4037 #define MISC_REGISTERS_GPIO_CLR_POS 16
4038 #define MISC_REGISTERS_GPIO_FLOAT (0xffL<<24)
4039 #define MISC_REGISTERS_GPIO_FLOAT_POS 24
4040 #define MISC_REGISTERS_GPIO_INPUT_HI_Z 2
4041 #define MISC_REGISTERS_GPIO_OUTPUT_HIGH 1
4042 #define MISC_REGISTERS_GPIO_OUTPUT_LOW 0
4043 #define MISC_REGISTERS_GPIO_PORT_SHIFT 4
4044 #define MISC_REGISTERS_GPIO_SET_POS 8
4045 #define MISC_REGISTERS_RESET_REG_1_CLEAR 0x588
4046 #define MISC_REGISTERS_RESET_REG_1_SET 0x584
4047 #define MISC_REGISTERS_RESET_REG_2_CLEAR 0x598
4048 #define MISC_REGISTERS_RESET_REG_2_RST_BMAC0 (0x1<<0)
4049 #define MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE (0x1<<14)
4050 #define MISC_REGISTERS_RESET_REG_2_SET 0x594
4051 #define MISC_REGISTERS_RESET_REG_3_CLEAR 0x5a8
4052 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ (0x1<<1)
4053 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN (0x1<<2)
4054 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD (0x1<<3)
4055 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW (0x1<<0)
4056 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ (0x1<<5)
4057 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN (0x1<<6)
4058 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD (0x1<<7)
4059 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW (0x1<<4)
4060 #define MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB (0x1<<8)
4061 #define MISC_REGISTERS_RESET_REG_3_SET 0x5a4
4062 #define MISC_REGISTERS_SPIO_4 4
4063 #define MISC_REGISTERS_SPIO_5 5
4064 #define MISC_REGISTERS_SPIO_7 7
4065 #define MISC_REGISTERS_SPIO_CLR_POS 16
4066 #define MISC_REGISTERS_SPIO_FLOAT (0xffL<<24)
4067 #define GRC_MISC_REGISTERS_SPIO_FLOAT7 0x80000000
4068 #define GRC_MISC_REGISTERS_SPIO_FLOAT6 0x40000000
4069 #define GRC_MISC_REGISTERS_SPIO_FLOAT5 0x20000000
4070 #define GRC_MISC_REGISTERS_SPIO_FLOAT4 0x10000000
4071 #define MISC_REGISTERS_SPIO_FLOAT_POS 24
4072 #define MISC_REGISTERS_SPIO_INPUT_HI_Z 2
4073 #define MISC_REGISTERS_SPIO_INT_OLD_SET_POS 16
4074 #define MISC_REGISTERS_SPIO_OUTPUT_HIGH 1
4075 #define MISC_REGISTERS_SPIO_OUTPUT_LOW 0
4076 #define MISC_REGISTERS_SPIO_SET_POS 8
4077 #define HW_LOCK_MAX_RESOURCE_VALUE 31
4078 #define HW_LOCK_RESOURCE_8072_MDIO 0
4079 #define HW_LOCK_RESOURCE_GPIO 1
4080 #define HW_LOCK_RESOURCE_SPIO 2
4081 #define AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR (1<<18)
4082 #define AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT (1<<31)
4083 #define AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT (1<<9)
4084 #define AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR (1<<8)
4085 #define AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT (1<<7)
4086 #define AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR (1<<6)
4087 #define AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT (1<<29)
4088 #define AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR (1<<28)
4089 #define AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT (1<<1)
4090 #define AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR (1<<0)
4091 #define AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR (1<<18)
4092 #define AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT (1<<11)
4093 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT (1<<13)
4094 #define AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR (1<<12)
4095 #define AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR (1<<12)
4096 #define AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT (1<<15)
4097 #define AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR (1<<14)
4098 #define AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR (1<<20)
4099 #define AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR (1<<0)
4100 #define AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT (1<<31)
4101 #define AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT (1<<3)
4102 #define AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR (1<<2)
4103 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT (1<<5)
4104 #define AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR (1<<4)
4105 #define AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT (1<<3)
4106 #define AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR (1<<2)
4107 #define AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR (1<<22)
4108 #define AEU_INPUTS_ATTN_BITS_SPIO5 (1<<15)
4109 #define AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT (1<<27)
4110 #define AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT (1<<5)
4111 #define AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT (1<<25)
4112 #define AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR (1<<24)
4113 #define AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT (1<<29)
4114 #define AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR (1<<28)
4115 #define AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT (1<<23)
4116 #define AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT (1<<27)
4117 #define AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR (1<<26)
4118 #define AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT (1<<21)
4119 #define AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR (1<<20)
4120 #define AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT (1<<25)
4121 #define AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR (1<<24)
4122 #define AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR (1<<16)
4123 #define AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT (1<<9)
4124 #define AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT (1<<7)
4125 #define AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR (1<<6)
4126 #define AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT (1<<11)
4127 #define AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR (1<<10)
4128 #define RESERVED_GENERAL_ATTENTION_BIT_0 0
4130 #define EVEREST_GEN_ATTN_IN_USE_MASK 0x3e0
4131 #define EVEREST_LATCHED_ATTN_IN_USE_MASK 0xffe00000
4133 #define RESERVED_GENERAL_ATTENTION_BIT_6 6
4134 #define RESERVED_GENERAL_ATTENTION_BIT_7 7
4135 #define RESERVED_GENERAL_ATTENTION_BIT_8 8
4136 #define RESERVED_GENERAL_ATTENTION_BIT_9 9
4137 #define RESERVED_GENERAL_ATTENTION_BIT_10 10
4138 #define RESERVED_GENERAL_ATTENTION_BIT_11 11
4139 #define RESERVED_GENERAL_ATTENTION_BIT_12 12
4140 #define RESERVED_GENERAL_ATTENTION_BIT_13 13
4141 #define RESERVED_GENERAL_ATTENTION_BIT_14 14
4142 #define RESERVED_GENERAL_ATTENTION_BIT_15 15
4143 #define RESERVED_GENERAL_ATTENTION_BIT_16 16
4144 #define RESERVED_GENERAL_ATTENTION_BIT_17 17
4145 #define RESERVED_GENERAL_ATTENTION_BIT_18 18
4146 #define RESERVED_GENERAL_ATTENTION_BIT_19 19
4147 #define RESERVED_GENERAL_ATTENTION_BIT_20 20
4148 #define RESERVED_GENERAL_ATTENTION_BIT_21 21
4150 /* storm asserts attention bits */
4151 #define TSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_7
4152 #define USTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_8
4153 #define CSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_9
4154 #define XSTORM_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_10
4156 /* mcp error attention bit */
4157 #define MCP_FATAL_ASSERT_ATTENTION_BIT RESERVED_GENERAL_ATTENTION_BIT_11
4159 #define LATCHED_ATTN_RBCR 23
4160 #define LATCHED_ATTN_RBCT 24
4161 #define LATCHED_ATTN_RBCN 25
4162 #define LATCHED_ATTN_RBCU 26
4163 #define LATCHED_ATTN_RBCP 27
4164 #define LATCHED_ATTN_TIMEOUT_GRC 28
4165 #define LATCHED_ATTN_RSVD_GRC 29
4166 #define LATCHED_ATTN_ROM_PARITY_MCP 30
4167 #define LATCHED_ATTN_UM_RX_PARITY_MCP 31
4168 #define LATCHED_ATTN_UM_TX_PARITY_MCP 32
4169 #define LATCHED_ATTN_SCPAD_PARITY_MCP 33
4171 #define GENERAL_ATTEN_WORD(atten_name) ((94 + atten_name) / 32)
4172 #define GENERAL_ATTEN_OFFSET(atten_name) (1 << ((94 + atten_name) % 32))
4173 /*
4174 * This file defines GRC base address for every block.
4175 * This file is included by chipsim, asm microcode and cpp microcode.
4176 * These values are used in Design.xml on regBase attribute
4177 * Use the base with the generated offsets of specific registers.
4178 */
4180 #define GRCBASE_PXPCS 0x000000
4181 #define GRCBASE_PCICONFIG 0x002000
4182 #define GRCBASE_PCIREG 0x002400
4183 #define GRCBASE_EMAC0 0x008000
4184 #define GRCBASE_EMAC1 0x008400
4185 #define GRCBASE_DBU 0x008800
4186 #define GRCBASE_MISC 0x00A000
4187 #define GRCBASE_DBG 0x00C000
4188 #define GRCBASE_NIG 0x010000
4189 #define GRCBASE_XCM 0x020000
4190 #define GRCBASE_PRS 0x040000
4191 #define GRCBASE_SRCH 0x040400
4192 #define GRCBASE_TSDM 0x042000
4193 #define GRCBASE_TCM 0x050000
4194 #define GRCBASE_BRB1 0x060000
4195 #define GRCBASE_MCP 0x080000
4196 #define GRCBASE_UPB 0x0C1000
4197 #define GRCBASE_CSDM 0x0C2000
4198 #define GRCBASE_USDM 0x0C4000
4199 #define GRCBASE_CCM 0x0D0000
4200 #define GRCBASE_UCM 0x0E0000
4201 #define GRCBASE_CDU 0x101000
4202 #define GRCBASE_DMAE 0x102000
4203 #define GRCBASE_PXP 0x103000
4204 #define GRCBASE_CFC 0x104000
4205 #define GRCBASE_HC 0x108000
4206 #define GRCBASE_PXP2 0x120000
4207 #define GRCBASE_PBF 0x140000
4208 #define GRCBASE_XPB 0x161000
4209 #define GRCBASE_TIMERS 0x164000
4210 #define GRCBASE_XSDM 0x166000
4211 #define GRCBASE_QM 0x168000
4212 #define GRCBASE_DQ 0x170000
4213 #define GRCBASE_TSEM 0x180000
4214 #define GRCBASE_CSEM 0x200000
4215 #define GRCBASE_XSEM 0x280000
4216 #define GRCBASE_USEM 0x300000
4217 #define GRCBASE_MISC_AEU GRCBASE_MISC
4220 /*the offset of the configuration space in the pci core register*/
4221 #define PCICFG_OFFSET 0x2000
4222 #define PCICFG_VENDOR_ID_OFFSET 0x00
4223 #define PCICFG_DEVICE_ID_OFFSET 0x02
4224 #define PCICFG_SUBSYSTEM_VENDOR_ID_OFFSET 0x2c
4225 #define PCICFG_SUBSYSTEM_ID_OFFSET 0x2e
4226 #define PCICFG_INT_LINE 0x3c
4227 #define PCICFG_INT_PIN 0x3d
4228 #define PCICFG_CACHE_LINE_SIZE 0x0c
4229 #define PCICFG_LATENCY_TIMER 0x0d
4230 #define PCICFG_REVESION_ID 0x08
4231 #define PCICFG_BAR_1_LOW 0x10
4232 #define PCICFG_BAR_1_HIGH 0x14
4233 #define PCICFG_BAR_2_LOW 0x18
4234 #define PCICFG_BAR_2_HIGH 0x1c
4235 #define PCICFG_GRC_ADDRESS 0x78
4236 #define PCICFG_GRC_DATA 0x80
4237 #define PCICFG_DEVICE_CONTROL 0xb4
4238 #define PCICFG_LINK_CONTROL 0xbc
4240 #define BAR_USTRORM_INTMEM 0x400000
4241 #define BAR_CSTRORM_INTMEM 0x410000
4242 #define BAR_XSTRORM_INTMEM 0x420000
4243 #define BAR_TSTRORM_INTMEM 0x430000
4245 #define BAR_IGU_INTMEM 0x440000
4247 #define BAR_DOORBELL_OFFSET 0x800000
4249 #define BAR_ME_REGISTER 0x450000
4253 #define PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
4254 #define PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
4255 #define PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
4256 #define PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
4257 #define PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
4258 #define PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
4259 #define PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
4260 #define PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
4261 #define PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
4262 #define PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
4263 #define PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
4264 #define PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
4265 #define PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
4266 #define PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
4267 #define PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
4268 #define PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
4269 #define PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
4270 #define PCI_CONFIG_2_BAR1_64ENA (1L<<4)
4271 #define PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
4272 #define PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
4273 #define PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
4274 #define PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
4275 #define PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
4276 #define PCI_CONFIG_2_EXP_ROM_SIZE_2K (1L<<8)
4277 #define PCI_CONFIG_2_EXP_ROM_SIZE_4K (2L<<8)
4278 #define PCI_CONFIG_2_EXP_ROM_SIZE_8K (3L<<8)
4279 #define PCI_CONFIG_2_EXP_ROM_SIZE_16K (4L<<8)
4280 #define PCI_CONFIG_2_EXP_ROM_SIZE_32K (5L<<8)
4281 #define PCI_CONFIG_2_EXP_ROM_SIZE_64K (6L<<8)
4282 #define PCI_CONFIG_2_EXP_ROM_SIZE_128K (7L<<8)
4283 #define PCI_CONFIG_2_EXP_ROM_SIZE_256K (8L<<8)
4284 #define PCI_CONFIG_2_EXP_ROM_SIZE_512K (9L<<8)
4285 #define PCI_CONFIG_2_EXP_ROM_SIZE_1M (10L<<8)
4286 #define PCI_CONFIG_2_EXP_ROM_SIZE_2M (11L<<8)
4287 #define PCI_CONFIG_2_EXP_ROM_SIZE_4M (12L<<8)
4288 #define PCI_CONFIG_2_EXP_ROM_SIZE_8M (13L<<8)
4289 #define PCI_CONFIG_2_EXP_ROM_SIZE_16M (14L<<8)
4290 #define PCI_CONFIG_2_EXP_ROM_SIZE_32M (15L<<8)
4291 #define PCI_CONFIG_2_BAR_PREFETCH (1L<<16)
4292 #define PCI_CONFIG_2_RESERVED0 (0x7fffL<<17)
4294 /* config_3 offset */
4295 #define GRC_CONFIG_3_SIZE_REG (0x40c)
4296 #define PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
4297 #define PCI_CONFIG_3_FORCE_PME (1L<<24)
4298 #define PCI_CONFIG_3_PME_STATUS (1L<<25)
4299 #define PCI_CONFIG_3_PME_ENABLE (1L<<26)
4300 #define PCI_CONFIG_3_PM_STATE (0x3L<<27)
4301 #define PCI_CONFIG_3_VAUX_PRESET (1L<<30)
4302 #define PCI_CONFIG_3_PCI_POWER (1L<<31)
4304 /* config_2 offset */
4305 #define GRC_CONFIG_2_SIZE_REG 0x408
4307 #define GRC_BAR2_CONFIG 0x4e0
4308 #define PCI_CONFIG_2_BAR2_SIZE (0xfL<<0)
4309 #define PCI_CONFIG_2_BAR2_SIZE_DISABLED (0L<<0)
4310 #define PCI_CONFIG_2_BAR2_SIZE_64K (1L<<0)
4311 #define PCI_CONFIG_2_BAR2_SIZE_128K (2L<<0)
4312 #define PCI_CONFIG_2_BAR2_SIZE_256K (3L<<0)
4313 #define PCI_CONFIG_2_BAR2_SIZE_512K (4L<<0)
4314 #define PCI_CONFIG_2_BAR2_SIZE_1M (5L<<0)
4315 #define PCI_CONFIG_2_BAR2_SIZE_2M (6L<<0)
4316 #define PCI_CONFIG_2_BAR2_SIZE_4M (7L<<0)
4317 #define PCI_CONFIG_2_BAR2_SIZE_8M (8L<<0)
4318 #define PCI_CONFIG_2_BAR2_SIZE_16M (9L<<0)
4319 #define PCI_CONFIG_2_BAR2_SIZE_32M (10L<<0)
4320 #define PCI_CONFIG_2_BAR2_SIZE_64M (11L<<0)
4321 #define PCI_CONFIG_2_BAR2_SIZE_128M (12L<<0)
4322 #define PCI_CONFIG_2_BAR2_SIZE_256M (13L<<0)
4323 #define PCI_CONFIG_2_BAR2_SIZE_512M (14L<<0)
4324 #define PCI_CONFIG_2_BAR2_SIZE_1G (15L<<0)
4325 #define PCI_CONFIG_2_BAR2_64ENA (1L<<4)
4327 #define PCI_PM_DATA_A (0x410)
4328 #define PCI_PM_DATA_B (0x414)
4329 #define PCI_ID_VAL1 (0x434)
4330 #define PCI_ID_VAL2 (0x438)
4332 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
4333 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
4334 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
4335 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
4336 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
4338 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
4339 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
4340 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
4341 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
4342 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
4343 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
4345 #define MDIO_REG_BANK_RX0 0x80b0
4346 #define MDIO_RX0_RX_EQ_BOOST 0x1c
4347 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4348 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
4350 #define MDIO_REG_BANK_RX1 0x80c0
4351 #define MDIO_RX1_RX_EQ_BOOST 0x1c
4352 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4353 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
4355 #define MDIO_REG_BANK_RX2 0x80d0
4356 #define MDIO_RX2_RX_EQ_BOOST 0x1c
4357 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4358 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
4360 #define MDIO_REG_BANK_RX3 0x80e0
4361 #define MDIO_RX3_RX_EQ_BOOST 0x1c
4362 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4363 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
4365 #define MDIO_REG_BANK_RX_ALL 0x80f0
4366 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
4367 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
4368 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
4370 #define MDIO_REG_BANK_TX0 0x8060
4371 #define MDIO_TX0_TX_DRIVER 0x17
4372 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
4373 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
4374 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
4375 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
4376 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
4377 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
4378 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
4379 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
4380 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
4382 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
4383 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
4385 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
4386 #define MDIO_BLOCK1_LANE_CTRL0 0x15
4387 #define MDIO_BLOCK1_LANE_CTRL1 0x16
4388 #define MDIO_BLOCK1_LANE_CTRL2 0x17
4389 #define MDIO_BLOCK1_LANE_PRBS 0x19
4391 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
4392 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
4393 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
4394 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
4395 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
4396 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
4397 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
4398 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
4399 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
4400 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
4402 #define MDIO_REG_BANK_GP_STATUS 0x8120
4403 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
4404 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
4405 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
4406 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
4407 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
4408 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
4409 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
4411 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
4412 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
4413 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
4414 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
4415 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
4416 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
4417 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
4418 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
4419 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
4420 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
4421 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
4422 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
4423 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
4424 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
4425 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
4426 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
4427 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
4428 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
4431 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
4432 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
4433 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
4434 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
4435 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
4437 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
4438 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
4439 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
4440 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
4441 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
4442 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
4443 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
4444 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
4445 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
4446 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
4447 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
4448 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
4449 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
4450 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
4451 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
4452 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
4453 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
4454 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
4455 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
4456 #define MDIO_SERDES_DIGITAL_MISC1 0x18
4457 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
4458 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
4459 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
4460 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
4461 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
4462 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
4463 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
4464 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
4465 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
4466 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
4467 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
4468 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
4469 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
4470 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
4471 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
4472 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
4473 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
4474 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
4476 #define MDIO_REG_BANK_OVER_1G 0x8320
4477 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
4478 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
4479 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
4480 #define MDIO_OVER_1G_UP1 0x19
4481 #define MDIO_OVER_1G_UP1_2_5G 0x0001
4482 #define MDIO_OVER_1G_UP1_5G 0x0002
4483 #define MDIO_OVER_1G_UP1_6G 0x0004
4484 #define MDIO_OVER_1G_UP1_10G 0x0010
4485 #define MDIO_OVER_1G_UP1_10GH 0x0008
4486 #define MDIO_OVER_1G_UP1_12G 0x0020
4487 #define MDIO_OVER_1G_UP1_12_5G 0x0040
4488 #define MDIO_OVER_1G_UP1_13G 0x0080
4489 #define MDIO_OVER_1G_UP1_15G 0x0100
4490 #define MDIO_OVER_1G_UP1_16G 0x0200
4491 #define MDIO_OVER_1G_UP2 0x1A
4492 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
4493 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
4494 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
4495 #define MDIO_OVER_1G_UP3 0x1B
4496 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
4497 #define MDIO_OVER_1G_LP_UP1 0x1C
4498 #define MDIO_OVER_1G_LP_UP2 0x1D
4499 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
4500 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
4501 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
4502 #define MDIO_OVER_1G_LP_UP3 0x1E
4504 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
4505 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
4506 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
4507 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
4509 #define MDIO_REG_BANK_CL73_USERB0 0x8370
4510 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
4511 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
4512 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
4513 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
4514 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
4515 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
4517 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
4518 #define MDIO_AER_BLOCK_AER_REG 0x1E
4520 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
4521 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
4522 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
4523 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
4524 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
4525 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
4526 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
4527 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
4528 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
4529 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
4530 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
4531 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
4532 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
4533 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
4534 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
4535 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
4536 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
4537 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
4538 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
4539 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
4540 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
4541 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
4542 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
4543 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
4544 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
4545 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
4546 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
4547 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE\
4548 0x0000
4549 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH\
4550 0x0180
4551 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
4552 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
4553 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
4556 #define EXT_PHY_AUTO_NEG_DEVAD 0x7
4557 #define EXT_PHY_OPT_PMA_PMD_DEVAD 0x1
4558 #define EXT_PHY_OPT_WIS_DEVAD 0x2
4559 #define EXT_PHY_OPT_PCS_DEVAD 0x3
4560 #define EXT_PHY_OPT_PHY_XS_DEVAD 0x4
4561 #define EXT_PHY_OPT_CNTL 0x0
4562 #define EXT_PHY_OPT_CNTL2 0x7
4563 #define EXT_PHY_OPT_PMD_RX_SD 0xa
4564 #define EXT_PHY_OPT_PMD_MISC_CNTL 0xca0a
4565 #define EXT_PHY_OPT_PHY_IDENTIFIER 0xc800
4566 #define EXT_PHY_OPT_PMD_DIGITAL_CNT 0xc808
4567 #define EXT_PHY_OPT_PMD_DIGITAL_SATUS 0xc809
4568 #define EXT_PHY_OPT_CMU_PLL_BYPASS 0xca09
4569 #define EXT_PHY_OPT_LASI_CNTL 0x9002
4570 #define EXT_PHY_OPT_RX_ALARM 0x9003
4571 #define EXT_PHY_OPT_LASI_STATUS 0x9005
4572 #define EXT_PHY_OPT_PCS_STATUS 0x0020
4573 #define EXT_PHY_OPT_XGXS_LANE_STATUS 0x0018
4574 #define EXT_PHY_OPT_AN_LINK_STATUS 0x8304
4575 #define EXT_PHY_OPT_AN_CL37_CL73 0x8370
4576 #define EXT_PHY_OPT_AN_CL37_FD 0xffe4
4577 #define EXT_PHY_OPT_AN_CL37_AN 0xffe0
4578 #define EXT_PHY_OPT_AN_ADV 0x11
4580 #define EXT_PHY_KR_PMA_PMD_DEVAD 0x1
4581 #define EXT_PHY_KR_PCS_DEVAD 0x3
4582 #define EXT_PHY_KR_AUTO_NEG_DEVAD 0x7
4583 #define EXT_PHY_KR_CTRL 0x0000
4584 #define EXT_PHY_KR_STATUS 0x0001
4585 #define EXT_PHY_KR_AUTO_NEG_COMPLETE 0x0020
4586 #define EXT_PHY_KR_AUTO_NEG_ADVERT 0x0010
4587 #define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE 0x0400
4588 #define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_ASYMMETRIC 0x0800
4589 #define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_BOTH 0x0C00
4590 #define EXT_PHY_KR_AUTO_NEG_ADVERT_PAUSE_MASK 0x0C00
4591 #define EXT_PHY_KR_LP_AUTO_NEG 0x0013
4592 #define EXT_PHY_KR_CTRL2 0x0007
4593 #define EXT_PHY_KR_PCS_STATUS 0x0020
4594 #define EXT_PHY_KR_PMD_CTRL 0x0096
4595 #define EXT_PHY_KR_LASI_CNTL 0x9002
4596 #define EXT_PHY_KR_LASI_STATUS 0x9005
4597 #define EXT_PHY_KR_MISC_CTRL1 0xca85
4598 #define EXT_PHY_KR_GEN_CTRL 0xca10
4599 #define EXT_PHY_KR_ROM_CODE 0xca19
4600 #define EXT_PHY_KR_ROM_RESET_INTERNAL_MP 0x0188
4601 #define EXT_PHY_KR_ROM_MICRO_RESET 0x018a
4603 #define EXT_PHY_SFX7101_XGXS_TEST1 0xc00a