Blackfin arch: build jtag tty driver as a module by default
[linux-2.6/mini2440.git] / include / asm-mn10300 / unit-asb2303 / serial.h
blob0d55cf5896ac3912bfeee4bb479b0951e9c4a804
1 /* ASB2303-specific 8250 serial ports
3 * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
4 * Written by David Howells (dhowells@redhat.com)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public Licence
8 * as published by the Free Software Foundation; either version
9 * 2 of the Licence, or (at your option) any later version.
12 #ifndef _ASM_UNIT_SERIAL_H
13 #define _ASM_UNIT_SERIAL_H
15 #include <asm/cpu-regs.h>
16 #include <asm/proc/irq.h>
17 #include <linux/serial_reg.h>
19 #define SERIAL_PORT0_BASE_ADDRESS 0xA6FB0000
20 #define SERIAL_PORT1_BASE_ADDRESS 0xA6FC0000
22 #define SERIAL_IRQ XIRQ0 /* Dual serial (PC16552) (Hi) */
25 * dispose of the /dev/ttyS0 and /dev/ttyS1 serial ports
27 #ifndef CONFIG_GDBSTUB_ON_TTYSx
29 #define SERIAL_PORT_DFNS \
30 { \
31 .baud_base = BASE_BAUD, \
32 .irq = SERIAL_IRQ, \
33 .flags = STD_COM_FLAGS, \
34 .iomem_base = (u8 *) SERIAL_PORT0_BASE_ADDRESS, \
35 .iomem_reg_shift = 2, \
36 .io_type = SERIAL_IO_MEM, \
37 }, \
38 { \
39 .baud_base = BASE_BAUD, \
40 .irq = SERIAL_IRQ, \
41 .flags = STD_COM_FLAGS, \
42 .iomem_base = (u8 *) SERIAL_PORT1_BASE_ADDRESS, \
43 .iomem_reg_shift = 2, \
44 .io_type = SERIAL_IO_MEM, \
47 #ifndef __ASSEMBLY__
49 static inline void __debug_to_serial(const char *p, int n)
53 #endif /* !__ASSEMBLY__ */
55 #else /* CONFIG_GDBSTUB_ON_TTYSx */
57 #define SERIAL_PORT_DFNS /* both stolen by gdb-stub because they share an IRQ */
59 #if defined(CONFIG_GDBSTUB_ON_TTYS0)
60 #define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_RX * 4, u8)
61 #define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_TX * 4, u8)
62 #define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLL * 4, u8)
63 #define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_DLM * 4, u8)
64 #define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IER * 4, u8)
65 #define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_IIR * 4, u8)
66 #define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_FCR * 4, u8)
67 #define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LCR * 4, u8)
68 #define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MCR * 4, u8)
69 #define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_LSR * 4, u8)
70 #define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_MSR * 4, u8)
71 #define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT0_BASE_ADDRESS + UART_SCR * 4, u8)
72 #define GDBPORT_SERIAL_IRQ SERIAL_IRQ
74 #elif defined(CONFIG_GDBSTUB_ON_TTYS1)
75 #define GDBPORT_SERIAL_RX __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_RX * 4, u8)
76 #define GDBPORT_SERIAL_TX __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_TX * 4, u8)
77 #define GDBPORT_SERIAL_DLL __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_DLL * 4, u8)
78 #define GDBPORT_SERIAL_DLM __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_DLM * 4, u8)
79 #define GDBPORT_SERIAL_IER __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_IER * 4, u8)
80 #define GDBPORT_SERIAL_IIR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_IIR * 4, u8)
81 #define GDBPORT_SERIAL_FCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_FCR * 4, u8)
82 #define GDBPORT_SERIAL_LCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_LCR * 4, u8)
83 #define GDBPORT_SERIAL_MCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_MCR * 4, u8)
84 #define GDBPORT_SERIAL_LSR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_LSR * 4, u8)
85 #define GDBPORT_SERIAL_MSR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_MSR * 4, u8)
86 #define GDBPORT_SERIAL_SCR __SYSREG(SERIAL_PORT1_BASE_ADDRESS + UART_SCR * 4, u8)
87 #define GDBPORT_SERIAL_IRQ SERIAL_IRQ
88 #endif
90 #ifndef __ASSEMBLY__
92 #define LSR_WAIT_FOR(STATE) \
93 do { \
94 while (!(GDBPORT_SERIAL_LSR & UART_LSR_##STATE)) {} \
95 } while (0)
96 #define FLOWCTL_WAIT_FOR(LINE) \
97 do { \
98 while (!(GDBPORT_SERIAL_MSR & UART_MSR_##LINE)) {} \
99 } while (0)
100 #define FLOWCTL_CLEAR(LINE) \
101 do { \
102 GDBPORT_SERIAL_MCR &= ~UART_MCR_##LINE; \
103 } while (0)
104 #define FLOWCTL_SET(LINE) \
105 do { \
106 GDBPORT_SERIAL_MCR |= UART_MCR_##LINE; \
107 } while (0)
108 #define FLOWCTL_QUERY(LINE) ({ GDBPORT_SERIAL_MSR & UART_MSR_##LINE; })
110 static inline void __debug_to_serial(const char *p, int n)
112 char ch;
114 FLOWCTL_SET(DTR);
116 for (; n > 0; n--) {
117 LSR_WAIT_FOR(THRE);
118 FLOWCTL_WAIT_FOR(CTS);
120 ch = *p++;
121 if (ch == 0x0a) {
122 GDBPORT_SERIAL_TX = 0x0d;
123 LSR_WAIT_FOR(THRE);
124 FLOWCTL_WAIT_FOR(CTS);
126 GDBPORT_SERIAL_TX = ch;
129 FLOWCTL_CLEAR(DTR);
132 #endif /* !__ASSEMBLY__ */
134 #endif /* CONFIG_GDBSTUB_ON_TTYSx */
136 #endif /* _ASM_UNIT_SERIAL_H */