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e1000: update the readme with the latest text
[linux-2.6/mini2440.git] / sound / pci / rme96.c
blob0e694b011dcc66b424097805cdea5fc37a241d08
1 /*
2 * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
3 * interfaces
4 *
5 * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
6 *
7 * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
8 * code.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 */
25
26 #include <sound/driver.h>
27 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/pci.h>
31 #include <linux/slab.h>
32 #include <linux/moduleparam.h>
33
34 #include <sound/core.h>
35 #include <sound/info.h>
36 #include <sound/control.h>
37 #include <sound/pcm.h>
38 #include <sound/pcm_params.h>
39 #include <sound/asoundef.h>
40 #include <sound/initval.h>
41
42 #include <asm/io.h>
43
44 /* note, two last pcis should be equal, it is not a bug */
45
46 MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
47 MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
48 "Digi96/8 PAD");
49 MODULE_LICENSE("GPL");
50 MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
51 "{RME,Digi96/8},"
52 "{RME,Digi96/8 PRO},"
53 "{RME,Digi96/8 PST},"
54 "{RME,Digi96/8 PAD}}");
55
56 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
57 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
58 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
59
60 module_param_array(index, int, NULL, 0444);
61 MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
62 module_param_array(id, charp, NULL, 0444);
63 MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
64 module_param_array(enable, bool, NULL, 0444);
65 MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
66
67 /*
68 * Defines for RME Digi96 series, from internal RME reference documents
69 * dated 12.01.00
70 */
71
72 #define RME96_SPDIF_NCHANNELS 2
73
74 /* Playback and capture buffer size */
75 #define RME96_BUFFER_SIZE 0x10000
76
77 /* IO area size */
78 #define RME96_IO_SIZE 0x60000
79
80 /* IO area offsets */
81 #define RME96_IO_PLAY_BUFFER 0x0
82 #define RME96_IO_REC_BUFFER 0x10000
83 #define RME96_IO_CONTROL_REGISTER 0x20000
84 #define RME96_IO_ADDITIONAL_REG 0x20004
85 #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
86 #define RME96_IO_CONFIRM_REC_IRQ 0x2000C
87 #define RME96_IO_SET_PLAY_POS 0x40000
88 #define RME96_IO_RESET_PLAY_POS 0x4FFFC
89 #define RME96_IO_SET_REC_POS 0x50000
90 #define RME96_IO_RESET_REC_POS 0x5FFFC
91 #define RME96_IO_GET_PLAY_POS 0x20000
92 #define RME96_IO_GET_REC_POS 0x30000
93
94 /* Write control register bits */
95 #define RME96_WCR_START (1 << 0)
96 #define RME96_WCR_START_2 (1 << 1)
97 #define RME96_WCR_GAIN_0 (1 << 2)
98 #define RME96_WCR_GAIN_1 (1 << 3)
99 #define RME96_WCR_MODE24 (1 << 4)
100 #define RME96_WCR_MODE24_2 (1 << 5)
101 #define RME96_WCR_BM (1 << 6)
102 #define RME96_WCR_BM_2 (1 << 7)
103 #define RME96_WCR_ADAT (1 << 8)
104 #define RME96_WCR_FREQ_0 (1 << 9)
105 #define RME96_WCR_FREQ_1 (1 << 10)
106 #define RME96_WCR_DS (1 << 11)
107 #define RME96_WCR_PRO (1 << 12)
108 #define RME96_WCR_EMP (1 << 13)
109 #define RME96_WCR_SEL (1 << 14)
110 #define RME96_WCR_MASTER (1 << 15)
111 #define RME96_WCR_PD (1 << 16)
112 #define RME96_WCR_INP_0 (1 << 17)
113 #define RME96_WCR_INP_1 (1 << 18)
114 #define RME96_WCR_THRU_0 (1 << 19)
115 #define RME96_WCR_THRU_1 (1 << 20)
116 #define RME96_WCR_THRU_2 (1 << 21)
117 #define RME96_WCR_THRU_3 (1 << 22)
118 #define RME96_WCR_THRU_4 (1 << 23)
119 #define RME96_WCR_THRU_5 (1 << 24)
120 #define RME96_WCR_THRU_6 (1 << 25)
121 #define RME96_WCR_THRU_7 (1 << 26)
122 #define RME96_WCR_DOLBY (1 << 27)
123 #define RME96_WCR_MONITOR_0 (1 << 28)
124 #define RME96_WCR_MONITOR_1 (1 << 29)
125 #define RME96_WCR_ISEL (1 << 30)
126 #define RME96_WCR_IDIS (1 << 31)
127
128 #define RME96_WCR_BITPOS_GAIN_0 2
129 #define RME96_WCR_BITPOS_GAIN_1 3
130 #define RME96_WCR_BITPOS_FREQ_0 9
131 #define RME96_WCR_BITPOS_FREQ_1 10
132 #define RME96_WCR_BITPOS_INP_0 17
133 #define RME96_WCR_BITPOS_INP_1 18
134 #define RME96_WCR_BITPOS_MONITOR_0 28
135 #define RME96_WCR_BITPOS_MONITOR_1 29
136
137 /* Read control register bits */
138 #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
139 #define RME96_RCR_IRQ_2 (1 << 16)
140 #define RME96_RCR_T_OUT (1 << 17)
141 #define RME96_RCR_DEV_ID_0 (1 << 21)
142 #define RME96_RCR_DEV_ID_1 (1 << 22)
143 #define RME96_RCR_LOCK (1 << 23)
144 #define RME96_RCR_VERF (1 << 26)
145 #define RME96_RCR_F0 (1 << 27)
146 #define RME96_RCR_F1 (1 << 28)
147 #define RME96_RCR_F2 (1 << 29)
148 #define RME96_RCR_AUTOSYNC (1 << 30)
149 #define RME96_RCR_IRQ (1 << 31)
150
151 #define RME96_RCR_BITPOS_F0 27
152 #define RME96_RCR_BITPOS_F1 28
153 #define RME96_RCR_BITPOS_F2 29
154
155 /* Additonal register bits */
156 #define RME96_AR_WSEL (1 << 0)
157 #define RME96_AR_ANALOG (1 << 1)
158 #define RME96_AR_FREQPAD_0 (1 << 2)
159 #define RME96_AR_FREQPAD_1 (1 << 3)
160 #define RME96_AR_FREQPAD_2 (1 << 4)
161 #define RME96_AR_PD2 (1 << 5)
162 #define RME96_AR_DAC_EN (1 << 6)
163 #define RME96_AR_CLATCH (1 << 7)
164 #define RME96_AR_CCLK (1 << 8)
165 #define RME96_AR_CDATA (1 << 9)
166
167 #define RME96_AR_BITPOS_F0 2
168 #define RME96_AR_BITPOS_F1 3
169 #define RME96_AR_BITPOS_F2 4
170
171 /* Monitor tracks */
172 #define RME96_MONITOR_TRACKS_1_2 0
173 #define RME96_MONITOR_TRACKS_3_4 1
174 #define RME96_MONITOR_TRACKS_5_6 2
175 #define RME96_MONITOR_TRACKS_7_8 3
176
177 /* Attenuation */
178 #define RME96_ATTENUATION_0 0
179 #define RME96_ATTENUATION_6 1
180 #define RME96_ATTENUATION_12 2
181 #define RME96_ATTENUATION_18 3
182
183 /* Input types */
184 #define RME96_INPUT_OPTICAL 0
185 #define RME96_INPUT_COAXIAL 1
186 #define RME96_INPUT_INTERNAL 2
187 #define RME96_INPUT_XLR 3
188 #define RME96_INPUT_ANALOG 4
189
190 /* Clock modes */
191 #define RME96_CLOCKMODE_SLAVE 0
192 #define RME96_CLOCKMODE_MASTER 1
193 #define RME96_CLOCKMODE_WORDCLOCK 2
194
195 /* Block sizes in bytes */
196 #define RME96_SMALL_BLOCK_SIZE 2048
197 #define RME96_LARGE_BLOCK_SIZE 8192
198
199 /* Volume control */
200 #define RME96_AD1852_VOL_BITS 14
201 #define RME96_AD1855_VOL_BITS 10
202
203
204 struct rme96 {
205 spinlock_t lock;
206 int irq;
207 unsigned long port;
208 void __iomem *iobase;
209
210 u32 wcreg; /* cached write control register value */
211 u32 wcreg_spdif; /* S/PDIF setup */
212 u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
213 u32 rcreg; /* cached read control register value */
214 u32 areg; /* cached additional register value */
215 u16 vol[2]; /* cached volume of analog output */
216
217 u8 rev; /* card revision number */
218
219 struct snd_pcm_substream *playback_substream;
220 struct snd_pcm_substream *capture_substream;
221
222 int playback_frlog; /* log2 of framesize */
223 int capture_frlog;
224
225 size_t playback_periodsize; /* in bytes, zero if not used */
226 size_t capture_periodsize; /* in bytes, zero if not used */
227
228 struct snd_card *card;
229 struct snd_pcm *spdif_pcm;
230 struct snd_pcm *adat_pcm;
231 struct pci_dev *pci;
232 struct snd_kcontrol *spdif_ctl;
233 };
234
235 static struct pci_device_id snd_rme96_ids[] = {
236 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_RME_DIGI96,
237 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
238 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_RME_DIGI96_8,
239 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
240 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO,
241 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
242 { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST,
243 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
244 { 0, }
245 };
246
247 MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
248
249 #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
250 #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
251 #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
252 #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
253 (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
254 #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
255 #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
256 ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
257 #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
258
259 static int
260 snd_rme96_playback_prepare(struct snd_pcm_substream *substream);
261
262 static int
263 snd_rme96_capture_prepare(struct snd_pcm_substream *substream);
264
265 static int
266 snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
267 int cmd);
268
269 static int
270 snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
271 int cmd);
272
273 static snd_pcm_uframes_t
274 snd_rme96_playback_pointer(struct snd_pcm_substream *substream);
275
276 static snd_pcm_uframes_t
277 snd_rme96_capture_pointer(struct snd_pcm_substream *substream);
278
279 static void __devinit
280 snd_rme96_proc_init(struct rme96 *rme96);
281
282 static int
283 snd_rme96_create_switches(struct snd_card *card,
284 struct rme96 *rme96);
285
286 static int
287 snd_rme96_getinputtype(struct rme96 *rme96);
288
289 static inline unsigned int
290 snd_rme96_playback_ptr(struct rme96 *rme96)
291 {
292 return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
293 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
294 }
295
296 static inline unsigned int
297 snd_rme96_capture_ptr(struct rme96 *rme96)
298 {
299 return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
300 & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
301 }
302
303 static int
304 snd_rme96_ratecode(int rate)
305 {
306 switch (rate) {
307 case 32000: return SNDRV_PCM_RATE_32000;
308 case 44100: return SNDRV_PCM_RATE_44100;
309 case 48000: return SNDRV_PCM_RATE_48000;
310 case 64000: return SNDRV_PCM_RATE_64000;
311 case 88200: return SNDRV_PCM_RATE_88200;
312 case 96000: return SNDRV_PCM_RATE_96000;
313 }
314 return 0;
315 }
316
317 static int
318 snd_rme96_playback_silence(struct snd_pcm_substream *substream,
319 int channel, /* not used (interleaved data) */
320 snd_pcm_uframes_t pos,
321 snd_pcm_uframes_t count)
322 {
323 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
324 count <<= rme96->playback_frlog;
325 pos <<= rme96->playback_frlog;
326 memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
327 0, count);
328 return 0;
329 }
330
331 static int
332 snd_rme96_playback_copy(struct snd_pcm_substream *substream,
333 int channel, /* not used (interleaved data) */
334 snd_pcm_uframes_t pos,
335 void __user *src,
336 snd_pcm_uframes_t count)
337 {
338 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
339 count <<= rme96->playback_frlog;
340 pos <<= rme96->playback_frlog;
341 copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src,
342 count);
343 return 0;
344 }
345
346 static int
347 snd_rme96_capture_copy(struct snd_pcm_substream *substream,
348 int channel, /* not used (interleaved data) */
349 snd_pcm_uframes_t pos,
350 void __user *dst,
351 snd_pcm_uframes_t count)
352 {
353 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
354 count <<= rme96->capture_frlog;
355 pos <<= rme96->capture_frlog;
356 copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos,
357 count);
358 return 0;
359 }
360
361 /*
362 * Digital output capabilites (S/PDIF)
363 */
364 static struct snd_pcm_hardware snd_rme96_playback_spdif_info =
365 {
366 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
367 SNDRV_PCM_INFO_MMAP_VALID |
368 SNDRV_PCM_INFO_INTERLEAVED |
369 SNDRV_PCM_INFO_PAUSE),
370 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
371 SNDRV_PCM_FMTBIT_S32_LE),
372 .rates = (SNDRV_PCM_RATE_32000 |
373 SNDRV_PCM_RATE_44100 |
374 SNDRV_PCM_RATE_48000 |
375 SNDRV_PCM_RATE_64000 |
376 SNDRV_PCM_RATE_88200 |
377 SNDRV_PCM_RATE_96000),
378 .rate_min = 32000,
379 .rate_max = 96000,
380 .channels_min = 2,
381 .channels_max = 2,
382 .buffer_bytes_max = RME96_BUFFER_SIZE,
383 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
384 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
385 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
386 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
387 .fifo_size = 0,
388 };
389
390 /*
391 * Digital input capabilites (S/PDIF)
392 */
393 static struct snd_pcm_hardware snd_rme96_capture_spdif_info =
394 {
395 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
396 SNDRV_PCM_INFO_MMAP_VALID |
397 SNDRV_PCM_INFO_INTERLEAVED |
398 SNDRV_PCM_INFO_PAUSE),
399 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
400 SNDRV_PCM_FMTBIT_S32_LE),
401 .rates = (SNDRV_PCM_RATE_32000 |
402 SNDRV_PCM_RATE_44100 |
403 SNDRV_PCM_RATE_48000 |
404 SNDRV_PCM_RATE_64000 |
405 SNDRV_PCM_RATE_88200 |
406 SNDRV_PCM_RATE_96000),
407 .rate_min = 32000,
408 .rate_max = 96000,
409 .channels_min = 2,
410 .channels_max = 2,
411 .buffer_bytes_max = RME96_BUFFER_SIZE,
412 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
413 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
414 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
415 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
416 .fifo_size = 0,
417 };
418
419 /*
420 * Digital output capabilites (ADAT)
421 */
422 static struct snd_pcm_hardware snd_rme96_playback_adat_info =
423 {
424 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
425 SNDRV_PCM_INFO_MMAP_VALID |
426 SNDRV_PCM_INFO_INTERLEAVED |
427 SNDRV_PCM_INFO_PAUSE),
428 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
429 SNDRV_PCM_FMTBIT_S32_LE),
430 .rates = (SNDRV_PCM_RATE_44100 |
431 SNDRV_PCM_RATE_48000),
432 .rate_min = 44100,
433 .rate_max = 48000,
434 .channels_min = 8,
435 .channels_max = 8,
436 .buffer_bytes_max = RME96_BUFFER_SIZE,
437 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
438 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
439 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
440 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
441 .fifo_size = 0,
442 };
443
444 /*
445 * Digital input capabilites (ADAT)
446 */
447 static struct snd_pcm_hardware snd_rme96_capture_adat_info =
448 {
449 .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
450 SNDRV_PCM_INFO_MMAP_VALID |
451 SNDRV_PCM_INFO_INTERLEAVED |
452 SNDRV_PCM_INFO_PAUSE),
453 .formats = (SNDRV_PCM_FMTBIT_S16_LE |
454 SNDRV_PCM_FMTBIT_S32_LE),
455 .rates = (SNDRV_PCM_RATE_44100 |
456 SNDRV_PCM_RATE_48000),
457 .rate_min = 44100,
458 .rate_max = 48000,
459 .channels_min = 8,
460 .channels_max = 8,
461 .buffer_bytes_max = RME96_BUFFER_SIZE,
462 .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
463 .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
464 .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
465 .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
466 .fifo_size = 0,
467 };
468
469 /*
470 * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
471 * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up
472 * on the falling edge of CCLK and be stable on the rising edge. The rising
473 * edge of CLATCH after the last data bit clocks in the whole data word.
474 * A fast processor could probably drive the SPI interface faster than the
475 * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1)
476 * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
477 *
478 * NOTE: increased delay from 1 to 10, since there where problems setting
479 * the volume.
480 */
481 static void
482 snd_rme96_write_SPI(struct rme96 *rme96, u16 val)
483 {
484 int i;
485
486 for (i = 0; i < 16; i++) {
487 if (val & 0x8000) {
488 rme96->areg |= RME96_AR_CDATA;
489 } else {
490 rme96->areg &= ~RME96_AR_CDATA;
491 }
492 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
493 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
494 udelay(10);
495 rme96->areg |= RME96_AR_CCLK;
496 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
497 udelay(10);
498 val <<= 1;
499 }
500 rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
501 rme96->areg |= RME96_AR_CLATCH;
502 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
503 udelay(10);
504 rme96->areg &= ~RME96_AR_CLATCH;
505 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
506 }
507
508 static void
509 snd_rme96_apply_dac_volume(struct rme96 *rme96)
510 {
511 if (RME96_DAC_IS_1852(rme96)) {
512 snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
513 snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
514 } else if (RME96_DAC_IS_1855(rme96)) {
515 snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
516 snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
517 }
518 }
519
520 static void
521 snd_rme96_reset_dac(struct rme96 *rme96)
522 {
523 writel(rme96->wcreg | RME96_WCR_PD,
524 rme96->iobase + RME96_IO_CONTROL_REGISTER);
525 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
526 }
527
528 static int
529 snd_rme96_getmontracks(struct rme96 *rme96)
530 {
531 return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
532 (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
533 }
534
535 static int
536 snd_rme96_setmontracks(struct rme96 *rme96,
537 int montracks)
538 {
539 if (montracks & 1) {
540 rme96->wcreg |= RME96_WCR_MONITOR_0;
541 } else {
542 rme96->wcreg &= ~RME96_WCR_MONITOR_0;
543 }
544 if (montracks & 2) {
545 rme96->wcreg |= RME96_WCR_MONITOR_1;
546 } else {
547 rme96->wcreg &= ~RME96_WCR_MONITOR_1;
548 }
549 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
550 return 0;
551 }
552
553 static int
554 snd_rme96_getattenuation(struct rme96 *rme96)
555 {
556 return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
557 (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
558 }
559
560 static int
561 snd_rme96_setattenuation(struct rme96 *rme96,
562 int attenuation)
563 {
564 switch (attenuation) {
565 case 0:
566 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
567 ~RME96_WCR_GAIN_1;
568 break;
569 case 1:
570 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
571 ~RME96_WCR_GAIN_1;
572 break;
573 case 2:
574 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
575 RME96_WCR_GAIN_1;
576 break;
577 case 3:
578 rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
579 RME96_WCR_GAIN_1;
580 break;
581 default:
582 return -EINVAL;
583 }
584 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
585 return 0;
586 }
587
588 static int
589 snd_rme96_capture_getrate(struct rme96 *rme96,
590 int *is_adat)
591 {
592 int n, rate;
593
594 *is_adat = 0;
595 if (rme96->areg & RME96_AR_ANALOG) {
596 /* Analog input, overrides S/PDIF setting */
597 n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
598 (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
599 switch (n) {
600 case 1:
601 rate = 32000;
602 break;
603 case 2:
604 rate = 44100;
605 break;
606 case 3:
607 rate = 48000;
608 break;
609 default:
610 return -1;
611 }
612 return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
613 }
614
615 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
616 if (rme96->rcreg & RME96_RCR_LOCK) {
617 /* ADAT rate */
618 *is_adat = 1;
619 if (rme96->rcreg & RME96_RCR_T_OUT) {
620 return 48000;
621 }
622 return 44100;
623 }
624
625 if (rme96->rcreg & RME96_RCR_VERF) {
626 return -1;
627 }
628
629 /* S/PDIF rate */
630 n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
631 (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
632 (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
633
634 switch (n) {
635 case 0:
636 if (rme96->rcreg & RME96_RCR_T_OUT) {
637 return 64000;
638 }
639 return -1;
640 case 3: return 96000;
641 case 4: return 88200;
642 case 5: return 48000;
643 case 6: return 44100;
644 case 7: return 32000;
645 default:
646 break;
647 }
648 return -1;
649 }
650
651 static int
652 snd_rme96_playback_getrate(struct rme96 *rme96)
653 {
654 int rate, dummy;
655
656 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
657 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
658 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
659 {
660 /* slave clock */
661 return rate;
662 }
663 rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
664 (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
665 switch (rate) {
666 case 1:
667 rate = 32000;
668 break;
669 case 2:
670 rate = 44100;
671 break;
672 case 3:
673 rate = 48000;
674 break;
675 default:
676 return -1;
677 }
678 return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
679 }
680
681 static int
682 snd_rme96_playback_setrate(struct rme96 *rme96,
683 int rate)
684 {
685 int ds;
686
687 ds = rme96->wcreg & RME96_WCR_DS;
688 switch (rate) {
689 case 32000:
690 rme96->wcreg &= ~RME96_WCR_DS;
691 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
692 ~RME96_WCR_FREQ_1;
693 break;
694 case 44100:
695 rme96->wcreg &= ~RME96_WCR_DS;
696 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
697 ~RME96_WCR_FREQ_0;
698 break;
699 case 48000:
700 rme96->wcreg &= ~RME96_WCR_DS;
701 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
702 RME96_WCR_FREQ_1;
703 break;
704 case 64000:
705 rme96->wcreg |= RME96_WCR_DS;
706 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
707 ~RME96_WCR_FREQ_1;
708 break;
709 case 88200:
710 rme96->wcreg |= RME96_WCR_DS;
711 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
712 ~RME96_WCR_FREQ_0;
713 break;
714 case 96000:
715 rme96->wcreg |= RME96_WCR_DS;
716 rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
717 RME96_WCR_FREQ_1;
718 break;
719 default:
720 return -EINVAL;
721 }
722 if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
723 (ds && !(rme96->wcreg & RME96_WCR_DS)))
724 {
725 /* change to/from double-speed: reset the DAC (if available) */
726 snd_rme96_reset_dac(rme96);
727 } else {
728 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
729 }
730 return 0;
731 }
732
733 static int
734 snd_rme96_capture_analog_setrate(struct rme96 *rme96,
735 int rate)
736 {
737 switch (rate) {
738 case 32000:
739 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
740 ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
741 break;
742 case 44100:
743 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
744 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
745 break;
746 case 48000:
747 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
748 RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
749 break;
750 case 64000:
751 if (rme96->rev < 4) {
752 return -EINVAL;
753 }
754 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
755 ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
756 break;
757 case 88200:
758 if (rme96->rev < 4) {
759 return -EINVAL;
760 }
761 rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
762 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
763 break;
764 case 96000:
765 rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
766 RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
767 break;
768 default:
769 return -EINVAL;
770 }
771 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
772 return 0;
773 }
774
775 static int
776 snd_rme96_setclockmode(struct rme96 *rme96,
777 int mode)
778 {
779 switch (mode) {
780 case RME96_CLOCKMODE_SLAVE:
781 /* AutoSync */
782 rme96->wcreg &= ~RME96_WCR_MASTER;
783 rme96->areg &= ~RME96_AR_WSEL;
784 break;
785 case RME96_CLOCKMODE_MASTER:
786 /* Internal */
787 rme96->wcreg |= RME96_WCR_MASTER;
788 rme96->areg &= ~RME96_AR_WSEL;
789 break;
790 case RME96_CLOCKMODE_WORDCLOCK:
791 /* Word clock is a master mode */
792 rme96->wcreg |= RME96_WCR_MASTER;
793 rme96->areg |= RME96_AR_WSEL;
794 break;
795 default:
796 return -EINVAL;
797 }
798 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
799 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
800 return 0;
801 }
802
803 static int
804 snd_rme96_getclockmode(struct rme96 *rme96)
805 {
806 if (rme96->areg & RME96_AR_WSEL) {
807 return RME96_CLOCKMODE_WORDCLOCK;
808 }
809 return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
810 RME96_CLOCKMODE_SLAVE;
811 }
812
813 static int
814 snd_rme96_setinputtype(struct rme96 *rme96,
815 int type)
816 {
817 int n;
818
819 switch (type) {
820 case RME96_INPUT_OPTICAL:
821 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
822 ~RME96_WCR_INP_1;
823 break;
824 case RME96_INPUT_COAXIAL:
825 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
826 ~RME96_WCR_INP_1;
827 break;
828 case RME96_INPUT_INTERNAL:
829 rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
830 RME96_WCR_INP_1;
831 break;
832 case RME96_INPUT_XLR:
833 if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
834 rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) ||
835 (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
836 rme96->rev > 4))
837 {
838 /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
839 return -EINVAL;
840 }
841 rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
842 RME96_WCR_INP_1;
843 break;
844 case RME96_INPUT_ANALOG:
845 if (!RME96_HAS_ANALOG_IN(rme96)) {
846 return -EINVAL;
847 }
848 rme96->areg |= RME96_AR_ANALOG;
849 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
850 if (rme96->rev < 4) {
851 /*
852 * Revision less than 004 does not support 64 and
853 * 88.2 kHz
854 */
855 if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
856 snd_rme96_capture_analog_setrate(rme96, 44100);
857 }
858 if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
859 snd_rme96_capture_analog_setrate(rme96, 32000);
860 }
861 }
862 return 0;
863 default:
864 return -EINVAL;
865 }
866 if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
867 rme96->areg &= ~RME96_AR_ANALOG;
868 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
869 }
870 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
871 return 0;
872 }
873
874 static int
875 snd_rme96_getinputtype(struct rme96 *rme96)
876 {
877 if (rme96->areg & RME96_AR_ANALOG) {
878 return RME96_INPUT_ANALOG;
879 }
880 return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
881 (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
882 }
883
884 static void
885 snd_rme96_setframelog(struct rme96 *rme96,
886 int n_channels,
887 int is_playback)
888 {
889 int frlog;
890
891 if (n_channels == 2) {
892 frlog = 1;
893 } else {
894 /* assume 8 channels */
895 frlog = 3;
896 }
897 if (is_playback) {
898 frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
899 rme96->playback_frlog = frlog;
900 } else {
901 frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
902 rme96->capture_frlog = frlog;
903 }
904 }
905
906 static int
907 snd_rme96_playback_setformat(struct rme96 *rme96,
908 int format)
909 {
910 switch (format) {
911 case SNDRV_PCM_FORMAT_S16_LE:
912 rme96->wcreg &= ~RME96_WCR_MODE24;
913 break;
914 case SNDRV_PCM_FORMAT_S32_LE:
915 rme96->wcreg |= RME96_WCR_MODE24;
916 break;
917 default:
918 return -EINVAL;
919 }
920 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
921 return 0;
922 }
923
924 static int
925 snd_rme96_capture_setformat(struct rme96 *rme96,
926 int format)
927 {
928 switch (format) {
929 case SNDRV_PCM_FORMAT_S16_LE:
930 rme96->wcreg &= ~RME96_WCR_MODE24_2;
931 break;
932 case SNDRV_PCM_FORMAT_S32_LE:
933 rme96->wcreg |= RME96_WCR_MODE24_2;
934 break;
935 default:
936 return -EINVAL;
937 }
938 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
939 return 0;
940 }
941
942 static void
943 snd_rme96_set_period_properties(struct rme96 *rme96,
944 size_t period_bytes)
945 {
946 switch (period_bytes) {
947 case RME96_LARGE_BLOCK_SIZE:
948 rme96->wcreg &= ~RME96_WCR_ISEL;
949 break;
950 case RME96_SMALL_BLOCK_SIZE:
951 rme96->wcreg |= RME96_WCR_ISEL;
952 break;
953 default:
954 snd_BUG();
955 break;
956 }
957 rme96->wcreg &= ~RME96_WCR_IDIS;
958 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
959 }
960
961 static int
962 snd_rme96_playback_hw_params(struct snd_pcm_substream *substream,
963 struct snd_pcm_hw_params *params)
964 {
965 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
966 struct snd_pcm_runtime *runtime = substream->runtime;
967 int err, rate, dummy;
968
969 runtime->dma_area = (void __force *)(rme96->iobase +
970 RME96_IO_PLAY_BUFFER);
971 runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
972 runtime->dma_bytes = RME96_BUFFER_SIZE;
973
974 spin_lock_irq(&rme96->lock);
975 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
976 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
977 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
978 {
979 /* slave clock */
980 if ((int)params_rate(params) != rate) {
981 spin_unlock_irq(&rme96->lock);
982 return -EIO;
983 }
984 } else if ((err = snd_rme96_playback_setrate(rme96, params_rate(params))) < 0) {
985 spin_unlock_irq(&rme96->lock);
986 return err;
987 }
988 if ((err = snd_rme96_playback_setformat(rme96, params_format(params))) < 0) {
989 spin_unlock_irq(&rme96->lock);
990 return err;
991 }
992 snd_rme96_setframelog(rme96, params_channels(params), 1);
993 if (rme96->capture_periodsize != 0) {
994 if (params_period_size(params) << rme96->playback_frlog !=
995 rme96->capture_periodsize)
996 {
997 spin_unlock_irq(&rme96->lock);
998 return -EBUSY;
999 }
1000 }
1001 rme96->playback_periodsize =
1002 params_period_size(params) << rme96->playback_frlog;
1003 snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
1004 /* S/PDIF setup */
1005 if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
1006 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
1007 writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1008 }
1009 spin_unlock_irq(&rme96->lock);
1010
1011 return 0;
1012 }
1013
1014 static int
1015 snd_rme96_capture_hw_params(struct snd_pcm_substream *substream,
1016 struct snd_pcm_hw_params *params)
1017 {
1018 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1019 struct snd_pcm_runtime *runtime = substream->runtime;
1020 int err, isadat, rate;
1021
1022 runtime->dma_area = (void __force *)(rme96->iobase +
1023 RME96_IO_REC_BUFFER);
1024 runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
1025 runtime->dma_bytes = RME96_BUFFER_SIZE;
1026
1027 spin_lock_irq(&rme96->lock);
1028 if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
1029 spin_unlock_irq(&rme96->lock);
1030 return err;
1031 }
1032 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1033 if ((err = snd_rme96_capture_analog_setrate(rme96,
1034 params_rate(params))) < 0)
1035 {
1036 spin_unlock_irq(&rme96->lock);
1037 return err;
1038 }
1039 } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1040 if ((int)params_rate(params) != rate) {
1041 spin_unlock_irq(&rme96->lock);
1042 return -EIO;
1043 }
1044 if ((isadat && runtime->hw.channels_min == 2) ||
1045 (!isadat && runtime->hw.channels_min == 8))
1046 {
1047 spin_unlock_irq(&rme96->lock);
1048 return -EIO;
1049 }
1050 }
1051 snd_rme96_setframelog(rme96, params_channels(params), 0);
1052 if (rme96->playback_periodsize != 0) {
1053 if (params_period_size(params) << rme96->capture_frlog !=
1054 rme96->playback_periodsize)
1055 {
1056 spin_unlock_irq(&rme96->lock);
1057 return -EBUSY;
1058 }
1059 }
1060 rme96->capture_periodsize =
1061 params_period_size(params) << rme96->capture_frlog;
1062 snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
1063 spin_unlock_irq(&rme96->lock);
1064
1065 return 0;
1066 }
1067
1068 static void
1069 snd_rme96_playback_start(struct rme96 *rme96,
1070 int from_pause)
1071 {
1072 if (!from_pause) {
1073 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1074 }
1075
1076 rme96->wcreg |= RME96_WCR_START;
1077 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1078 }
1079
1080 static void
1081 snd_rme96_capture_start(struct rme96 *rme96,
1082 int from_pause)
1083 {
1084 if (!from_pause) {
1085 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1086 }
1087
1088 rme96->wcreg |= RME96_WCR_START_2;
1089 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1090 }
1091
1092 static void
1093 snd_rme96_playback_stop(struct rme96 *rme96)
1094 {
1095 /*
1096 * Check if there is an unconfirmed IRQ, if so confirm it, or else
1097 * the hardware will not stop generating interrupts
1098 */
1099 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1100 if (rme96->rcreg & RME96_RCR_IRQ) {
1101 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1102 }
1103 rme96->wcreg &= ~RME96_WCR_START;
1104 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1105 }
1106
1107 static void
1108 snd_rme96_capture_stop(struct rme96 *rme96)
1109 {
1110 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1111 if (rme96->rcreg & RME96_RCR_IRQ_2) {
1112 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1113 }
1114 rme96->wcreg &= ~RME96_WCR_START_2;
1115 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1116 }
1117
1118 static irqreturn_t
1119 snd_rme96_interrupt(int irq,
1120 void *dev_id,
1121 struct pt_regs *regs)
1122 {
1123 struct rme96 *rme96 = (struct rme96 *)dev_id;
1124
1125 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1126 /* fastpath out, to ease interrupt sharing */
1127 if (!((rme96->rcreg & RME96_RCR_IRQ) ||
1128 (rme96->rcreg & RME96_RCR_IRQ_2)))
1129 {
1130 return IRQ_NONE;
1131 }
1132
1133 if (rme96->rcreg & RME96_RCR_IRQ) {
1134 /* playback */
1135 snd_pcm_period_elapsed(rme96->playback_substream);
1136 writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
1137 }
1138 if (rme96->rcreg & RME96_RCR_IRQ_2) {
1139 /* capture */
1140 snd_pcm_period_elapsed(rme96->capture_substream);
1141 writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
1142 }
1143 return IRQ_HANDLED;
1144 }
1145
1146 static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
1147
1148 static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
1149 .count = ARRAY_SIZE(period_bytes),
1150 .list = period_bytes,
1151 .mask = 0
1152 };
1153
1154 static int
1155 snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream)
1156 {
1157 int rate, dummy;
1158 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1159 struct snd_pcm_runtime *runtime = substream->runtime;
1160
1161 snd_pcm_set_sync(substream);
1162
1163 spin_lock_irq(&rme96->lock);
1164 if (rme96->playback_substream != NULL) {
1165 spin_unlock_irq(&rme96->lock);
1166 return -EBUSY;
1167 }
1168 rme96->wcreg &= ~RME96_WCR_ADAT;
1169 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1170 rme96->playback_substream = substream;
1171 spin_unlock_irq(&rme96->lock);
1172
1173 runtime->hw = snd_rme96_playback_spdif_info;
1174 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1175 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1176 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1177 {
1178 /* slave clock */
1179 runtime->hw.rates = snd_rme96_ratecode(rate);
1180 runtime->hw.rate_min = rate;
1181 runtime->hw.rate_max = rate;
1182 }
1183 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1184 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1185
1186 rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
1187 rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1188 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1189 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1190 return 0;
1191 }
1192
1193 static int
1194 snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream)
1195 {
1196 int isadat, rate;
1197 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1198 struct snd_pcm_runtime *runtime = substream->runtime;
1199
1200 snd_pcm_set_sync(substream);
1201
1202 runtime->hw = snd_rme96_capture_spdif_info;
1203 if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1204 (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
1205 {
1206 if (isadat) {
1207 return -EIO;
1208 }
1209 runtime->hw.rates = snd_rme96_ratecode(rate);
1210 runtime->hw.rate_min = rate;
1211 runtime->hw.rate_max = rate;
1212 }
1213
1214 spin_lock_irq(&rme96->lock);
1215 if (rme96->capture_substream != NULL) {
1216 spin_unlock_irq(&rme96->lock);
1217 return -EBUSY;
1218 }
1219 rme96->capture_substream = substream;
1220 spin_unlock_irq(&rme96->lock);
1221
1222 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1223 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1224
1225 return 0;
1226 }
1227
1228 static int
1229 snd_rme96_playback_adat_open(struct snd_pcm_substream *substream)
1230 {
1231 int rate, dummy;
1232 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1233 struct snd_pcm_runtime *runtime = substream->runtime;
1234
1235 snd_pcm_set_sync(substream);
1236
1237 spin_lock_irq(&rme96->lock);
1238 if (rme96->playback_substream != NULL) {
1239 spin_unlock_irq(&rme96->lock);
1240 return -EBUSY;
1241 }
1242 rme96->wcreg |= RME96_WCR_ADAT;
1243 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1244 rme96->playback_substream = substream;
1245 spin_unlock_irq(&rme96->lock);
1246
1247 runtime->hw = snd_rme96_playback_adat_info;
1248 if (!(rme96->wcreg & RME96_WCR_MASTER) &&
1249 snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
1250 (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
1251 {
1252 /* slave clock */
1253 runtime->hw.rates = snd_rme96_ratecode(rate);
1254 runtime->hw.rate_min = rate;
1255 runtime->hw.rate_max = rate;
1256 }
1257 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1258 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1259 return 0;
1260 }
1261
1262 static int
1263 snd_rme96_capture_adat_open(struct snd_pcm_substream *substream)
1264 {
1265 int isadat, rate;
1266 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1267 struct snd_pcm_runtime *runtime = substream->runtime;
1268
1269 snd_pcm_set_sync(substream);
1270
1271 runtime->hw = snd_rme96_capture_adat_info;
1272 if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1273 /* makes no sense to use analog input. Note that analog
1274 expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
1275 return -EIO;
1276 }
1277 if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
1278 if (!isadat) {
1279 return -EIO;
1280 }
1281 runtime->hw.rates = snd_rme96_ratecode(rate);
1282 runtime->hw.rate_min = rate;
1283 runtime->hw.rate_max = rate;
1284 }
1285
1286 spin_lock_irq(&rme96->lock);
1287 if (rme96->capture_substream != NULL) {
1288 spin_unlock_irq(&rme96->lock);
1289 return -EBUSY;
1290 }
1291 rme96->capture_substream = substream;
1292 spin_unlock_irq(&rme96->lock);
1293
1294 snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES, RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
1295 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES, &hw_constraints_period_bytes);
1296 return 0;
1297 }
1298
1299 static int
1300 snd_rme96_playback_close(struct snd_pcm_substream *substream)
1301 {
1302 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1303 int spdif = 0;
1304
1305 spin_lock_irq(&rme96->lock);
1306 if (RME96_ISPLAYING(rme96)) {
1307 snd_rme96_playback_stop(rme96);
1308 }
1309 rme96->playback_substream = NULL;
1310 rme96->playback_periodsize = 0;
1311 spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
1312 spin_unlock_irq(&rme96->lock);
1313 if (spdif) {
1314 rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
1315 snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
1316 SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
1317 }
1318 return 0;
1319 }
1320
1321 static int
1322 snd_rme96_capture_close(struct snd_pcm_substream *substream)
1323 {
1324 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1325
1326 spin_lock_irq(&rme96->lock);
1327 if (RME96_ISRECORDING(rme96)) {
1328 snd_rme96_capture_stop(rme96);
1329 }
1330 rme96->capture_substream = NULL;
1331 rme96->capture_periodsize = 0;
1332 spin_unlock_irq(&rme96->lock);
1333 return 0;
1334 }
1335
1336 static int
1337 snd_rme96_playback_prepare(struct snd_pcm_substream *substream)
1338 {
1339 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1340
1341 spin_lock_irq(&rme96->lock);
1342 if (RME96_ISPLAYING(rme96)) {
1343 snd_rme96_playback_stop(rme96);
1344 }
1345 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1346 spin_unlock_irq(&rme96->lock);
1347 return 0;
1348 }
1349
1350 static int
1351 snd_rme96_capture_prepare(struct snd_pcm_substream *substream)
1352 {
1353 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1354
1355 spin_lock_irq(&rme96->lock);
1356 if (RME96_ISRECORDING(rme96)) {
1357 snd_rme96_capture_stop(rme96);
1358 }
1359 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1360 spin_unlock_irq(&rme96->lock);
1361 return 0;
1362 }
1363
1364 static int
1365 snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
1366 int cmd)
1367 {
1368 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1369
1370 switch (cmd) {
1371 case SNDRV_PCM_TRIGGER_START:
1372 if (!RME96_ISPLAYING(rme96)) {
1373 if (substream != rme96->playback_substream) {
1374 return -EBUSY;
1375 }
1376 snd_rme96_playback_start(rme96, 0);
1377 }
1378 break;
1379
1380 case SNDRV_PCM_TRIGGER_STOP:
1381 if (RME96_ISPLAYING(rme96)) {
1382 if (substream != rme96->playback_substream) {
1383 return -EBUSY;
1384 }
1385 snd_rme96_playback_stop(rme96);
1386 }
1387 break;
1388
1389 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1390 if (RME96_ISPLAYING(rme96)) {
1391 snd_rme96_playback_stop(rme96);
1392 }
1393 break;
1394
1395 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1396 if (!RME96_ISPLAYING(rme96)) {
1397 snd_rme96_playback_start(rme96, 1);
1398 }
1399 break;
1400
1401 default:
1402 return -EINVAL;
1403 }
1404 return 0;
1405 }
1406
1407 static int
1408 snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
1409 int cmd)
1410 {
1411 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1412
1413 switch (cmd) {
1414 case SNDRV_PCM_TRIGGER_START:
1415 if (!RME96_ISRECORDING(rme96)) {
1416 if (substream != rme96->capture_substream) {
1417 return -EBUSY;
1418 }
1419 snd_rme96_capture_start(rme96, 0);
1420 }
1421 break;
1422
1423 case SNDRV_PCM_TRIGGER_STOP:
1424 if (RME96_ISRECORDING(rme96)) {
1425 if (substream != rme96->capture_substream) {
1426 return -EBUSY;
1427 }
1428 snd_rme96_capture_stop(rme96);
1429 }
1430 break;
1431
1432 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1433 if (RME96_ISRECORDING(rme96)) {
1434 snd_rme96_capture_stop(rme96);
1435 }
1436 break;
1437
1438 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1439 if (!RME96_ISRECORDING(rme96)) {
1440 snd_rme96_capture_start(rme96, 1);
1441 }
1442 break;
1443
1444 default:
1445 return -EINVAL;
1446 }
1447
1448 return 0;
1449 }
1450
1451 static snd_pcm_uframes_t
1452 snd_rme96_playback_pointer(struct snd_pcm_substream *substream)
1453 {
1454 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1455 return snd_rme96_playback_ptr(rme96);
1456 }
1457
1458 static snd_pcm_uframes_t
1459 snd_rme96_capture_pointer(struct snd_pcm_substream *substream)
1460 {
1461 struct rme96 *rme96 = snd_pcm_substream_chip(substream);
1462 return snd_rme96_capture_ptr(rme96);
1463 }
1464
1465 static struct snd_pcm_ops snd_rme96_playback_spdif_ops = {
1466 .open = snd_rme96_playback_spdif_open,
1467 .close = snd_rme96_playback_close,
1468 .ioctl = snd_pcm_lib_ioctl,
1469 .hw_params = snd_rme96_playback_hw_params,
1470 .prepare = snd_rme96_playback_prepare,
1471 .trigger = snd_rme96_playback_trigger,
1472 .pointer = snd_rme96_playback_pointer,
1473 .copy = snd_rme96_playback_copy,
1474 .silence = snd_rme96_playback_silence,
1475 .mmap = snd_pcm_lib_mmap_iomem,
1476 };
1477
1478 static struct snd_pcm_ops snd_rme96_capture_spdif_ops = {
1479 .open = snd_rme96_capture_spdif_open,
1480 .close = snd_rme96_capture_close,
1481 .ioctl = snd_pcm_lib_ioctl,
1482 .hw_params = snd_rme96_capture_hw_params,
1483 .prepare = snd_rme96_capture_prepare,
1484 .trigger = snd_rme96_capture_trigger,
1485 .pointer = snd_rme96_capture_pointer,
1486 .copy = snd_rme96_capture_copy,
1487 .mmap = snd_pcm_lib_mmap_iomem,
1488 };
1489
1490 static struct snd_pcm_ops snd_rme96_playback_adat_ops = {
1491 .open = snd_rme96_playback_adat_open,
1492 .close = snd_rme96_playback_close,
1493 .ioctl = snd_pcm_lib_ioctl,
1494 .hw_params = snd_rme96_playback_hw_params,
1495 .prepare = snd_rme96_playback_prepare,
1496 .trigger = snd_rme96_playback_trigger,
1497 .pointer = snd_rme96_playback_pointer,
1498 .copy = snd_rme96_playback_copy,
1499 .silence = snd_rme96_playback_silence,
1500 .mmap = snd_pcm_lib_mmap_iomem,
1501 };
1502
1503 static struct snd_pcm_ops snd_rme96_capture_adat_ops = {
1504 .open = snd_rme96_capture_adat_open,
1505 .close = snd_rme96_capture_close,
1506 .ioctl = snd_pcm_lib_ioctl,
1507 .hw_params = snd_rme96_capture_hw_params,
1508 .prepare = snd_rme96_capture_prepare,
1509 .trigger = snd_rme96_capture_trigger,
1510 .pointer = snd_rme96_capture_pointer,
1511 .copy = snd_rme96_capture_copy,
1512 .mmap = snd_pcm_lib_mmap_iomem,
1513 };
1514
1515 static void
1516 snd_rme96_free(void *private_data)
1517 {
1518 struct rme96 *rme96 = (struct rme96 *)private_data;
1519
1520 if (rme96 == NULL) {
1521 return;
1522 }
1523 if (rme96->irq >= 0) {
1524 snd_rme96_playback_stop(rme96);
1525 snd_rme96_capture_stop(rme96);
1526 rme96->areg &= ~RME96_AR_DAC_EN;
1527 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1528 free_irq(rme96->irq, (void *)rme96);
1529 rme96->irq = -1;
1530 }
1531 if (rme96->iobase) {
1532 iounmap(rme96->iobase);
1533 rme96->iobase = NULL;
1534 }
1535 if (rme96->port) {
1536 pci_release_regions(rme96->pci);
1537 rme96->port = 0;
1538 }
1539 pci_disable_device(rme96->pci);
1540 }
1541
1542 static void
1543 snd_rme96_free_spdif_pcm(struct snd_pcm *pcm)
1544 {
1545 struct rme96 *rme96 = (struct rme96 *) pcm->private_data;
1546 rme96->spdif_pcm = NULL;
1547 }
1548
1549 static void
1550 snd_rme96_free_adat_pcm(struct snd_pcm *pcm)
1551 {
1552 struct rme96 *rme96 = (struct rme96 *) pcm->private_data;
1553 rme96->adat_pcm = NULL;
1554 }
1555
1556 static int __devinit
1557 snd_rme96_create(struct rme96 *rme96)
1558 {
1559 struct pci_dev *pci = rme96->pci;
1560 int err;
1561
1562 rme96->irq = -1;
1563 spin_lock_init(&rme96->lock);
1564
1565 if ((err = pci_enable_device(pci)) < 0)
1566 return err;
1567
1568 if ((err = pci_request_regions(pci, "RME96")) < 0)
1569 return err;
1570 rme96->port = pci_resource_start(rme96->pci, 0);
1571
1572 if (request_irq(pci->irq, snd_rme96_interrupt, SA_INTERRUPT|SA_SHIRQ, "RME96", (void *)rme96)) {
1573 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1574 return -EBUSY;
1575 }
1576 rme96->irq = pci->irq;
1577
1578 if ((rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE)) == 0) {
1579 snd_printk(KERN_ERR "unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1);
1580 return -ENOMEM;
1581 }
1582
1583 /* read the card's revision number */
1584 pci_read_config_byte(pci, 8, &rme96->rev);
1585
1586 /* set up ALSA pcm device for S/PDIF */
1587 if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
1588 1, 1, &rme96->spdif_pcm)) < 0)
1589 {
1590 return err;
1591 }
1592 rme96->spdif_pcm->private_data = rme96;
1593 rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
1594 strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
1595 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
1596 snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
1597
1598 rme96->spdif_pcm->info_flags = 0;
1599
1600 /* set up ALSA pcm device for ADAT */
1601 if (pci->device == PCI_DEVICE_ID_RME_DIGI96) {
1602 /* ADAT is not available on the base model */
1603 rme96->adat_pcm = NULL;
1604 } else {
1605 if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
1606 1, 1, &rme96->adat_pcm)) < 0)
1607 {
1608 return err;
1609 }
1610 rme96->adat_pcm->private_data = rme96;
1611 rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
1612 strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
1613 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
1614 snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
1615
1616 rme96->adat_pcm->info_flags = 0;
1617 }
1618
1619 rme96->playback_periodsize = 0;
1620 rme96->capture_periodsize = 0;
1621
1622 /* make sure playback/capture is stopped, if by some reason active */
1623 snd_rme96_playback_stop(rme96);
1624 snd_rme96_capture_stop(rme96);
1625
1626 /* set default values in registers */
1627 rme96->wcreg =
1628 RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
1629 RME96_WCR_SEL | /* normal playback */
1630 RME96_WCR_MASTER | /* set to master clock mode */
1631 RME96_WCR_INP_0; /* set coaxial input */
1632
1633 rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
1634
1635 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1636 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1637
1638 /* reset the ADC */
1639 writel(rme96->areg | RME96_AR_PD2,
1640 rme96->iobase + RME96_IO_ADDITIONAL_REG);
1641 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1642
1643 /* reset and enable the DAC (order is important). */
1644 snd_rme96_reset_dac(rme96);
1645 rme96->areg |= RME96_AR_DAC_EN;
1646 writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
1647
1648 /* reset playback and record buffer pointers */
1649 writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
1650 writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
1651
1652 /* reset volume */
1653 rme96->vol[0] = rme96->vol[1] = 0;
1654 if (RME96_HAS_ANALOG_OUT(rme96)) {
1655 snd_rme96_apply_dac_volume(rme96);
1656 }
1657
1658 /* init switch interface */
1659 if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
1660 return err;
1661 }
1662
1663 /* init proc interface */
1664 snd_rme96_proc_init(rme96);
1665
1666 return 0;
1667 }
1668
1669 /*
1670 * proc interface
1671 */
1672
1673 static void
1674 snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
1675 {
1676 int n;
1677 struct rme96 *rme96 = (struct rme96 *)entry->private_data;
1678
1679 rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
1680
1681 snd_iprintf(buffer, rme96->card->longname);
1682 snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
1683
1684 snd_iprintf(buffer, "\nGeneral settings\n");
1685 if (rme96->wcreg & RME96_WCR_IDIS) {
1686 snd_iprintf(buffer, " period size: N/A (interrupts "
1687 "disabled)\n");
1688 } else if (rme96->wcreg & RME96_WCR_ISEL) {
1689 snd_iprintf(buffer, " period size: 2048 bytes\n");
1690 } else {
1691 snd_iprintf(buffer, " period size: 8192 bytes\n");
1692 }
1693 snd_iprintf(buffer, "\nInput settings\n");
1694 switch (snd_rme96_getinputtype(rme96)) {
1695 case RME96_INPUT_OPTICAL:
1696 snd_iprintf(buffer, " input: optical");
1697 break;
1698 case RME96_INPUT_COAXIAL:
1699 snd_iprintf(buffer, " input: coaxial");
1700 break;
1701 case RME96_INPUT_INTERNAL:
1702 snd_iprintf(buffer, " input: internal");
1703 break;
1704 case RME96_INPUT_XLR:
1705 snd_iprintf(buffer, " input: XLR");
1706 break;
1707 case RME96_INPUT_ANALOG:
1708 snd_iprintf(buffer, " input: analog");
1709 break;
1710 }
1711 if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1712 snd_iprintf(buffer, "\n sample rate: no valid signal\n");
1713 } else {
1714 if (n) {
1715 snd_iprintf(buffer, " (8 channels)\n");
1716 } else {
1717 snd_iprintf(buffer, " (2 channels)\n");
1718 }
1719 snd_iprintf(buffer, " sample rate: %d Hz\n",
1720 snd_rme96_capture_getrate(rme96, &n));
1721 }
1722 if (rme96->wcreg & RME96_WCR_MODE24_2) {
1723 snd_iprintf(buffer, " sample format: 24 bit\n");
1724 } else {
1725 snd_iprintf(buffer, " sample format: 16 bit\n");
1726 }
1727
1728 snd_iprintf(buffer, "\nOutput settings\n");
1729 if (rme96->wcreg & RME96_WCR_SEL) {
1730 snd_iprintf(buffer, " output signal: normal playback\n");
1731 } else {
1732 snd_iprintf(buffer, " output signal: same as input\n");
1733 }
1734 snd_iprintf(buffer, " sample rate: %d Hz\n",
1735 snd_rme96_playback_getrate(rme96));
1736 if (rme96->wcreg & RME96_WCR_MODE24) {
1737 snd_iprintf(buffer, " sample format: 24 bit\n");
1738 } else {
1739 snd_iprintf(buffer, " sample format: 16 bit\n");
1740 }
1741 if (rme96->areg & RME96_AR_WSEL) {
1742 snd_iprintf(buffer, " sample clock source: word clock\n");
1743 } else if (rme96->wcreg & RME96_WCR_MASTER) {
1744 snd_iprintf(buffer, " sample clock source: internal\n");
1745 } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
1746 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n");
1747 } else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
1748 snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n");
1749 } else {
1750 snd_iprintf(buffer, " sample clock source: autosync\n");
1751 }
1752 if (rme96->wcreg & RME96_WCR_PRO) {
1753 snd_iprintf(buffer, " format: AES/EBU (professional)\n");
1754 } else {
1755 snd_iprintf(buffer, " format: IEC958 (consumer)\n");
1756 }
1757 if (rme96->wcreg & RME96_WCR_EMP) {
1758 snd_iprintf(buffer, " emphasis: on\n");
1759 } else {
1760 snd_iprintf(buffer, " emphasis: off\n");
1761 }
1762 if (rme96->wcreg & RME96_WCR_DOLBY) {
1763 snd_iprintf(buffer, " non-audio (dolby): on\n");
1764 } else {
1765 snd_iprintf(buffer, " non-audio (dolby): off\n");
1766 }
1767 if (RME96_HAS_ANALOG_IN(rme96)) {
1768 snd_iprintf(buffer, "\nAnalog output settings\n");
1769 switch (snd_rme96_getmontracks(rme96)) {
1770 case RME96_MONITOR_TRACKS_1_2:
1771 snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n");
1772 break;
1773 case RME96_MONITOR_TRACKS_3_4:
1774 snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n");
1775 break;
1776 case RME96_MONITOR_TRACKS_5_6:
1777 snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n");
1778 break;
1779 case RME96_MONITOR_TRACKS_7_8:
1780 snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n");
1781 break;
1782 }
1783 switch (snd_rme96_getattenuation(rme96)) {
1784 case RME96_ATTENUATION_0:
1785 snd_iprintf(buffer, " attenuation: 0 dB\n");
1786 break;
1787 case RME96_ATTENUATION_6:
1788 snd_iprintf(buffer, " attenuation: -6 dB\n");
1789 break;
1790 case RME96_ATTENUATION_12:
1791 snd_iprintf(buffer, " attenuation: -12 dB\n");
1792 break;
1793 case RME96_ATTENUATION_18:
1794 snd_iprintf(buffer, " attenuation: -18 dB\n");
1795 break;
1796 }
1797 snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]);
1798 snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]);
1799 }
1800 }
1801
1802 static void __devinit
1803 snd_rme96_proc_init(struct rme96 *rme96)
1804 {
1805 struct snd_info_entry *entry;
1806
1807 if (! snd_card_proc_new(rme96->card, "rme96", &entry))
1808 snd_info_set_text_ops(entry, rme96, 1024, snd_rme96_proc_read);
1809 }
1810
1811 /*
1812 * control interface
1813 */
1814
1815 static int
1816 snd_rme96_info_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1817 {
1818 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
1819 uinfo->count = 1;
1820 uinfo->value.integer.min = 0;
1821 uinfo->value.integer.max = 1;
1822 return 0;
1823 }
1824 static int
1825 snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1826 {
1827 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1828
1829 spin_lock_irq(&rme96->lock);
1830 ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
1831 spin_unlock_irq(&rme96->lock);
1832 return 0;
1833 }
1834 static int
1835 snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1836 {
1837 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1838 unsigned int val;
1839 int change;
1840
1841 val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
1842 spin_lock_irq(&rme96->lock);
1843 val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
1844 change = val != rme96->wcreg;
1845 rme96->wcreg = val;
1846 writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
1847 spin_unlock_irq(&rme96->lock);
1848 return change;
1849 }
1850
1851 static int
1852 snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1853 {
1854 static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
1855 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1856 char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] };
1857
1858 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1859 uinfo->count = 1;
1860 switch (rme96->pci->device) {
1861 case PCI_DEVICE_ID_RME_DIGI96:
1862 case PCI_DEVICE_ID_RME_DIGI96_8:
1863 uinfo->value.enumerated.items = 3;
1864 break;
1865 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1866 uinfo->value.enumerated.items = 4;
1867 break;
1868 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1869 if (rme96->rev > 4) {
1870 /* PST */
1871 uinfo->value.enumerated.items = 4;
1872 texts[3] = _texts[4]; /* Analog instead of XLR */
1873 } else {
1874 /* PAD */
1875 uinfo->value.enumerated.items = 5;
1876 }
1877 break;
1878 default:
1879 snd_BUG();
1880 break;
1881 }
1882 if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) {
1883 uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
1884 }
1885 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1886 return 0;
1887 }
1888 static int
1889 snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1890 {
1891 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1892 unsigned int items = 3;
1893
1894 spin_lock_irq(&rme96->lock);
1895 ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
1896
1897 switch (rme96->pci->device) {
1898 case PCI_DEVICE_ID_RME_DIGI96:
1899 case PCI_DEVICE_ID_RME_DIGI96_8:
1900 items = 3;
1901 break;
1902 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1903 items = 4;
1904 break;
1905 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1906 if (rme96->rev > 4) {
1907 /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
1908 if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
1909 ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
1910 }
1911 items = 4;
1912 } else {
1913 items = 5;
1914 }
1915 break;
1916 default:
1917 snd_BUG();
1918 break;
1919 }
1920 if (ucontrol->value.enumerated.item[0] >= items) {
1921 ucontrol->value.enumerated.item[0] = items - 1;
1922 }
1923
1924 spin_unlock_irq(&rme96->lock);
1925 return 0;
1926 }
1927 static int
1928 snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1929 {
1930 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1931 unsigned int val;
1932 int change, items = 3;
1933
1934 switch (rme96->pci->device) {
1935 case PCI_DEVICE_ID_RME_DIGI96:
1936 case PCI_DEVICE_ID_RME_DIGI96_8:
1937 items = 3;
1938 break;
1939 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
1940 items = 4;
1941 break;
1942 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
1943 if (rme96->rev > 4) {
1944 items = 4;
1945 } else {
1946 items = 5;
1947 }
1948 break;
1949 default:
1950 snd_BUG();
1951 break;
1952 }
1953 val = ucontrol->value.enumerated.item[0] % items;
1954
1955 /* special case for PST */
1956 if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
1957 if (val == RME96_INPUT_XLR) {
1958 val = RME96_INPUT_ANALOG;
1959 }
1960 }
1961
1962 spin_lock_irq(&rme96->lock);
1963 change = (int)val != snd_rme96_getinputtype(rme96);
1964 snd_rme96_setinputtype(rme96, val);
1965 spin_unlock_irq(&rme96->lock);
1966 return change;
1967 }
1968
1969 static int
1970 snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1971 {
1972 static char *texts[3] = { "AutoSync", "Internal", "Word" };
1973
1974 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
1975 uinfo->count = 1;
1976 uinfo->value.enumerated.items = 3;
1977 if (uinfo->value.enumerated.item > 2) {
1978 uinfo->value.enumerated.item = 2;
1979 }
1980 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
1981 return 0;
1982 }
1983 static int
1984 snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1985 {
1986 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1987
1988 spin_lock_irq(&rme96->lock);
1989 ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
1990 spin_unlock_irq(&rme96->lock);
1991 return 0;
1992 }
1993 static int
1994 snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1995 {
1996 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
1997 unsigned int val;
1998 int change;
1999
2000 val = ucontrol->value.enumerated.item[0] % 3;
2001 spin_lock_irq(&rme96->lock);
2002 change = (int)val != snd_rme96_getclockmode(rme96);
2003 snd_rme96_setclockmode(rme96, val);
2004 spin_unlock_irq(&rme96->lock);
2005 return change;
2006 }
2007
2008 static int
2009 snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2010 {
2011 static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" };
2012
2013 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2014 uinfo->count = 1;
2015 uinfo->value.enumerated.items = 4;
2016 if (uinfo->value.enumerated.item > 3) {
2017 uinfo->value.enumerated.item = 3;
2018 }
2019 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2020 return 0;
2021 }
2022 static int
2023 snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2024 {
2025 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2026
2027 spin_lock_irq(&rme96->lock);
2028 ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
2029 spin_unlock_irq(&rme96->lock);
2030 return 0;
2031 }
2032 static int
2033 snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2034 {
2035 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2036 unsigned int val;
2037 int change;
2038
2039 val = ucontrol->value.enumerated.item[0] % 4;
2040 spin_lock_irq(&rme96->lock);
2041
2042 change = (int)val != snd_rme96_getattenuation(rme96);
2043 snd_rme96_setattenuation(rme96, val);
2044 spin_unlock_irq(&rme96->lock);
2045 return change;
2046 }
2047
2048 static int
2049 snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2050 {
2051 static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" };
2052
2053 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
2054 uinfo->count = 1;
2055 uinfo->value.enumerated.items = 4;
2056 if (uinfo->value.enumerated.item > 3) {
2057 uinfo->value.enumerated.item = 3;
2058 }
2059 strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
2060 return 0;
2061 }
2062 static int
2063 snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2064 {
2065 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2066
2067 spin_lock_irq(&rme96->lock);
2068 ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
2069 spin_unlock_irq(&rme96->lock);
2070 return 0;
2071 }
2072 static int
2073 snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2074 {
2075 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2076 unsigned int val;
2077 int change;
2078
2079 val = ucontrol->value.enumerated.item[0] % 4;
2080 spin_lock_irq(&rme96->lock);
2081 change = (int)val != snd_rme96_getmontracks(rme96);
2082 snd_rme96_setmontracks(rme96, val);
2083 spin_unlock_irq(&rme96->lock);
2084 return change;
2085 }
2086
2087 static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes)
2088 {
2089 u32 val = 0;
2090 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
2091 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
2092 if (val & RME96_WCR_PRO)
2093 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2094 else
2095 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
2096 return val;
2097 }
2098
2099 static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
2100 {
2101 aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
2102 ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
2103 if (val & RME96_WCR_PRO)
2104 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
2105 else
2106 aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
2107 }
2108
2109 static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2110 {
2111 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2112 uinfo->count = 1;
2113 return 0;
2114 }
2115
2116 static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2117 {
2118 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2119
2120 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
2121 return 0;
2122 }
2123
2124 static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2125 {
2126 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2127 int change;
2128 u32 val;
2129
2130 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2131 spin_lock_irq(&rme96->lock);
2132 change = val != rme96->wcreg_spdif;
2133 rme96->wcreg_spdif = val;
2134 spin_unlock_irq(&rme96->lock);
2135 return change;
2136 }
2137
2138 static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2139 {
2140 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2141 uinfo->count = 1;
2142 return 0;
2143 }
2144
2145 static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2146 {
2147 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2148
2149 snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
2150 return 0;
2151 }
2152
2153 static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2154 {
2155 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2156 int change;
2157 u32 val;
2158
2159 val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
2160 spin_lock_irq(&rme96->lock);
2161 change = val != rme96->wcreg_spdif_stream;
2162 rme96->wcreg_spdif_stream = val;
2163 rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
2164 rme96->wcreg |= val;
2165 writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
2166 spin_unlock_irq(&rme96->lock);
2167 return change;
2168 }
2169
2170 static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2171 {
2172 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
2173 uinfo->count = 1;
2174 return 0;
2175 }
2176
2177 static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2178 {
2179 ucontrol->value.iec958.status[0] = kcontrol->private_value;
2180 return 0;
2181 }
2182
2183 static int
2184 snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2185 {
2186 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2187
2188 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2189 uinfo->count = 2;
2190 uinfo->value.integer.min = 0;
2191 uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
2192 return 0;
2193 }
2194
2195 static int
2196 snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
2197 {
2198 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2199
2200 spin_lock_irq(&rme96->lock);
2201 u->value.integer.value[0] = rme96->vol[0];
2202 u->value.integer.value[1] = rme96->vol[1];
2203 spin_unlock_irq(&rme96->lock);
2204
2205 return 0;
2206 }
2207
2208 static int
2209 snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
2210 {
2211 struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
2212 int change = 0;
2213
2214 if (!RME96_HAS_ANALOG_OUT(rme96)) {
2215 return -EINVAL;
2216 }
2217 spin_lock_irq(&rme96->lock);
2218 if (u->value.integer.value[0] != rme96->vol[0]) {
2219 rme96->vol[0] = u->value.integer.value[0];
2220 change = 1;
2221 }
2222 if (u->value.integer.value[1] != rme96->vol[1]) {
2223 rme96->vol[1] = u->value.integer.value[1];
2224 change = 1;
2225 }
2226 if (change) {
2227 snd_rme96_apply_dac_volume(rme96);
2228 }
2229 spin_unlock_irq(&rme96->lock);
2230
2231 return change;
2232 }
2233
2234 static struct snd_kcontrol_new snd_rme96_controls[] = {
2235 {
2236 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2237 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2238 .info = snd_rme96_control_spdif_info,
2239 .get = snd_rme96_control_spdif_get,
2240 .put = snd_rme96_control_spdif_put
2241 },
2242 {
2243 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2244 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2245 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2246 .info = snd_rme96_control_spdif_stream_info,
2247 .get = snd_rme96_control_spdif_stream_get,
2248 .put = snd_rme96_control_spdif_stream_put
2249 },
2250 {
2251 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2252 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2253 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2254 .info = snd_rme96_control_spdif_mask_info,
2255 .get = snd_rme96_control_spdif_mask_get,
2256 .private_value = IEC958_AES0_NONAUDIO |
2257 IEC958_AES0_PROFESSIONAL |
2258 IEC958_AES0_CON_EMPHASIS
2259 },
2260 {
2261 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2262 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2263 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2264 .info = snd_rme96_control_spdif_mask_info,
2265 .get = snd_rme96_control_spdif_mask_get,
2266 .private_value = IEC958_AES0_NONAUDIO |
2267 IEC958_AES0_PROFESSIONAL |
2268 IEC958_AES0_PRO_EMPHASIS
2269 },
2270 {
2271 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2272 .name = "Input Connector",
2273 .info = snd_rme96_info_inputtype_control,
2274 .get = snd_rme96_get_inputtype_control,
2275 .put = snd_rme96_put_inputtype_control
2276 },
2277 {
2278 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2279 .name = "Loopback Input",
2280 .info = snd_rme96_info_loopback_control,
2281 .get = snd_rme96_get_loopback_control,
2282 .put = snd_rme96_put_loopback_control
2283 },
2284 {
2285 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2286 .name = "Sample Clock Source",
2287 .info = snd_rme96_info_clockmode_control,
2288 .get = snd_rme96_get_clockmode_control,
2289 .put = snd_rme96_put_clockmode_control
2290 },
2291 {
2292 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2293 .name = "Monitor Tracks",
2294 .info = snd_rme96_info_montracks_control,
2295 .get = snd_rme96_get_montracks_control,
2296 .put = snd_rme96_put_montracks_control
2297 },
2298 {
2299 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2300 .name = "Attenuation",
2301 .info = snd_rme96_info_attenuation_control,
2302 .get = snd_rme96_get_attenuation_control,
2303 .put = snd_rme96_put_attenuation_control
2304 },
2305 {
2306 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2307 .name = "DAC Playback Volume",
2308 .info = snd_rme96_dac_volume_info,
2309 .get = snd_rme96_dac_volume_get,
2310 .put = snd_rme96_dac_volume_put
2311 }
2312 };
2313
2314 static int
2315 snd_rme96_create_switches(struct snd_card *card,
2316 struct rme96 *rme96)
2317 {
2318 int idx, err;
2319 struct snd_kcontrol *kctl;
2320
2321 for (idx = 0; idx < 7; idx++) {
2322 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2323 return err;
2324 if (idx == 1) /* IEC958 (S/PDIF) Stream */
2325 rme96->spdif_ctl = kctl;
2326 }
2327
2328 if (RME96_HAS_ANALOG_OUT(rme96)) {
2329 for (idx = 7; idx < 10; idx++)
2330 if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
2331 return err;
2332 }
2333
2334 return 0;
2335 }
2336
2337 /*
2338 * Card initialisation
2339 */
2340
2341 static void snd_rme96_card_free(struct snd_card *card)
2342 {
2343 snd_rme96_free(card->private_data);
2344 }
2345
2346 static int __devinit
2347 snd_rme96_probe(struct pci_dev *pci,
2348 const struct pci_device_id *pci_id)
2349 {
2350 static int dev;
2351 struct rme96 *rme96;
2352 struct snd_card *card;
2353 int err;
2354 u8 val;
2355
2356 if (dev >= SNDRV_CARDS) {
2357 return -ENODEV;
2358 }
2359 if (!enable[dev]) {
2360 dev++;
2361 return -ENOENT;
2362 }
2363 if ((card = snd_card_new(index[dev], id[dev], THIS_MODULE,
2364 sizeof(struct rme96))) == NULL)
2365 return -ENOMEM;
2366 card->private_free = snd_rme96_card_free;
2367 rme96 = (struct rme96 *)card->private_data;
2368 rme96->card = card;
2369 rme96->pci = pci;
2370 snd_card_set_dev(card, &pci->dev);
2371 if ((err = snd_rme96_create(rme96)) < 0) {
2372 snd_card_free(card);
2373 return err;
2374 }
2375
2376 strcpy(card->driver, "Digi96");
2377 switch (rme96->pci->device) {
2378 case PCI_DEVICE_ID_RME_DIGI96:
2379 strcpy(card->shortname, "RME Digi96");
2380 break;
2381 case PCI_DEVICE_ID_RME_DIGI96_8:
2382 strcpy(card->shortname, "RME Digi96/8");
2383 break;
2384 case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
2385 strcpy(card->shortname, "RME Digi96/8 PRO");
2386 break;
2387 case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
2388 pci_read_config_byte(rme96->pci, 8, &val);
2389 if (val < 5) {
2390 strcpy(card->shortname, "RME Digi96/8 PAD");
2391 } else {
2392 strcpy(card->shortname, "RME Digi96/8 PST");
2393 }
2394 break;
2395 }
2396 sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
2397 rme96->port, rme96->irq);
2398
2399 if ((err = snd_card_register(card)) < 0) {
2400 snd_card_free(card);
2401 return err;
2402 }
2403 pci_set_drvdata(pci, card);
2404 dev++;
2405 return 0;
2406 }
2407
2408 static void __devexit snd_rme96_remove(struct pci_dev *pci)
2409 {
2410 snd_card_free(pci_get_drvdata(pci));
2411 pci_set_drvdata(pci, NULL);
2412 }
2413
2414 static struct pci_driver driver = {
2415 .name = "RME Digi96",
2416 .id_table = snd_rme96_ids,
2417 .probe = snd_rme96_probe,
2418 .remove = __devexit_p(snd_rme96_remove),
2419 };
2420
2421 static int __init alsa_card_rme96_init(void)
2422 {
2423 return pci_register_driver(&driver);
2424 }
2425
2426 static void __exit alsa_card_rme96_exit(void)
2427 {
2428 pci_unregister_driver(&driver);
2429 }
2430
2431 module_init(alsa_card_rme96_init)
2432 module_exit(alsa_card_rme96_exit)
Support for the Chinese Samsung S3C2440 based development boards