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sh: Tie sparseirq in to Kconfig.
[linux-2.6/mini2440.git] / drivers / sh / intc.c
blobd687a9b93d03bac737e02d02ce4d292fd1ef018d
1 /*
2 * Shared interrupt handling code for IPR and INTC2 types of IRQs.
3 *
4 * Copyright (C) 2007, 2008 Magnus Damm
5 *
6 * Based on intc2.c and ipr.c
7 *
8 * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
9 * Copyright (C) 2000 Kazumoto Kojima
10 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
11 * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
12 * Copyright (C) 2005, 2006 Paul Mundt
13 *
14 * This file is subject to the terms and conditions of the GNU General Public
15 * License. See the file "COPYING" in the main directory of this archive
16 * for more details.
17 */
18 #include <linux/init.h>
19 #include <linux/irq.h>
20 #include <linux/module.h>
21 #include <linux/io.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/sh_intc.h>
25 #include <linux/sysdev.h>
26 #include <linux/list.h>
27 #include <linux/topology.h>
28
29 #define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
30 ((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
31 ((addr_e) << 16) | ((addr_d << 24)))
32
33 #define _INTC_SHIFT(h) (h & 0x1f)
34 #define _INTC_WIDTH(h) ((h >> 5) & 0xf)
35 #define _INTC_FN(h) ((h >> 9) & 0xf)
36 #define _INTC_MODE(h) ((h >> 13) & 0x7)
37 #define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
38 #define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
39
40 struct intc_handle_int {
41 unsigned int irq;
42 unsigned long handle;
43 };
44
45 struct intc_desc_int {
46 struct list_head list;
47 struct sys_device sysdev;
48 pm_message_t state;
49 unsigned long *reg;
50 #ifdef CONFIG_SMP
51 unsigned long *smp;
52 #endif
53 unsigned int nr_reg;
54 struct intc_handle_int *prio;
55 unsigned int nr_prio;
56 struct intc_handle_int *sense;
57 unsigned int nr_sense;
58 struct irq_chip chip;
59 };
60
61 static LIST_HEAD(intc_list);
62
63 #ifdef CONFIG_SMP
64 #define IS_SMP(x) x.smp
65 #define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
66 #define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
67 #else
68 #define IS_SMP(x) 0
69 #define INTC_REG(d, x, c) (d->reg[(x)])
70 #define SMP_NR(d, x) 1
71 #endif
72
73 static unsigned int intc_prio_level[NR_IRQS]; /* for now */
74 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
75 static unsigned long ack_handle[NR_IRQS];
76 #endif
77
78 static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
79 {
80 struct irq_chip *chip = get_irq_chip(irq);
81 return (void *)((char *)chip - offsetof(struct intc_desc_int, chip));
82 }
83
84 static inline unsigned int set_field(unsigned int value,
85 unsigned int field_value,
86 unsigned int handle)
87 {
88 unsigned int width = _INTC_WIDTH(handle);
89 unsigned int shift = _INTC_SHIFT(handle);
90
91 value &= ~(((1 << width) - 1) << shift);
92 value |= field_value << shift;
93 return value;
94 }
95
96 static void write_8(unsigned long addr, unsigned long h, unsigned long data)
97 {
98 __raw_writeb(set_field(0, data, h), addr);
99 }
100
101 static void write_16(unsigned long addr, unsigned long h, unsigned long data)
102 {
103 __raw_writew(set_field(0, data, h), addr);
104 }
105
106 static void write_32(unsigned long addr, unsigned long h, unsigned long data)
107 {
108 __raw_writel(set_field(0, data, h), addr);
109 }
110
111 static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
112 {
113 unsigned long flags;
114 local_irq_save(flags);
115 __raw_writeb(set_field(__raw_readb(addr), data, h), addr);
116 local_irq_restore(flags);
117 }
118
119 static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
120 {
121 unsigned long flags;
122 local_irq_save(flags);
123 __raw_writew(set_field(__raw_readw(addr), data, h), addr);
124 local_irq_restore(flags);
125 }
126
127 static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
128 {
129 unsigned long flags;
130 local_irq_save(flags);
131 __raw_writel(set_field(__raw_readl(addr), data, h), addr);
132 local_irq_restore(flags);
133 }
134
135 enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
136
137 static void (*intc_reg_fns[])(unsigned long addr,
138 unsigned long h,
139 unsigned long data) = {
140 [REG_FN_WRITE_BASE + 0] = write_8,
141 [REG_FN_WRITE_BASE + 1] = write_16,
142 [REG_FN_WRITE_BASE + 3] = write_32,
143 [REG_FN_MODIFY_BASE + 0] = modify_8,
144 [REG_FN_MODIFY_BASE + 1] = modify_16,
145 [REG_FN_MODIFY_BASE + 3] = modify_32,
146 };
147
148 enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
149 MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
150 MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
151 MODE_PRIO_REG, /* Priority value written to enable interrupt */
152 MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
153 };
154
155 static void intc_mode_field(unsigned long addr,
156 unsigned long handle,
157 void (*fn)(unsigned long,
158 unsigned long,
159 unsigned long),
160 unsigned int irq)
161 {
162 fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
163 }
164
165 static void intc_mode_zero(unsigned long addr,
166 unsigned long handle,
167 void (*fn)(unsigned long,
168 unsigned long,
169 unsigned long),
170 unsigned int irq)
171 {
172 fn(addr, handle, 0);
173 }
174
175 static void intc_mode_prio(unsigned long addr,
176 unsigned long handle,
177 void (*fn)(unsigned long,
178 unsigned long,
179 unsigned long),
180 unsigned int irq)
181 {
182 fn(addr, handle, intc_prio_level[irq]);
183 }
184
185 static void (*intc_enable_fns[])(unsigned long addr,
186 unsigned long handle,
187 void (*fn)(unsigned long,
188 unsigned long,
189 unsigned long),
190 unsigned int irq) = {
191 [MODE_ENABLE_REG] = intc_mode_field,
192 [MODE_MASK_REG] = intc_mode_zero,
193 [MODE_DUAL_REG] = intc_mode_field,
194 [MODE_PRIO_REG] = intc_mode_prio,
195 [MODE_PCLR_REG] = intc_mode_prio,
196 };
197
198 static void (*intc_disable_fns[])(unsigned long addr,
199 unsigned long handle,
200 void (*fn)(unsigned long,
201 unsigned long,
202 unsigned long),
203 unsigned int irq) = {
204 [MODE_ENABLE_REG] = intc_mode_zero,
205 [MODE_MASK_REG] = intc_mode_field,
206 [MODE_DUAL_REG] = intc_mode_field,
207 [MODE_PRIO_REG] = intc_mode_zero,
208 [MODE_PCLR_REG] = intc_mode_field,
209 };
210
211 static inline void _intc_enable(unsigned int irq, unsigned long handle)
212 {
213 struct intc_desc_int *d = get_intc_desc(irq);
214 unsigned long addr;
215 unsigned int cpu;
216
217 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
218 addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
219 intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
220 [_INTC_FN(handle)], irq);
221 }
222 }
223
224 static void intc_enable(unsigned int irq)
225 {
226 _intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
227 }
228
229 static void intc_disable(unsigned int irq)
230 {
231 struct intc_desc_int *d = get_intc_desc(irq);
232 unsigned long handle = (unsigned long) get_irq_chip_data(irq);
233 unsigned long addr;
234 unsigned int cpu;
235
236 for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
237 addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
238 intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
239 [_INTC_FN(handle)], irq);
240 }
241 }
242
243 static int intc_set_wake(unsigned int irq, unsigned int on)
244 {
245 return 0; /* allow wakeup, but setup hardware in intc_suspend() */
246 }
247
248 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
249 static void intc_mask_ack(unsigned int irq)
250 {
251 struct intc_desc_int *d = get_intc_desc(irq);
252 unsigned long handle = ack_handle[irq];
253 unsigned long addr;
254
255 intc_disable(irq);
256
257 /* read register and write zero only to the assocaited bit */
258
259 if (handle) {
260 addr = INTC_REG(d, _INTC_ADDR_D(handle), 0);
261 switch (_INTC_FN(handle)) {
262 case REG_FN_MODIFY_BASE + 0: /* 8bit */
263 __raw_readb(addr);
264 __raw_writeb(0xff ^ set_field(0, 1, handle), addr);
265 break;
266 case REG_FN_MODIFY_BASE + 1: /* 16bit */
267 __raw_readw(addr);
268 __raw_writew(0xffff ^ set_field(0, 1, handle), addr);
269 break;
270 case REG_FN_MODIFY_BASE + 3: /* 32bit */
271 __raw_readl(addr);
272 __raw_writel(0xffffffff ^ set_field(0, 1, handle), addr);
273 break;
274 default:
275 BUG();
276 break;
277 }
278 }
279 }
280 #endif
281
282 static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
283 unsigned int nr_hp,
284 unsigned int irq)
285 {
286 int i;
287
288 /* this doesn't scale well, but...
289 *
290 * this function should only be used for cerain uncommon
291 * operations such as intc_set_priority() and intc_set_sense()
292 * and in those rare cases performance doesn't matter that much.
293 * keeping the memory footprint low is more important.
294 *
295 * one rather simple way to speed this up and still keep the
296 * memory footprint down is to make sure the array is sorted
297 * and then perform a bisect to lookup the irq.
298 */
299
300 for (i = 0; i < nr_hp; i++) {
301 if ((hp + i)->irq != irq)
302 continue;
303
304 return hp + i;
305 }
306
307 return NULL;
308 }
309
310 int intc_set_priority(unsigned int irq, unsigned int prio)
311 {
312 struct intc_desc_int *d = get_intc_desc(irq);
313 struct intc_handle_int *ihp;
314
315 if (!intc_prio_level[irq] || prio <= 1)
316 return -EINVAL;
317
318 ihp = intc_find_irq(d->prio, d->nr_prio, irq);
319 if (ihp) {
320 if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
321 return -EINVAL;
322
323 intc_prio_level[irq] = prio;
324
325 /*
326 * only set secondary masking method directly
327 * primary masking method is using intc_prio_level[irq]
328 * priority level will be set during next enable()
329 */
330
331 if (_INTC_FN(ihp->handle) != REG_FN_ERR)
332 _intc_enable(irq, ihp->handle);
333 }
334 return 0;
335 }
336
337 #define VALID(x) (x | 0x80)
338
339 static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
340 [IRQ_TYPE_EDGE_FALLING] = VALID(0),
341 [IRQ_TYPE_EDGE_RISING] = VALID(1),
342 [IRQ_TYPE_LEVEL_LOW] = VALID(2),
343 /* SH7706, SH7707 and SH7709 do not support high level triggered */
344 #if !defined(CONFIG_CPU_SUBTYPE_SH7706) && \
345 !defined(CONFIG_CPU_SUBTYPE_SH7707) && \
346 !defined(CONFIG_CPU_SUBTYPE_SH7709)
347 [IRQ_TYPE_LEVEL_HIGH] = VALID(3),
348 #endif
349 };
350
351 static int intc_set_sense(unsigned int irq, unsigned int type)
352 {
353 struct intc_desc_int *d = get_intc_desc(irq);
354 unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
355 struct intc_handle_int *ihp;
356 unsigned long addr;
357
358 if (!value)
359 return -EINVAL;
360
361 ihp = intc_find_irq(d->sense, d->nr_sense, irq);
362 if (ihp) {
363 addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
364 intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
365 }
366 return 0;
367 }
368
369 static unsigned int __init intc_get_reg(struct intc_desc_int *d,
370 unsigned long address)
371 {
372 unsigned int k;
373
374 for (k = 0; k < d->nr_reg; k++) {
375 if (d->reg[k] == address)
376 return k;
377 }
378
379 BUG();
380 return 0;
381 }
382
383 static intc_enum __init intc_grp_id(struct intc_desc *desc,
384 intc_enum enum_id)
385 {
386 struct intc_group *g = desc->groups;
387 unsigned int i, j;
388
389 for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
390 g = desc->groups + i;
391
392 for (j = 0; g->enum_ids[j]; j++) {
393 if (g->enum_ids[j] != enum_id)
394 continue;
395
396 return g->enum_id;
397 }
398 }
399
400 return 0;
401 }
402
403 static unsigned int __init intc_mask_data(struct intc_desc *desc,
404 struct intc_desc_int *d,
405 intc_enum enum_id, int do_grps)
406 {
407 struct intc_mask_reg *mr = desc->mask_regs;
408 unsigned int i, j, fn, mode;
409 unsigned long reg_e, reg_d;
410
411 for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
412 mr = desc->mask_regs + i;
413
414 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
415 if (mr->enum_ids[j] != enum_id)
416 continue;
417
418 if (mr->set_reg && mr->clr_reg) {
419 fn = REG_FN_WRITE_BASE;
420 mode = MODE_DUAL_REG;
421 reg_e = mr->clr_reg;
422 reg_d = mr->set_reg;
423 } else {
424 fn = REG_FN_MODIFY_BASE;
425 if (mr->set_reg) {
426 mode = MODE_ENABLE_REG;
427 reg_e = mr->set_reg;
428 reg_d = mr->set_reg;
429 } else {
430 mode = MODE_MASK_REG;
431 reg_e = mr->clr_reg;
432 reg_d = mr->clr_reg;
433 }
434 }
435
436 fn += (mr->reg_width >> 3) - 1;
437 return _INTC_MK(fn, mode,
438 intc_get_reg(d, reg_e),
439 intc_get_reg(d, reg_d),
440 1,
441 (mr->reg_width - 1) - j);
442 }
443 }
444
445 if (do_grps)
446 return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
447
448 return 0;
449 }
450
451 static unsigned int __init intc_prio_data(struct intc_desc *desc,
452 struct intc_desc_int *d,
453 intc_enum enum_id, int do_grps)
454 {
455 struct intc_prio_reg *pr = desc->prio_regs;
456 unsigned int i, j, fn, mode, bit;
457 unsigned long reg_e, reg_d;
458
459 for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
460 pr = desc->prio_regs + i;
461
462 for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
463 if (pr->enum_ids[j] != enum_id)
464 continue;
465
466 if (pr->set_reg && pr->clr_reg) {
467 fn = REG_FN_WRITE_BASE;
468 mode = MODE_PCLR_REG;
469 reg_e = pr->set_reg;
470 reg_d = pr->clr_reg;
471 } else {
472 fn = REG_FN_MODIFY_BASE;
473 mode = MODE_PRIO_REG;
474 if (!pr->set_reg)
475 BUG();
476 reg_e = pr->set_reg;
477 reg_d = pr->set_reg;
478 }
479
480 fn += (pr->reg_width >> 3) - 1;
481
482 BUG_ON((j + 1) * pr->field_width > pr->reg_width);
483
484 bit = pr->reg_width - ((j + 1) * pr->field_width);
485
486 return _INTC_MK(fn, mode,
487 intc_get_reg(d, reg_e),
488 intc_get_reg(d, reg_d),
489 pr->field_width, bit);
490 }
491 }
492
493 if (do_grps)
494 return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
495
496 return 0;
497 }
498
499 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
500 static unsigned int __init intc_ack_data(struct intc_desc *desc,
501 struct intc_desc_int *d,
502 intc_enum enum_id)
503 {
504 struct intc_mask_reg *mr = desc->ack_regs;
505 unsigned int i, j, fn, mode;
506 unsigned long reg_e, reg_d;
507
508 for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) {
509 mr = desc->ack_regs + i;
510
511 for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
512 if (mr->enum_ids[j] != enum_id)
513 continue;
514
515 fn = REG_FN_MODIFY_BASE;
516 mode = MODE_ENABLE_REG;
517 reg_e = mr->set_reg;
518 reg_d = mr->set_reg;
519
520 fn += (mr->reg_width >> 3) - 1;
521 return _INTC_MK(fn, mode,
522 intc_get_reg(d, reg_e),
523 intc_get_reg(d, reg_d),
524 1,
525 (mr->reg_width - 1) - j);
526 }
527 }
528
529 return 0;
530 }
531 #endif
532
533 static unsigned int __init intc_sense_data(struct intc_desc *desc,
534 struct intc_desc_int *d,
535 intc_enum enum_id)
536 {
537 struct intc_sense_reg *sr = desc->sense_regs;
538 unsigned int i, j, fn, bit;
539
540 for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
541 sr = desc->sense_regs + i;
542
543 for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
544 if (sr->enum_ids[j] != enum_id)
545 continue;
546
547 fn = REG_FN_MODIFY_BASE;
548 fn += (sr->reg_width >> 3) - 1;
549
550 BUG_ON((j + 1) * sr->field_width > sr->reg_width);
551
552 bit = sr->reg_width - ((j + 1) * sr->field_width);
553
554 return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
555 0, sr->field_width, bit);
556 }
557 }
558
559 return 0;
560 }
561
562 static void __init intc_register_irq(struct intc_desc *desc,
563 struct intc_desc_int *d,
564 intc_enum enum_id,
565 unsigned int irq)
566 {
567 struct intc_handle_int *hp;
568 unsigned int data[2], primary;
569
570 /* Prefer single interrupt source bitmap over other combinations:
571 * 1. bitmap, single interrupt source
572 * 2. priority, single interrupt source
573 * 3. bitmap, multiple interrupt sources (groups)
574 * 4. priority, multiple interrupt sources (groups)
575 */
576
577 data[0] = intc_mask_data(desc, d, enum_id, 0);
578 data[1] = intc_prio_data(desc, d, enum_id, 0);
579
580 primary = 0;
581 if (!data[0] && data[1])
582 primary = 1;
583
584 if (!data[0] && !data[1])
585 pr_warning("intc: missing unique irq mask for "
586 "irq %d (vect 0x%04x)\n", irq, irq2evt(irq));
587
588 data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
589 data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
590
591 if (!data[primary])
592 primary ^= 1;
593
594 BUG_ON(!data[primary]); /* must have primary masking method */
595
596 disable_irq_nosync(irq);
597 set_irq_chip_and_handler_name(irq, &d->chip,
598 handle_level_irq, "level");
599 set_irq_chip_data(irq, (void *)data[primary]);
600
601 /* set priority level
602 * - this needs to be at least 2 for 5-bit priorities on 7780
603 */
604 intc_prio_level[irq] = 2;
605
606 /* enable secondary masking method if present */
607 if (data[!primary])
608 _intc_enable(irq, data[!primary]);
609
610 /* add irq to d->prio list if priority is available */
611 if (data[1]) {
612 hp = d->prio + d->nr_prio;
613 hp->irq = irq;
614 hp->handle = data[1];
615
616 if (primary) {
617 /*
618 * only secondary priority should access registers, so
619 * set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
620 */
621
622 hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
623 hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
624 }
625 d->nr_prio++;
626 }
627
628 /* add irq to d->sense list if sense is available */
629 data[0] = intc_sense_data(desc, d, enum_id);
630 if (data[0]) {
631 (d->sense + d->nr_sense)->irq = irq;
632 (d->sense + d->nr_sense)->handle = data[0];
633 d->nr_sense++;
634 }
635
636 /* irq should be disabled by default */
637 d->chip.mask(irq);
638
639 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
640 if (desc->ack_regs)
641 ack_handle[irq] = intc_ack_data(desc, d, enum_id);
642 #endif
643 }
644
645 static unsigned int __init save_reg(struct intc_desc_int *d,
646 unsigned int cnt,
647 unsigned long value,
648 unsigned int smp)
649 {
650 if (value) {
651 d->reg[cnt] = value;
652 #ifdef CONFIG_SMP
653 d->smp[cnt] = smp;
654 #endif
655 return 1;
656 }
657
658 return 0;
659 }
660
661 static unsigned char *intc_evt2irq_table;
662
663 unsigned int intc_evt2irq(unsigned int vector)
664 {
665 unsigned int irq = evt2irq(vector);
666
667 if (intc_evt2irq_table && intc_evt2irq_table[irq])
668 irq = intc_evt2irq_table[irq];
669
670 return irq;
671 }
672
673 void __init register_intc_controller(struct intc_desc *desc)
674 {
675 unsigned int i, k, smp;
676 struct intc_desc_int *d;
677
678 d = alloc_bootmem(sizeof(*d));
679
680 INIT_LIST_HEAD(&d->list);
681 list_add(&d->list, &intc_list);
682
683 d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
684 d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
685 d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
686
687 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
688 d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0;
689 #endif
690 d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg));
691 #ifdef CONFIG_SMP
692 d->smp = alloc_bootmem(d->nr_reg * sizeof(*d->smp));
693 #endif
694 k = 0;
695
696 if (desc->mask_regs) {
697 for (i = 0; i < desc->nr_mask_regs; i++) {
698 smp = IS_SMP(desc->mask_regs[i]);
699 k += save_reg(d, k, desc->mask_regs[i].set_reg, smp);
700 k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp);
701 }
702 }
703
704 if (desc->prio_regs) {
705 d->prio = alloc_bootmem(desc->nr_vectors * sizeof(*d->prio));
706
707 for (i = 0; i < desc->nr_prio_regs; i++) {
708 smp = IS_SMP(desc->prio_regs[i]);
709 k += save_reg(d, k, desc->prio_regs[i].set_reg, smp);
710 k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp);
711 }
712 }
713
714 if (desc->sense_regs) {
715 d->sense = alloc_bootmem(desc->nr_vectors * sizeof(*d->sense));
716
717 for (i = 0; i < desc->nr_sense_regs; i++) {
718 k += save_reg(d, k, desc->sense_regs[i].reg, 0);
719 }
720 }
721
722 d->chip.name = desc->name;
723 d->chip.mask = intc_disable;
724 d->chip.unmask = intc_enable;
725 d->chip.mask_ack = intc_disable;
726 d->chip.enable = intc_enable;
727 d->chip.disable = intc_disable;
728 d->chip.shutdown = intc_disable;
729 d->chip.set_type = intc_set_sense;
730 d->chip.set_wake = intc_set_wake;
731
732 #if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4A)
733 if (desc->ack_regs) {
734 for (i = 0; i < desc->nr_ack_regs; i++)
735 k += save_reg(d, k, desc->ack_regs[i].set_reg, 0);
736
737 d->chip.mask_ack = intc_mask_ack;
738 }
739 #endif
740
741 BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
742
743 /* keep the first vector only if same enum is used multiple times */
744 for (i = 0; i < desc->nr_vectors; i++) {
745 struct intc_vect *vect = desc->vectors + i;
746 int first_irq = evt2irq(vect->vect);
747
748 if (!vect->enum_id)
749 continue;
750
751 for (k = i + 1; k < desc->nr_vectors; k++) {
752 struct intc_vect *vect2 = desc->vectors + k;
753
754 if (vect->enum_id != vect2->enum_id)
755 continue;
756
757 vect2->enum_id = 0;
758
759 if (!intc_evt2irq_table)
760 intc_evt2irq_table = alloc_bootmem(NR_IRQS);
761
762 if (!intc_evt2irq_table) {
763 pr_warning("intc: cannot allocate evt2irq!\n");
764 continue;
765 }
766
767 intc_evt2irq_table[evt2irq(vect2->vect)] = first_irq;
768 }
769 }
770
771 /* register the vectors one by one */
772 for (i = 0; i < desc->nr_vectors; i++) {
773 struct intc_vect *vect = desc->vectors + i;
774 unsigned int irq = evt2irq(vect->vect);
775 struct irq_desc *irq_desc;
776
777 if (!vect->enum_id)
778 continue;
779
780 irq_desc = irq_to_desc_alloc_node(irq, numa_node_id());
781 if (unlikely(!irq_desc)) {
782 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
783 continue;
784 }
785
786 intc_register_irq(desc, d, vect->enum_id, irq);
787 }
788 }
789
790 static int intc_suspend(struct sys_device *dev, pm_message_t state)
791 {
792 struct intc_desc_int *d;
793 struct irq_desc *desc;
794 int irq;
795
796 /* get intc controller associated with this sysdev */
797 d = container_of(dev, struct intc_desc_int, sysdev);
798
799 switch (state.event) {
800 case PM_EVENT_ON:
801 if (d->state.event != PM_EVENT_FREEZE)
802 break;
803 for_each_irq_desc(irq, desc) {
804 if (desc->chip != &d->chip)
805 continue;
806 if (desc->status & IRQ_DISABLED)
807 intc_disable(irq);
808 else
809 intc_enable(irq);
810 }
811 break;
812 case PM_EVENT_FREEZE:
813 /* nothing has to be done */
814 break;
815 case PM_EVENT_SUSPEND:
816 /* enable wakeup irqs belonging to this intc controller */
817 for_each_irq_desc(irq, desc) {
818 if ((desc->status & IRQ_WAKEUP) && (desc->chip == &d->chip))
819 intc_enable(irq);
820 }
821 break;
822 }
823 d->state = state;
824
825 return 0;
826 }
827
828 static int intc_resume(struct sys_device *dev)
829 {
830 return intc_suspend(dev, PMSG_ON);
831 }
832
833 static struct sysdev_class intc_sysdev_class = {
834 .name = "intc",
835 .suspend = intc_suspend,
836 .resume = intc_resume,
837 };
838
839 /* register this intc as sysdev to allow suspend/resume */
840 static int __init register_intc_sysdevs(void)
841 {
842 struct intc_desc_int *d;
843 int error;
844 int id = 0;
845
846 error = sysdev_class_register(&intc_sysdev_class);
847 if (!error) {
848 list_for_each_entry(d, &intc_list, list) {
849 d->sysdev.id = id;
850 d->sysdev.cls = &intc_sysdev_class;
851 error = sysdev_register(&d->sysdev);
852 if (error)
853 break;
854 id++;
855 }
856 }
857
858 if (error)
859 pr_warning("intc: sysdev registration error\n");
860
861 return error;
862 }
863
864 device_initcall(register_intc_sysdevs);
Support for the Chinese Samsung S3C2440 based development boards