arch/arm/mach-s3c2410/mach-bast.c

   1 /* linux/arch/arm/mach-s3c2410/mach-bast.c
   2  *
   3  * Copyright (c) 2003-2005 Simtec Electronics
   4  *   Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * http://www.simtec.co.uk/products/EB2410ITX/
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Modifications:
  13  *     14-Sep-2004 BJD  USB power control
  14  *     20-Aug-2004 BJD  Added s3c2410_board struct
  15  *     18-Aug-2004 BJD  Added platform devices from default set
  16  *     16-May-2003 BJD  Created initial version
  17  *     16-Aug-2003 BJD  Fixed header files and copyright, added URL
  18  *     05-Sep-2003 BJD  Moved to v2.6 kernel
  19  *     06-Jan-2003 BJD  Updates for <arch/map.h>
  20  *     18-Jan-2003 BJD  Added serial port configuration
  21  *     05-Oct-2004 BJD  Power management code
  22  *     04-Nov-2004 BJD  Updated serial port clocks
  23  *     04-Jan-2005 BJD  New uart init call
  24  *     10-Jan-2005 BJD  Removed include of s3c2410.h
  25  *     14-Jan-2005 BJD  Add support for muitlple NAND devices
  26  *     03-Mar-2005 BJD  Ensured that bast-cpld.h is included
  27  *     10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
  28  *     14-Mar-2005 BJD  Updated for __iomem changes
  29  *     22-Jun-2005 BJD  Added DM9000 platform information
  30  *     28-Jun-2005 BJD  Moved pm functionality out to common code
  31  *     17-Jul-2005 BJD  Changed to platform device for SuperIO 16550s
  32  *     25-Jul-2005 BJD  Removed ASIX static mappings
  33  *     27-Jul-2005 BJD  Ensure maximum frequency of i2c bus
  34  *     20-Sep-2005 BJD  Added static to non-exported items
  35  *     26-Oct-2005 BJD  Added FB platform data
  36 */
  37
  38 #include <linux/kernel.h>
  39 #include <linux/types.h>
  40 #include <linux/interrupt.h>
  41 #include <linux/list.h>
  42 #include <linux/timer.h>
  43 #include <linux/init.h>
  44 #include <linux/platform_device.h>
  45 #include <linux/dm9000.h>
  46
  47 #include <asm/mach/arch.h>
  48 #include <asm/mach/map.h>
  49 #include <asm/mach/irq.h>
  50
  51 #include <asm/arch/bast-map.h>
  52 #include <asm/arch/bast-irq.h>
  53 #include <asm/arch/bast-cpld.h>
  54
  55 #include <asm/hardware.h>
  56 #include <asm/io.h>
  57 #include <asm/irq.h>
  58 #include <asm/mach-types.h>
  59
  60 //#include <asm/debug-ll.h>
  61 #include <asm/arch/regs-serial.h>
  62 #include <asm/arch/regs-gpio.h>
  63 #include <asm/arch/regs-mem.h>
  64 #include <asm/arch/regs-lcd.h>
  65
  66 #include <asm/arch/nand.h>
  67 #include <asm/arch/iic.h>
  68 #include <asm/arch/fb.h>
  69
  70 #include <linux/mtd/mtd.h>
  71 #include <linux/mtd/nand.h>
  72 #include <linux/mtd/nand_ecc.h>
  73 #include <linux/mtd/partitions.h>
  74
  75 #include <linux/serial_8250.h>
  76
  77 #include "clock.h"
  78 #include "devs.h"
  79 #include "cpu.h"
  80 #include "usb-simtec.h"
  81
  82 #define COPYRIGHT ", (c) 2004-2005 Simtec Electronics"
  83
  84 /* macros for virtual address mods for the io space entries */
  85 #define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
  86 #define VA_C4(item) ((unsigned long)(item) + BAST_VAM_CS4)
  87 #define VA_C3(item) ((unsigned long)(item) + BAST_VAM_CS3)
  88 #define VA_C2(item) ((unsigned long)(item) + BAST_VAM_CS2)
  89
  90 /* macros to modify the physical addresses for io space */
  91
  92 #define PA_CS2(item) (__phys_to_pfn((item) + S3C2410_CS2))
  93 #define PA_CS3(item) (__phys_to_pfn((item) + S3C2410_CS3))
  94 #define PA_CS4(item) (__phys_to_pfn((item) + S3C2410_CS4))
  95 #define PA_CS5(item) (__phys_to_pfn((item) + S3C2410_CS5))
  96
  97 static struct map_desc bast_iodesc[] __initdata = {
  98   /* ISA IO areas */
  99   {
 100           .virtual      = (u32)S3C24XX_VA_ISA_BYTE,
 101           .pfn          = PA_CS2(BAST_PA_ISAIO),
 102           .length       = SZ_16M,
 103           .type         = MT_DEVICE,
 104   }, {
 105           .virtual      = (u32)S3C24XX_VA_ISA_WORD,
 106           .pfn          = PA_CS3(BAST_PA_ISAIO),
 107           .length       = SZ_16M,
 108           .type         = MT_DEVICE,
 109   },
 110   /* bast CPLD control registers, and external interrupt controls */
 111   {
 112           .virtual      = (u32)BAST_VA_CTRL1,
 113           .pfn          = __phys_to_pfn(BAST_PA_CTRL1),
 114           .length       = SZ_1M,
 115           .type         = MT_DEVICE,
 116   }, {
 117           .virtual      = (u32)BAST_VA_CTRL2,
 118           .pfn          = __phys_to_pfn(BAST_PA_CTRL2),
 119           .length       = SZ_1M,
 120           .type         = MT_DEVICE,
 121   }, {
 122           .virtual      = (u32)BAST_VA_CTRL3,
 123           .pfn          = __phys_to_pfn(BAST_PA_CTRL3),
 124           .length       = SZ_1M,
 125           .type         = MT_DEVICE,
 126   }, {
 127           .virtual      = (u32)BAST_VA_CTRL4,
 128           .pfn          = __phys_to_pfn(BAST_PA_CTRL4),
 129           .length       = SZ_1M,
 130           .type         = MT_DEVICE,
 131   },
 132   /* PC104 IRQ mux */
 133   {
 134           .virtual      = (u32)BAST_VA_PC104_IRQREQ,
 135           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQREQ),
 136           .length       = SZ_1M,
 137           .type         = MT_DEVICE,
 138   }, {
 139           .virtual      = (u32)BAST_VA_PC104_IRQRAW,
 140           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQRAW),
 141           .length       = SZ_1M,
 142           .type         = MT_DEVICE,
 143   }, {
 144           .virtual      = (u32)BAST_VA_PC104_IRQMASK,
 145           .pfn          = __phys_to_pfn(BAST_PA_PC104_IRQMASK),
 146           .length       = SZ_1M,
 147           .type         = MT_DEVICE,
 148   },
 149
 150   /* peripheral space... one for each of fast/slow/byte/16bit */
 151   /* note, ide is only decoded in word space, even though some registers
 152    * are only 8bit */
 153
 154   /* slow, byte */
 155   { VA_C2(BAST_VA_ISAIO),   PA_CS2(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 156   { VA_C2(BAST_VA_ISAMEM),  PA_CS2(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 157   { VA_C2(BAST_VA_SUPERIO), PA_CS2(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 158   { VA_C2(BAST_VA_IDEPRI),  PA_CS3(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
 159   { VA_C2(BAST_VA_IDESEC),  PA_CS3(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
 160   { VA_C2(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
 161   { VA_C2(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
 162
 163   /* slow, word */
 164   { VA_C3(BAST_VA_ISAIO),   PA_CS3(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 165   { VA_C3(BAST_VA_ISAMEM),  PA_CS3(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 166   { VA_C3(BAST_VA_SUPERIO), PA_CS3(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 167   { VA_C3(BAST_VA_IDEPRI),  PA_CS3(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
 168   { VA_C3(BAST_VA_IDESEC),  PA_CS3(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
 169   { VA_C3(BAST_VA_IDEPRIAUX), PA_CS3(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
 170   { VA_C3(BAST_VA_IDESECAUX), PA_CS3(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
 171
 172   /* fast, byte */
 173   { VA_C4(BAST_VA_ISAIO),   PA_CS4(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 174   { VA_C4(BAST_VA_ISAMEM),  PA_CS4(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 175   { VA_C4(BAST_VA_SUPERIO), PA_CS4(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 176   { VA_C4(BAST_VA_IDEPRI),  PA_CS5(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
 177   { VA_C4(BAST_VA_IDESEC),  PA_CS5(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
 178   { VA_C4(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
 179   { VA_C4(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
 180
 181   /* fast, word */
 182   { VA_C5(BAST_VA_ISAIO),   PA_CS5(BAST_PA_ISAIO),    SZ_16M, MT_DEVICE },
 183   { VA_C5(BAST_VA_ISAMEM),  PA_CS5(BAST_PA_ISAMEM),   SZ_16M, MT_DEVICE },
 184   { VA_C5(BAST_VA_SUPERIO), PA_CS5(BAST_PA_SUPERIO),  SZ_1M,  MT_DEVICE },
 185   { VA_C5(BAST_VA_IDEPRI),  PA_CS5(BAST_PA_IDEPRI),   SZ_1M,  MT_DEVICE },
 186   { VA_C5(BAST_VA_IDESEC),  PA_CS5(BAST_PA_IDESEC),   SZ_1M,  MT_DEVICE },
 187   { VA_C5(BAST_VA_IDEPRIAUX), PA_CS5(BAST_PA_IDEPRIAUX), SZ_1M, MT_DEVICE },
 188   { VA_C5(BAST_VA_IDESECAUX), PA_CS5(BAST_PA_IDESECAUX), SZ_1M, MT_DEVICE },
 189 };
 190
 191 #define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
 192 #define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
 193 #define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
 194
 195 static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
 196         [0] = {
 197                 .name           = "uclk",
 198                 .divisor        = 1,
 199                 .min_baud       = 0,
 200                 .max_baud       = 0,
 201         },
 202         [1] = {
 203                 .name           = "pclk",
 204                 .divisor        = 1,
 205                 .min_baud       = 0,
 206                 .max_baud       = 0,
 207         }
 208 };
 209
 210
 211 static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
 212         [0] = {
 213                 .hwport      = 0,
 214                 .flags       = 0,
 215                 .ucon        = UCON,
 216                 .ulcon       = ULCON,
 217                 .ufcon       = UFCON,
 218                 .clocks      = bast_serial_clocks,
 219                 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
 220         },
 221         [1] = {
 222                 .hwport      = 1,
 223                 .flags       = 0,
 224                 .ucon        = UCON,
 225                 .ulcon       = ULCON,
 226                 .ufcon       = UFCON,
 227                 .clocks      = bast_serial_clocks,
 228                 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
 229         },
 230         /* port 2 is not actually used */
 231         [2] = {
 232                 .hwport      = 2,
 233                 .flags       = 0,
 234                 .ucon        = UCON,
 235                 .ulcon       = ULCON,
 236                 .ufcon       = UFCON,
 237                 .clocks      = bast_serial_clocks,
 238                 .clocks_size = ARRAY_SIZE(bast_serial_clocks),
 239         }
 240 };
 241
 242 /* NOR Flash on BAST board */
 243
 244 static struct resource bast_nor_resource[] = {
 245         [0] = {
 246                 .start = S3C2410_CS1 + 0x4000000,
 247                 .end   = S3C2410_CS1 + 0x4000000 + (32*1024*1024) - 1,
 248                 .flags = IORESOURCE_MEM,
 249         }
 250 };
 251
 252 static struct platform_device bast_device_nor = {
 253         .name           = "bast-nor",
 254         .id             = -1,
 255         .num_resources  = ARRAY_SIZE(bast_nor_resource),
 256         .resource       = bast_nor_resource,
 257 };
 258
 259 /* NAND Flash on BAST board */
 260
 261
 262 static int smartmedia_map[] = { 0 };
 263 static int chip0_map[] = { 1 };
 264 static int chip1_map[] = { 2 };
 265 static int chip2_map[] = { 3 };
 266
 267 static struct mtd_partition bast_default_nand_part[] = {
 268         [0] = {
 269                 .name   = "Boot Agent",
 270                 .size   = SZ_16K,
 271                 .offset = 0,
 272         },
 273         [1] = {
 274                 .name   = "/boot",
 275                 .size   = SZ_4M - SZ_16K,
 276                 .offset = SZ_16K,
 277         },
 278         [2] = {
 279                 .name   = "user",
 280                 .offset = SZ_4M,
 281                 .size   = MTDPART_SIZ_FULL,
 282         }
 283 };
 284
 285 /* the bast has 4 selectable slots for nand-flash, the three
 286  * on-board chip areas, as well as the external SmartMedia
 287  * slot.
 288  *
 289  * Note, there is no current hot-plug support for the SmartMedia
 290  * socket.
 291 */
 292
 293 static struct s3c2410_nand_set bast_nand_sets[] = {
 294         [0] = {
 295                 .name           = "SmartMedia",
 296                 .nr_chips       = 1,
 297                 .nr_map         = smartmedia_map,
 298                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 299                 .partitions     = bast_default_nand_part,
 300         },
 301         [1] = {
 302                 .name           = "chip0",
 303                 .nr_chips       = 1,
 304                 .nr_map         = chip0_map,
 305                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 306                 .partitions     = bast_default_nand_part,
 307         },
 308         [2] = {
 309                 .name           = "chip1",
 310                 .nr_chips       = 1,
 311                 .nr_map         = chip1_map,
 312                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 313                 .partitions     = bast_default_nand_part,
 314         },
 315         [3] = {
 316                 .name           = "chip2",
 317                 .nr_chips       = 1,
 318                 .nr_map         = chip2_map,
 319                 .nr_partitions  = ARRAY_SIZE(bast_default_nand_part),
 320                 .partitions     = bast_default_nand_part,
 321         }
 322 };
 323
 324 static void bast_nand_select(struct s3c2410_nand_set *set, int slot)
 325 {
 326         unsigned int tmp;
 327
 328         slot = set->nr_map[slot] & 3;
 329
 330         pr_debug("bast_nand: selecting slot %d (set %p,%p)\n",
 331                  slot, set, set->nr_map);
 332
 333         tmp = __raw_readb(BAST_VA_CTRL2);
 334         tmp &= BAST_CPLD_CTLR2_IDERST;
 335         tmp |= slot;
 336         tmp |= BAST_CPLD_CTRL2_WNAND;
 337
 338         pr_debug("bast_nand: ctrl2 now %02x\n", tmp);
 339
 340         __raw_writeb(tmp, BAST_VA_CTRL2);
 341 }
 342
 343 static struct s3c2410_platform_nand bast_nand_info = {
 344         .tacls          = 30,
 345         .twrph0         = 60,
 346         .twrph1         = 60,
 347         .nr_sets        = ARRAY_SIZE(bast_nand_sets),
 348         .sets           = bast_nand_sets,
 349         .select_chip    = bast_nand_select,
 350 };
 351
 352 /* DM9000 */
 353
 354 static struct resource bast_dm9k_resource[] = {
 355         [0] = {
 356                 .start = S3C2410_CS5 + BAST_PA_DM9000,
 357                 .end   = S3C2410_CS5 + BAST_PA_DM9000 + 3,
 358                 .flags = IORESOURCE_MEM,
 359         },
 360         [1] = {
 361                 .start = S3C2410_CS5 + BAST_PA_DM9000 + 0x40,
 362                 .end   = S3C2410_CS5 + BAST_PA_DM9000 + 0x40 + 0x3f,
 363                 .flags = IORESOURCE_MEM,
 364         },
 365         [2] = {
 366                 .start = IRQ_DM9000,
 367                 .end   = IRQ_DM9000,
 368                 .flags = IORESOURCE_IRQ,
 369         }
 370
 371 };
 372
 373 /* for the moment we limit ourselves to 16bit IO until some
 374  * better IO routines can be written and tested
 375 */
 376
 377 static struct dm9000_plat_data bast_dm9k_platdata = {
 378         .flags          = DM9000_PLATF_16BITONLY,
 379 };
 380
 381 static struct platform_device bast_device_dm9k = {
 382         .name           = "dm9000",
 383         .id             = 0,
 384         .num_resources  = ARRAY_SIZE(bast_dm9k_resource),
 385         .resource       = bast_dm9k_resource,
 386         .dev            = {
 387                 .platform_data = &bast_dm9k_platdata,
 388         }
 389 };
 390
 391 /* serial devices */
 392
 393 #define SERIAL_BASE  (S3C2410_CS2 + BAST_PA_SUPERIO)
 394 #define SERIAL_FLAGS (UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_SHARE_IRQ)
 395 #define SERIAL_CLK   (1843200)
 396
 397 static struct plat_serial8250_port bast_sio_data[] = {
 398         [0] = {
 399                 .mapbase        = SERIAL_BASE + 0x2f8,
 400                 .irq            = IRQ_PCSERIAL1,
 401                 .flags          = SERIAL_FLAGS,
 402                 .iotype         = UPIO_MEM,
 403                 .regshift       = 0,
 404                 .uartclk        = SERIAL_CLK,
 405         },
 406         [1] = {
 407                 .mapbase        = SERIAL_BASE + 0x3f8,
 408                 .irq            = IRQ_PCSERIAL2,
 409                 .flags          = SERIAL_FLAGS,
 410                 .iotype         = UPIO_MEM,
 411                 .regshift       = 0,
 412                 .uartclk        = SERIAL_CLK,
 413         },
 414         { }
 415 };
 416
 417 static struct platform_device bast_sio = {
 418         .name                   = "serial8250",
 419         .id                     = PLAT8250_DEV_PLATFORM,
 420         .dev                    = {
 421                 .platform_data  = &bast_sio_data,
 422         },
 423 };
 424
 425 /* we have devices on the bus which cannot work much over the
 426  * standard 100KHz i2c bus frequency
 427 */
 428
 429 static struct s3c2410_platform_i2c bast_i2c_info = {
 430         .flags          = 0,
 431         .slave_addr     = 0x10,
 432         .bus_freq       = 100*1000,
 433         .max_freq       = 130*1000,
 434 };
 435
 436
 437 static struct s3c2410fb_mach_info __initdata bast_lcd_info = {
 438         .width          = 640,
 439         .height         = 480,
 440
 441         .xres           = {
 442                 .min            = 320,
 443                 .max            = 1024,
 444                 .defval         = 640,
 445         },
 446
 447         .yres           = {
 448                 .min            = 240,
 449                 .max            = 600,
 450                 .defval         = 480,
 451         },
 452
 453         .bpp            = {
 454                 .min            = 4,
 455                 .max            = 16,
 456                 .defval         = 8,
 457         },
 458
 459         .regs           = {
 460                 .lcdcon1        = 0x00000176,
 461                 .lcdcon2        = 0x1d77c7c2,
 462                 .lcdcon3        = 0x013a7f13,
 463                 .lcdcon4        = 0x00000057,
 464                 .lcdcon5        = 0x00014b02,
 465         }
 466 };
 467
 468 /* Standard BAST devices */
 469
 470 static struct platform_device *bast_devices[] __initdata = {
 471         &s3c_device_usb,
 472         &s3c_device_lcd,
 473         &s3c_device_wdt,
 474         &s3c_device_i2c,
 475         &s3c_device_iis,
 476         &s3c_device_rtc,
 477         &s3c_device_nand,
 478         &bast_device_nor,
 479         &bast_device_dm9k,
 480         &bast_sio,
 481 };
 482
 483 static struct clk *bast_clocks[] = {
 484         &s3c24xx_dclk0,
 485         &s3c24xx_dclk1,
 486         &s3c24xx_clkout0,
 487         &s3c24xx_clkout1,
 488         &s3c24xx_uclk,
 489 };
 490
 491 static struct s3c24xx_board bast_board __initdata = {
 492         .devices       = bast_devices,
 493         .devices_count = ARRAY_SIZE(bast_devices),
 494         .clocks        = bast_clocks,
 495         .clocks_count  = ARRAY_SIZE(bast_clocks),
 496 };
 497
 498 static void __init bast_map_io(void)
 499 {
 500         /* initialise the clocks */
 501
 502         s3c24xx_dclk0.parent = NULL;
 503         s3c24xx_dclk0.rate   = 12*1000*1000;
 504
 505         s3c24xx_dclk1.parent = NULL;
 506         s3c24xx_dclk1.rate   = 24*1000*1000;
 507
 508         s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
 509         s3c24xx_clkout1.parent  = &s3c24xx_dclk1;
 510
 511         s3c24xx_uclk.parent  = &s3c24xx_clkout1;
 512
 513         s3c_device_nand.dev.platform_data = &bast_nand_info;
 514         s3c_device_i2c.dev.platform_data = &bast_i2c_info;
 515
 516         s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
 517         s3c24xx_init_clocks(0);
 518         s3c24xx_init_uarts(bast_uartcfgs, ARRAY_SIZE(bast_uartcfgs));
 519         s3c24xx_set_board(&bast_board);
 520         usb_simtec_init();
 521 }
 522
 523 static void __init bast_init(void)
 524 {
 525         s3c24xx_fb_set_platdata(&bast_lcd_info);
 526 }
 527
 528 MACHINE_START(BAST, "Simtec-BAST")
 529         /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
 530         .phys_io        = S3C2410_PA_UART,
 531         .io_pg_offst    = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
 532         .boot_params    = S3C2410_SDRAM_PA + 0x100,
 533         .map_io         = bast_map_io,
 534         .init_irq       = s3c24xx_init_irq,
 535         .init_machine   = bast_init,
 536         .timer          = &s3c24xx_timer,
 537 MACHINE_END