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Merge branch 'upstream-fixes' into upstream
[linux-2.6/mini2440.git] / arch / arm / mach-s3c2410 / irq.c
blob6822dc7f779953f072ab8873fd770bcfcc5e2da3
1 /* linux/arch/arm/mach-s3c2410/irq.c
2 *
3 * Copyright (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 * Changelog:
21 *
22 * 22-Jul-2004 Ben Dooks <ben@simtec.co.uk>
23 * Fixed compile warnings
24 *
25 * 22-Jul-2004 Roc Wu <cooloney@yahoo.com.cn>
26 * Fixed s3c_extirq_type
27 *
28 * 21-Jul-2004 Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
29 * Addition of ADC/TC demux
30 *
31 * 04-Oct-2004 Klaus Fetscher <k.fetscher@fetron.de>
32 * Fix for set_irq_type() on low EINT numbers
33 *
34 * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk>
35 * Tidy up KF's patch and sort out new release
36 *
37 * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk>
38 * Add support for power management controls
39 *
40 * 04-Nov-2004 Ben Dooks
41 * Fix standard IRQ wake for EINT0..4 and RTC
42 *
43 * 22-Feb-2005 Ben Dooks
44 * Fixed edge-triggering on ADC IRQ
45 *
46 * 28-Jun-2005 Ben Dooks
47 * Mark IRQ_LCD valid
48 *
49 * 25-Jul-2005 Ben Dooks
50 * Split the S3C2440 IRQ code to seperate file
51 */
52
53 #include <linux/init.h>
54 #include <linux/module.h>
55 #include <linux/interrupt.h>
56 #include <linux/ioport.h>
57 #include <linux/ptrace.h>
58 #include <linux/sysdev.h>
59
60 #include <asm/hardware.h>
61 #include <asm/irq.h>
62 #include <asm/io.h>
63
64 #include <asm/mach/irq.h>
65
66 #include <asm/arch/regs-irq.h>
67 #include <asm/arch/regs-gpio.h>
68
69 #include "cpu.h"
70 #include "pm.h"
71 #include "irq.h"
72
73 /* wakeup irq control */
74
75 #ifdef CONFIG_PM
76
77 /* state for IRQs over sleep */
78
79 /* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources
80 *
81 * set bit to 1 in allow bitfield to enable the wakeup settings on it
82 */
83
84 unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL;
85 unsigned long s3c_irqwake_intmask = 0xffffffffL;
86 unsigned long s3c_irqwake_eintallow = 0x0000fff0L;
87 unsigned long s3c_irqwake_eintmask = 0xffffffffL;
88
89 static int
90 s3c_irq_wake(unsigned int irqno, unsigned int state)
91 {
92 unsigned long irqbit = 1 << (irqno - IRQ_EINT0);
93
94 if (!(s3c_irqwake_intallow & irqbit))
95 return -ENOENT;
96
97 printk(KERN_INFO "wake %s for irq %d\n",
98 state ? "enabled" : "disabled", irqno);
99
100 if (!state)
101 s3c_irqwake_intmask |= irqbit;
102 else
103 s3c_irqwake_intmask &= ~irqbit;
104
105 return 0;
106 }
107
108 static int
109 s3c_irqext_wake(unsigned int irqno, unsigned int state)
110 {
111 unsigned long bit = 1L << (irqno - EXTINT_OFF);
112
113 if (!(s3c_irqwake_eintallow & bit))
114 return -ENOENT;
115
116 printk(KERN_INFO "wake %s for irq %d\n",
117 state ? "enabled" : "disabled", irqno);
118
119 if (!state)
120 s3c_irqwake_eintmask |= bit;
121 else
122 s3c_irqwake_eintmask &= ~bit;
123
124 return 0;
125 }
126
127 #else
128 #define s3c_irqext_wake NULL
129 #define s3c_irq_wake NULL
130 #endif
131
132
133 static void
134 s3c_irq_mask(unsigned int irqno)
135 {
136 unsigned long mask;
137
138 irqno -= IRQ_EINT0;
139
140 mask = __raw_readl(S3C2410_INTMSK);
141 mask |= 1UL << irqno;
142 __raw_writel(mask, S3C2410_INTMSK);
143 }
144
145 static inline void
146 s3c_irq_ack(unsigned int irqno)
147 {
148 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
149
150 __raw_writel(bitval, S3C2410_SRCPND);
151 __raw_writel(bitval, S3C2410_INTPND);
152 }
153
154 static inline void
155 s3c_irq_maskack(unsigned int irqno)
156 {
157 unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
158 unsigned long mask;
159
160 mask = __raw_readl(S3C2410_INTMSK);
161 __raw_writel(mask|bitval, S3C2410_INTMSK);
162
163 __raw_writel(bitval, S3C2410_SRCPND);
164 __raw_writel(bitval, S3C2410_INTPND);
165 }
166
167
168 static void
169 s3c_irq_unmask(unsigned int irqno)
170 {
171 unsigned long mask;
172
173 if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
174 irqdbf2("s3c_irq_unmask %d\n", irqno);
175
176 irqno -= IRQ_EINT0;
177
178 mask = __raw_readl(S3C2410_INTMSK);
179 mask &= ~(1UL << irqno);
180 __raw_writel(mask, S3C2410_INTMSK);
181 }
182
183 struct irqchip s3c_irq_level_chip = {
184 .ack = s3c_irq_maskack,
185 .mask = s3c_irq_mask,
186 .unmask = s3c_irq_unmask,
187 .set_wake = s3c_irq_wake
188 };
189
190 static struct irqchip s3c_irq_chip = {
191 .ack = s3c_irq_ack,
192 .mask = s3c_irq_mask,
193 .unmask = s3c_irq_unmask,
194 .set_wake = s3c_irq_wake
195 };
196
197 static void
198 s3c_irqext_mask(unsigned int irqno)
199 {
200 unsigned long mask;
201
202 irqno -= EXTINT_OFF;
203
204 mask = __raw_readl(S3C24XX_EINTMASK);
205 mask |= ( 1UL << irqno);
206 __raw_writel(mask, S3C24XX_EINTMASK);
207
208 if (irqno <= (IRQ_EINT7 - EXTINT_OFF)) {
209 /* check to see if all need masking */
210
211 if ((mask & (0xf << 4)) == (0xf << 4)) {
212 /* all masked, mask the parent */
213 s3c_irq_mask(IRQ_EINT4t7);
214 }
215 } else {
216 /* todo: the same check as above for the rest of the irq regs...*/
217
218 }
219 }
220
221 static void
222 s3c_irqext_ack(unsigned int irqno)
223 {
224 unsigned long req;
225 unsigned long bit;
226 unsigned long mask;
227
228 bit = 1UL << (irqno - EXTINT_OFF);
229
230
231 mask = __raw_readl(S3C24XX_EINTMASK);
232
233 __raw_writel(bit, S3C24XX_EINTPEND);
234
235 req = __raw_readl(S3C24XX_EINTPEND);
236 req &= ~mask;
237
238 /* not sure if we should be acking the parent irq... */
239
240 if (irqno <= IRQ_EINT7 ) {
241 if ((req & 0xf0) == 0)
242 s3c_irq_ack(IRQ_EINT4t7);
243 } else {
244 if ((req >> 8) == 0)
245 s3c_irq_ack(IRQ_EINT8t23);
246 }
247 }
248
249 static void
250 s3c_irqext_unmask(unsigned int irqno)
251 {
252 unsigned long mask;
253
254 irqno -= EXTINT_OFF;
255
256 mask = __raw_readl(S3C24XX_EINTMASK);
257 mask &= ~( 1UL << irqno);
258 __raw_writel(mask, S3C24XX_EINTMASK);
259
260 s3c_irq_unmask((irqno <= (IRQ_EINT7 - EXTINT_OFF)) ? IRQ_EINT4t7 : IRQ_EINT8t23);
261 }
262
263 static int
264 s3c_irqext_type(unsigned int irq, unsigned int type)
265 {
266 void __iomem *extint_reg;
267 void __iomem *gpcon_reg;
268 unsigned long gpcon_offset, extint_offset;
269 unsigned long newvalue = 0, value;
270
271 if ((irq >= IRQ_EINT0) && (irq <= IRQ_EINT3))
272 {
273 gpcon_reg = S3C2410_GPFCON;
274 extint_reg = S3C24XX_EXTINT0;
275 gpcon_offset = (irq - IRQ_EINT0) * 2;
276 extint_offset = (irq - IRQ_EINT0) * 4;
277 }
278 else if ((irq >= IRQ_EINT4) && (irq <= IRQ_EINT7))
279 {
280 gpcon_reg = S3C2410_GPFCON;
281 extint_reg = S3C24XX_EXTINT0;
282 gpcon_offset = (irq - (EXTINT_OFF)) * 2;
283 extint_offset = (irq - (EXTINT_OFF)) * 4;
284 }
285 else if ((irq >= IRQ_EINT8) && (irq <= IRQ_EINT15))
286 {
287 gpcon_reg = S3C2410_GPGCON;
288 extint_reg = S3C24XX_EXTINT1;
289 gpcon_offset = (irq - IRQ_EINT8) * 2;
290 extint_offset = (irq - IRQ_EINT8) * 4;
291 }
292 else if ((irq >= IRQ_EINT16) && (irq <= IRQ_EINT23))
293 {
294 gpcon_reg = S3C2410_GPGCON;
295 extint_reg = S3C24XX_EXTINT2;
296 gpcon_offset = (irq - IRQ_EINT8) * 2;
297 extint_offset = (irq - IRQ_EINT16) * 4;
298 } else
299 return -1;
300
301 /* Set the GPIO to external interrupt mode */
302 value = __raw_readl(gpcon_reg);
303 value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset);
304 __raw_writel(value, gpcon_reg);
305
306 /* Set the external interrupt to pointed trigger type */
307 switch (type)
308 {
309 case IRQT_NOEDGE:
310 printk(KERN_WARNING "No edge setting!\n");
311 break;
312
313 case IRQT_RISING:
314 newvalue = S3C2410_EXTINT_RISEEDGE;
315 break;
316
317 case IRQT_FALLING:
318 newvalue = S3C2410_EXTINT_FALLEDGE;
319 break;
320
321 case IRQT_BOTHEDGE:
322 newvalue = S3C2410_EXTINT_BOTHEDGE;
323 break;
324
325 case IRQT_LOW:
326 newvalue = S3C2410_EXTINT_LOWLEV;
327 break;
328
329 case IRQT_HIGH:
330 newvalue = S3C2410_EXTINT_HILEV;
331 break;
332
333 default:
334 printk(KERN_ERR "No such irq type %d", type);
335 return -1;
336 }
337
338 value = __raw_readl(extint_reg);
339 value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset);
340 __raw_writel(value, extint_reg);
341
342 return 0;
343 }
344
345 static struct irqchip s3c_irqext_chip = {
346 .mask = s3c_irqext_mask,
347 .unmask = s3c_irqext_unmask,
348 .ack = s3c_irqext_ack,
349 .set_type = s3c_irqext_type,
350 .set_wake = s3c_irqext_wake
351 };
352
353 static struct irqchip s3c_irq_eint0t4 = {
354 .ack = s3c_irq_ack,
355 .mask = s3c_irq_mask,
356 .unmask = s3c_irq_unmask,
357 .set_wake = s3c_irq_wake,
358 .set_type = s3c_irqext_type,
359 };
360
361 /* mask values for the parent registers for each of the interrupt types */
362
363 #define INTMSK_UART0 (1UL << (IRQ_UART0 - IRQ_EINT0))
364 #define INTMSK_UART1 (1UL << (IRQ_UART1 - IRQ_EINT0))
365 #define INTMSK_UART2 (1UL << (IRQ_UART2 - IRQ_EINT0))
366 #define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0))
367
368
369 /* UART0 */
370
371 static void
372 s3c_irq_uart0_mask(unsigned int irqno)
373 {
374 s3c_irqsub_mask(irqno, INTMSK_UART0, 7);
375 }
376
377 static void
378 s3c_irq_uart0_unmask(unsigned int irqno)
379 {
380 s3c_irqsub_unmask(irqno, INTMSK_UART0);
381 }
382
383 static void
384 s3c_irq_uart0_ack(unsigned int irqno)
385 {
386 s3c_irqsub_maskack(irqno, INTMSK_UART0, 7);
387 }
388
389 static struct irqchip s3c_irq_uart0 = {
390 .mask = s3c_irq_uart0_mask,
391 .unmask = s3c_irq_uart0_unmask,
392 .ack = s3c_irq_uart0_ack,
393 };
394
395 /* UART1 */
396
397 static void
398 s3c_irq_uart1_mask(unsigned int irqno)
399 {
400 s3c_irqsub_mask(irqno, INTMSK_UART1, 7 << 3);
401 }
402
403 static void
404 s3c_irq_uart1_unmask(unsigned int irqno)
405 {
406 s3c_irqsub_unmask(irqno, INTMSK_UART1);
407 }
408
409 static void
410 s3c_irq_uart1_ack(unsigned int irqno)
411 {
412 s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3);
413 }
414
415 static struct irqchip s3c_irq_uart1 = {
416 .mask = s3c_irq_uart1_mask,
417 .unmask = s3c_irq_uart1_unmask,
418 .ack = s3c_irq_uart1_ack,
419 };
420
421 /* UART2 */
422
423 static void
424 s3c_irq_uart2_mask(unsigned int irqno)
425 {
426 s3c_irqsub_mask(irqno, INTMSK_UART2, 7 << 6);
427 }
428
429 static void
430 s3c_irq_uart2_unmask(unsigned int irqno)
431 {
432 s3c_irqsub_unmask(irqno, INTMSK_UART2);
433 }
434
435 static void
436 s3c_irq_uart2_ack(unsigned int irqno)
437 {
438 s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6);
439 }
440
441 static struct irqchip s3c_irq_uart2 = {
442 .mask = s3c_irq_uart2_mask,
443 .unmask = s3c_irq_uart2_unmask,
444 .ack = s3c_irq_uart2_ack,
445 };
446
447 /* ADC and Touchscreen */
448
449 static void
450 s3c_irq_adc_mask(unsigned int irqno)
451 {
452 s3c_irqsub_mask(irqno, INTMSK_ADCPARENT, 3 << 9);
453 }
454
455 static void
456 s3c_irq_adc_unmask(unsigned int irqno)
457 {
458 s3c_irqsub_unmask(irqno, INTMSK_ADCPARENT);
459 }
460
461 static void
462 s3c_irq_adc_ack(unsigned int irqno)
463 {
464 s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9);
465 }
466
467 static struct irqchip s3c_irq_adc = {
468 .mask = s3c_irq_adc_mask,
469 .unmask = s3c_irq_adc_unmask,
470 .ack = s3c_irq_adc_ack,
471 };
472
473 /* irq demux for adc */
474 static void s3c_irq_demux_adc(unsigned int irq,
475 struct irqdesc *desc,
476 struct pt_regs *regs)
477 {
478 unsigned int subsrc, submsk;
479 unsigned int offset = 9;
480 struct irqdesc *mydesc;
481
482 /* read the current pending interrupts, and the mask
483 * for what it is available */
484
485 subsrc = __raw_readl(S3C2410_SUBSRCPND);
486 submsk = __raw_readl(S3C2410_INTSUBMSK);
487
488 subsrc &= ~submsk;
489 subsrc >>= offset;
490 subsrc &= 3;
491
492 if (subsrc != 0) {
493 if (subsrc & 1) {
494 mydesc = irq_desc + IRQ_TC;
495 desc_handle_irq(IRQ_TC, mydesc, regs);
496 }
497 if (subsrc & 2) {
498 mydesc = irq_desc + IRQ_ADC;
499 desc_handle_irq(IRQ_ADC, mydesc, regs);
500 }
501 }
502 }
503
504 static void s3c_irq_demux_uart(unsigned int start,
505 struct pt_regs *regs)
506 {
507 unsigned int subsrc, submsk;
508 unsigned int offset = start - IRQ_S3CUART_RX0;
509 struct irqdesc *desc;
510
511 /* read the current pending interrupts, and the mask
512 * for what it is available */
513
514 subsrc = __raw_readl(S3C2410_SUBSRCPND);
515 submsk = __raw_readl(S3C2410_INTSUBMSK);
516
517 irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n",
518 start, offset, subsrc, submsk);
519
520 subsrc &= ~submsk;
521 subsrc >>= offset;
522 subsrc &= 7;
523
524 if (subsrc != 0) {
525 desc = irq_desc + start;
526
527 if (subsrc & 1)
528 desc_handle_irq(start, desc, regs);
529
530 desc++;
531
532 if (subsrc & 2)
533 desc_handle_irq(start+1, desc, regs);
534
535 desc++;
536
537 if (subsrc & 4)
538 desc_handle_irq(start+2, desc, regs);
539 }
540 }
541
542 /* uart demux entry points */
543
544 static void
545 s3c_irq_demux_uart0(unsigned int irq,
546 struct irqdesc *desc,
547 struct pt_regs *regs)
548 {
549 irq = irq;
550 s3c_irq_demux_uart(IRQ_S3CUART_RX0, regs);
551 }
552
553 static void
554 s3c_irq_demux_uart1(unsigned int irq,
555 struct irqdesc *desc,
556 struct pt_regs *regs)
557 {
558 irq = irq;
559 s3c_irq_demux_uart(IRQ_S3CUART_RX1, regs);
560 }
561
562 static void
563 s3c_irq_demux_uart2(unsigned int irq,
564 struct irqdesc *desc,
565 struct pt_regs *regs)
566 {
567 irq = irq;
568 s3c_irq_demux_uart(IRQ_S3CUART_RX2, regs);
569 }
570
571 static void
572 s3c_irq_demux_extint(unsigned int irq,
573 struct irqdesc *desc,
574 struct pt_regs *regs)
575 {
576 unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
577 unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
578
579 eintpnd &= ~eintmsk;
580
581 if (eintpnd) {
582 irq = fls(eintpnd);
583 irq += (IRQ_EINT4 - (4 + 1));
584
585 desc_handle_irq(irq, irq_desc + irq, regs);
586 }
587 }
588
589 /* s3c24xx_init_irq
590 *
591 * Initialise S3C2410 IRQ system
592 */
593
594 void __init s3c24xx_init_irq(void)
595 {
596 unsigned long pend;
597 unsigned long last;
598 int irqno;
599 int i;
600
601 irqdbf("s3c2410_init_irq: clearing interrupt status flags\n");
602
603 /* first, clear all interrupts pending... */
604
605 last = 0;
606 for (i = 0; i < 4; i++) {
607 pend = __raw_readl(S3C24XX_EINTPEND);
608
609 if (pend == 0 || pend == last)
610 break;
611
612 __raw_writel(pend, S3C24XX_EINTPEND);
613 printk("irq: clearing pending ext status %08x\n", (int)pend);
614 last = pend;
615 }
616
617 last = 0;
618 for (i = 0; i < 4; i++) {
619 pend = __raw_readl(S3C2410_INTPND);
620
621 if (pend == 0 || pend == last)
622 break;
623
624 __raw_writel(pend, S3C2410_SRCPND);
625 __raw_writel(pend, S3C2410_INTPND);
626 printk("irq: clearing pending status %08x\n", (int)pend);
627 last = pend;
628 }
629
630 last = 0;
631 for (i = 0; i < 4; i++) {
632 pend = __raw_readl(S3C2410_SUBSRCPND);
633
634 if (pend == 0 || pend == last)
635 break;
636
637 printk("irq: clearing subpending status %08x\n", (int)pend);
638 __raw_writel(pend, S3C2410_SUBSRCPND);
639 last = pend;
640 }
641
642 /* register the main interrupts */
643
644 irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n");
645
646 for (irqno = IRQ_EINT4t7; irqno <= IRQ_ADCPARENT; irqno++) {
647 /* set all the s3c2410 internal irqs */
648
649 switch (irqno) {
650 /* deal with the special IRQs (cascaded) */
651
652 case IRQ_EINT4t7:
653 case IRQ_EINT8t23:
654 case IRQ_UART0:
655 case IRQ_UART1:
656 case IRQ_UART2:
657 case IRQ_ADCPARENT:
658 set_irq_chip(irqno, &s3c_irq_level_chip);
659 set_irq_handler(irqno, do_level_IRQ);
660 break;
661
662 case IRQ_RESERVED6:
663 case IRQ_RESERVED24:
664 /* no IRQ here */
665 break;
666
667 default:
668 //irqdbf("registering irq %d (s3c irq)\n", irqno);
669 set_irq_chip(irqno, &s3c_irq_chip);
670 set_irq_handler(irqno, do_edge_IRQ);
671 set_irq_flags(irqno, IRQF_VALID);
672 }
673 }
674
675 /* setup the cascade irq handlers */
676
677 set_irq_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint);
678 set_irq_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint);
679
680 set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
681 set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
682 set_irq_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
683 set_irq_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
684
685 /* external interrupts */
686
687 for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
688 irqdbf("registering irq %d (ext int)\n", irqno);
689 set_irq_chip(irqno, &s3c_irq_eint0t4);
690 set_irq_handler(irqno, do_edge_IRQ);
691 set_irq_flags(irqno, IRQF_VALID);
692 }
693
694 for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) {
695 irqdbf("registering irq %d (extended s3c irq)\n", irqno);
696 set_irq_chip(irqno, &s3c_irqext_chip);
697 set_irq_handler(irqno, do_edge_IRQ);
698 set_irq_flags(irqno, IRQF_VALID);
699 }
700
701 /* register the uart interrupts */
702
703 irqdbf("s3c2410: registering external interrupts\n");
704
705 for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) {
706 irqdbf("registering irq %d (s3c uart0 irq)\n", irqno);
707 set_irq_chip(irqno, &s3c_irq_uart0);
708 set_irq_handler(irqno, do_level_IRQ);
709 set_irq_flags(irqno, IRQF_VALID);
710 }
711
712 for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) {
713 irqdbf("registering irq %d (s3c uart1 irq)\n", irqno);
714 set_irq_chip(irqno, &s3c_irq_uart1);
715 set_irq_handler(irqno, do_level_IRQ);
716 set_irq_flags(irqno, IRQF_VALID);
717 }
718
719 for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) {
720 irqdbf("registering irq %d (s3c uart2 irq)\n", irqno);
721 set_irq_chip(irqno, &s3c_irq_uart2);
722 set_irq_handler(irqno, do_level_IRQ);
723 set_irq_flags(irqno, IRQF_VALID);
724 }
725
726 for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) {
727 irqdbf("registering irq %d (s3c adc irq)\n", irqno);
728 set_irq_chip(irqno, &s3c_irq_adc);
729 set_irq_handler(irqno, do_edge_IRQ);
730 set_irq_flags(irqno, IRQF_VALID);
731 }
732
733 irqdbf("s3c2410: registered interrupt handlers\n");
734 }
Support for the Chinese Samsung S3C2440 based development boards