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x86: move devmem_is_allowed() to common mm/init.c
[linux-2.6/mini2440.git] / sound / pci / maestro3.c
blob59bbaf8f3e5b9bbe026fe13162e5258408598958
1 /*
2 * Driver for ESS Maestro3/Allegro (ES1988) soundcards.
3 * Copyright (c) 2000 by Zach Brown <zab@zabbo.net>
4 * Takashi Iwai <tiwai@suse.de>
5 *
6 * Most of the hardware init stuffs are based on maestro3 driver for
7 * OSS/Free by Zach Brown. Many thanks to Zach!
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 *
24 * ChangeLog:
25 * Aug. 27, 2001
26 * - Fixed deadlock on capture
27 * - Added Canyon3D-2 support by Rob Riggs <rob@pangalactic.org>
28 *
29 */
30
31 #define CARD_NAME "ESS Maestro3/Allegro/Canyon3D-2"
32 #define DRIVER_NAME "Maestro3"
33
34 #include <asm/io.h>
35 #include <linux/delay.h>
36 #include <linux/interrupt.h>
37 #include <linux/init.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <linux/vmalloc.h>
42 #include <linux/moduleparam.h>
43 #include <linux/firmware.h>
44 #include <sound/core.h>
45 #include <sound/info.h>
46 #include <sound/control.h>
47 #include <sound/pcm.h>
48 #include <sound/mpu401.h>
49 #include <sound/ac97_codec.h>
50 #include <sound/initval.h>
51 #include <asm/byteorder.h>
52
53 MODULE_AUTHOR("Zach Brown <zab@zabbo.net>, Takashi Iwai <tiwai@suse.de>");
54 MODULE_DESCRIPTION("ESS Maestro3 PCI");
55 MODULE_LICENSE("GPL");
56 MODULE_SUPPORTED_DEVICE("{{ESS,Maestro3 PCI},"
57 "{ESS,ES1988},"
58 "{ESS,Allegro PCI},"
59 "{ESS,Allegro-1 PCI},"
60 "{ESS,Canyon3D-2/LE PCI}}");
61 MODULE_FIRMWARE("ess/maestro3_assp_kernel.fw");
62 MODULE_FIRMWARE("ess/maestro3_assp_minisrc.fw");
63
64 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
65 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
66 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* all enabled */
67 static int external_amp[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1};
68 static int amp_gpio[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
69
70 module_param_array(index, int, NULL, 0444);
71 MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
72 module_param_array(id, charp, NULL, 0444);
73 MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
74 module_param_array(enable, bool, NULL, 0444);
75 MODULE_PARM_DESC(enable, "Enable this soundcard.");
76 module_param_array(external_amp, bool, NULL, 0444);
77 MODULE_PARM_DESC(external_amp, "Enable external amp for " CARD_NAME " soundcard.");
78 module_param_array(amp_gpio, int, NULL, 0444);
79 MODULE_PARM_DESC(amp_gpio, "GPIO pin number for external amp. (default = -1)");
80
81 #define MAX_PLAYBACKS 2
82 #define MAX_CAPTURES 1
83 #define NR_DSPS (MAX_PLAYBACKS + MAX_CAPTURES)
84
85
86 /*
87 * maestro3 registers
88 */
89
90 /* Allegro PCI configuration registers */
91 #define PCI_LEGACY_AUDIO_CTRL 0x40
92 #define SOUND_BLASTER_ENABLE 0x00000001
93 #define FM_SYNTHESIS_ENABLE 0x00000002
94 #define GAME_PORT_ENABLE 0x00000004
95 #define MPU401_IO_ENABLE 0x00000008
96 #define MPU401_IRQ_ENABLE 0x00000010
97 #define ALIAS_10BIT_IO 0x00000020
98 #define SB_DMA_MASK 0x000000C0
99 #define SB_DMA_0 0x00000040
100 #define SB_DMA_1 0x00000040
101 #define SB_DMA_R 0x00000080
102 #define SB_DMA_3 0x000000C0
103 #define SB_IRQ_MASK 0x00000700
104 #define SB_IRQ_5 0x00000000
105 #define SB_IRQ_7 0x00000100
106 #define SB_IRQ_9 0x00000200
107 #define SB_IRQ_10 0x00000300
108 #define MIDI_IRQ_MASK 0x00003800
109 #define SERIAL_IRQ_ENABLE 0x00004000
110 #define DISABLE_LEGACY 0x00008000
111
112 #define PCI_ALLEGRO_CONFIG 0x50
113 #define SB_ADDR_240 0x00000004
114 #define MPU_ADDR_MASK 0x00000018
115 #define MPU_ADDR_330 0x00000000
116 #define MPU_ADDR_300 0x00000008
117 #define MPU_ADDR_320 0x00000010
118 #define MPU_ADDR_340 0x00000018
119 #define USE_PCI_TIMING 0x00000040
120 #define POSTED_WRITE_ENABLE 0x00000080
121 #define DMA_POLICY_MASK 0x00000700
122 #define DMA_DDMA 0x00000000
123 #define DMA_TDMA 0x00000100
124 #define DMA_PCPCI 0x00000200
125 #define DMA_WBDMA16 0x00000400
126 #define DMA_WBDMA4 0x00000500
127 #define DMA_WBDMA2 0x00000600
128 #define DMA_WBDMA1 0x00000700
129 #define DMA_SAFE_GUARD 0x00000800
130 #define HI_PERF_GP_ENABLE 0x00001000
131 #define PIC_SNOOP_MODE_0 0x00002000
132 #define PIC_SNOOP_MODE_1 0x00004000
133 #define SOUNDBLASTER_IRQ_MASK 0x00008000
134 #define RING_IN_ENABLE 0x00010000
135 #define SPDIF_TEST_MODE 0x00020000
136 #define CLK_MULT_MODE_SELECT_2 0x00040000
137 #define EEPROM_WRITE_ENABLE 0x00080000
138 #define CODEC_DIR_IN 0x00100000
139 #define HV_BUTTON_FROM_GD 0x00200000
140 #define REDUCED_DEBOUNCE 0x00400000
141 #define HV_CTRL_ENABLE 0x00800000
142 #define SPDIF_ENABLE 0x01000000
143 #define CLK_DIV_SELECT 0x06000000
144 #define CLK_DIV_BY_48 0x00000000
145 #define CLK_DIV_BY_49 0x02000000
146 #define CLK_DIV_BY_50 0x04000000
147 #define CLK_DIV_RESERVED 0x06000000
148 #define PM_CTRL_ENABLE 0x08000000
149 #define CLK_MULT_MODE_SELECT 0x30000000
150 #define CLK_MULT_MODE_SHIFT 28
151 #define CLK_MULT_MODE_0 0x00000000
152 #define CLK_MULT_MODE_1 0x10000000
153 #define CLK_MULT_MODE_2 0x20000000
154 #define CLK_MULT_MODE_3 0x30000000
155 #define INT_CLK_SELECT 0x40000000
156 #define INT_CLK_MULT_RESET 0x80000000
157
158 /* M3 */
159 #define INT_CLK_SRC_NOT_PCI 0x00100000
160 #define INT_CLK_MULT_ENABLE 0x80000000
161
162 #define PCI_ACPI_CONTROL 0x54
163 #define PCI_ACPI_D0 0x00000000
164 #define PCI_ACPI_D1 0xB4F70000
165 #define PCI_ACPI_D2 0xB4F7B4F7
166
167 #define PCI_USER_CONFIG 0x58
168 #define EXT_PCI_MASTER_ENABLE 0x00000001
169 #define SPDIF_OUT_SELECT 0x00000002
170 #define TEST_PIN_DIR_CTRL 0x00000004
171 #define AC97_CODEC_TEST 0x00000020
172 #define TRI_STATE_BUFFER 0x00000080
173 #define IN_CLK_12MHZ_SELECT 0x00000100
174 #define MULTI_FUNC_DISABLE 0x00000200
175 #define EXT_MASTER_PAIR_SEL 0x00000400
176 #define PCI_MASTER_SUPPORT 0x00000800
177 #define STOP_CLOCK_ENABLE 0x00001000
178 #define EAPD_DRIVE_ENABLE 0x00002000
179 #define REQ_TRI_STATE_ENABLE 0x00004000
180 #define REQ_LOW_ENABLE 0x00008000
181 #define MIDI_1_ENABLE 0x00010000
182 #define MIDI_2_ENABLE 0x00020000
183 #define SB_AUDIO_SYNC 0x00040000
184 #define HV_CTRL_TEST 0x00100000
185 #define SOUNDBLASTER_TEST 0x00400000
186
187 #define PCI_USER_CONFIG_C 0x5C
188
189 #define PCI_DDMA_CTRL 0x60
190 #define DDMA_ENABLE 0x00000001
191
192
193 /* Allegro registers */
194 #define HOST_INT_CTRL 0x18
195 #define SB_INT_ENABLE 0x0001
196 #define MPU401_INT_ENABLE 0x0002
197 #define ASSP_INT_ENABLE 0x0010
198 #define RING_INT_ENABLE 0x0020
199 #define HV_INT_ENABLE 0x0040
200 #define CLKRUN_GEN_ENABLE 0x0100
201 #define HV_CTRL_TO_PME 0x0400
202 #define SOFTWARE_RESET_ENABLE 0x8000
203
204 /*
205 * should be using the above defines, probably.
206 */
207 #define REGB_ENABLE_RESET 0x01
208 #define REGB_STOP_CLOCK 0x10
209
210 #define HOST_INT_STATUS 0x1A
211 #define SB_INT_PENDING 0x01
212 #define MPU401_INT_PENDING 0x02
213 #define ASSP_INT_PENDING 0x10
214 #define RING_INT_PENDING 0x20
215 #define HV_INT_PENDING 0x40
216
217 #define HARDWARE_VOL_CTRL 0x1B
218 #define SHADOW_MIX_REG_VOICE 0x1C
219 #define HW_VOL_COUNTER_VOICE 0x1D
220 #define SHADOW_MIX_REG_MASTER 0x1E
221 #define HW_VOL_COUNTER_MASTER 0x1F
222
223 #define CODEC_COMMAND 0x30
224 #define CODEC_READ_B 0x80
225
226 #define CODEC_STATUS 0x30
227 #define CODEC_BUSY_B 0x01
228
229 #define CODEC_DATA 0x32
230
231 #define RING_BUS_CTRL_A 0x36
232 #define RAC_PME_ENABLE 0x0100
233 #define RAC_SDFS_ENABLE 0x0200
234 #define LAC_PME_ENABLE 0x0400
235 #define LAC_SDFS_ENABLE 0x0800
236 #define SERIAL_AC_LINK_ENABLE 0x1000
237 #define IO_SRAM_ENABLE 0x2000
238 #define IIS_INPUT_ENABLE 0x8000
239
240 #define RING_BUS_CTRL_B 0x38
241 #define SECOND_CODEC_ID_MASK 0x0003
242 #define SPDIF_FUNC_ENABLE 0x0010
243 #define SECOND_AC_ENABLE 0x0020
244 #define SB_MODULE_INTF_ENABLE 0x0040
245 #define SSPE_ENABLE 0x0040
246 #define M3I_DOCK_ENABLE 0x0080
247
248 #define SDO_OUT_DEST_CTRL 0x3A
249 #define COMMAND_ADDR_OUT 0x0003
250 #define PCM_LR_OUT_LOCAL 0x0000
251 #define PCM_LR_OUT_REMOTE 0x0004
252 #define PCM_LR_OUT_MUTE 0x0008
253 #define PCM_LR_OUT_BOTH 0x000C
254 #define LINE1_DAC_OUT_LOCAL 0x0000
255 #define LINE1_DAC_OUT_REMOTE 0x0010
256 #define LINE1_DAC_OUT_MUTE 0x0020
257 #define LINE1_DAC_OUT_BOTH 0x0030
258 #define PCM_CLS_OUT_LOCAL 0x0000
259 #define PCM_CLS_OUT_REMOTE 0x0040
260 #define PCM_CLS_OUT_MUTE 0x0080
261 #define PCM_CLS_OUT_BOTH 0x00C0
262 #define PCM_RLF_OUT_LOCAL 0x0000
263 #define PCM_RLF_OUT_REMOTE 0x0100
264 #define PCM_RLF_OUT_MUTE 0x0200
265 #define PCM_RLF_OUT_BOTH 0x0300
266 #define LINE2_DAC_OUT_LOCAL 0x0000
267 #define LINE2_DAC_OUT_REMOTE 0x0400
268 #define LINE2_DAC_OUT_MUTE 0x0800
269 #define LINE2_DAC_OUT_BOTH 0x0C00
270 #define HANDSET_OUT_LOCAL 0x0000
271 #define HANDSET_OUT_REMOTE 0x1000
272 #define HANDSET_OUT_MUTE 0x2000
273 #define HANDSET_OUT_BOTH 0x3000
274 #define IO_CTRL_OUT_LOCAL 0x0000
275 #define IO_CTRL_OUT_REMOTE 0x4000
276 #define IO_CTRL_OUT_MUTE 0x8000
277 #define IO_CTRL_OUT_BOTH 0xC000
278
279 #define SDO_IN_DEST_CTRL 0x3C
280 #define STATUS_ADDR_IN 0x0003
281 #define PCM_LR_IN_LOCAL 0x0000
282 #define PCM_LR_IN_REMOTE 0x0004
283 #define PCM_LR_RESERVED 0x0008
284 #define PCM_LR_IN_BOTH 0x000C
285 #define LINE1_ADC_IN_LOCAL 0x0000
286 #define LINE1_ADC_IN_REMOTE 0x0010
287 #define LINE1_ADC_IN_MUTE 0x0020
288 #define MIC_ADC_IN_LOCAL 0x0000
289 #define MIC_ADC_IN_REMOTE 0x0040
290 #define MIC_ADC_IN_MUTE 0x0080
291 #define LINE2_DAC_IN_LOCAL 0x0000
292 #define LINE2_DAC_IN_REMOTE 0x0400
293 #define LINE2_DAC_IN_MUTE 0x0800
294 #define HANDSET_IN_LOCAL 0x0000
295 #define HANDSET_IN_REMOTE 0x1000
296 #define HANDSET_IN_MUTE 0x2000
297 #define IO_STATUS_IN_LOCAL 0x0000
298 #define IO_STATUS_IN_REMOTE 0x4000
299
300 #define SPDIF_IN_CTRL 0x3E
301 #define SPDIF_IN_ENABLE 0x0001
302
303 #define GPIO_DATA 0x60
304 #define GPIO_DATA_MASK 0x0FFF
305 #define GPIO_HV_STATUS 0x3000
306 #define GPIO_PME_STATUS 0x4000
307
308 #define GPIO_MASK 0x64
309 #define GPIO_DIRECTION 0x68
310 #define GPO_PRIMARY_AC97 0x0001
311 #define GPI_LINEOUT_SENSE 0x0004
312 #define GPO_SECONDARY_AC97 0x0008
313 #define GPI_VOL_DOWN 0x0010
314 #define GPI_VOL_UP 0x0020
315 #define GPI_IIS_CLK 0x0040
316 #define GPI_IIS_LRCLK 0x0080
317 #define GPI_IIS_DATA 0x0100
318 #define GPI_DOCKING_STATUS 0x0100
319 #define GPI_HEADPHONE_SENSE 0x0200
320 #define GPO_EXT_AMP_SHUTDOWN 0x1000
321
322 #define GPO_EXT_AMP_M3 1 /* default m3 amp */
323 #define GPO_EXT_AMP_ALLEGRO 8 /* default allegro amp */
324
325 /* M3 */
326 #define GPO_M3_EXT_AMP_SHUTDN 0x0002
327
328 #define ASSP_INDEX_PORT 0x80
329 #define ASSP_MEMORY_PORT 0x82
330 #define ASSP_DATA_PORT 0x84
331
332 #define MPU401_DATA_PORT 0x98
333 #define MPU401_STATUS_PORT 0x99
334
335 #define CLK_MULT_DATA_PORT 0x9C
336
337 #define ASSP_CONTROL_A 0xA2
338 #define ASSP_0_WS_ENABLE 0x01
339 #define ASSP_CTRL_A_RESERVED1 0x02
340 #define ASSP_CTRL_A_RESERVED2 0x04
341 #define ASSP_CLK_49MHZ_SELECT 0x08
342 #define FAST_PLU_ENABLE 0x10
343 #define ASSP_CTRL_A_RESERVED3 0x20
344 #define DSP_CLK_36MHZ_SELECT 0x40
345
346 #define ASSP_CONTROL_B 0xA4
347 #define RESET_ASSP 0x00
348 #define RUN_ASSP 0x01
349 #define ENABLE_ASSP_CLOCK 0x00
350 #define STOP_ASSP_CLOCK 0x10
351 #define RESET_TOGGLE 0x40
352
353 #define ASSP_CONTROL_C 0xA6
354 #define ASSP_HOST_INT_ENABLE 0x01
355 #define FM_ADDR_REMAP_DISABLE 0x02
356 #define HOST_WRITE_PORT_ENABLE 0x08
357
358 #define ASSP_HOST_INT_STATUS 0xAC
359 #define DSP2HOST_REQ_PIORECORD 0x01
360 #define DSP2HOST_REQ_I2SRATE 0x02
361 #define DSP2HOST_REQ_TIMER 0x04
362
363 /* AC97 registers */
364 /* XXX fix this crap up */
365 /*#define AC97_RESET 0x00*/
366
367 #define AC97_VOL_MUTE_B 0x8000
368 #define AC97_VOL_M 0x1F
369 #define AC97_LEFT_VOL_S 8
370
371 #define AC97_MASTER_VOL 0x02
372 #define AC97_LINE_LEVEL_VOL 0x04
373 #define AC97_MASTER_MONO_VOL 0x06
374 #define AC97_PC_BEEP_VOL 0x0A
375 #define AC97_PC_BEEP_VOL_M 0x0F
376 #define AC97_SROUND_MASTER_VOL 0x38
377 #define AC97_PC_BEEP_VOL_S 1
378
379 /*#define AC97_PHONE_VOL 0x0C
380 #define AC97_MIC_VOL 0x0E*/
381 #define AC97_MIC_20DB_ENABLE 0x40
382
383 /*#define AC97_LINEIN_VOL 0x10
384 #define AC97_CD_VOL 0x12
385 #define AC97_VIDEO_VOL 0x14
386 #define AC97_AUX_VOL 0x16*/
387 #define AC97_PCM_OUT_VOL 0x18
388 /*#define AC97_RECORD_SELECT 0x1A*/
389 #define AC97_RECORD_MIC 0x00
390 #define AC97_RECORD_CD 0x01
391 #define AC97_RECORD_VIDEO 0x02
392 #define AC97_RECORD_AUX 0x03
393 #define AC97_RECORD_MONO_MUX 0x02
394 #define AC97_RECORD_DIGITAL 0x03
395 #define AC97_RECORD_LINE 0x04
396 #define AC97_RECORD_STEREO 0x05
397 #define AC97_RECORD_MONO 0x06
398 #define AC97_RECORD_PHONE 0x07
399
400 /*#define AC97_RECORD_GAIN 0x1C*/
401 #define AC97_RECORD_VOL_M 0x0F
402
403 /*#define AC97_GENERAL_PURPOSE 0x20*/
404 #define AC97_POWER_DOWN_CTRL 0x26
405 #define AC97_ADC_READY 0x0001
406 #define AC97_DAC_READY 0x0002
407 #define AC97_ANALOG_READY 0x0004
408 #define AC97_VREF_ON 0x0008
409 #define AC97_PR0 0x0100
410 #define AC97_PR1 0x0200
411 #define AC97_PR2 0x0400
412 #define AC97_PR3 0x0800
413 #define AC97_PR4 0x1000
414
415 #define AC97_RESERVED1 0x28
416
417 #define AC97_VENDOR_TEST 0x5A
418
419 #define AC97_CLOCK_DELAY 0x5C
420 #define AC97_LINEOUT_MUX_SEL 0x0001
421 #define AC97_MONO_MUX_SEL 0x0002
422 #define AC97_CLOCK_DELAY_SEL 0x1F
423 #define AC97_DAC_CDS_SHIFT 6
424 #define AC97_ADC_CDS_SHIFT 11
425
426 #define AC97_MULTI_CHANNEL_SEL 0x74
427
428 /*#define AC97_VENDOR_ID1 0x7C
429 #define AC97_VENDOR_ID2 0x7E*/
430
431 /*
432 * ASSP control regs
433 */
434 #define DSP_PORT_TIMER_COUNT 0x06
435
436 #define DSP_PORT_MEMORY_INDEX 0x80
437
438 #define DSP_PORT_MEMORY_TYPE 0x82
439 #define MEMTYPE_INTERNAL_CODE 0x0002
440 #define MEMTYPE_INTERNAL_DATA 0x0003
441 #define MEMTYPE_MASK 0x0003
442
443 #define DSP_PORT_MEMORY_DATA 0x84
444
445 #define DSP_PORT_CONTROL_REG_A 0xA2
446 #define DSP_PORT_CONTROL_REG_B 0xA4
447 #define DSP_PORT_CONTROL_REG_C 0xA6
448
449 #define REV_A_CODE_MEMORY_BEGIN 0x0000
450 #define REV_A_CODE_MEMORY_END 0x0FFF
451 #define REV_A_CODE_MEMORY_UNIT_LENGTH 0x0040
452 #define REV_A_CODE_MEMORY_LENGTH (REV_A_CODE_MEMORY_END - REV_A_CODE_MEMORY_BEGIN + 1)
453
454 #define REV_B_CODE_MEMORY_BEGIN 0x0000
455 #define REV_B_CODE_MEMORY_END 0x0BFF
456 #define REV_B_CODE_MEMORY_UNIT_LENGTH 0x0040
457 #define REV_B_CODE_MEMORY_LENGTH (REV_B_CODE_MEMORY_END - REV_B_CODE_MEMORY_BEGIN + 1)
458
459 #define REV_A_DATA_MEMORY_BEGIN 0x1000
460 #define REV_A_DATA_MEMORY_END 0x2FFF
461 #define REV_A_DATA_MEMORY_UNIT_LENGTH 0x0080
462 #define REV_A_DATA_MEMORY_LENGTH (REV_A_DATA_MEMORY_END - REV_A_DATA_MEMORY_BEGIN + 1)
463
464 #define REV_B_DATA_MEMORY_BEGIN 0x1000
465 #define REV_B_DATA_MEMORY_END 0x2BFF
466 #define REV_B_DATA_MEMORY_UNIT_LENGTH 0x0080
467 #define REV_B_DATA_MEMORY_LENGTH (REV_B_DATA_MEMORY_END - REV_B_DATA_MEMORY_BEGIN + 1)
468
469
470 #define NUM_UNITS_KERNEL_CODE 16
471 #define NUM_UNITS_KERNEL_DATA 2
472
473 #define NUM_UNITS_KERNEL_CODE_WITH_HSP 16
474 #define NUM_UNITS_KERNEL_DATA_WITH_HSP 5
475
476 /*
477 * Kernel data layout
478 */
479
480 #define DP_SHIFT_COUNT 7
481
482 #define KDATA_BASE_ADDR 0x1000
483 #define KDATA_BASE_ADDR2 0x1080
484
485 #define KDATA_TASK0 (KDATA_BASE_ADDR + 0x0000)
486 #define KDATA_TASK1 (KDATA_BASE_ADDR + 0x0001)
487 #define KDATA_TASK2 (KDATA_BASE_ADDR + 0x0002)
488 #define KDATA_TASK3 (KDATA_BASE_ADDR + 0x0003)
489 #define KDATA_TASK4 (KDATA_BASE_ADDR + 0x0004)
490 #define KDATA_TASK5 (KDATA_BASE_ADDR + 0x0005)
491 #define KDATA_TASK6 (KDATA_BASE_ADDR + 0x0006)
492 #define KDATA_TASK7 (KDATA_BASE_ADDR + 0x0007)
493 #define KDATA_TASK_ENDMARK (KDATA_BASE_ADDR + 0x0008)
494
495 #define KDATA_CURRENT_TASK (KDATA_BASE_ADDR + 0x0009)
496 #define KDATA_TASK_SWITCH (KDATA_BASE_ADDR + 0x000A)
497
498 #define KDATA_INSTANCE0_POS3D (KDATA_BASE_ADDR + 0x000B)
499 #define KDATA_INSTANCE1_POS3D (KDATA_BASE_ADDR + 0x000C)
500 #define KDATA_INSTANCE2_POS3D (KDATA_BASE_ADDR + 0x000D)
501 #define KDATA_INSTANCE3_POS3D (KDATA_BASE_ADDR + 0x000E)
502 #define KDATA_INSTANCE4_POS3D (KDATA_BASE_ADDR + 0x000F)
503 #define KDATA_INSTANCE5_POS3D (KDATA_BASE_ADDR + 0x0010)
504 #define KDATA_INSTANCE6_POS3D (KDATA_BASE_ADDR + 0x0011)
505 #define KDATA_INSTANCE7_POS3D (KDATA_BASE_ADDR + 0x0012)
506 #define KDATA_INSTANCE8_POS3D (KDATA_BASE_ADDR + 0x0013)
507 #define KDATA_INSTANCE_POS3D_ENDMARK (KDATA_BASE_ADDR + 0x0014)
508
509 #define KDATA_INSTANCE0_SPKVIRT (KDATA_BASE_ADDR + 0x0015)
510 #define KDATA_INSTANCE_SPKVIRT_ENDMARK (KDATA_BASE_ADDR + 0x0016)
511
512 #define KDATA_INSTANCE0_SPDIF (KDATA_BASE_ADDR + 0x0017)
513 #define KDATA_INSTANCE_SPDIF_ENDMARK (KDATA_BASE_ADDR + 0x0018)
514
515 #define KDATA_INSTANCE0_MODEM (KDATA_BASE_ADDR + 0x0019)
516 #define KDATA_INSTANCE_MODEM_ENDMARK (KDATA_BASE_ADDR + 0x001A)
517
518 #define KDATA_INSTANCE0_SRC (KDATA_BASE_ADDR + 0x001B)
519 #define KDATA_INSTANCE1_SRC (KDATA_BASE_ADDR + 0x001C)
520 #define KDATA_INSTANCE_SRC_ENDMARK (KDATA_BASE_ADDR + 0x001D)
521
522 #define KDATA_INSTANCE0_MINISRC (KDATA_BASE_ADDR + 0x001E)
523 #define KDATA_INSTANCE1_MINISRC (KDATA_BASE_ADDR + 0x001F)
524 #define KDATA_INSTANCE2_MINISRC (KDATA_BASE_ADDR + 0x0020)
525 #define KDATA_INSTANCE3_MINISRC (KDATA_BASE_ADDR + 0x0021)
526 #define KDATA_INSTANCE_MINISRC_ENDMARK (KDATA_BASE_ADDR + 0x0022)
527
528 #define KDATA_INSTANCE0_CPYTHRU (KDATA_BASE_ADDR + 0x0023)
529 #define KDATA_INSTANCE1_CPYTHRU (KDATA_BASE_ADDR + 0x0024)
530 #define KDATA_INSTANCE_CPYTHRU_ENDMARK (KDATA_BASE_ADDR + 0x0025)
531
532 #define KDATA_CURRENT_DMA (KDATA_BASE_ADDR + 0x0026)
533 #define KDATA_DMA_SWITCH (KDATA_BASE_ADDR + 0x0027)
534 #define KDATA_DMA_ACTIVE (KDATA_BASE_ADDR + 0x0028)
535
536 #define KDATA_DMA_XFER0 (KDATA_BASE_ADDR + 0x0029)
537 #define KDATA_DMA_XFER1 (KDATA_BASE_ADDR + 0x002A)
538 #define KDATA_DMA_XFER2 (KDATA_BASE_ADDR + 0x002B)
539 #define KDATA_DMA_XFER3 (KDATA_BASE_ADDR + 0x002C)
540 #define KDATA_DMA_XFER4 (KDATA_BASE_ADDR + 0x002D)
541 #define KDATA_DMA_XFER5 (KDATA_BASE_ADDR + 0x002E)
542 #define KDATA_DMA_XFER6 (KDATA_BASE_ADDR + 0x002F)
543 #define KDATA_DMA_XFER7 (KDATA_BASE_ADDR + 0x0030)
544 #define KDATA_DMA_XFER8 (KDATA_BASE_ADDR + 0x0031)
545 #define KDATA_DMA_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0032)
546
547 #define KDATA_I2S_SAMPLE_COUNT (KDATA_BASE_ADDR + 0x0033)
548 #define KDATA_I2S_INT_METER (KDATA_BASE_ADDR + 0x0034)
549 #define KDATA_I2S_ACTIVE (KDATA_BASE_ADDR + 0x0035)
550
551 #define KDATA_TIMER_COUNT_RELOAD (KDATA_BASE_ADDR + 0x0036)
552 #define KDATA_TIMER_COUNT_CURRENT (KDATA_BASE_ADDR + 0x0037)
553
554 #define KDATA_HALT_SYNCH_CLIENT (KDATA_BASE_ADDR + 0x0038)
555 #define KDATA_HALT_SYNCH_DMA (KDATA_BASE_ADDR + 0x0039)
556 #define KDATA_HALT_ACKNOWLEDGE (KDATA_BASE_ADDR + 0x003A)
557
558 #define KDATA_ADC1_XFER0 (KDATA_BASE_ADDR + 0x003B)
559 #define KDATA_ADC1_XFER_ENDMARK (KDATA_BASE_ADDR + 0x003C)
560 #define KDATA_ADC1_LEFT_VOLUME (KDATA_BASE_ADDR + 0x003D)
561 #define KDATA_ADC1_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x003E)
562 #define KDATA_ADC1_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x003F)
563 #define KDATA_ADC1_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0040)
564
565 #define KDATA_ADC2_XFER0 (KDATA_BASE_ADDR + 0x0041)
566 #define KDATA_ADC2_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0042)
567 #define KDATA_ADC2_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0043)
568 #define KDATA_ADC2_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x0044)
569 #define KDATA_ADC2_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x0045)
570 #define KDATA_ADC2_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x0046)
571
572 #define KDATA_CD_XFER0 (KDATA_BASE_ADDR + 0x0047)
573 #define KDATA_CD_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0048)
574 #define KDATA_CD_LEFT_VOLUME (KDATA_BASE_ADDR + 0x0049)
575 #define KDATA_CD_RIGHT_VOLUME (KDATA_BASE_ADDR + 0x004A)
576 #define KDATA_CD_LEFT_SUR_VOL (KDATA_BASE_ADDR + 0x004B)
577 #define KDATA_CD_RIGHT_SUR_VOL (KDATA_BASE_ADDR + 0x004C)
578
579 #define KDATA_MIC_XFER0 (KDATA_BASE_ADDR + 0x004D)
580 #define KDATA_MIC_XFER_ENDMARK (KDATA_BASE_ADDR + 0x004E)
581 #define KDATA_MIC_VOLUME (KDATA_BASE_ADDR + 0x004F)
582 #define KDATA_MIC_SUR_VOL (KDATA_BASE_ADDR + 0x0050)
583
584 #define KDATA_I2S_XFER0 (KDATA_BASE_ADDR + 0x0051)
585 #define KDATA_I2S_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0052)
586
587 #define KDATA_CHI_XFER0 (KDATA_BASE_ADDR + 0x0053)
588 #define KDATA_CHI_XFER_ENDMARK (KDATA_BASE_ADDR + 0x0054)
589
590 #define KDATA_SPDIF_XFER (KDATA_BASE_ADDR + 0x0055)
591 #define KDATA_SPDIF_CURRENT_FRAME (KDATA_BASE_ADDR + 0x0056)
592 #define KDATA_SPDIF_FRAME0 (KDATA_BASE_ADDR + 0x0057)
593 #define KDATA_SPDIF_FRAME1 (KDATA_BASE_ADDR + 0x0058)
594 #define KDATA_SPDIF_FRAME2 (KDATA_BASE_ADDR + 0x0059)
595
596 #define KDATA_SPDIF_REQUEST (KDATA_BASE_ADDR + 0x005A)
597 #define KDATA_SPDIF_TEMP (KDATA_BASE_ADDR + 0x005B)
598
599 #define KDATA_SPDIFIN_XFER0 (KDATA_BASE_ADDR + 0x005C)
600 #define KDATA_SPDIFIN_XFER_ENDMARK (KDATA_BASE_ADDR + 0x005D)
601 #define KDATA_SPDIFIN_INT_METER (KDATA_BASE_ADDR + 0x005E)
602
603 #define KDATA_DSP_RESET_COUNT (KDATA_BASE_ADDR + 0x005F)
604 #define KDATA_DEBUG_OUTPUT (KDATA_BASE_ADDR + 0x0060)
605
606 #define KDATA_KERNEL_ISR_LIST (KDATA_BASE_ADDR + 0x0061)
607
608 #define KDATA_KERNEL_ISR_CBSR1 (KDATA_BASE_ADDR + 0x0062)
609 #define KDATA_KERNEL_ISR_CBER1 (KDATA_BASE_ADDR + 0x0063)
610 #define KDATA_KERNEL_ISR_CBCR (KDATA_BASE_ADDR + 0x0064)
611 #define KDATA_KERNEL_ISR_AR0 (KDATA_BASE_ADDR + 0x0065)
612 #define KDATA_KERNEL_ISR_AR1 (KDATA_BASE_ADDR + 0x0066)
613 #define KDATA_KERNEL_ISR_AR2 (KDATA_BASE_ADDR + 0x0067)
614 #define KDATA_KERNEL_ISR_AR3 (KDATA_BASE_ADDR + 0x0068)
615 #define KDATA_KERNEL_ISR_AR4 (KDATA_BASE_ADDR + 0x0069)
616 #define KDATA_KERNEL_ISR_AR5 (KDATA_BASE_ADDR + 0x006A)
617 #define KDATA_KERNEL_ISR_BRCR (KDATA_BASE_ADDR + 0x006B)
618 #define KDATA_KERNEL_ISR_PASR (KDATA_BASE_ADDR + 0x006C)
619 #define KDATA_KERNEL_ISR_PAER (KDATA_BASE_ADDR + 0x006D)
620
621 #define KDATA_CLIENT_SCRATCH0 (KDATA_BASE_ADDR + 0x006E)
622 #define KDATA_CLIENT_SCRATCH1 (KDATA_BASE_ADDR + 0x006F)
623 #define KDATA_KERNEL_SCRATCH (KDATA_BASE_ADDR + 0x0070)
624 #define KDATA_KERNEL_ISR_SCRATCH (KDATA_BASE_ADDR + 0x0071)
625
626 #define KDATA_OUEUE_LEFT (KDATA_BASE_ADDR + 0x0072)
627 #define KDATA_QUEUE_RIGHT (KDATA_BASE_ADDR + 0x0073)
628
629 #define KDATA_ADC1_REQUEST (KDATA_BASE_ADDR + 0x0074)
630 #define KDATA_ADC2_REQUEST (KDATA_BASE_ADDR + 0x0075)
631 #define KDATA_CD_REQUEST (KDATA_BASE_ADDR + 0x0076)
632 #define KDATA_MIC_REQUEST (KDATA_BASE_ADDR + 0x0077)
633
634 #define KDATA_ADC1_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0078)
635 #define KDATA_ADC2_MIXER_REQUEST (KDATA_BASE_ADDR + 0x0079)
636 #define KDATA_CD_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007A)
637 #define KDATA_MIC_MIXER_REQUEST (KDATA_BASE_ADDR + 0x007B)
638 #define KDATA_MIC_SYNC_COUNTER (KDATA_BASE_ADDR + 0x007C)
639
640 /*
641 * second 'segment' (?) reserved for mixer
642 * buffers..
643 */
644
645 #define KDATA_MIXER_WORD0 (KDATA_BASE_ADDR2 + 0x0000)
646 #define KDATA_MIXER_WORD1 (KDATA_BASE_ADDR2 + 0x0001)
647 #define KDATA_MIXER_WORD2 (KDATA_BASE_ADDR2 + 0x0002)
648 #define KDATA_MIXER_WORD3 (KDATA_BASE_ADDR2 + 0x0003)
649 #define KDATA_MIXER_WORD4 (KDATA_BASE_ADDR2 + 0x0004)
650 #define KDATA_MIXER_WORD5 (KDATA_BASE_ADDR2 + 0x0005)
651 #define KDATA_MIXER_WORD6 (KDATA_BASE_ADDR2 + 0x0006)
652 #define KDATA_MIXER_WORD7 (KDATA_BASE_ADDR2 + 0x0007)
653 #define KDATA_MIXER_WORD8 (KDATA_BASE_ADDR2 + 0x0008)
654 #define KDATA_MIXER_WORD9 (KDATA_BASE_ADDR2 + 0x0009)
655 #define KDATA_MIXER_WORDA (KDATA_BASE_ADDR2 + 0x000A)
656 #define KDATA_MIXER_WORDB (KDATA_BASE_ADDR2 + 0x000B)
657 #define KDATA_MIXER_WORDC (KDATA_BASE_ADDR2 + 0x000C)
658 #define KDATA_MIXER_WORDD (KDATA_BASE_ADDR2 + 0x000D)
659 #define KDATA_MIXER_WORDE (KDATA_BASE_ADDR2 + 0x000E)
660 #define KDATA_MIXER_WORDF (KDATA_BASE_ADDR2 + 0x000F)
661
662 #define KDATA_MIXER_XFER0 (KDATA_BASE_ADDR2 + 0x0010)
663 #define KDATA_MIXER_XFER1 (KDATA_BASE_ADDR2 + 0x0011)
664 #define KDATA_MIXER_XFER2 (KDATA_BASE_ADDR2 + 0x0012)
665 #define KDATA_MIXER_XFER3 (KDATA_BASE_ADDR2 + 0x0013)
666 #define KDATA_MIXER_XFER4 (KDATA_BASE_ADDR2 + 0x0014)
667 #define KDATA_MIXER_XFER5 (KDATA_BASE_ADDR2 + 0x0015)
668 #define KDATA_MIXER_XFER6 (KDATA_BASE_ADDR2 + 0x0016)
669 #define KDATA_MIXER_XFER7 (KDATA_BASE_ADDR2 + 0x0017)
670 #define KDATA_MIXER_XFER8 (KDATA_BASE_ADDR2 + 0x0018)
671 #define KDATA_MIXER_XFER9 (KDATA_BASE_ADDR2 + 0x0019)
672 #define KDATA_MIXER_XFER_ENDMARK (KDATA_BASE_ADDR2 + 0x001A)
673
674 #define KDATA_MIXER_TASK_NUMBER (KDATA_BASE_ADDR2 + 0x001B)
675 #define KDATA_CURRENT_MIXER (KDATA_BASE_ADDR2 + 0x001C)
676 #define KDATA_MIXER_ACTIVE (KDATA_BASE_ADDR2 + 0x001D)
677 #define KDATA_MIXER_BANK_STATUS (KDATA_BASE_ADDR2 + 0x001E)
678 #define KDATA_DAC_LEFT_VOLUME (KDATA_BASE_ADDR2 + 0x001F)
679 #define KDATA_DAC_RIGHT_VOLUME (KDATA_BASE_ADDR2 + 0x0020)
680
681 #define MAX_INSTANCE_MINISRC (KDATA_INSTANCE_MINISRC_ENDMARK - KDATA_INSTANCE0_MINISRC)
682 #define MAX_VIRTUAL_DMA_CHANNELS (KDATA_DMA_XFER_ENDMARK - KDATA_DMA_XFER0)
683 #define MAX_VIRTUAL_MIXER_CHANNELS (KDATA_MIXER_XFER_ENDMARK - KDATA_MIXER_XFER0)
684 #define MAX_VIRTUAL_ADC1_CHANNELS (KDATA_ADC1_XFER_ENDMARK - KDATA_ADC1_XFER0)
685
686 /*
687 * client data area offsets
688 */
689 #define CDATA_INSTANCE_READY 0x00
690
691 #define CDATA_HOST_SRC_ADDRL 0x01
692 #define CDATA_HOST_SRC_ADDRH 0x02
693 #define CDATA_HOST_SRC_END_PLUS_1L 0x03
694 #define CDATA_HOST_SRC_END_PLUS_1H 0x04
695 #define CDATA_HOST_SRC_CURRENTL 0x05
696 #define CDATA_HOST_SRC_CURRENTH 0x06
697
698 #define CDATA_IN_BUF_CONNECT 0x07
699 #define CDATA_OUT_BUF_CONNECT 0x08
700
701 #define CDATA_IN_BUF_BEGIN 0x09
702 #define CDATA_IN_BUF_END_PLUS_1 0x0A
703 #define CDATA_IN_BUF_HEAD 0x0B
704 #define CDATA_IN_BUF_TAIL 0x0C
705 #define CDATA_OUT_BUF_BEGIN 0x0D
706 #define CDATA_OUT_BUF_END_PLUS_1 0x0E
707 #define CDATA_OUT_BUF_HEAD 0x0F
708 #define CDATA_OUT_BUF_TAIL 0x10
709
710 #define CDATA_DMA_CONTROL 0x11
711 #define CDATA_RESERVED 0x12
712
713 #define CDATA_FREQUENCY 0x13
714 #define CDATA_LEFT_VOLUME 0x14
715 #define CDATA_RIGHT_VOLUME 0x15
716 #define CDATA_LEFT_SUR_VOL 0x16
717 #define CDATA_RIGHT_SUR_VOL 0x17
718
719 #define CDATA_HEADER_LEN 0x18
720
721 #define SRC3_DIRECTION_OFFSET CDATA_HEADER_LEN
722 #define SRC3_MODE_OFFSET (CDATA_HEADER_LEN + 1)
723 #define SRC3_WORD_LENGTH_OFFSET (CDATA_HEADER_LEN + 2)
724 #define SRC3_PARAMETER_OFFSET (CDATA_HEADER_LEN + 3)
725 #define SRC3_COEFF_ADDR_OFFSET (CDATA_HEADER_LEN + 8)
726 #define SRC3_FILTAP_ADDR_OFFSET (CDATA_HEADER_LEN + 10)
727 #define SRC3_TEMP_INBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 16)
728 #define SRC3_TEMP_OUTBUF_ADDR_OFFSET (CDATA_HEADER_LEN + 17)
729
730 #define MINISRC_IN_BUFFER_SIZE ( 0x50 * 2 )
731 #define MINISRC_OUT_BUFFER_SIZE ( 0x50 * 2 * 2)
732 #define MINISRC_TMP_BUFFER_SIZE ( 112 + ( MINISRC_BIQUAD_STAGE * 3 + 4 ) * 2 * 2 )
733 #define MINISRC_BIQUAD_STAGE 2
734 #define MINISRC_COEF_LOC 0x175
735
736 #define DMACONTROL_BLOCK_MASK 0x000F
737 #define DMAC_BLOCK0_SELECTOR 0x0000
738 #define DMAC_BLOCK1_SELECTOR 0x0001
739 #define DMAC_BLOCK2_SELECTOR 0x0002
740 #define DMAC_BLOCK3_SELECTOR 0x0003
741 #define DMAC_BLOCK4_SELECTOR 0x0004
742 #define DMAC_BLOCK5_SELECTOR 0x0005
743 #define DMAC_BLOCK6_SELECTOR 0x0006
744 #define DMAC_BLOCK7_SELECTOR 0x0007
745 #define DMAC_BLOCK8_SELECTOR 0x0008
746 #define DMAC_BLOCK9_SELECTOR 0x0009
747 #define DMAC_BLOCKA_SELECTOR 0x000A
748 #define DMAC_BLOCKB_SELECTOR 0x000B
749 #define DMAC_BLOCKC_SELECTOR 0x000C
750 #define DMAC_BLOCKD_SELECTOR 0x000D
751 #define DMAC_BLOCKE_SELECTOR 0x000E
752 #define DMAC_BLOCKF_SELECTOR 0x000F
753 #define DMACONTROL_PAGE_MASK 0x00F0
754 #define DMAC_PAGE0_SELECTOR 0x0030
755 #define DMAC_PAGE1_SELECTOR 0x0020
756 #define DMAC_PAGE2_SELECTOR 0x0010
757 #define DMAC_PAGE3_SELECTOR 0x0000
758 #define DMACONTROL_AUTOREPEAT 0x1000
759 #define DMACONTROL_STOPPED 0x2000
760 #define DMACONTROL_DIRECTION 0x0100
761
762 /*
763 * an arbitrary volume we set the internal
764 * volume settings to so that the ac97 volume
765 * range is a little less insane. 0x7fff is
766 * max.
767 */
768 #define ARB_VOLUME ( 0x6800 )
769
770 /*
771 */
772
773 struct m3_list {
774 int curlen;
775 int mem_addr;
776 int max;
777 };
778
779 struct m3_dma {
780
781 int number;
782 struct snd_pcm_substream *substream;
783
784 struct assp_instance {
785 unsigned short code, data;
786 } inst;
787
788 int running;
789 int opened;
790
791 unsigned long buffer_addr;
792 int dma_size;
793 int period_size;
794 unsigned int hwptr;
795 int count;
796
797 int index[3];
798 struct m3_list *index_list[3];
799
800 int in_lists;
801
802 struct list_head list;
803
804 };
805
806 struct snd_m3 {
807
808 struct snd_card *card;
809
810 unsigned long iobase;
811
812 int irq;
813 unsigned int allegro_flag : 1;
814
815 struct snd_ac97 *ac97;
816
817 struct snd_pcm *pcm;
818
819 struct pci_dev *pci;
820
821 int dacs_active;
822 int timer_users;
823
824 struct m3_list msrc_list;
825 struct m3_list mixer_list;
826 struct m3_list adc1_list;
827 struct m3_list dma_list;
828
829 /* for storing reset state..*/
830 u8 reset_state;
831
832 int external_amp;
833 int amp_gpio; /* gpio pin # for external amp, -1 = default */
834 unsigned int hv_config; /* hardware-volume config bits */
835 unsigned irda_workaround :1; /* avoid to touch 0x10 on GPIO_DIRECTION
836 (e.g. for IrDA on Dell Inspirons) */
837 unsigned is_omnibook :1; /* Do HP OmniBook GPIO magic? */
838
839 /* midi */
840 struct snd_rawmidi *rmidi;
841
842 /* pcm streams */
843 int num_substreams;
844 struct m3_dma *substreams;
845
846 spinlock_t reg_lock;
847 spinlock_t ac97_lock;
848
849 struct snd_kcontrol *master_switch;
850 struct snd_kcontrol *master_volume;
851 struct tasklet_struct hwvol_tq;
852
853 #ifdef CONFIG_PM
854 u16 *suspend_mem;
855 #endif
856
857 const struct firmware *assp_kernel_image;
858 const struct firmware *assp_minisrc_image;
859 };
860
861 /*
862 * pci ids
863 */
864 static struct pci_device_id snd_m3_ids[] = {
865 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO_1, PCI_ANY_ID, PCI_ANY_ID,
866 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
867 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_ALLEGRO, PCI_ANY_ID, PCI_ANY_ID,
868 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
869 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2LE, PCI_ANY_ID, PCI_ANY_ID,
870 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
871 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_CANYON3D_2, PCI_ANY_ID, PCI_ANY_ID,
872 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
873 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3, PCI_ANY_ID, PCI_ANY_ID,
874 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
875 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_1, PCI_ANY_ID, PCI_ANY_ID,
876 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
877 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_HW, PCI_ANY_ID, PCI_ANY_ID,
878 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
879 {PCI_VENDOR_ID_ESS, PCI_DEVICE_ID_ESS_MAESTRO3_2, PCI_ANY_ID, PCI_ANY_ID,
880 PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0},
881 {0,},
882 };
883
884 MODULE_DEVICE_TABLE(pci, snd_m3_ids);
885
886 static struct snd_pci_quirk m3_amp_quirk_list[] __devinitdata = {
887 SND_PCI_QUIRK(0x10f7, 0x833e, "Panasonic CF-28", 0x0d),
888 SND_PCI_QUIRK(0x10f7, 0x833d, "Panasonic CF-72", 0x0d),
889 SND_PCI_QUIRK(0x1033, 0x80f1, "NEC LM800J/7", 0x03),
890 SND_PCI_QUIRK(0x1509, 0x1740, "LEGEND ZhaoYang 3100CF", 0x03),
891 { } /* END */
892 };
893
894 static struct snd_pci_quirk m3_irda_quirk_list[] __devinitdata = {
895 SND_PCI_QUIRK(0x1028, 0x00b0, "Dell Inspiron 4000", 1),
896 SND_PCI_QUIRK(0x1028, 0x00a4, "Dell Inspiron 8000", 1),
897 SND_PCI_QUIRK(0x1028, 0x00e6, "Dell Inspiron 8100", 1),
898 { } /* END */
899 };
900
901 /* hardware volume quirks */
902 static struct snd_pci_quirk m3_hv_quirk_list[] __devinitdata = {
903 /* Allegro chips */
904 SND_PCI_QUIRK(0x0E11, 0x002E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
905 SND_PCI_QUIRK(0x0E11, 0x0094, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
906 SND_PCI_QUIRK(0x0E11, 0xB112, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
907 SND_PCI_QUIRK(0x0E11, 0xB114, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
908 SND_PCI_QUIRK(0x103C, 0x0012, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
909 SND_PCI_QUIRK(0x103C, 0x0018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
910 SND_PCI_QUIRK(0x103C, 0x001C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
911 SND_PCI_QUIRK(0x103C, 0x001D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
912 SND_PCI_QUIRK(0x103C, 0x001E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
913 SND_PCI_QUIRK(0x107B, 0x3350, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
914 SND_PCI_QUIRK(0x10F7, 0x8338, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
915 SND_PCI_QUIRK(0x10F7, 0x833C, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
916 SND_PCI_QUIRK(0x10F7, 0x833D, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
917 SND_PCI_QUIRK(0x10F7, 0x833E, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
918 SND_PCI_QUIRK(0x10F7, 0x833F, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
919 SND_PCI_QUIRK(0x13BD, 0x1018, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
920 SND_PCI_QUIRK(0x13BD, 0x1019, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
921 SND_PCI_QUIRK(0x13BD, 0x101A, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
922 SND_PCI_QUIRK(0x14FF, 0x0F03, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
923 SND_PCI_QUIRK(0x14FF, 0x0F04, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
924 SND_PCI_QUIRK(0x14FF, 0x0F05, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
925 SND_PCI_QUIRK(0x156D, 0xB400, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
926 SND_PCI_QUIRK(0x156D, 0xB795, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
927 SND_PCI_QUIRK(0x156D, 0xB797, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
928 SND_PCI_QUIRK(0x156D, 0xC700, NULL, HV_CTRL_ENABLE | HV_BUTTON_FROM_GD),
929 SND_PCI_QUIRK(0x1033, 0x80F1, NULL,
930 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
931 SND_PCI_QUIRK(0x103C, 0x001A, NULL, /* HP OmniBook 6100 */
932 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
933 SND_PCI_QUIRK(0x107B, 0x340A, NULL,
934 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
935 SND_PCI_QUIRK(0x107B, 0x3450, NULL,
936 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
937 SND_PCI_QUIRK(0x109F, 0x3134, NULL,
938 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
939 SND_PCI_QUIRK(0x109F, 0x3161, NULL,
940 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
941 SND_PCI_QUIRK(0x144D, 0x3280, NULL,
942 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
943 SND_PCI_QUIRK(0x144D, 0x3281, NULL,
944 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
945 SND_PCI_QUIRK(0x144D, 0xC002, NULL,
946 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
947 SND_PCI_QUIRK(0x144D, 0xC003, NULL,
948 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
949 SND_PCI_QUIRK(0x1509, 0x1740, NULL,
950 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
951 SND_PCI_QUIRK(0x1610, 0x0010, NULL,
952 HV_CTRL_ENABLE | HV_BUTTON_FROM_GD | REDUCED_DEBOUNCE),
953 SND_PCI_QUIRK(0x1042, 0x1042, NULL, HV_CTRL_ENABLE),
954 SND_PCI_QUIRK(0x107B, 0x9500, NULL, HV_CTRL_ENABLE),
955 SND_PCI_QUIRK(0x14FF, 0x0F06, NULL, HV_CTRL_ENABLE),
956 SND_PCI_QUIRK(0x1558, 0x8586, NULL, HV_CTRL_ENABLE),
957 SND_PCI_QUIRK(0x161F, 0x2011, NULL, HV_CTRL_ENABLE),
958 /* Maestro3 chips */
959 SND_PCI_QUIRK(0x103C, 0x000E, NULL, HV_CTRL_ENABLE),
960 SND_PCI_QUIRK(0x103C, 0x0010, NULL, HV_CTRL_ENABLE),
961 SND_PCI_QUIRK(0x103C, 0x0011, NULL, HV_CTRL_ENABLE),
962 SND_PCI_QUIRK(0x103C, 0x001B, NULL, HV_CTRL_ENABLE),
963 SND_PCI_QUIRK(0x104D, 0x80A6, NULL, HV_CTRL_ENABLE),
964 SND_PCI_QUIRK(0x104D, 0x80AA, NULL, HV_CTRL_ENABLE),
965 SND_PCI_QUIRK(0x107B, 0x5300, NULL, HV_CTRL_ENABLE),
966 SND_PCI_QUIRK(0x110A, 0x1998, NULL, HV_CTRL_ENABLE),
967 SND_PCI_QUIRK(0x13BD, 0x1015, NULL, HV_CTRL_ENABLE),
968 SND_PCI_QUIRK(0x13BD, 0x101C, NULL, HV_CTRL_ENABLE),
969 SND_PCI_QUIRK(0x13BD, 0x1802, NULL, HV_CTRL_ENABLE),
970 SND_PCI_QUIRK(0x1599, 0x0715, NULL, HV_CTRL_ENABLE),
971 SND_PCI_QUIRK(0x5643, 0x5643, NULL, HV_CTRL_ENABLE),
972 SND_PCI_QUIRK(0x144D, 0x3260, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
973 SND_PCI_QUIRK(0x144D, 0x3261, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
974 SND_PCI_QUIRK(0x144D, 0xC000, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
975 SND_PCI_QUIRK(0x144D, 0xC001, NULL, HV_CTRL_ENABLE | REDUCED_DEBOUNCE),
976 { } /* END */
977 };
978
979 /* HP Omnibook quirks */
980 static struct snd_pci_quirk m3_omnibook_quirk_list[] __devinitdata = {
981 SND_PCI_QUIRK_ID(0x103c, 0x0010), /* HP OmniBook 6000 */
982 SND_PCI_QUIRK_ID(0x103c, 0x0011), /* HP OmniBook 500 */
983 { } /* END */
984 };
985
986 /*
987 * lowlevel functions
988 */
989
990 static inline void snd_m3_outw(struct snd_m3 *chip, u16 value, unsigned long reg)
991 {
992 outw(value, chip->iobase + reg);
993 }
994
995 static inline u16 snd_m3_inw(struct snd_m3 *chip, unsigned long reg)
996 {
997 return inw(chip->iobase + reg);
998 }
999
1000 static inline void snd_m3_outb(struct snd_m3 *chip, u8 value, unsigned long reg)
1001 {
1002 outb(value, chip->iobase + reg);
1003 }
1004
1005 static inline u8 snd_m3_inb(struct snd_m3 *chip, unsigned long reg)
1006 {
1007 return inb(chip->iobase + reg);
1008 }
1009
1010 /*
1011 * access 16bit words to the code or data regions of the dsp's memory.
1012 * index addresses 16bit words.
1013 */
1014 static u16 snd_m3_assp_read(struct snd_m3 *chip, u16 region, u16 index)
1015 {
1016 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1017 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1018 return snd_m3_inw(chip, DSP_PORT_MEMORY_DATA);
1019 }
1020
1021 static void snd_m3_assp_write(struct snd_m3 *chip, u16 region, u16 index, u16 data)
1022 {
1023 snd_m3_outw(chip, region & MEMTYPE_MASK, DSP_PORT_MEMORY_TYPE);
1024 snd_m3_outw(chip, index, DSP_PORT_MEMORY_INDEX);
1025 snd_m3_outw(chip, data, DSP_PORT_MEMORY_DATA);
1026 }
1027
1028 static void snd_m3_assp_halt(struct snd_m3 *chip)
1029 {
1030 chip->reset_state = snd_m3_inb(chip, DSP_PORT_CONTROL_REG_B) & ~REGB_STOP_CLOCK;
1031 msleep(10);
1032 snd_m3_outb(chip, chip->reset_state & ~REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1033 }
1034
1035 static void snd_m3_assp_continue(struct snd_m3 *chip)
1036 {
1037 snd_m3_outb(chip, chip->reset_state | REGB_ENABLE_RESET, DSP_PORT_CONTROL_REG_B);
1038 }
1039
1040
1041 /*
1042 * This makes me sad. the maestro3 has lists
1043 * internally that must be packed.. 0 terminates,
1044 * apparently, or maybe all unused entries have
1045 * to be 0, the lists have static lengths set
1046 * by the binary code images.
1047 */
1048
1049 static int snd_m3_add_list(struct snd_m3 *chip, struct m3_list *list, u16 val)
1050 {
1051 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1052 list->mem_addr + list->curlen,
1053 val);
1054 return list->curlen++;
1055 }
1056
1057 static void snd_m3_remove_list(struct snd_m3 *chip, struct m3_list *list, int index)
1058 {
1059 u16 val;
1060 int lastindex = list->curlen - 1;
1061
1062 if (index != lastindex) {
1063 val = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1064 list->mem_addr + lastindex);
1065 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1066 list->mem_addr + index,
1067 val);
1068 }
1069
1070 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1071 list->mem_addr + lastindex,
1072 0);
1073
1074 list->curlen--;
1075 }
1076
1077 static void snd_m3_inc_timer_users(struct snd_m3 *chip)
1078 {
1079 chip->timer_users++;
1080 if (chip->timer_users != 1)
1081 return;
1082
1083 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1084 KDATA_TIMER_COUNT_RELOAD,
1085 240);
1086
1087 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1088 KDATA_TIMER_COUNT_CURRENT,
1089 240);
1090
1091 snd_m3_outw(chip,
1092 snd_m3_inw(chip, HOST_INT_CTRL) | CLKRUN_GEN_ENABLE,
1093 HOST_INT_CTRL);
1094 }
1095
1096 static void snd_m3_dec_timer_users(struct snd_m3 *chip)
1097 {
1098 chip->timer_users--;
1099 if (chip->timer_users > 0)
1100 return;
1101
1102 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1103 KDATA_TIMER_COUNT_RELOAD,
1104 0);
1105
1106 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1107 KDATA_TIMER_COUNT_CURRENT,
1108 0);
1109
1110 snd_m3_outw(chip,
1111 snd_m3_inw(chip, HOST_INT_CTRL) & ~CLKRUN_GEN_ENABLE,
1112 HOST_INT_CTRL);
1113 }
1114
1115 /*
1116 * start/stop
1117 */
1118
1119 /* spinlock held! */
1120 static int snd_m3_pcm_start(struct snd_m3 *chip, struct m3_dma *s,
1121 struct snd_pcm_substream *subs)
1122 {
1123 if (! s || ! subs)
1124 return -EINVAL;
1125
1126 snd_m3_inc_timer_users(chip);
1127 switch (subs->stream) {
1128 case SNDRV_PCM_STREAM_PLAYBACK:
1129 chip->dacs_active++;
1130 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1131 s->inst.data + CDATA_INSTANCE_READY, 1);
1132 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1133 KDATA_MIXER_TASK_NUMBER,
1134 chip->dacs_active);
1135 break;
1136 case SNDRV_PCM_STREAM_CAPTURE:
1137 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1138 KDATA_ADC1_REQUEST, 1);
1139 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1140 s->inst.data + CDATA_INSTANCE_READY, 1);
1141 break;
1142 }
1143 return 0;
1144 }
1145
1146 /* spinlock held! */
1147 static int snd_m3_pcm_stop(struct snd_m3 *chip, struct m3_dma *s,
1148 struct snd_pcm_substream *subs)
1149 {
1150 if (! s || ! subs)
1151 return -EINVAL;
1152
1153 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1154 s->inst.data + CDATA_INSTANCE_READY, 0);
1155 snd_m3_dec_timer_users(chip);
1156 switch (subs->stream) {
1157 case SNDRV_PCM_STREAM_PLAYBACK:
1158 chip->dacs_active--;
1159 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1160 KDATA_MIXER_TASK_NUMBER,
1161 chip->dacs_active);
1162 break;
1163 case SNDRV_PCM_STREAM_CAPTURE:
1164 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1165 KDATA_ADC1_REQUEST, 0);
1166 break;
1167 }
1168 return 0;
1169 }
1170
1171 static int
1172 snd_m3_pcm_trigger(struct snd_pcm_substream *subs, int cmd)
1173 {
1174 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1175 struct m3_dma *s = subs->runtime->private_data;
1176 int err = -EINVAL;
1177
1178 if (snd_BUG_ON(!s))
1179 return -ENXIO;
1180
1181 spin_lock(&chip->reg_lock);
1182 switch (cmd) {
1183 case SNDRV_PCM_TRIGGER_START:
1184 case SNDRV_PCM_TRIGGER_RESUME:
1185 if (s->running)
1186 err = -EBUSY;
1187 else {
1188 s->running = 1;
1189 err = snd_m3_pcm_start(chip, s, subs);
1190 }
1191 break;
1192 case SNDRV_PCM_TRIGGER_STOP:
1193 case SNDRV_PCM_TRIGGER_SUSPEND:
1194 if (! s->running)
1195 err = 0; /* should return error? */
1196 else {
1197 s->running = 0;
1198 err = snd_m3_pcm_stop(chip, s, subs);
1199 }
1200 break;
1201 }
1202 spin_unlock(&chip->reg_lock);
1203 return err;
1204 }
1205
1206 /*
1207 * setup
1208 */
1209 static void
1210 snd_m3_pcm_setup1(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1211 {
1212 int dsp_in_size, dsp_out_size, dsp_in_buffer, dsp_out_buffer;
1213 struct snd_pcm_runtime *runtime = subs->runtime;
1214
1215 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1216 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
1217 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
1218 } else {
1219 dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x10 * 2);
1220 dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
1221 }
1222 dsp_in_buffer = s->inst.data + (MINISRC_TMP_BUFFER_SIZE / 2);
1223 dsp_out_buffer = dsp_in_buffer + (dsp_in_size / 2) + 1;
1224
1225 s->dma_size = frames_to_bytes(runtime, runtime->buffer_size);
1226 s->period_size = frames_to_bytes(runtime, runtime->period_size);
1227 s->hwptr = 0;
1228 s->count = 0;
1229
1230 #define LO(x) ((x) & 0xffff)
1231 #define HI(x) LO((x) >> 16)
1232
1233 /* host dma buffer pointers */
1234 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1235 s->inst.data + CDATA_HOST_SRC_ADDRL,
1236 LO(s->buffer_addr));
1237
1238 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1239 s->inst.data + CDATA_HOST_SRC_ADDRH,
1240 HI(s->buffer_addr));
1241
1242 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1243 s->inst.data + CDATA_HOST_SRC_END_PLUS_1L,
1244 LO(s->buffer_addr + s->dma_size));
1245
1246 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1247 s->inst.data + CDATA_HOST_SRC_END_PLUS_1H,
1248 HI(s->buffer_addr + s->dma_size));
1249
1250 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1251 s->inst.data + CDATA_HOST_SRC_CURRENTL,
1252 LO(s->buffer_addr));
1253
1254 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1255 s->inst.data + CDATA_HOST_SRC_CURRENTH,
1256 HI(s->buffer_addr));
1257 #undef LO
1258 #undef HI
1259
1260 /* dsp buffers */
1261
1262 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1263 s->inst.data + CDATA_IN_BUF_BEGIN,
1264 dsp_in_buffer);
1265
1266 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1267 s->inst.data + CDATA_IN_BUF_END_PLUS_1,
1268 dsp_in_buffer + (dsp_in_size / 2));
1269
1270 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1271 s->inst.data + CDATA_IN_BUF_HEAD,
1272 dsp_in_buffer);
1273
1274 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1275 s->inst.data + CDATA_IN_BUF_TAIL,
1276 dsp_in_buffer);
1277
1278 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1279 s->inst.data + CDATA_OUT_BUF_BEGIN,
1280 dsp_out_buffer);
1281
1282 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1283 s->inst.data + CDATA_OUT_BUF_END_PLUS_1,
1284 dsp_out_buffer + (dsp_out_size / 2));
1285
1286 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1287 s->inst.data + CDATA_OUT_BUF_HEAD,
1288 dsp_out_buffer);
1289
1290 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1291 s->inst.data + CDATA_OUT_BUF_TAIL,
1292 dsp_out_buffer);
1293 }
1294
1295 static void snd_m3_pcm_setup2(struct snd_m3 *chip, struct m3_dma *s,
1296 struct snd_pcm_runtime *runtime)
1297 {
1298 u32 freq;
1299
1300 /*
1301 * put us in the lists if we're not already there
1302 */
1303 if (! s->in_lists) {
1304 s->index[0] = snd_m3_add_list(chip, s->index_list[0],
1305 s->inst.data >> DP_SHIFT_COUNT);
1306 s->index[1] = snd_m3_add_list(chip, s->index_list[1],
1307 s->inst.data >> DP_SHIFT_COUNT);
1308 s->index[2] = snd_m3_add_list(chip, s->index_list[2],
1309 s->inst.data >> DP_SHIFT_COUNT);
1310 s->in_lists = 1;
1311 }
1312
1313 /* write to 'mono' word */
1314 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1315 s->inst.data + SRC3_DIRECTION_OFFSET + 1,
1316 runtime->channels == 2 ? 0 : 1);
1317 /* write to '8bit' word */
1318 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1319 s->inst.data + SRC3_DIRECTION_OFFSET + 2,
1320 snd_pcm_format_width(runtime->format) == 16 ? 0 : 1);
1321
1322 /* set up dac/adc rate */
1323 freq = ((runtime->rate << 15) + 24000 ) / 48000;
1324 if (freq)
1325 freq--;
1326
1327 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1328 s->inst.data + CDATA_FREQUENCY,
1329 freq);
1330 }
1331
1332
1333 static const struct play_vals {
1334 u16 addr, val;
1335 } pv[] = {
1336 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1337 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1338 {SRC3_DIRECTION_OFFSET, 0} ,
1339 /* +1, +2 are stereo/16 bit */
1340 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1341 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1342 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1343 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1344 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1345 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1346 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1347 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1348 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1349 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1350 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1351 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1352 {SRC3_DIRECTION_OFFSET + 16, 8}, /* numin */
1353 {SRC3_DIRECTION_OFFSET + 17, 50*2}, /* numout */
1354 {SRC3_DIRECTION_OFFSET + 18, MINISRC_BIQUAD_STAGE - 1}, /* numstage */
1355 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1356 {SRC3_DIRECTION_OFFSET + 21, 0} /* booster */
1357 };
1358
1359
1360 /* the mode passed should be already shifted and masked */
1361 static void
1362 snd_m3_playback_setup(struct snd_m3 *chip, struct m3_dma *s,
1363 struct snd_pcm_substream *subs)
1364 {
1365 unsigned int i;
1366
1367 /*
1368 * some per client initializers
1369 */
1370
1371 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1372 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1373 s->inst.data + 40 + 8);
1374
1375 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1376 s->inst.data + SRC3_DIRECTION_OFFSET + 19,
1377 s->inst.code + MINISRC_COEF_LOC);
1378
1379 /* enable or disable low pass filter? */
1380 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1381 s->inst.data + SRC3_DIRECTION_OFFSET + 22,
1382 subs->runtime->rate > 45000 ? 0xff : 0);
1383
1384 /* tell it which way dma is going? */
1385 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1386 s->inst.data + CDATA_DMA_CONTROL,
1387 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1388
1389 /*
1390 * set an armload of static initializers
1391 */
1392 for (i = 0; i < ARRAY_SIZE(pv); i++)
1393 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1394 s->inst.data + pv[i].addr, pv[i].val);
1395 }
1396
1397 /*
1398 * Native record driver
1399 */
1400 static const struct rec_vals {
1401 u16 addr, val;
1402 } rv[] = {
1403 {CDATA_LEFT_VOLUME, ARB_VOLUME},
1404 {CDATA_RIGHT_VOLUME, ARB_VOLUME},
1405 {SRC3_DIRECTION_OFFSET, 1} ,
1406 /* +1, +2 are stereo/16 bit */
1407 {SRC3_DIRECTION_OFFSET + 3, 0x0000}, /* fraction? */
1408 {SRC3_DIRECTION_OFFSET + 4, 0}, /* first l */
1409 {SRC3_DIRECTION_OFFSET + 5, 0}, /* first r */
1410 {SRC3_DIRECTION_OFFSET + 6, 0}, /* second l */
1411 {SRC3_DIRECTION_OFFSET + 7, 0}, /* second r */
1412 {SRC3_DIRECTION_OFFSET + 8, 0}, /* delta l */
1413 {SRC3_DIRECTION_OFFSET + 9, 0}, /* delta r */
1414 {SRC3_DIRECTION_OFFSET + 10, 0x8000}, /* round */
1415 {SRC3_DIRECTION_OFFSET + 11, 0xFF00}, /* higher bute mark */
1416 {SRC3_DIRECTION_OFFSET + 13, 0}, /* temp0 */
1417 {SRC3_DIRECTION_OFFSET + 14, 0}, /* c fraction */
1418 {SRC3_DIRECTION_OFFSET + 15, 0}, /* counter */
1419 {SRC3_DIRECTION_OFFSET + 16, 50},/* numin */
1420 {SRC3_DIRECTION_OFFSET + 17, 8}, /* numout */
1421 {SRC3_DIRECTION_OFFSET + 18, 0}, /* numstage */
1422 {SRC3_DIRECTION_OFFSET + 19, 0}, /* coef */
1423 {SRC3_DIRECTION_OFFSET + 20, 0}, /* filtertap */
1424 {SRC3_DIRECTION_OFFSET + 21, 0}, /* booster */
1425 {SRC3_DIRECTION_OFFSET + 22, 0xff} /* skip lpf */
1426 };
1427
1428 static void
1429 snd_m3_capture_setup(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1430 {
1431 unsigned int i;
1432
1433 /*
1434 * some per client initializers
1435 */
1436
1437 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1438 s->inst.data + SRC3_DIRECTION_OFFSET + 12,
1439 s->inst.data + 40 + 8);
1440
1441 /* tell it which way dma is going? */
1442 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1443 s->inst.data + CDATA_DMA_CONTROL,
1444 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
1445 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
1446
1447 /*
1448 * set an armload of static initializers
1449 */
1450 for (i = 0; i < ARRAY_SIZE(rv); i++)
1451 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
1452 s->inst.data + rv[i].addr, rv[i].val);
1453 }
1454
1455 static int snd_m3_pcm_hw_params(struct snd_pcm_substream *substream,
1456 struct snd_pcm_hw_params *hw_params)
1457 {
1458 struct m3_dma *s = substream->runtime->private_data;
1459 int err;
1460
1461 if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
1462 return err;
1463 /* set buffer address */
1464 s->buffer_addr = substream->runtime->dma_addr;
1465 if (s->buffer_addr & 0x3) {
1466 snd_printk(KERN_ERR "oh my, not aligned\n");
1467 s->buffer_addr = s->buffer_addr & ~0x3;
1468 }
1469 return 0;
1470 }
1471
1472 static int snd_m3_pcm_hw_free(struct snd_pcm_substream *substream)
1473 {
1474 struct m3_dma *s;
1475
1476 if (substream->runtime->private_data == NULL)
1477 return 0;
1478 s = substream->runtime->private_data;
1479 snd_pcm_lib_free_pages(substream);
1480 s->buffer_addr = 0;
1481 return 0;
1482 }
1483
1484 static int
1485 snd_m3_pcm_prepare(struct snd_pcm_substream *subs)
1486 {
1487 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1488 struct snd_pcm_runtime *runtime = subs->runtime;
1489 struct m3_dma *s = runtime->private_data;
1490
1491 if (snd_BUG_ON(!s))
1492 return -ENXIO;
1493
1494 if (runtime->format != SNDRV_PCM_FORMAT_U8 &&
1495 runtime->format != SNDRV_PCM_FORMAT_S16_LE)
1496 return -EINVAL;
1497 if (runtime->rate > 48000 ||
1498 runtime->rate < 8000)
1499 return -EINVAL;
1500
1501 spin_lock_irq(&chip->reg_lock);
1502
1503 snd_m3_pcm_setup1(chip, s, subs);
1504
1505 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK)
1506 snd_m3_playback_setup(chip, s, subs);
1507 else
1508 snd_m3_capture_setup(chip, s, subs);
1509
1510 snd_m3_pcm_setup2(chip, s, runtime);
1511
1512 spin_unlock_irq(&chip->reg_lock);
1513
1514 return 0;
1515 }
1516
1517 /*
1518 * get current pointer
1519 */
1520 static unsigned int
1521 snd_m3_get_pointer(struct snd_m3 *chip, struct m3_dma *s, struct snd_pcm_substream *subs)
1522 {
1523 u16 hi = 0, lo = 0;
1524 int retry = 10;
1525 u32 addr;
1526
1527 /*
1528 * try and get a valid answer
1529 */
1530 while (retry--) {
1531 hi = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1532 s->inst.data + CDATA_HOST_SRC_CURRENTH);
1533
1534 lo = snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1535 s->inst.data + CDATA_HOST_SRC_CURRENTL);
1536
1537 if (hi == snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA,
1538 s->inst.data + CDATA_HOST_SRC_CURRENTH))
1539 break;
1540 }
1541 addr = lo | ((u32)hi<<16);
1542 return (unsigned int)(addr - s->buffer_addr);
1543 }
1544
1545 static snd_pcm_uframes_t
1546 snd_m3_pcm_pointer(struct snd_pcm_substream *subs)
1547 {
1548 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1549 unsigned int ptr;
1550 struct m3_dma *s = subs->runtime->private_data;
1551
1552 if (snd_BUG_ON(!s))
1553 return 0;
1554
1555 spin_lock(&chip->reg_lock);
1556 ptr = snd_m3_get_pointer(chip, s, subs);
1557 spin_unlock(&chip->reg_lock);
1558 return bytes_to_frames(subs->runtime, ptr);
1559 }
1560
1561
1562 /* update pointer */
1563 /* spinlock held! */
1564 static void snd_m3_update_ptr(struct snd_m3 *chip, struct m3_dma *s)
1565 {
1566 struct snd_pcm_substream *subs = s->substream;
1567 unsigned int hwptr;
1568 int diff;
1569
1570 if (! s->running)
1571 return;
1572
1573 hwptr = snd_m3_get_pointer(chip, s, subs);
1574
1575 /* try to avoid expensive modulo divisions */
1576 if (hwptr >= s->dma_size)
1577 hwptr %= s->dma_size;
1578
1579 diff = s->dma_size + hwptr - s->hwptr;
1580 if (diff >= s->dma_size)
1581 diff %= s->dma_size;
1582
1583 s->hwptr = hwptr;
1584 s->count += diff;
1585
1586 if (s->count >= (signed)s->period_size) {
1587
1588 if (s->count < 2 * (signed)s->period_size)
1589 s->count -= (signed)s->period_size;
1590 else
1591 s->count %= s->period_size;
1592
1593 spin_unlock(&chip->reg_lock);
1594 snd_pcm_period_elapsed(subs);
1595 spin_lock(&chip->reg_lock);
1596 }
1597 }
1598
1599 static void snd_m3_update_hw_volume(unsigned long private_data)
1600 {
1601 struct snd_m3 *chip = (struct snd_m3 *) private_data;
1602 int x, val;
1603 unsigned long flags;
1604
1605 /* Figure out which volume control button was pushed,
1606 based on differences from the default register
1607 values. */
1608 x = inb(chip->iobase + SHADOW_MIX_REG_VOICE) & 0xee;
1609
1610 /* Reset the volume control registers. */
1611 outb(0x88, chip->iobase + SHADOW_MIX_REG_VOICE);
1612 outb(0x88, chip->iobase + HW_VOL_COUNTER_VOICE);
1613 outb(0x88, chip->iobase + SHADOW_MIX_REG_MASTER);
1614 outb(0x88, chip->iobase + HW_VOL_COUNTER_MASTER);
1615
1616 if (!chip->master_switch || !chip->master_volume)
1617 return;
1618
1619 /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
1620 spin_lock_irqsave(&chip->ac97_lock, flags);
1621
1622 val = chip->ac97->regs[AC97_MASTER_VOL];
1623 switch (x) {
1624 case 0x88:
1625 /* mute */
1626 val ^= 0x8000;
1627 chip->ac97->regs[AC97_MASTER_VOL] = val;
1628 outw(val, chip->iobase + CODEC_DATA);
1629 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1630 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1631 &chip->master_switch->id);
1632 break;
1633 case 0xaa:
1634 /* volume up */
1635 if ((val & 0x7f) > 0)
1636 val--;
1637 if ((val & 0x7f00) > 0)
1638 val -= 0x0100;
1639 chip->ac97->regs[AC97_MASTER_VOL] = val;
1640 outw(val, chip->iobase + CODEC_DATA);
1641 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1642 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1643 &chip->master_volume->id);
1644 break;
1645 case 0x66:
1646 /* volume down */
1647 if ((val & 0x7f) < 0x1f)
1648 val++;
1649 if ((val & 0x7f00) < 0x1f00)
1650 val += 0x0100;
1651 chip->ac97->regs[AC97_MASTER_VOL] = val;
1652 outw(val, chip->iobase + CODEC_DATA);
1653 outb(AC97_MASTER_VOL, chip->iobase + CODEC_COMMAND);
1654 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1655 &chip->master_volume->id);
1656 break;
1657 }
1658 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1659 }
1660
1661 static irqreturn_t snd_m3_interrupt(int irq, void *dev_id)
1662 {
1663 struct snd_m3 *chip = dev_id;
1664 u8 status;
1665 int i;
1666
1667 status = inb(chip->iobase + HOST_INT_STATUS);
1668
1669 if (status == 0xff)
1670 return IRQ_NONE;
1671
1672 if (status & HV_INT_PENDING)
1673 tasklet_schedule(&chip->hwvol_tq);
1674
1675 /*
1676 * ack an assp int if its running
1677 * and has an int pending
1678 */
1679 if (status & ASSP_INT_PENDING) {
1680 u8 ctl = inb(chip->iobase + ASSP_CONTROL_B);
1681 if (!(ctl & STOP_ASSP_CLOCK)) {
1682 ctl = inb(chip->iobase + ASSP_HOST_INT_STATUS);
1683 if (ctl & DSP2HOST_REQ_TIMER) {
1684 outb(DSP2HOST_REQ_TIMER, chip->iobase + ASSP_HOST_INT_STATUS);
1685 /* update adc/dac info if it was a timer int */
1686 spin_lock(&chip->reg_lock);
1687 for (i = 0; i < chip->num_substreams; i++) {
1688 struct m3_dma *s = &chip->substreams[i];
1689 if (s->running)
1690 snd_m3_update_ptr(chip, s);
1691 }
1692 spin_unlock(&chip->reg_lock);
1693 }
1694 }
1695 }
1696
1697 #if 0 /* TODO: not supported yet */
1698 if ((status & MPU401_INT_PENDING) && chip->rmidi)
1699 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data, regs);
1700 #endif
1701
1702 /* ack ints */
1703 outb(status, chip->iobase + HOST_INT_STATUS);
1704
1705 return IRQ_HANDLED;
1706 }
1707
1708
1709 /*
1710 */
1711
1712 static struct snd_pcm_hardware snd_m3_playback =
1713 {
1714 .info = (SNDRV_PCM_INFO_MMAP |
1715 SNDRV_PCM_INFO_INTERLEAVED |
1716 SNDRV_PCM_INFO_MMAP_VALID |
1717 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1718 /*SNDRV_PCM_INFO_PAUSE |*/
1719 SNDRV_PCM_INFO_RESUME),
1720 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1721 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1722 .rate_min = 8000,
1723 .rate_max = 48000,
1724 .channels_min = 1,
1725 .channels_max = 2,
1726 .buffer_bytes_max = (512*1024),
1727 .period_bytes_min = 64,
1728 .period_bytes_max = (512*1024),
1729 .periods_min = 1,
1730 .periods_max = 1024,
1731 };
1732
1733 static struct snd_pcm_hardware snd_m3_capture =
1734 {
1735 .info = (SNDRV_PCM_INFO_MMAP |
1736 SNDRV_PCM_INFO_INTERLEAVED |
1737 SNDRV_PCM_INFO_MMAP_VALID |
1738 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1739 /*SNDRV_PCM_INFO_PAUSE |*/
1740 SNDRV_PCM_INFO_RESUME),
1741 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1742 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1743 .rate_min = 8000,
1744 .rate_max = 48000,
1745 .channels_min = 1,
1746 .channels_max = 2,
1747 .buffer_bytes_max = (512*1024),
1748 .period_bytes_min = 64,
1749 .period_bytes_max = (512*1024),
1750 .periods_min = 1,
1751 .periods_max = 1024,
1752 };
1753
1754
1755 /*
1756 */
1757
1758 static int
1759 snd_m3_substream_open(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1760 {
1761 int i;
1762 struct m3_dma *s;
1763
1764 spin_lock_irq(&chip->reg_lock);
1765 for (i = 0; i < chip->num_substreams; i++) {
1766 s = &chip->substreams[i];
1767 if (! s->opened)
1768 goto __found;
1769 }
1770 spin_unlock_irq(&chip->reg_lock);
1771 return -ENOMEM;
1772 __found:
1773 s->opened = 1;
1774 s->running = 0;
1775 spin_unlock_irq(&chip->reg_lock);
1776
1777 subs->runtime->private_data = s;
1778 s->substream = subs;
1779
1780 /* set list owners */
1781 if (subs->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1782 s->index_list[0] = &chip->mixer_list;
1783 } else
1784 s->index_list[0] = &chip->adc1_list;
1785 s->index_list[1] = &chip->msrc_list;
1786 s->index_list[2] = &chip->dma_list;
1787
1788 return 0;
1789 }
1790
1791 static void
1792 snd_m3_substream_close(struct snd_m3 *chip, struct snd_pcm_substream *subs)
1793 {
1794 struct m3_dma *s = subs->runtime->private_data;
1795
1796 if (s == NULL)
1797 return; /* not opened properly */
1798
1799 spin_lock_irq(&chip->reg_lock);
1800 if (s->substream && s->running)
1801 snd_m3_pcm_stop(chip, s, s->substream); /* does this happen? */
1802 if (s->in_lists) {
1803 snd_m3_remove_list(chip, s->index_list[0], s->index[0]);
1804 snd_m3_remove_list(chip, s->index_list[1], s->index[1]);
1805 snd_m3_remove_list(chip, s->index_list[2], s->index[2]);
1806 s->in_lists = 0;
1807 }
1808 s->running = 0;
1809 s->opened = 0;
1810 spin_unlock_irq(&chip->reg_lock);
1811 }
1812
1813 static int
1814 snd_m3_playback_open(struct snd_pcm_substream *subs)
1815 {
1816 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1817 struct snd_pcm_runtime *runtime = subs->runtime;
1818 int err;
1819
1820 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1821 return err;
1822
1823 runtime->hw = snd_m3_playback;
1824
1825 return 0;
1826 }
1827
1828 static int
1829 snd_m3_playback_close(struct snd_pcm_substream *subs)
1830 {
1831 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1832
1833 snd_m3_substream_close(chip, subs);
1834 return 0;
1835 }
1836
1837 static int
1838 snd_m3_capture_open(struct snd_pcm_substream *subs)
1839 {
1840 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1841 struct snd_pcm_runtime *runtime = subs->runtime;
1842 int err;
1843
1844 if ((err = snd_m3_substream_open(chip, subs)) < 0)
1845 return err;
1846
1847 runtime->hw = snd_m3_capture;
1848
1849 return 0;
1850 }
1851
1852 static int
1853 snd_m3_capture_close(struct snd_pcm_substream *subs)
1854 {
1855 struct snd_m3 *chip = snd_pcm_substream_chip(subs);
1856
1857 snd_m3_substream_close(chip, subs);
1858 return 0;
1859 }
1860
1861 /*
1862 * create pcm instance
1863 */
1864
1865 static struct snd_pcm_ops snd_m3_playback_ops = {
1866 .open = snd_m3_playback_open,
1867 .close = snd_m3_playback_close,
1868 .ioctl = snd_pcm_lib_ioctl,
1869 .hw_params = snd_m3_pcm_hw_params,
1870 .hw_free = snd_m3_pcm_hw_free,
1871 .prepare = snd_m3_pcm_prepare,
1872 .trigger = snd_m3_pcm_trigger,
1873 .pointer = snd_m3_pcm_pointer,
1874 };
1875
1876 static struct snd_pcm_ops snd_m3_capture_ops = {
1877 .open = snd_m3_capture_open,
1878 .close = snd_m3_capture_close,
1879 .ioctl = snd_pcm_lib_ioctl,
1880 .hw_params = snd_m3_pcm_hw_params,
1881 .hw_free = snd_m3_pcm_hw_free,
1882 .prepare = snd_m3_pcm_prepare,
1883 .trigger = snd_m3_pcm_trigger,
1884 .pointer = snd_m3_pcm_pointer,
1885 };
1886
1887 static int __devinit
1888 snd_m3_pcm(struct snd_m3 * chip, int device)
1889 {
1890 struct snd_pcm *pcm;
1891 int err;
1892
1893 err = snd_pcm_new(chip->card, chip->card->driver, device,
1894 MAX_PLAYBACKS, MAX_CAPTURES, &pcm);
1895 if (err < 0)
1896 return err;
1897
1898 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_m3_playback_ops);
1899 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_m3_capture_ops);
1900
1901 pcm->private_data = chip;
1902 pcm->info_flags = 0;
1903 strcpy(pcm->name, chip->card->driver);
1904 chip->pcm = pcm;
1905
1906 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1907 snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
1908
1909 return 0;
1910 }
1911
1912
1913 /*
1914 * ac97 interface
1915 */
1916
1917 /*
1918 * Wait for the ac97 serial bus to be free.
1919 * return nonzero if the bus is still busy.
1920 */
1921 static int snd_m3_ac97_wait(struct snd_m3 *chip)
1922 {
1923 int i = 10000;
1924
1925 do {
1926 if (! (snd_m3_inb(chip, 0x30) & 1))
1927 return 0;
1928 cpu_relax();
1929 } while (i-- > 0);
1930
1931 snd_printk(KERN_ERR "ac97 serial bus busy\n");
1932 return 1;
1933 }
1934
1935 static unsigned short
1936 snd_m3_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
1937 {
1938 struct snd_m3 *chip = ac97->private_data;
1939 unsigned long flags;
1940 unsigned short data = 0xffff;
1941
1942 if (snd_m3_ac97_wait(chip))
1943 goto fail;
1944 spin_lock_irqsave(&chip->ac97_lock, flags);
1945 snd_m3_outb(chip, 0x80 | (reg & 0x7f), CODEC_COMMAND);
1946 if (snd_m3_ac97_wait(chip))
1947 goto fail_unlock;
1948 data = snd_m3_inw(chip, CODEC_DATA);
1949 fail_unlock:
1950 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1951 fail:
1952 return data;
1953 }
1954
1955 static void
1956 snd_m3_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
1957 {
1958 struct snd_m3 *chip = ac97->private_data;
1959 unsigned long flags;
1960
1961 if (snd_m3_ac97_wait(chip))
1962 return;
1963 spin_lock_irqsave(&chip->ac97_lock, flags);
1964 snd_m3_outw(chip, val, CODEC_DATA);
1965 snd_m3_outb(chip, reg & 0x7f, CODEC_COMMAND);
1966 spin_unlock_irqrestore(&chip->ac97_lock, flags);
1967 }
1968
1969
1970 static void snd_m3_remote_codec_config(int io, int isremote)
1971 {
1972 isremote = isremote ? 1 : 0;
1973
1974 outw((inw(io + RING_BUS_CTRL_B) & ~SECOND_CODEC_ID_MASK) | isremote,
1975 io + RING_BUS_CTRL_B);
1976 outw((inw(io + SDO_OUT_DEST_CTRL) & ~COMMAND_ADDR_OUT) | isremote,
1977 io + SDO_OUT_DEST_CTRL);
1978 outw((inw(io + SDO_IN_DEST_CTRL) & ~STATUS_ADDR_IN) | isremote,
1979 io + SDO_IN_DEST_CTRL);
1980 }
1981
1982 /*
1983 * hack, returns non zero on err
1984 */
1985 static int snd_m3_try_read_vendor(struct snd_m3 *chip)
1986 {
1987 u16 ret;
1988
1989 if (snd_m3_ac97_wait(chip))
1990 return 1;
1991
1992 snd_m3_outb(chip, 0x80 | (AC97_VENDOR_ID1 & 0x7f), 0x30);
1993
1994 if (snd_m3_ac97_wait(chip))
1995 return 1;
1996
1997 ret = snd_m3_inw(chip, 0x32);
1998
1999 return (ret == 0) || (ret == 0xffff);
2000 }
2001
2002 static void snd_m3_ac97_reset(struct snd_m3 *chip)
2003 {
2004 u16 dir;
2005 int delay1 = 0, delay2 = 0, i;
2006 int io = chip->iobase;
2007
2008 if (chip->allegro_flag) {
2009 /*
2010 * the onboard codec on the allegro seems
2011 * to want to wait a very long time before
2012 * coming back to life
2013 */
2014 delay1 = 50;
2015 delay2 = 800;
2016 } else {
2017 /* maestro3 */
2018 delay1 = 20;
2019 delay2 = 500;
2020 }
2021
2022 for (i = 0; i < 5; i++) {
2023 dir = inw(io + GPIO_DIRECTION);
2024 if (!chip->irda_workaround)
2025 dir |= 0x10; /* assuming pci bus master? */
2026
2027 snd_m3_remote_codec_config(io, 0);
2028
2029 outw(IO_SRAM_ENABLE, io + RING_BUS_CTRL_A);
2030 udelay(20);
2031
2032 outw(dir & ~GPO_PRIMARY_AC97 , io + GPIO_DIRECTION);
2033 outw(~GPO_PRIMARY_AC97 , io + GPIO_MASK);
2034 outw(0, io + GPIO_DATA);
2035 outw(dir | GPO_PRIMARY_AC97, io + GPIO_DIRECTION);
2036
2037 schedule_timeout_uninterruptible(msecs_to_jiffies(delay1));
2038
2039 outw(GPO_PRIMARY_AC97, io + GPIO_DATA);
2040 udelay(5);
2041 /* ok, bring back the ac-link */
2042 outw(IO_SRAM_ENABLE | SERIAL_AC_LINK_ENABLE, io + RING_BUS_CTRL_A);
2043 outw(~0, io + GPIO_MASK);
2044
2045 schedule_timeout_uninterruptible(msecs_to_jiffies(delay2));
2046
2047 if (! snd_m3_try_read_vendor(chip))
2048 break;
2049
2050 delay1 += 10;
2051 delay2 += 100;
2052
2053 snd_printd("maestro3: retrying codec reset with delays of %d and %d ms\n",
2054 delay1, delay2);
2055 }
2056
2057 #if 0
2058 /* more gung-ho reset that doesn't
2059 * seem to work anywhere :)
2060 */
2061 tmp = inw(io + RING_BUS_CTRL_A);
2062 outw(RAC_SDFS_ENABLE|LAC_SDFS_ENABLE, io + RING_BUS_CTRL_A);
2063 msleep(20);
2064 outw(tmp, io + RING_BUS_CTRL_A);
2065 msleep(50);
2066 #endif
2067 }
2068
2069 static int __devinit snd_m3_mixer(struct snd_m3 *chip)
2070 {
2071 struct snd_ac97_bus *pbus;
2072 struct snd_ac97_template ac97;
2073 struct snd_ctl_elem_id elem_id;
2074 int err;
2075 static struct snd_ac97_bus_ops ops = {
2076 .write = snd_m3_ac97_write,
2077 .read = snd_m3_ac97_read,
2078 };
2079
2080 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2081 return err;
2082
2083 memset(&ac97, 0, sizeof(ac97));
2084 ac97.private_data = chip;
2085 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2086 return err;
2087
2088 /* seems ac97 PCM needs initialization.. hack hack.. */
2089 snd_ac97_write(chip->ac97, AC97_PCM, 0x8000 | (15 << 8) | 15);
2090 schedule_timeout_uninterruptible(msecs_to_jiffies(100));
2091 snd_ac97_write(chip->ac97, AC97_PCM, 0);
2092
2093 memset(&elem_id, 0, sizeof(elem_id));
2094 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2095 strcpy(elem_id.name, "Master Playback Switch");
2096 chip->master_switch = snd_ctl_find_id(chip->card, &elem_id);
2097 memset(&elem_id, 0, sizeof(elem_id));
2098 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2099 strcpy(elem_id.name, "Master Playback Volume");
2100 chip->master_volume = snd_ctl_find_id(chip->card, &elem_id);
2101
2102 return 0;
2103 }
2104
2105
2106 /*
2107 * initialize ASSP
2108 */
2109
2110 #define MINISRC_LPF_LEN 10
2111 static const u16 minisrc_lpf[MINISRC_LPF_LEN] = {
2112 0X0743, 0X1104, 0X0A4C, 0XF88D, 0X242C,
2113 0X1023, 0X1AA9, 0X0B60, 0XEFDD, 0X186F
2114 };
2115
2116 static void snd_m3_assp_init(struct snd_m3 *chip)
2117 {
2118 unsigned int i;
2119 const u16 *data;
2120
2121 /* zero kernel data */
2122 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2123 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2124 KDATA_BASE_ADDR + i, 0);
2125
2126 /* zero mixer data? */
2127 for (i = 0; i < (REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA) / 2; i++)
2128 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2129 KDATA_BASE_ADDR2 + i, 0);
2130
2131 /* init dma pointer */
2132 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2133 KDATA_CURRENT_DMA,
2134 KDATA_DMA_XFER0);
2135
2136 /* write kernel into code memory.. */
2137 data = (const u16 *)chip->assp_kernel_image->data;
2138 for (i = 0 ; i * 2 < chip->assp_kernel_image->size; i++) {
2139 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2140 REV_B_CODE_MEMORY_BEGIN + i,
2141 le16_to_cpu(data[i]));
2142 }
2143
2144 /*
2145 * We only have this one client and we know that 0x400
2146 * is free in our kernel's mem map, so lets just
2147 * drop it there. It seems that the minisrc doesn't
2148 * need vectors, so we won't bother with them..
2149 */
2150 data = (const u16 *)chip->assp_minisrc_image->data;
2151 for (i = 0; i * 2 < chip->assp_minisrc_image->size; i++) {
2152 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2153 0x400 + i, le16_to_cpu(data[i]));
2154 }
2155
2156 /*
2157 * write the coefficients for the low pass filter?
2158 */
2159 for (i = 0; i < MINISRC_LPF_LEN ; i++) {
2160 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2161 0x400 + MINISRC_COEF_LOC + i,
2162 minisrc_lpf[i]);
2163 }
2164
2165 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE,
2166 0x400 + MINISRC_COEF_LOC + MINISRC_LPF_LEN,
2167 0x8000);
2168
2169 /*
2170 * the minisrc is the only thing on
2171 * our task list..
2172 */
2173 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2174 KDATA_TASK0,
2175 0x400);
2176
2177 /*
2178 * init the mixer number..
2179 */
2180
2181 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2182 KDATA_MIXER_TASK_NUMBER,0);
2183
2184 /*
2185 * EXTREME KERNEL MASTER VOLUME
2186 */
2187 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2188 KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
2189 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2190 KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
2191
2192 chip->mixer_list.curlen = 0;
2193 chip->mixer_list.mem_addr = KDATA_MIXER_XFER0;
2194 chip->mixer_list.max = MAX_VIRTUAL_MIXER_CHANNELS;
2195 chip->adc1_list.curlen = 0;
2196 chip->adc1_list.mem_addr = KDATA_ADC1_XFER0;
2197 chip->adc1_list.max = MAX_VIRTUAL_ADC1_CHANNELS;
2198 chip->dma_list.curlen = 0;
2199 chip->dma_list.mem_addr = KDATA_DMA_XFER0;
2200 chip->dma_list.max = MAX_VIRTUAL_DMA_CHANNELS;
2201 chip->msrc_list.curlen = 0;
2202 chip->msrc_list.mem_addr = KDATA_INSTANCE0_MINISRC;
2203 chip->msrc_list.max = MAX_INSTANCE_MINISRC;
2204 }
2205
2206
2207 static int __devinit snd_m3_assp_client_init(struct snd_m3 *chip, struct m3_dma *s, int index)
2208 {
2209 int data_bytes = 2 * ( MINISRC_TMP_BUFFER_SIZE / 2 +
2210 MINISRC_IN_BUFFER_SIZE / 2 +
2211 1 + MINISRC_OUT_BUFFER_SIZE / 2 + 1 );
2212 int address, i;
2213
2214 /*
2215 * the revb memory map has 0x1100 through 0x1c00
2216 * free.
2217 */
2218
2219 /*
2220 * align instance address to 256 bytes so that its
2221 * shifted list address is aligned.
2222 * list address = (mem address >> 1) >> 7;
2223 */
2224 data_bytes = ALIGN(data_bytes, 256);
2225 address = 0x1100 + ((data_bytes/2) * index);
2226
2227 if ((address + (data_bytes/2)) >= 0x1c00) {
2228 snd_printk(KERN_ERR "no memory for %d bytes at ind %d (addr 0x%x)\n",
2229 data_bytes, index, address);
2230 return -ENOMEM;
2231 }
2232
2233 s->number = index;
2234 s->inst.code = 0x400;
2235 s->inst.data = address;
2236
2237 for (i = data_bytes / 2; i > 0; address++, i--) {
2238 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2239 address, 0);
2240 }
2241
2242 return 0;
2243 }
2244
2245
2246 /*
2247 * this works for the reference board, have to find
2248 * out about others
2249 *
2250 * this needs more magic for 4 speaker, but..
2251 */
2252 static void
2253 snd_m3_amp_enable(struct snd_m3 *chip, int enable)
2254 {
2255 int io = chip->iobase;
2256 u16 gpo, polarity;
2257
2258 if (! chip->external_amp)
2259 return;
2260
2261 polarity = enable ? 0 : 1;
2262 polarity = polarity << chip->amp_gpio;
2263 gpo = 1 << chip->amp_gpio;
2264
2265 outw(~gpo, io + GPIO_MASK);
2266
2267 outw(inw(io + GPIO_DIRECTION) | gpo,
2268 io + GPIO_DIRECTION);
2269
2270 outw((GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity),
2271 io + GPIO_DATA);
2272
2273 outw(0xffff, io + GPIO_MASK);
2274 }
2275
2276 static void
2277 snd_m3_hv_init(struct snd_m3 *chip)
2278 {
2279 unsigned long io = chip->iobase;
2280 u16 val = GPI_VOL_DOWN | GPI_VOL_UP;
2281
2282 if (!chip->is_omnibook)
2283 return;
2284
2285 /*
2286 * Volume buttons on some HP OmniBook laptops
2287 * require some GPIO magic to work correctly.
2288 */
2289 outw(0xffff, io + GPIO_MASK);
2290 outw(0x0000, io + GPIO_DATA);
2291
2292 outw(~val, io + GPIO_MASK);
2293 outw(inw(io + GPIO_DIRECTION) & ~val, io + GPIO_DIRECTION);
2294 outw(val, io + GPIO_MASK);
2295
2296 outw(0xffff, io + GPIO_MASK);
2297 }
2298
2299 static int
2300 snd_m3_chip_init(struct snd_m3 *chip)
2301 {
2302 struct pci_dev *pcidev = chip->pci;
2303 unsigned long io = chip->iobase;
2304 u32 n;
2305 u16 w;
2306 u8 t; /* makes as much sense as 'n', no? */
2307
2308 pci_read_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, &w);
2309 w &= ~(SOUND_BLASTER_ENABLE|FM_SYNTHESIS_ENABLE|
2310 MPU401_IO_ENABLE|MPU401_IRQ_ENABLE|ALIAS_10BIT_IO|
2311 DISABLE_LEGACY);
2312 pci_write_config_word(pcidev, PCI_LEGACY_AUDIO_CTRL, w);
2313
2314 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2315 n &= ~(HV_CTRL_ENABLE | REDUCED_DEBOUNCE | HV_BUTTON_FROM_GD);
2316 n |= chip->hv_config;
2317 /* For some reason we must always use reduced debounce. */
2318 n |= REDUCED_DEBOUNCE;
2319 n |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
2320 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2321
2322 outb(RESET_ASSP, chip->iobase + ASSP_CONTROL_B);
2323 pci_read_config_dword(pcidev, PCI_ALLEGRO_CONFIG, &n);
2324 n &= ~INT_CLK_SELECT;
2325 if (!chip->allegro_flag) {
2326 n &= ~INT_CLK_MULT_ENABLE;
2327 n |= INT_CLK_SRC_NOT_PCI;
2328 }
2329 n &= ~( CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2 );
2330 pci_write_config_dword(pcidev, PCI_ALLEGRO_CONFIG, n);
2331
2332 if (chip->allegro_flag) {
2333 pci_read_config_dword(pcidev, PCI_USER_CONFIG, &n);
2334 n |= IN_CLK_12MHZ_SELECT;
2335 pci_write_config_dword(pcidev, PCI_USER_CONFIG, n);
2336 }
2337
2338 t = inb(chip->iobase + ASSP_CONTROL_A);
2339 t &= ~( DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
2340 t |= ASSP_CLK_49MHZ_SELECT;
2341 t |= ASSP_0_WS_ENABLE;
2342 outb(t, chip->iobase + ASSP_CONTROL_A);
2343
2344 snd_m3_assp_init(chip); /* download DSP code before starting ASSP below */
2345 outb(RUN_ASSP, chip->iobase + ASSP_CONTROL_B);
2346
2347 outb(0x00, io + HARDWARE_VOL_CTRL);
2348 outb(0x88, io + SHADOW_MIX_REG_VOICE);
2349 outb(0x88, io + HW_VOL_COUNTER_VOICE);
2350 outb(0x88, io + SHADOW_MIX_REG_MASTER);
2351 outb(0x88, io + HW_VOL_COUNTER_MASTER);
2352
2353 return 0;
2354 }
2355
2356 static void
2357 snd_m3_enable_ints(struct snd_m3 *chip)
2358 {
2359 unsigned long io = chip->iobase;
2360 unsigned short val;
2361
2362 /* TODO: MPU401 not supported yet */
2363 val = ASSP_INT_ENABLE /*| MPU401_INT_ENABLE*/;
2364 if (chip->hv_config & HV_CTRL_ENABLE)
2365 val |= HV_INT_ENABLE;
2366 outw(val, io + HOST_INT_CTRL);
2367 outb(inb(io + ASSP_CONTROL_C) | ASSP_HOST_INT_ENABLE,
2368 io + ASSP_CONTROL_C);
2369 }
2370
2371
2372 /*
2373 */
2374
2375 static int snd_m3_free(struct snd_m3 *chip)
2376 {
2377 struct m3_dma *s;
2378 int i;
2379
2380 if (chip->substreams) {
2381 spin_lock_irq(&chip->reg_lock);
2382 for (i = 0; i < chip->num_substreams; i++) {
2383 s = &chip->substreams[i];
2384 /* check surviving pcms; this should not happen though.. */
2385 if (s->substream && s->running)
2386 snd_m3_pcm_stop(chip, s, s->substream);
2387 }
2388 spin_unlock_irq(&chip->reg_lock);
2389 kfree(chip->substreams);
2390 }
2391 if (chip->iobase) {
2392 outw(0, chip->iobase + HOST_INT_CTRL); /* disable ints */
2393 }
2394
2395 #ifdef CONFIG_PM
2396 vfree(chip->suspend_mem);
2397 #endif
2398
2399 if (chip->irq >= 0)
2400 free_irq(chip->irq, chip);
2401
2402 if (chip->iobase)
2403 pci_release_regions(chip->pci);
2404
2405 release_firmware(chip->assp_kernel_image);
2406 release_firmware(chip->assp_minisrc_image);
2407
2408 pci_disable_device(chip->pci);
2409 kfree(chip);
2410 return 0;
2411 }
2412
2413
2414 /*
2415 * APM support
2416 */
2417 #ifdef CONFIG_PM
2418 static int m3_suspend(struct pci_dev *pci, pm_message_t state)
2419 {
2420 struct snd_card *card = pci_get_drvdata(pci);
2421 struct snd_m3 *chip = card->private_data;
2422 int i, dsp_index;
2423
2424 if (chip->suspend_mem == NULL)
2425 return 0;
2426
2427 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2428 snd_pcm_suspend_all(chip->pcm);
2429 snd_ac97_suspend(chip->ac97);
2430
2431 msleep(10); /* give the assp a chance to idle.. */
2432
2433 snd_m3_assp_halt(chip);
2434
2435 /* save dsp image */
2436 dsp_index = 0;
2437 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2438 chip->suspend_mem[dsp_index++] =
2439 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_CODE, i);
2440 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2441 chip->suspend_mem[dsp_index++] =
2442 snd_m3_assp_read(chip, MEMTYPE_INTERNAL_DATA, i);
2443
2444 pci_disable_device(pci);
2445 pci_save_state(pci);
2446 pci_set_power_state(pci, pci_choose_state(pci, state));
2447 return 0;
2448 }
2449
2450 static int m3_resume(struct pci_dev *pci)
2451 {
2452 struct snd_card *card = pci_get_drvdata(pci);
2453 struct snd_m3 *chip = card->private_data;
2454 int i, dsp_index;
2455
2456 if (chip->suspend_mem == NULL)
2457 return 0;
2458
2459 pci_set_power_state(pci, PCI_D0);
2460 pci_restore_state(pci);
2461 if (pci_enable_device(pci) < 0) {
2462 printk(KERN_ERR "maestor3: pci_enable_device failed, "
2463 "disabling device\n");
2464 snd_card_disconnect(card);
2465 return -EIO;
2466 }
2467 pci_set_master(pci);
2468
2469 /* first lets just bring everything back. .*/
2470 snd_m3_outw(chip, 0, 0x54);
2471 snd_m3_outw(chip, 0, 0x56);
2472
2473 snd_m3_chip_init(chip);
2474 snd_m3_assp_halt(chip);
2475 snd_m3_ac97_reset(chip);
2476
2477 /* restore dsp image */
2478 dsp_index = 0;
2479 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
2480 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_CODE, i,
2481 chip->suspend_mem[dsp_index++]);
2482 for (i = REV_B_DATA_MEMORY_BEGIN ; i <= REV_B_DATA_MEMORY_END; i++)
2483 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA, i,
2484 chip->suspend_mem[dsp_index++]);
2485
2486 /* tell the dma engine to restart itself */
2487 snd_m3_assp_write(chip, MEMTYPE_INTERNAL_DATA,
2488 KDATA_DMA_ACTIVE, 0);
2489
2490 /* restore ac97 registers */
2491 snd_ac97_resume(chip->ac97);
2492
2493 snd_m3_assp_continue(chip);
2494 snd_m3_enable_ints(chip);
2495 snd_m3_amp_enable(chip, 1);
2496
2497 snd_m3_hv_init(chip);
2498
2499 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2500 return 0;
2501 }
2502 #endif /* CONFIG_PM */
2503
2504
2505 /*
2506 */
2507
2508 static int snd_m3_dev_free(struct snd_device *device)
2509 {
2510 struct snd_m3 *chip = device->device_data;
2511 return snd_m3_free(chip);
2512 }
2513
2514 static int __devinit
2515 snd_m3_create(struct snd_card *card, struct pci_dev *pci,
2516 int enable_amp,
2517 int amp_gpio,
2518 struct snd_m3 **chip_ret)
2519 {
2520 struct snd_m3 *chip;
2521 int i, err;
2522 const struct snd_pci_quirk *quirk;
2523 static struct snd_device_ops ops = {
2524 .dev_free = snd_m3_dev_free,
2525 };
2526
2527 *chip_ret = NULL;
2528
2529 if (pci_enable_device(pci))
2530 return -EIO;
2531
2532 /* check, if we can restrict PCI DMA transfers to 28 bits */
2533 if (pci_set_dma_mask(pci, DMA_28BIT_MASK) < 0 ||
2534 pci_set_consistent_dma_mask(pci, DMA_28BIT_MASK) < 0) {
2535 snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
2536 pci_disable_device(pci);
2537 return -ENXIO;
2538 }
2539
2540 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2541 if (chip == NULL) {
2542 pci_disable_device(pci);
2543 return -ENOMEM;
2544 }
2545
2546 spin_lock_init(&chip->reg_lock);
2547 spin_lock_init(&chip->ac97_lock);
2548
2549 switch (pci->device) {
2550 case PCI_DEVICE_ID_ESS_ALLEGRO:
2551 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2552 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2553 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2554 chip->allegro_flag = 1;
2555 break;
2556 }
2557
2558 chip->card = card;
2559 chip->pci = pci;
2560 chip->irq = -1;
2561
2562 chip->external_amp = enable_amp;
2563 if (amp_gpio >= 0 && amp_gpio <= 0x0f)
2564 chip->amp_gpio = amp_gpio;
2565 else {
2566 quirk = snd_pci_quirk_lookup(pci, m3_amp_quirk_list);
2567 if (quirk) {
2568 snd_printdd(KERN_INFO "maestro3: set amp-gpio "
2569 "for '%s'\n", quirk->name);
2570 chip->amp_gpio = quirk->value;
2571 } else if (chip->allegro_flag)
2572 chip->amp_gpio = GPO_EXT_AMP_ALLEGRO;
2573 else /* presumably this is for all 'maestro3's.. */
2574 chip->amp_gpio = GPO_EXT_AMP_M3;
2575 }
2576
2577 quirk = snd_pci_quirk_lookup(pci, m3_irda_quirk_list);
2578 if (quirk) {
2579 snd_printdd(KERN_INFO "maestro3: enabled irda workaround "
2580 "for '%s'\n", quirk->name);
2581 chip->irda_workaround = 1;
2582 }
2583 quirk = snd_pci_quirk_lookup(pci, m3_hv_quirk_list);
2584 if (quirk)
2585 chip->hv_config = quirk->value;
2586 if (snd_pci_quirk_lookup(pci, m3_omnibook_quirk_list))
2587 chip->is_omnibook = 1;
2588
2589 chip->num_substreams = NR_DSPS;
2590 chip->substreams = kcalloc(chip->num_substreams, sizeof(struct m3_dma),
2591 GFP_KERNEL);
2592 if (chip->substreams == NULL) {
2593 kfree(chip);
2594 pci_disable_device(pci);
2595 return -ENOMEM;
2596 }
2597
2598 err = request_firmware(&chip->assp_kernel_image,
2599 "ess/maestro3_assp_kernel.fw", &pci->dev);
2600 if (err < 0) {
2601 snd_m3_free(chip);
2602 return err;
2603 }
2604
2605 err = request_firmware(&chip->assp_minisrc_image,
2606 "ess/maestro3_assp_minisrc.fw", &pci->dev);
2607 if (err < 0) {
2608 snd_m3_free(chip);
2609 return err;
2610 }
2611
2612 if ((err = pci_request_regions(pci, card->driver)) < 0) {
2613 snd_m3_free(chip);
2614 return err;
2615 }
2616 chip->iobase = pci_resource_start(pci, 0);
2617
2618 /* just to be sure */
2619 pci_set_master(pci);
2620
2621 snd_m3_chip_init(chip);
2622 snd_m3_assp_halt(chip);
2623
2624 snd_m3_ac97_reset(chip);
2625
2626 snd_m3_amp_enable(chip, 1);
2627
2628 snd_m3_hv_init(chip);
2629
2630 tasklet_init(&chip->hwvol_tq, snd_m3_update_hw_volume, (unsigned long)chip);
2631
2632 if (request_irq(pci->irq, snd_m3_interrupt, IRQF_SHARED,
2633 card->driver, chip)) {
2634 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
2635 snd_m3_free(chip);
2636 return -ENOMEM;
2637 }
2638 chip->irq = pci->irq;
2639
2640 #ifdef CONFIG_PM
2641 chip->suspend_mem = vmalloc(sizeof(u16) * (REV_B_CODE_MEMORY_LENGTH + REV_B_DATA_MEMORY_LENGTH));
2642 if (chip->suspend_mem == NULL)
2643 snd_printk(KERN_WARNING "can't allocate apm buffer\n");
2644 #endif
2645
2646 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2647 snd_m3_free(chip);
2648 return err;
2649 }
2650
2651 if ((err = snd_m3_mixer(chip)) < 0)
2652 return err;
2653
2654 for (i = 0; i < chip->num_substreams; i++) {
2655 struct m3_dma *s = &chip->substreams[i];
2656 if ((err = snd_m3_assp_client_init(chip, s, i)) < 0)
2657 return err;
2658 }
2659
2660 if ((err = snd_m3_pcm(chip, 0)) < 0)
2661 return err;
2662
2663 snd_m3_enable_ints(chip);
2664 snd_m3_assp_continue(chip);
2665
2666 snd_card_set_dev(card, &pci->dev);
2667
2668 *chip_ret = chip;
2669
2670 return 0;
2671 }
2672
2673 /*
2674 */
2675 static int __devinit
2676 snd_m3_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
2677 {
2678 static int dev;
2679 struct snd_card *card;
2680 struct snd_m3 *chip;
2681 int err;
2682
2683 /* don't pick up modems */
2684 if (((pci->class >> 8) & 0xffff) != PCI_CLASS_MULTIMEDIA_AUDIO)
2685 return -ENODEV;
2686
2687 if (dev >= SNDRV_CARDS)
2688 return -ENODEV;
2689 if (!enable[dev]) {
2690 dev++;
2691 return -ENOENT;
2692 }
2693
2694 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2695 if (card == NULL)
2696 return -ENOMEM;
2697
2698 switch (pci->device) {
2699 case PCI_DEVICE_ID_ESS_ALLEGRO:
2700 case PCI_DEVICE_ID_ESS_ALLEGRO_1:
2701 strcpy(card->driver, "Allegro");
2702 break;
2703 case PCI_DEVICE_ID_ESS_CANYON3D_2LE:
2704 case PCI_DEVICE_ID_ESS_CANYON3D_2:
2705 strcpy(card->driver, "Canyon3D-2");
2706 break;
2707 default:
2708 strcpy(card->driver, "Maestro3");
2709 break;
2710 }
2711
2712 if ((err = snd_m3_create(card, pci,
2713 external_amp[dev],
2714 amp_gpio[dev],
2715 &chip)) < 0) {
2716 snd_card_free(card);
2717 return err;
2718 }
2719 card->private_data = chip;
2720
2721 sprintf(card->shortname, "ESS %s PCI", card->driver);
2722 sprintf(card->longname, "%s at 0x%lx, irq %d",
2723 card->shortname, chip->iobase, chip->irq);
2724
2725 if ((err = snd_card_register(card)) < 0) {
2726 snd_card_free(card);
2727 return err;
2728 }
2729
2730 #if 0 /* TODO: not supported yet */
2731 /* TODO enable MIDI IRQ and I/O */
2732 err = snd_mpu401_uart_new(chip->card, 0, MPU401_HW_MPU401,
2733 chip->iobase + MPU401_DATA_PORT,
2734 MPU401_INFO_INTEGRATED,
2735 chip->irq, 0, &chip->rmidi);
2736 if (err < 0)
2737 printk(KERN_WARNING "maestro3: no MIDI support.\n");
2738 #endif
2739
2740 pci_set_drvdata(pci, card);
2741 dev++;
2742 return 0;
2743 }
2744
2745 static void __devexit snd_m3_remove(struct pci_dev *pci)
2746 {
2747 snd_card_free(pci_get_drvdata(pci));
2748 pci_set_drvdata(pci, NULL);
2749 }
2750
2751 static struct pci_driver driver = {
2752 .name = "Maestro3",
2753 .id_table = snd_m3_ids,
2754 .probe = snd_m3_probe,
2755 .remove = __devexit_p(snd_m3_remove),
2756 #ifdef CONFIG_PM
2757 .suspend = m3_suspend,
2758 .resume = m3_resume,
2759 #endif
2760 };
2761
2762 static int __init alsa_card_m3_init(void)
2763 {
2764 return pci_register_driver(&driver);
2765 }
2766
2767 static void __exit alsa_card_m3_exit(void)
2768 {
2769 pci_unregister_driver(&driver);
2770 }
2771
2772 module_init(alsa_card_m3_init)
2773 module_exit(alsa_card_m3_exit)
Support for the Chinese Samsung S3C2440 based development boards