drivers/watchdog/iTCO_wdt.c

   1 /*
   2  *      intel TCO Watchdog Driver (Used in i82801 and i63xxESB chipsets)
   3  *
   4  *      (c) Copyright 2006-2009 Wim Van Sebroeck <wim@iguana.be>.
   5  *
   6  *      This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License
   8  *      as published by the Free Software Foundation; either version
   9  *      2 of the License, or (at your option) any later version.
  10  *
  11  *      Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
  12  *      provide warranty for any of this software. This material is
  13  *      provided "AS-IS" and at no charge.
  14  *
  15  *      The TCO watchdog is implemented in the following I/O controller hubs:
  16  *      (See the intel documentation on http://developer.intel.com.)
  17  *      82801AA  (ICH)       : document number 290655-003, 290677-014,
  18  *      82801AB  (ICHO)      : document number 290655-003, 290677-014,
  19  *      82801BA  (ICH2)      : document number 290687-002, 298242-027,
  20  *      82801BAM (ICH2-M)    : document number 290687-002, 298242-027,
  21  *      82801CA  (ICH3-S)    : document number 290733-003, 290739-013,
  22  *      82801CAM (ICH3-M)    : document number 290716-001, 290718-007,
  23  *      82801DB  (ICH4)      : document number 290744-001, 290745-025,
  24  *      82801DBM (ICH4-M)    : document number 252337-001, 252663-008,
  25  *      82801E   (C-ICH)     : document number 273599-001, 273645-002,
  26  *      82801EB  (ICH5)      : document number 252516-001, 252517-028,
  27  *      82801ER  (ICH5R)     : document number 252516-001, 252517-028,
  28  *      6300ESB  (6300ESB)   : document number 300641-004, 300884-013,
  29  *      82801FB  (ICH6)      : document number 301473-002, 301474-026,
  30  *      82801FR  (ICH6R)     : document number 301473-002, 301474-026,
  31  *      82801FBM (ICH6-M)    : document number 301473-002, 301474-026,
  32  *      82801FW  (ICH6W)     : document number 301473-001, 301474-026,
  33  *      82801FRW (ICH6RW)    : document number 301473-001, 301474-026,
  34  *      631xESB  (631xESB)   : document number 313082-001, 313075-006,
  35  *      632xESB  (632xESB)   : document number 313082-001, 313075-006,
  36  *      82801GB  (ICH7)      : document number 307013-003, 307014-024,
  37  *      82801GR  (ICH7R)     : document number 307013-003, 307014-024,
  38  *      82801GDH (ICH7DH)    : document number 307013-003, 307014-024,
  39  *      82801GBM (ICH7-M)    : document number 307013-003, 307014-024,
  40  *      82801GHM (ICH7-M DH) : document number 307013-003, 307014-024,
  41  *      82801GU  (ICH7-U)    : document number 307013-003, 307014-024,
  42  *      82801HB  (ICH8)      : document number 313056-003, 313057-017,
  43  *      82801HR  (ICH8R)     : document number 313056-003, 313057-017,
  44  *      82801HBM (ICH8M)     : document number 313056-003, 313057-017,
  45  *      82801HH  (ICH8DH)    : document number 313056-003, 313057-017,
  46  *      82801HO  (ICH8DO)    : document number 313056-003, 313057-017,
  47  *      82801HEM (ICH8M-E)   : document number 313056-003, 313057-017,
  48  *      82801IB  (ICH9)      : document number 316972-004, 316973-012,
  49  *      82801IR  (ICH9R)     : document number 316972-004, 316973-012,
  50  *      82801IH  (ICH9DH)    : document number 316972-004, 316973-012,
  51  *      82801IO  (ICH9DO)    : document number 316972-004, 316973-012,
  52  *      82801IBM (ICH9M)     : document number 316972-004, 316973-012,
  53  *      82801IEM (ICH9M-E)   : document number 316972-004, 316973-012,
  54  *      82801JIB (ICH10)     : document number 319973-002, 319974-002,
  55  *      82801JIR (ICH10R)    : document number 319973-002, 319974-002,
  56  *      82801JD  (ICH10D)    : document number 319973-002, 319974-002,
  57  *      82801JDO (ICH10DO)   : document number 319973-002, 319974-002
  58  */
  59
  60 /*
  61  *      Includes, defines, variables, module parameters, ...
  62  */
  63
  64 /* Module and version information */
  65 #define DRV_NAME        "iTCO_wdt"
  66 #define DRV_VERSION     "1.05"
  67 #define PFX             DRV_NAME ": "
  68
  69 /* Includes */
  70 #include <linux/module.h>               /* For module specific items */
  71 #include <linux/moduleparam.h>          /* For new moduleparam's */
  72 #include <linux/types.h>                /* For standard types (like size_t) */
  73 #include <linux/errno.h>                /* For the -ENODEV/... values */
  74 #include <linux/kernel.h>               /* For printk/panic/... */
  75 #include <linux/miscdevice.h>           /* For MODULE_ALIAS_MISCDEV
  76                                                         (WATCHDOG_MINOR) */
  77 #include <linux/watchdog.h>             /* For the watchdog specific items */
  78 #include <linux/init.h>                 /* For __init/__exit/... */
  79 #include <linux/fs.h>                   /* For file operations */
  80 #include <linux/platform_device.h>      /* For platform_driver framework */
  81 #include <linux/pci.h>                  /* For pci functions */
  82 #include <linux/ioport.h>               /* For io-port access */
  83 #include <linux/spinlock.h>             /* For spin_lock/spin_unlock/... */
  84 #include <linux/uaccess.h>              /* For copy_to_user/put_user/... */
  85 #include <linux/io.h>                   /* For inb/outb/... */
  86
  87 #include "iTCO_vendor.h"
  88
  89 /* TCO related info */
  90 enum iTCO_chipsets {
  91         TCO_ICH = 0,    /* ICH */
  92         TCO_ICH0,       /* ICH0 */
  93         TCO_ICH2,       /* ICH2 */
  94         TCO_ICH2M,      /* ICH2-M */
  95         TCO_ICH3,       /* ICH3-S */
  96         TCO_ICH3M,      /* ICH3-M */
  97         TCO_ICH4,       /* ICH4 */
  98         TCO_ICH4M,      /* ICH4-M */
  99         TCO_CICH,       /* C-ICH */
 100         TCO_ICH5,       /* ICH5 & ICH5R */
 101         TCO_6300ESB,    /* 6300ESB */
 102         TCO_ICH6,       /* ICH6 & ICH6R */
 103         TCO_ICH6M,      /* ICH6-M */
 104         TCO_ICH6W,      /* ICH6W & ICH6RW */
 105         TCO_631XESB,    /* 631xESB/632xESB */
 106         TCO_ICH7,       /* ICH7 & ICH7R */
 107         TCO_ICH7DH,     /* ICH7DH */
 108         TCO_ICH7M,      /* ICH7-M & ICH7-U */
 109         TCO_ICH7MDH,    /* ICH7-M DH */
 110         TCO_ICH8,       /* ICH8 & ICH8R */
 111         TCO_ICH8DH,     /* ICH8DH */
 112         TCO_ICH8DO,     /* ICH8DO */
 113         TCO_ICH8M,      /* ICH8M */
 114         TCO_ICH8ME,     /* ICH8M-E */
 115         TCO_ICH9,       /* ICH9 */
 116         TCO_ICH9R,      /* ICH9R */
 117         TCO_ICH9DH,     /* ICH9DH */
 118         TCO_ICH9DO,     /* ICH9DO */
 119         TCO_ICH9M,      /* ICH9M */
 120         TCO_ICH9ME,     /* ICH9M-E */
 121         TCO_ICH10,      /* ICH10 */
 122         TCO_ICH10R,     /* ICH10R */
 123         TCO_ICH10D,     /* ICH10D */
 124         TCO_ICH10DO,    /* ICH10DO */
 125 };
 126
 127 static struct {
 128         char *name;
 129         unsigned int iTCO_version;
 130 } iTCO_chipset_info[] __devinitdata = {
 131         {"ICH", 1},
 132         {"ICH0", 1},
 133         {"ICH2", 1},
 134         {"ICH2-M", 1},
 135         {"ICH3-S", 1},
 136         {"ICH3-M", 1},
 137         {"ICH4", 1},
 138         {"ICH4-M", 1},
 139         {"C-ICH", 1},
 140         {"ICH5 or ICH5R", 1},
 141         {"6300ESB", 1},
 142         {"ICH6 or ICH6R", 2},
 143         {"ICH6-M", 2},
 144         {"ICH6W or ICH6RW", 2},
 145         {"631xESB/632xESB", 2},
 146         {"ICH7 or ICH7R", 2},
 147         {"ICH7DH", 2},
 148         {"ICH7-M or ICH7-U", 2},
 149         {"ICH7-M DH", 2},
 150         {"ICH8 or ICH8R", 2},
 151         {"ICH8DH", 2},
 152         {"ICH8DO", 2},
 153         {"ICH8M", 2},
 154         {"ICH8M-E", 2},
 155         {"ICH9", 2},
 156         {"ICH9R", 2},
 157         {"ICH9DH", 2},
 158         {"ICH9DO", 2},
 159         {"ICH9M", 2},
 160         {"ICH9M-E", 2},
 161         {"ICH10", 2},
 162         {"ICH10R", 2},
 163         {"ICH10D", 2},
 164         {"ICH10DO", 2},
 165         {NULL, 0}
 166 };
 167
 168 #define ITCO_PCI_DEVICE(dev, data)      \
 169         .vendor = PCI_VENDOR_ID_INTEL,  \
 170         .device = dev,                  \
 171         .subvendor = PCI_ANY_ID,        \
 172         .subdevice = PCI_ANY_ID,        \
 173         .class = 0,                     \
 174         .class_mask = 0,                \
 175         .driver_data = data
 176
 177 /*
 178  * This data only exists for exporting the supported PCI ids
 179  * via MODULE_DEVICE_TABLE.  We do not actually register a
 180  * pci_driver, because the I/O Controller Hub has also other
 181  * functions that probably will be registered by other drivers.
 182  */
 183 static struct pci_device_id iTCO_wdt_pci_tbl[] = {
 184         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AA_0,        TCO_ICH)},
 185         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801AB_0,        TCO_ICH0)},
 186         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_0,        TCO_ICH2)},
 187         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801BA_10,       TCO_ICH2M)},
 188         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_0,        TCO_ICH3)},
 189         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801CA_12,       TCO_ICH3M)},
 190         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_0,        TCO_ICH4)},
 191         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801DB_12,       TCO_ICH4M)},
 192         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801E_0,         TCO_CICH)},
 193         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_82801EB_0,        TCO_ICH5)},
 194         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB_1,            TCO_6300ESB)},
 195         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_0,           TCO_ICH6)},
 196         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_1,           TCO_ICH6M)},
 197         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH6_2,           TCO_ICH6W)},
 198         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ESB2_0,           TCO_631XESB)},
 199         { ITCO_PCI_DEVICE(0x2671,                               TCO_631XESB)},
 200         { ITCO_PCI_DEVICE(0x2672,                               TCO_631XESB)},
 201         { ITCO_PCI_DEVICE(0x2673,                               TCO_631XESB)},
 202         { ITCO_PCI_DEVICE(0x2674,                               TCO_631XESB)},
 203         { ITCO_PCI_DEVICE(0x2675,                               TCO_631XESB)},
 204         { ITCO_PCI_DEVICE(0x2676,                               TCO_631XESB)},
 205         { ITCO_PCI_DEVICE(0x2677,                               TCO_631XESB)},
 206         { ITCO_PCI_DEVICE(0x2678,                               TCO_631XESB)},
 207         { ITCO_PCI_DEVICE(0x2679,                               TCO_631XESB)},
 208         { ITCO_PCI_DEVICE(0x267a,                               TCO_631XESB)},
 209         { ITCO_PCI_DEVICE(0x267b,                               TCO_631XESB)},
 210         { ITCO_PCI_DEVICE(0x267c,                               TCO_631XESB)},
 211         { ITCO_PCI_DEVICE(0x267d,                               TCO_631XESB)},
 212         { ITCO_PCI_DEVICE(0x267e,                               TCO_631XESB)},
 213         { ITCO_PCI_DEVICE(0x267f,                               TCO_631XESB)},
 214         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_0,           TCO_ICH7)},
 215         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_30,          TCO_ICH7DH)},
 216         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_1,           TCO_ICH7M)},
 217         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH7_31,          TCO_ICH7MDH)},
 218         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_0,           TCO_ICH8)},
 219         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_2,           TCO_ICH8DH)},
 220         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_3,           TCO_ICH8DO)},
 221         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_4,           TCO_ICH8M)},
 222         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH8_1,           TCO_ICH8ME)},
 223         { ITCO_PCI_DEVICE(0x2918,                               TCO_ICH9)},
 224         { ITCO_PCI_DEVICE(0x2916,                               TCO_ICH9R)},
 225         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_2,           TCO_ICH9DH)},
 226         { ITCO_PCI_DEVICE(PCI_DEVICE_ID_INTEL_ICH9_4,           TCO_ICH9DO)},
 227         { ITCO_PCI_DEVICE(0x2919,                               TCO_ICH9M)},
 228         { ITCO_PCI_DEVICE(0x2917,                               TCO_ICH9ME)},
 229         { ITCO_PCI_DEVICE(0x3a18,                               TCO_ICH10)},
 230         { ITCO_PCI_DEVICE(0x3a16,                               TCO_ICH10R)},
 231         { ITCO_PCI_DEVICE(0x3a1a,                               TCO_ICH10D)},
 232         { ITCO_PCI_DEVICE(0x3a14,                               TCO_ICH10DO)},
 233         { 0, },                 /* End of list */
 234 };
 235 MODULE_DEVICE_TABLE(pci, iTCO_wdt_pci_tbl);
 236
 237 /* Address definitions for the TCO */
 238 /* TCO base address */
 239 #define TCOBASE         iTCO_wdt_private.ACPIBASE + 0x60
 240 /* SMI Control and Enable Register */
 241 #define SMI_EN          iTCO_wdt_private.ACPIBASE + 0x30
 242
 243 #define TCO_RLD         TCOBASE + 0x00  /* TCO Timer Reload and Curr. Value */
 244 #define TCOv1_TMR       TCOBASE + 0x01  /* TCOv1 Timer Initial Value    */
 245 #define TCO_DAT_IN      TCOBASE + 0x02  /* TCO Data In Register         */
 246 #define TCO_DAT_OUT     TCOBASE + 0x03  /* TCO Data Out Register        */
 247 #define TCO1_STS        TCOBASE + 0x04  /* TCO1 Status Register         */
 248 #define TCO2_STS        TCOBASE + 0x06  /* TCO2 Status Register         */
 249 #define TCO1_CNT        TCOBASE + 0x08  /* TCO1 Control Register        */
 250 #define TCO2_CNT        TCOBASE + 0x0a  /* TCO2 Control Register        */
 251 #define TCOv2_TMR       TCOBASE + 0x12  /* TCOv2 Timer Initial Value    */
 252
 253 /* internal variables */
 254 static unsigned long is_active;
 255 static char expect_release;
 256 static struct {         /* this is private data for the iTCO_wdt device */
 257         /* TCO version/generation */
 258         unsigned int iTCO_version;
 259         /* The cards ACPIBASE address (TCOBASE = ACPIBASE+0x60) */
 260         unsigned long ACPIBASE;
 261         /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2)*/
 262         unsigned long __iomem *gcs;
 263         /* the lock for io operations */
 264         spinlock_t io_lock;
 265         /* the PCI-device */
 266         struct pci_dev *pdev;
 267 } iTCO_wdt_private;
 268
 269 /* the watchdog platform device */
 270 static struct platform_device *iTCO_wdt_platform_device;
 271
 272 /* module parameters */
 273 #define WATCHDOG_HEARTBEAT 30   /* 30 sec default heartbeat */
 274 static int heartbeat = WATCHDOG_HEARTBEAT;  /* in seconds */
 275 module_param(heartbeat, int, 0);
 276 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (2<heartbeat<39 (TCO v1) or 613 (TCO v2), default=" __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
 277
 278 static int nowayout = WATCHDOG_NOWAYOUT;
 279 module_param(nowayout, int, 0);
 280 MODULE_PARM_DESC(nowayout,
 281         "Watchdog cannot be stopped once started (default="
 282                                 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
 283
 284 /*
 285  * Some TCO specific functions
 286  */
 287
 288 static inline unsigned int seconds_to_ticks(int seconds)
 289 {
 290         /* the internal timer is stored as ticks which decrement
 291          * every 0.6 seconds */
 292         return (seconds * 10) / 6;
 293 }
 294
 295 static void iTCO_wdt_set_NO_REBOOT_bit(void)
 296 {
 297         u32 val32;
 298
 299         /* Set the NO_REBOOT bit: this disables reboots */
 300         if (iTCO_wdt_private.iTCO_version == 2) {
 301                 val32 = readl(iTCO_wdt_private.gcs);
 302                 val32 |= 0x00000020;
 303                 writel(val32, iTCO_wdt_private.gcs);
 304         } else if (iTCO_wdt_private.iTCO_version == 1) {
 305                 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
 306                 val32 |= 0x00000002;
 307                 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
 308         }
 309 }
 310
 311 static int iTCO_wdt_unset_NO_REBOOT_bit(void)
 312 {
 313         int ret = 0;
 314         u32 val32;
 315
 316         /* Unset the NO_REBOOT bit: this enables reboots */
 317         if (iTCO_wdt_private.iTCO_version == 2) {
 318                 val32 = readl(iTCO_wdt_private.gcs);
 319                 val32 &= 0xffffffdf;
 320                 writel(val32, iTCO_wdt_private.gcs);
 321
 322                 val32 = readl(iTCO_wdt_private.gcs);
 323                 if (val32 & 0x00000020)
 324                         ret = -EIO;
 325         } else if (iTCO_wdt_private.iTCO_version == 1) {
 326                 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
 327                 val32 &= 0xfffffffd;
 328                 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
 329
 330                 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
 331                 if (val32 & 0x00000002)
 332                         ret = -EIO;
 333         }
 334
 335         return ret; /* returns: 0 = OK, -EIO = Error */
 336 }
 337
 338 static int iTCO_wdt_start(void)
 339 {
 340         unsigned int val;
 341
 342         spin_lock(&iTCO_wdt_private.io_lock);
 343
 344         iTCO_vendor_pre_start(iTCO_wdt_private.ACPIBASE, heartbeat);
 345
 346         /* disable chipset's NO_REBOOT bit */
 347         if (iTCO_wdt_unset_NO_REBOOT_bit()) {
 348                 spin_unlock(&iTCO_wdt_private.io_lock);
 349                 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
 350                 return -EIO;
 351         }
 352
 353         /* Force the timer to its reload value by writing to the TCO_RLD
 354            register */
 355         if (iTCO_wdt_private.iTCO_version == 2)
 356                 outw(0x01, TCO_RLD);
 357         else if (iTCO_wdt_private.iTCO_version == 1)
 358                 outb(0x01, TCO_RLD);
 359
 360         /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
 361         val = inw(TCO1_CNT);
 362         val &= 0xf7ff;
 363         outw(val, TCO1_CNT);
 364         val = inw(TCO1_CNT);
 365         spin_unlock(&iTCO_wdt_private.io_lock);
 366
 367         if (val & 0x0800)
 368                 return -1;
 369         return 0;
 370 }
 371
 372 static int iTCO_wdt_stop(void)
 373 {
 374         unsigned int val;
 375
 376         spin_lock(&iTCO_wdt_private.io_lock);
 377
 378         iTCO_vendor_pre_stop(iTCO_wdt_private.ACPIBASE);
 379
 380         /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
 381         val = inw(TCO1_CNT);
 382         val |= 0x0800;
 383         outw(val, TCO1_CNT);
 384         val = inw(TCO1_CNT);
 385
 386         /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
 387         iTCO_wdt_set_NO_REBOOT_bit();
 388
 389         spin_unlock(&iTCO_wdt_private.io_lock);
 390
 391         if ((val & 0x0800) == 0)
 392                 return -1;
 393         return 0;
 394 }
 395
 396 static int iTCO_wdt_keepalive(void)
 397 {
 398         spin_lock(&iTCO_wdt_private.io_lock);
 399
 400         iTCO_vendor_pre_keepalive(iTCO_wdt_private.ACPIBASE, heartbeat);
 401
 402         /* Reload the timer by writing to the TCO Timer Counter register */
 403         if (iTCO_wdt_private.iTCO_version == 2)
 404                 outw(0x01, TCO_RLD);
 405         else if (iTCO_wdt_private.iTCO_version == 1)
 406                 outb(0x01, TCO_RLD);
 407
 408         spin_unlock(&iTCO_wdt_private.io_lock);
 409         return 0;
 410 }
 411
 412 static int iTCO_wdt_set_heartbeat(int t)
 413 {
 414         unsigned int val16;
 415         unsigned char val8;
 416         unsigned int tmrval;
 417
 418         tmrval = seconds_to_ticks(t);
 419         /* from the specs: */
 420         /* "Values of 0h-3h are ignored and should not be attempted" */
 421         if (tmrval < 0x04)
 422                 return -EINVAL;
 423         if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) ||
 424             ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
 425                 return -EINVAL;
 426
 427         iTCO_vendor_pre_set_heartbeat(tmrval);
 428
 429         /* Write new heartbeat to watchdog */
 430         if (iTCO_wdt_private.iTCO_version == 2) {
 431                 spin_lock(&iTCO_wdt_private.io_lock);
 432                 val16 = inw(TCOv2_TMR);
 433                 val16 &= 0xfc00;
 434                 val16 |= tmrval;
 435                 outw(val16, TCOv2_TMR);
 436                 val16 = inw(TCOv2_TMR);
 437                 spin_unlock(&iTCO_wdt_private.io_lock);
 438
 439                 if ((val16 & 0x3ff) != tmrval)
 440                         return -EINVAL;
 441         } else if (iTCO_wdt_private.iTCO_version == 1) {
 442                 spin_lock(&iTCO_wdt_private.io_lock);
 443                 val8 = inb(TCOv1_TMR);
 444                 val8 &= 0xc0;
 445                 val8 |= (tmrval & 0xff);
 446                 outb(val8, TCOv1_TMR);
 447                 val8 = inb(TCOv1_TMR);
 448                 spin_unlock(&iTCO_wdt_private.io_lock);
 449
 450                 if ((val8 & 0x3f) != tmrval)
 451                         return -EINVAL;
 452         }
 453
 454         heartbeat = t;
 455         return 0;
 456 }
 457
 458 static int iTCO_wdt_get_timeleft(int *time_left)
 459 {
 460         unsigned int val16;
 461         unsigned char val8;
 462
 463         /* read the TCO Timer */
 464         if (iTCO_wdt_private.iTCO_version == 2) {
 465                 spin_lock(&iTCO_wdt_private.io_lock);
 466                 val16 = inw(TCO_RLD);
 467                 val16 &= 0x3ff;
 468                 spin_unlock(&iTCO_wdt_private.io_lock);
 469
 470                 *time_left = (val16 * 6) / 10;
 471         } else if (iTCO_wdt_private.iTCO_version == 1) {
 472                 spin_lock(&iTCO_wdt_private.io_lock);
 473                 val8 = inb(TCO_RLD);
 474                 val8 &= 0x3f;
 475                 spin_unlock(&iTCO_wdt_private.io_lock);
 476
 477                 *time_left = (val8 * 6) / 10;
 478         } else
 479                 return -EINVAL;
 480         return 0;
 481 }
 482
 483 /*
 484  *      /dev/watchdog handling
 485  */
 486
 487 static int iTCO_wdt_open(struct inode *inode, struct file *file)
 488 {
 489         /* /dev/watchdog can only be opened once */
 490         if (test_and_set_bit(0, &is_active))
 491                 return -EBUSY;
 492
 493         /*
 494          *      Reload and activate timer
 495          */
 496         iTCO_wdt_start();
 497         return nonseekable_open(inode, file);
 498 }
 499
 500 static int iTCO_wdt_release(struct inode *inode, struct file *file)
 501 {
 502         /*
 503          *      Shut off the timer.
 504          */
 505         if (expect_release == 42) {
 506                 iTCO_wdt_stop();
 507         } else {
 508                 printk(KERN_CRIT PFX
 509                         "Unexpected close, not stopping watchdog!\n");
 510                 iTCO_wdt_keepalive();
 511         }
 512         clear_bit(0, &is_active);
 513         expect_release = 0;
 514         return 0;
 515 }
 516
 517 static ssize_t iTCO_wdt_write(struct file *file, const char __user *data,
 518                               size_t len, loff_t *ppos)
 519 {
 520         /* See if we got the magic character 'V' and reload the timer */
 521         if (len) {
 522                 if (!nowayout) {
 523                         size_t i;
 524
 525                         /* note: just in case someone wrote the magic
 526                            character five months ago... */
 527                         expect_release = 0;
 528
 529                         /* scan to see whether or not we got the
 530                            magic character */
 531                         for (i = 0; i != len; i++) {
 532                                 char c;
 533                                 if (get_user(c, data + i))
 534                                         return -EFAULT;
 535                                 if (c == 'V')
 536                                         expect_release = 42;
 537                         }
 538                 }
 539
 540                 /* someone wrote to us, we should reload the timer */
 541                 iTCO_wdt_keepalive();
 542         }
 543         return len;
 544 }
 545
 546 static long iTCO_wdt_ioctl(struct file *file, unsigned int cmd,
 547                                                         unsigned long arg)
 548 {
 549         int new_options, retval = -EINVAL;
 550         int new_heartbeat;
 551         void __user *argp = (void __user *)arg;
 552         int __user *p = argp;
 553         static struct watchdog_info ident = {
 554                 .options =              WDIOF_SETTIMEOUT |
 555                                         WDIOF_KEEPALIVEPING |
 556                                         WDIOF_MAGICCLOSE,
 557                 .firmware_version =     0,
 558                 .identity =             DRV_NAME,
 559         };
 560
 561         switch (cmd) {
 562         case WDIOC_GETSUPPORT:
 563                 return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
 564         case WDIOC_GETSTATUS:
 565         case WDIOC_GETBOOTSTATUS:
 566                 return put_user(0, p);
 567
 568         case WDIOC_SETOPTIONS:
 569         {
 570                 if (get_user(new_options, p))
 571                         return -EFAULT;
 572
 573                 if (new_options & WDIOS_DISABLECARD) {
 574                         iTCO_wdt_stop();
 575                         retval = 0;
 576                 }
 577                 if (new_options & WDIOS_ENABLECARD) {
 578                         iTCO_wdt_keepalive();
 579                         iTCO_wdt_start();
 580                         retval = 0;
 581                 }
 582                 return retval;
 583         }
 584         case WDIOC_KEEPALIVE:
 585                 iTCO_wdt_keepalive();
 586                 return 0;
 587
 588         case WDIOC_SETTIMEOUT:
 589         {
 590                 if (get_user(new_heartbeat, p))
 591                         return -EFAULT;
 592                 if (iTCO_wdt_set_heartbeat(new_heartbeat))
 593                         return -EINVAL;
 594                 iTCO_wdt_keepalive();
 595                 /* Fall */
 596         }
 597         case WDIOC_GETTIMEOUT:
 598                 return put_user(heartbeat, p);
 599         case WDIOC_GETTIMELEFT:
 600         {
 601                 int time_left;
 602                 if (iTCO_wdt_get_timeleft(&time_left))
 603                         return -EINVAL;
 604                 return put_user(time_left, p);
 605         }
 606         default:
 607                 return -ENOTTY;
 608         }
 609 }
 610
 611 /*
 612  *      Kernel Interfaces
 613  */
 614
 615 static const struct file_operations iTCO_wdt_fops = {
 616         .owner =                THIS_MODULE,
 617         .llseek =               no_llseek,
 618         .write =                iTCO_wdt_write,
 619         .unlocked_ioctl =       iTCO_wdt_ioctl,
 620         .open =                 iTCO_wdt_open,
 621         .release =              iTCO_wdt_release,
 622 };
 623
 624 static struct miscdevice iTCO_wdt_miscdev = {
 625         .minor =        WATCHDOG_MINOR,
 626         .name =         "watchdog",
 627         .fops =         &iTCO_wdt_fops,
 628 };
 629
 630 /*
 631  *      Init & exit routines
 632  */
 633
 634 static int __devinit iTCO_wdt_init(struct pci_dev *pdev,
 635                 const struct pci_device_id *ent, struct platform_device *dev)
 636 {
 637         int ret;
 638         u32 base_address;
 639         unsigned long RCBA;
 640         unsigned long val32;
 641
 642         /*
 643          *      Find the ACPI/PM base I/O address which is the base
 644          *      for the TCO registers (TCOBASE=ACPIBASE + 0x60)
 645          *      ACPIBASE is bits [15:7] from 0x40-0x43
 646          */
 647         pci_read_config_dword(pdev, 0x40, &base_address);
 648         base_address &= 0x0000ff80;
 649         if (base_address == 0x00000000) {
 650                 /* Something's wrong here, ACPIBASE has to be set */
 651                 printk(KERN_ERR PFX "failed to get TCOBASE address\n");
 652                 pci_dev_put(pdev);
 653                 return -ENODEV;
 654         }
 655         iTCO_wdt_private.iTCO_version =
 656                         iTCO_chipset_info[ent->driver_data].iTCO_version;
 657         iTCO_wdt_private.ACPIBASE = base_address;
 658         iTCO_wdt_private.pdev = pdev;
 659
 660         /* Get the Memory-Mapped GCS register, we need it for the
 661            NO_REBOOT flag (TCO v2). To get access to it you have to
 662            read RCBA from PCI Config space 0xf0 and use it as base.
 663            GCS = RCBA + ICH6_GCS(0x3410). */
 664         if (iTCO_wdt_private.iTCO_version == 2) {
 665                 pci_read_config_dword(pdev, 0xf0, &base_address);
 666                 RCBA = base_address & 0xffffc000;
 667                 iTCO_wdt_private.gcs = ioremap((RCBA + 0x3410), 4);
 668         }
 669
 670         /* Check chipset's NO_REBOOT bit */
 671         if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
 672                 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, reboot disabled by hardware\n");
 673                 ret = -ENODEV;  /* Cannot reset NO_REBOOT bit */
 674                 goto out;
 675         }
 676
 677         /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
 678         iTCO_wdt_set_NO_REBOOT_bit();
 679
 680         /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
 681         if (!request_region(SMI_EN, 4, "iTCO_wdt")) {
 682                 printk(KERN_ERR PFX
 683                         "I/O address 0x%04lx already in use\n", SMI_EN);
 684                 ret = -EIO;
 685                 goto out;
 686         }
 687         /* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */
 688         val32 = inl(SMI_EN);
 689         val32 &= 0xffffdfff;    /* Turn off SMI clearing watchdog */
 690         outl(val32, SMI_EN);
 691
 692         /* The TCO I/O registers reside in a 32-byte range pointed to
 693            by the TCOBASE value */
 694         if (!request_region(TCOBASE, 0x20, "iTCO_wdt")) {
 695                 printk(KERN_ERR PFX "I/O address 0x%04lx already in use\n",
 696                         TCOBASE);
 697                 ret = -EIO;
 698                 goto unreg_smi_en;
 699         }
 700
 701         printk(KERN_INFO PFX
 702                 "Found a %s TCO device (Version=%d, TCOBASE=0x%04lx)\n",
 703                         iTCO_chipset_info[ent->driver_data].name,
 704                         iTCO_chipset_info[ent->driver_data].iTCO_version,
 705                         TCOBASE);
 706
 707         /* Clear out the (probably old) status */
 708         outb(8, TCO1_STS);      /* Clear the Time Out Status bit */
 709         outb(2, TCO2_STS);      /* Clear SECOND_TO_STS bit */
 710         outb(4, TCO2_STS);      /* Clear BOOT_STS bit */
 711
 712         /* Make sure the watchdog is not running */
 713         iTCO_wdt_stop();
 714
 715         /* Check that the heartbeat value is within it's range;
 716            if not reset to the default */
 717         if (iTCO_wdt_set_heartbeat(heartbeat)) {
 718                 iTCO_wdt_set_heartbeat(WATCHDOG_HEARTBEAT);
 719                 printk(KERN_INFO PFX "heartbeat value must be 2 < heartbeat < 39 (TCO v1) or 613 (TCO v2), using %d\n",
 720                                                         heartbeat);
 721         }
 722
 723         ret = misc_register(&iTCO_wdt_miscdev);
 724         if (ret != 0) {
 725                 printk(KERN_ERR PFX
 726                         "cannot register miscdev on minor=%d (err=%d)\n",
 727                                                         WATCHDOG_MINOR, ret);
 728                 goto unreg_region;
 729         }
 730
 731         printk(KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n",
 732                                                         heartbeat, nowayout);
 733
 734         return 0;
 735
 736 unreg_region:
 737         release_region(TCOBASE, 0x20);
 738 unreg_smi_en:
 739         release_region(SMI_EN, 4);
 740 out:
 741         if (iTCO_wdt_private.iTCO_version == 2)
 742                 iounmap(iTCO_wdt_private.gcs);
 743         pci_dev_put(iTCO_wdt_private.pdev);
 744         iTCO_wdt_private.ACPIBASE = 0;
 745         return ret;
 746 }
 747
 748 static void __devexit iTCO_wdt_cleanup(void)
 749 {
 750         /* Stop the timer before we leave */
 751         if (!nowayout)
 752                 iTCO_wdt_stop();
 753
 754         /* Deregister */
 755         misc_deregister(&iTCO_wdt_miscdev);
 756         release_region(TCOBASE, 0x20);
 757         release_region(SMI_EN, 4);
 758         if (iTCO_wdt_private.iTCO_version == 2)
 759                 iounmap(iTCO_wdt_private.gcs);
 760         pci_dev_put(iTCO_wdt_private.pdev);
 761         iTCO_wdt_private.ACPIBASE = 0;
 762 }
 763
 764 static int __devinit iTCO_wdt_probe(struct platform_device *dev)
 765 {
 766         int found = 0;
 767         struct pci_dev *pdev = NULL;
 768         const struct pci_device_id *ent;
 769
 770         spin_lock_init(&iTCO_wdt_private.io_lock);
 771
 772         for_each_pci_dev(pdev) {
 773                 ent = pci_match_id(iTCO_wdt_pci_tbl, pdev);
 774                 if (ent) {
 775                         if (!(iTCO_wdt_init(pdev, ent, dev))) {
 776                                 found++;
 777                                 break;
 778                         }
 779                 }
 780         }
 781
 782         if (!found) {
 783                 printk(KERN_INFO PFX "No card detected\n");
 784                 return -ENODEV;
 785         }
 786
 787         return 0;
 788 }
 789
 790 static int __devexit iTCO_wdt_remove(struct platform_device *dev)
 791 {
 792         if (iTCO_wdt_private.ACPIBASE)
 793                 iTCO_wdt_cleanup();
 794
 795         return 0;
 796 }
 797
 798 static void iTCO_wdt_shutdown(struct platform_device *dev)
 799 {
 800         iTCO_wdt_stop();
 801 }
 802
 803 #define iTCO_wdt_suspend NULL
 804 #define iTCO_wdt_resume  NULL
 805
 806 static struct platform_driver iTCO_wdt_driver = {
 807         .probe          = iTCO_wdt_probe,
 808         .remove         = __devexit_p(iTCO_wdt_remove),
 809         .shutdown       = iTCO_wdt_shutdown,
 810         .suspend        = iTCO_wdt_suspend,
 811         .resume         = iTCO_wdt_resume,
 812         .driver         = {
 813                 .owner  = THIS_MODULE,
 814                 .name   = DRV_NAME,
 815         },
 816 };
 817
 818 static int __init iTCO_wdt_init_module(void)
 819 {
 820         int err;
 821
 822         printk(KERN_INFO PFX "Intel TCO WatchDog Timer Driver v%s\n",
 823                 DRV_VERSION);
 824
 825         err = platform_driver_register(&iTCO_wdt_driver);
 826         if (err)
 827                 return err;
 828
 829         iTCO_wdt_platform_device = platform_device_register_simple(DRV_NAME,
 830                                                                 -1, NULL, 0);
 831         if (IS_ERR(iTCO_wdt_platform_device)) {
 832                 err = PTR_ERR(iTCO_wdt_platform_device);
 833                 goto unreg_platform_driver;
 834         }
 835
 836         return 0;
 837
 838 unreg_platform_driver:
 839         platform_driver_unregister(&iTCO_wdt_driver);
 840         return err;
 841 }
 842
 843 static void __exit iTCO_wdt_cleanup_module(void)
 844 {
 845         platform_device_unregister(iTCO_wdt_platform_device);
 846         platform_driver_unregister(&iTCO_wdt_driver);
 847         printk(KERN_INFO PFX "Watchdog Module Unloaded.\n");
 848 }
 849
 850 module_init(iTCO_wdt_init_module);
 851 module_exit(iTCO_wdt_cleanup_module);
 852
 853 MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
 854 MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
 855 MODULE_VERSION(DRV_VERSION);
 856 MODULE_LICENSE("GPL");
 857 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);