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[ALSA] ice1712 - disable unused ADCs & DACs on DMX6fire
[linux-2.6/mini2440.git] / drivers / scsi / sata_mv.c
blob2770005324b4bac76781154ffe6543ecda049a82
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2005: EMC Corporation, all rights reserved.
5 * Copyright 2005 Red Hat, Inc. All rights reserved.
6 *
7 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include <linux/interrupt.h>
31 #include <linux/sched.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/device.h>
34 #include <scsi/scsi_host.h>
35 #include <scsi/scsi_cmnd.h>
36 #include <linux/libata.h>
37 #include <asm/io.h>
38
39 #define DRV_NAME "sata_mv"
40 #define DRV_VERSION "0.5"
41
42 enum {
43 /* BAR's are enumerated in terms of pci_resource_start() terms */
44 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
45 MV_IO_BAR = 2, /* offset 0x18: IO space */
46 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
47
48 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
49 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
50
51 MV_PCI_REG_BASE = 0,
52 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
53 MV_SATAHC0_REG_BASE = 0x20000,
54 MV_FLASH_CTL = 0x1046c,
55 MV_GPIO_PORT_CTL = 0x104f0,
56 MV_RESET_CFG = 0x180d8,
57
58 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
59 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
60 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
61 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
62
63 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
64
65 MV_MAX_Q_DEPTH = 32,
66 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
67
68 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
69 * CRPB needs alignment on a 256B boundary. Size == 256B
70 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
71 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
72 */
73 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
74 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
75 MV_MAX_SG_CT = 176,
76 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
77 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
78
79 MV_PORTS_PER_HC = 4,
80 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
81 MV_PORT_HC_SHIFT = 2,
82 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
83 MV_PORT_MASK = 3,
84
85 /* Host Flags */
86 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
87 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
88 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
89 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
90 ATA_FLAG_NO_ATAPI),
91 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
92
93 CRQB_FLAG_READ = (1 << 0),
94 CRQB_TAG_SHIFT = 1,
95 CRQB_CMD_ADDR_SHIFT = 8,
96 CRQB_CMD_CS = (0x2 << 11),
97 CRQB_CMD_LAST = (1 << 15),
98
99 CRPB_FLAG_STATUS_SHIFT = 8,
100
101 EPRD_FLAG_END_OF_TBL = (1 << 31),
102
103 /* PCI interface registers */
104
105 PCI_COMMAND_OFS = 0xc00,
106
107 PCI_MAIN_CMD_STS_OFS = 0xd30,
108 STOP_PCI_MASTER = (1 << 2),
109 PCI_MASTER_EMPTY = (1 << 3),
110 GLOB_SFT_RST = (1 << 4),
111
112 MV_PCI_MODE = 0xd00,
113 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
114 MV_PCI_DISC_TIMER = 0xd04,
115 MV_PCI_MSI_TRIGGER = 0xc38,
116 MV_PCI_SERR_MASK = 0xc28,
117 MV_PCI_XBAR_TMOUT = 0x1d04,
118 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
119 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
120 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
121 MV_PCI_ERR_COMMAND = 0x1d50,
122
123 PCI_IRQ_CAUSE_OFS = 0x1d58,
124 PCI_IRQ_MASK_OFS = 0x1d5c,
125 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
126
127 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
128 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
129 PORT0_ERR = (1 << 0), /* shift by port # */
130 PORT0_DONE = (1 << 1), /* shift by port # */
131 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
132 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
133 PCI_ERR = (1 << 18),
134 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
135 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
136 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
137 GPIO_INT = (1 << 22),
138 SELF_INT = (1 << 23),
139 TWSI_INT = (1 << 24),
140 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
141 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
142 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
143 HC_MAIN_RSVD),
144
145 /* SATAHC registers */
146 HC_CFG_OFS = 0,
147
148 HC_IRQ_CAUSE_OFS = 0x14,
149 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
150 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
151 DEV_IRQ = (1 << 8), /* shift by port # */
152
153 /* Shadow block registers */
154 SHD_BLK_OFS = 0x100,
155 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
156
157 /* SATA registers */
158 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
159 SATA_ACTIVE_OFS = 0x350,
160 PHY_MODE3 = 0x310,
161 PHY_MODE4 = 0x314,
162 PHY_MODE2 = 0x330,
163 MV5_PHY_MODE = 0x74,
164 MV5_LT_MODE = 0x30,
165 MV5_PHY_CTL = 0x0C,
166 SATA_INTERFACE_CTL = 0x050,
167
168 MV_M2_PREAMP_MASK = 0x7e0,
169
170 /* Port registers */
171 EDMA_CFG_OFS = 0,
172 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
173 EDMA_CFG_NCQ = (1 << 5),
174 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
175 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
176 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
177
178 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
179 EDMA_ERR_IRQ_MASK_OFS = 0xc,
180 EDMA_ERR_D_PAR = (1 << 0),
181 EDMA_ERR_PRD_PAR = (1 << 1),
182 EDMA_ERR_DEV = (1 << 2),
183 EDMA_ERR_DEV_DCON = (1 << 3),
184 EDMA_ERR_DEV_CON = (1 << 4),
185 EDMA_ERR_SERR = (1 << 5),
186 EDMA_ERR_SELF_DIS = (1 << 7),
187 EDMA_ERR_BIST_ASYNC = (1 << 8),
188 EDMA_ERR_CRBQ_PAR = (1 << 9),
189 EDMA_ERR_CRPB_PAR = (1 << 10),
190 EDMA_ERR_INTRL_PAR = (1 << 11),
191 EDMA_ERR_IORDY = (1 << 12),
192 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
193 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
194 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
195 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
196 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
197 EDMA_ERR_TRANS_PROTO = (1 << 31),
198 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
199 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
200 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
201 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
202 EDMA_ERR_LNK_DATA_RX |
203 EDMA_ERR_LNK_DATA_TX |
204 EDMA_ERR_TRANS_PROTO),
205
206 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
207 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
208
209 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
210 EDMA_REQ_Q_PTR_SHIFT = 5,
211
212 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
213 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
214 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
215 EDMA_RSP_Q_PTR_SHIFT = 3,
216
217 EDMA_CMD_OFS = 0x28,
218 EDMA_EN = (1 << 0),
219 EDMA_DS = (1 << 1),
220 ATA_RST = (1 << 2),
221
222 EDMA_IORDY_TMOUT = 0x34,
223 EDMA_ARB_CFG = 0x38,
224
225 /* Host private flags (hp_flags) */
226 MV_HP_FLAG_MSI = (1 << 0),
227 MV_HP_ERRATA_50XXB0 = (1 << 1),
228 MV_HP_ERRATA_50XXB2 = (1 << 2),
229 MV_HP_ERRATA_60X1B2 = (1 << 3),
230 MV_HP_ERRATA_60X1C0 = (1 << 4),
231 MV_HP_50XX = (1 << 5),
232
233 /* Port private flags (pp_flags) */
234 MV_PP_FLAG_EDMA_EN = (1 << 0),
235 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
236 };
237
238 #define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
239 #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
240
241 enum {
242 /* Our DMA boundary is determined by an ePRD being unable to handle
243 * anything larger than 64KB
244 */
245 MV_DMA_BOUNDARY = 0xffffU,
246
247 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
248
249 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
250 };
251
252 enum chip_type {
253 chip_504x,
254 chip_508x,
255 chip_5080,
256 chip_604x,
257 chip_608x,
258 };
259
260 /* Command ReQuest Block: 32B */
261 struct mv_crqb {
262 u32 sg_addr;
263 u32 sg_addr_hi;
264 u16 ctrl_flags;
265 u16 ata_cmd[11];
266 };
267
268 /* Command ResPonse Block: 8B */
269 struct mv_crpb {
270 u16 id;
271 u16 flags;
272 u32 tmstmp;
273 };
274
275 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
276 struct mv_sg {
277 u32 addr;
278 u32 flags_size;
279 u32 addr_hi;
280 u32 reserved;
281 };
282
283 struct mv_port_priv {
284 struct mv_crqb *crqb;
285 dma_addr_t crqb_dma;
286 struct mv_crpb *crpb;
287 dma_addr_t crpb_dma;
288 struct mv_sg *sg_tbl;
289 dma_addr_t sg_tbl_dma;
290
291 unsigned req_producer; /* cp of req_in_ptr */
292 unsigned rsp_consumer; /* cp of rsp_out_ptr */
293 u32 pp_flags;
294 };
295
296 struct mv_port_signal {
297 u32 amps;
298 u32 pre;
299 };
300
301 struct mv_host_priv;
302 struct mv_hw_ops {
303 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
304 unsigned int port);
305 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
306 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
307 void __iomem *mmio);
308 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
309 unsigned int n_hc);
310 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
311 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
312 };
313
314 struct mv_host_priv {
315 u32 hp_flags;
316 struct mv_port_signal signal[8];
317 const struct mv_hw_ops *ops;
318 };
319
320 static void mv_irq_clear(struct ata_port *ap);
321 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
322 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
323 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
324 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
325 static void mv_phy_reset(struct ata_port *ap);
326 static void __mv_phy_reset(struct ata_port *ap, int can_sleep);
327 static void mv_host_stop(struct ata_host_set *host_set);
328 static int mv_port_start(struct ata_port *ap);
329 static void mv_port_stop(struct ata_port *ap);
330 static void mv_qc_prep(struct ata_queued_cmd *qc);
331 static int mv_qc_issue(struct ata_queued_cmd *qc);
332 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
333 struct pt_regs *regs);
334 static void mv_eng_timeout(struct ata_port *ap);
335 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
336
337 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
338 unsigned int port);
339 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
340 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
341 void __iomem *mmio);
342 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
343 unsigned int n_hc);
344 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
345 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
346
347 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
348 unsigned int port);
349 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
350 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
351 void __iomem *mmio);
352 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
353 unsigned int n_hc);
354 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
355 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
356 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
357 unsigned int port_no);
358 static void mv_stop_and_reset(struct ata_port *ap);
359
360 static struct scsi_host_template mv_sht = {
361 .module = THIS_MODULE,
362 .name = DRV_NAME,
363 .ioctl = ata_scsi_ioctl,
364 .queuecommand = ata_scsi_queuecmd,
365 .eh_strategy_handler = ata_scsi_error,
366 .can_queue = MV_USE_Q_DEPTH,
367 .this_id = ATA_SHT_THIS_ID,
368 .sg_tablesize = MV_MAX_SG_CT / 2,
369 .max_sectors = ATA_MAX_SECTORS,
370 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
371 .emulated = ATA_SHT_EMULATED,
372 .use_clustering = ATA_SHT_USE_CLUSTERING,
373 .proc_name = DRV_NAME,
374 .dma_boundary = MV_DMA_BOUNDARY,
375 .slave_configure = ata_scsi_slave_config,
376 .bios_param = ata_std_bios_param,
377 };
378
379 static const struct ata_port_operations mv5_ops = {
380 .port_disable = ata_port_disable,
381
382 .tf_load = ata_tf_load,
383 .tf_read = ata_tf_read,
384 .check_status = ata_check_status,
385 .exec_command = ata_exec_command,
386 .dev_select = ata_std_dev_select,
387
388 .phy_reset = mv_phy_reset,
389
390 .qc_prep = mv_qc_prep,
391 .qc_issue = mv_qc_issue,
392
393 .eng_timeout = mv_eng_timeout,
394
395 .irq_handler = mv_interrupt,
396 .irq_clear = mv_irq_clear,
397
398 .scr_read = mv5_scr_read,
399 .scr_write = mv5_scr_write,
400
401 .port_start = mv_port_start,
402 .port_stop = mv_port_stop,
403 .host_stop = mv_host_stop,
404 };
405
406 static const struct ata_port_operations mv6_ops = {
407 .port_disable = ata_port_disable,
408
409 .tf_load = ata_tf_load,
410 .tf_read = ata_tf_read,
411 .check_status = ata_check_status,
412 .exec_command = ata_exec_command,
413 .dev_select = ata_std_dev_select,
414
415 .phy_reset = mv_phy_reset,
416
417 .qc_prep = mv_qc_prep,
418 .qc_issue = mv_qc_issue,
419
420 .eng_timeout = mv_eng_timeout,
421
422 .irq_handler = mv_interrupt,
423 .irq_clear = mv_irq_clear,
424
425 .scr_read = mv_scr_read,
426 .scr_write = mv_scr_write,
427
428 .port_start = mv_port_start,
429 .port_stop = mv_port_stop,
430 .host_stop = mv_host_stop,
431 };
432
433 static const struct ata_port_info mv_port_info[] = {
434 { /* chip_504x */
435 .sht = &mv_sht,
436 .host_flags = MV_COMMON_FLAGS,
437 .pio_mask = 0x1f, /* pio0-4 */
438 .udma_mask = 0x7f, /* udma0-6 */
439 .port_ops = &mv5_ops,
440 },
441 { /* chip_508x */
442 .sht = &mv_sht,
443 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
444 .pio_mask = 0x1f, /* pio0-4 */
445 .udma_mask = 0x7f, /* udma0-6 */
446 .port_ops = &mv5_ops,
447 },
448 { /* chip_5080 */
449 .sht = &mv_sht,
450 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
451 .pio_mask = 0x1f, /* pio0-4 */
452 .udma_mask = 0x7f, /* udma0-6 */
453 .port_ops = &mv5_ops,
454 },
455 { /* chip_604x */
456 .sht = &mv_sht,
457 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
458 .pio_mask = 0x1f, /* pio0-4 */
459 .udma_mask = 0x7f, /* udma0-6 */
460 .port_ops = &mv6_ops,
461 },
462 { /* chip_608x */
463 .sht = &mv_sht,
464 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
465 MV_FLAG_DUAL_HC),
466 .pio_mask = 0x1f, /* pio0-4 */
467 .udma_mask = 0x7f, /* udma0-6 */
468 .port_ops = &mv6_ops,
469 },
470 };
471
472 static const struct pci_device_id mv_pci_tbl[] = {
473 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x},
474 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x},
475 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_5080},
476 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x},
477
478 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x},
479 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6041), 0, 0, chip_604x},
480 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6080), 0, 0, chip_608x},
481 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6081), 0, 0, chip_608x},
482
483 {PCI_DEVICE(PCI_VENDOR_ID_ADAPTEC2, 0x0241), 0, 0, chip_604x},
484 {} /* terminate list */
485 };
486
487 static struct pci_driver mv_pci_driver = {
488 .name = DRV_NAME,
489 .id_table = mv_pci_tbl,
490 .probe = mv_init_one,
491 .remove = ata_pci_remove_one,
492 };
493
494 static const struct mv_hw_ops mv5xxx_ops = {
495 .phy_errata = mv5_phy_errata,
496 .enable_leds = mv5_enable_leds,
497 .read_preamp = mv5_read_preamp,
498 .reset_hc = mv5_reset_hc,
499 .reset_flash = mv5_reset_flash,
500 .reset_bus = mv5_reset_bus,
501 };
502
503 static const struct mv_hw_ops mv6xxx_ops = {
504 .phy_errata = mv6_phy_errata,
505 .enable_leds = mv6_enable_leds,
506 .read_preamp = mv6_read_preamp,
507 .reset_hc = mv6_reset_hc,
508 .reset_flash = mv6_reset_flash,
509 .reset_bus = mv_reset_pci_bus,
510 };
511
512 /*
513 * module options
514 */
515 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
516
517
518 /*
519 * Functions
520 */
521
522 static inline void writelfl(unsigned long data, void __iomem *addr)
523 {
524 writel(data, addr);
525 (void) readl(addr); /* flush to avoid PCI posted write */
526 }
527
528 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
529 {
530 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
531 }
532
533 static inline unsigned int mv_hc_from_port(unsigned int port)
534 {
535 return port >> MV_PORT_HC_SHIFT;
536 }
537
538 static inline unsigned int mv_hardport_from_port(unsigned int port)
539 {
540 return port & MV_PORT_MASK;
541 }
542
543 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
544 unsigned int port)
545 {
546 return mv_hc_base(base, mv_hc_from_port(port));
547 }
548
549 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
550 {
551 return mv_hc_base_from_port(base, port) +
552 MV_SATAHC_ARBTR_REG_SZ +
553 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
554 }
555
556 static inline void __iomem *mv_ap_base(struct ata_port *ap)
557 {
558 return mv_port_base(ap->host_set->mmio_base, ap->port_no);
559 }
560
561 static inline int mv_get_hc_count(unsigned long host_flags)
562 {
563 return ((host_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
564 }
565
566 static void mv_irq_clear(struct ata_port *ap)
567 {
568 }
569
570 /**
571 * mv_start_dma - Enable eDMA engine
572 * @base: port base address
573 * @pp: port private data
574 *
575 * Verify the local cache of the eDMA state is accurate with an
576 * assert.
577 *
578 * LOCKING:
579 * Inherited from caller.
580 */
581 static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
582 {
583 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
584 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
585 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
586 }
587 assert(EDMA_EN & readl(base + EDMA_CMD_OFS));
588 }
589
590 /**
591 * mv_stop_dma - Disable eDMA engine
592 * @ap: ATA channel to manipulate
593 *
594 * Verify the local cache of the eDMA state is accurate with an
595 * assert.
596 *
597 * LOCKING:
598 * Inherited from caller.
599 */
600 static void mv_stop_dma(struct ata_port *ap)
601 {
602 void __iomem *port_mmio = mv_ap_base(ap);
603 struct mv_port_priv *pp = ap->private_data;
604 u32 reg;
605 int i;
606
607 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
608 /* Disable EDMA if active. The disable bit auto clears.
609 */
610 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
611 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
612 } else {
613 assert(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS)));
614 }
615
616 /* now properly wait for the eDMA to stop */
617 for (i = 1000; i > 0; i--) {
618 reg = readl(port_mmio + EDMA_CMD_OFS);
619 if (!(EDMA_EN & reg)) {
620 break;
621 }
622 udelay(100);
623 }
624
625 if (EDMA_EN & reg) {
626 printk(KERN_ERR "ata%u: Unable to stop eDMA\n", ap->id);
627 /* FIXME: Consider doing a reset here to recover */
628 }
629 }
630
631 #ifdef ATA_DEBUG
632 static void mv_dump_mem(void __iomem *start, unsigned bytes)
633 {
634 int b, w;
635 for (b = 0; b < bytes; ) {
636 DPRINTK("%p: ", start + b);
637 for (w = 0; b < bytes && w < 4; w++) {
638 printk("%08x ",readl(start + b));
639 b += sizeof(u32);
640 }
641 printk("\n");
642 }
643 }
644 #endif
645
646 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
647 {
648 #ifdef ATA_DEBUG
649 int b, w;
650 u32 dw;
651 for (b = 0; b < bytes; ) {
652 DPRINTK("%02x: ", b);
653 for (w = 0; b < bytes && w < 4; w++) {
654 (void) pci_read_config_dword(pdev,b,&dw);
655 printk("%08x ",dw);
656 b += sizeof(u32);
657 }
658 printk("\n");
659 }
660 #endif
661 }
662 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
663 struct pci_dev *pdev)
664 {
665 #ifdef ATA_DEBUG
666 void __iomem *hc_base = mv_hc_base(mmio_base,
667 port >> MV_PORT_HC_SHIFT);
668 void __iomem *port_base;
669 int start_port, num_ports, p, start_hc, num_hcs, hc;
670
671 if (0 > port) {
672 start_hc = start_port = 0;
673 num_ports = 8; /* shld be benign for 4 port devs */
674 num_hcs = 2;
675 } else {
676 start_hc = port >> MV_PORT_HC_SHIFT;
677 start_port = port;
678 num_ports = num_hcs = 1;
679 }
680 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
681 num_ports > 1 ? num_ports - 1 : start_port);
682
683 if (NULL != pdev) {
684 DPRINTK("PCI config space regs:\n");
685 mv_dump_pci_cfg(pdev, 0x68);
686 }
687 DPRINTK("PCI regs:\n");
688 mv_dump_mem(mmio_base+0xc00, 0x3c);
689 mv_dump_mem(mmio_base+0xd00, 0x34);
690 mv_dump_mem(mmio_base+0xf00, 0x4);
691 mv_dump_mem(mmio_base+0x1d00, 0x6c);
692 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
693 hc_base = mv_hc_base(mmio_base, port >> MV_PORT_HC_SHIFT);
694 DPRINTK("HC regs (HC %i):\n", hc);
695 mv_dump_mem(hc_base, 0x1c);
696 }
697 for (p = start_port; p < start_port + num_ports; p++) {
698 port_base = mv_port_base(mmio_base, p);
699 DPRINTK("EDMA regs (port %i):\n",p);
700 mv_dump_mem(port_base, 0x54);
701 DPRINTK("SATA regs (port %i):\n",p);
702 mv_dump_mem(port_base+0x300, 0x60);
703 }
704 #endif
705 }
706
707 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
708 {
709 unsigned int ofs;
710
711 switch (sc_reg_in) {
712 case SCR_STATUS:
713 case SCR_CONTROL:
714 case SCR_ERROR:
715 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
716 break;
717 case SCR_ACTIVE:
718 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
719 break;
720 default:
721 ofs = 0xffffffffU;
722 break;
723 }
724 return ofs;
725 }
726
727 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
728 {
729 unsigned int ofs = mv_scr_offset(sc_reg_in);
730
731 if (0xffffffffU != ofs) {
732 return readl(mv_ap_base(ap) + ofs);
733 } else {
734 return (u32) ofs;
735 }
736 }
737
738 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
739 {
740 unsigned int ofs = mv_scr_offset(sc_reg_in);
741
742 if (0xffffffffU != ofs) {
743 writelfl(val, mv_ap_base(ap) + ofs);
744 }
745 }
746
747 /**
748 * mv_host_stop - Host specific cleanup/stop routine.
749 * @host_set: host data structure
750 *
751 * Disable ints, cleanup host memory, call general purpose
752 * host_stop.
753 *
754 * LOCKING:
755 * Inherited from caller.
756 */
757 static void mv_host_stop(struct ata_host_set *host_set)
758 {
759 struct mv_host_priv *hpriv = host_set->private_data;
760 struct pci_dev *pdev = to_pci_dev(host_set->dev);
761
762 if (hpriv->hp_flags & MV_HP_FLAG_MSI) {
763 pci_disable_msi(pdev);
764 } else {
765 pci_intx(pdev, 0);
766 }
767 kfree(hpriv);
768 ata_host_stop(host_set);
769 }
770
771 static inline void mv_priv_free(struct mv_port_priv *pp, struct device *dev)
772 {
773 dma_free_coherent(dev, MV_PORT_PRIV_DMA_SZ, pp->crpb, pp->crpb_dma);
774 }
775
776 /**
777 * mv_port_start - Port specific init/start routine.
778 * @ap: ATA channel to manipulate
779 *
780 * Allocate and point to DMA memory, init port private memory,
781 * zero indices.
782 *
783 * LOCKING:
784 * Inherited from caller.
785 */
786 static int mv_port_start(struct ata_port *ap)
787 {
788 struct device *dev = ap->host_set->dev;
789 struct mv_port_priv *pp;
790 void __iomem *port_mmio = mv_ap_base(ap);
791 void *mem;
792 dma_addr_t mem_dma;
793 int rc = -ENOMEM;
794
795 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
796 if (!pp)
797 goto err_out;
798 memset(pp, 0, sizeof(*pp));
799
800 mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
801 GFP_KERNEL);
802 if (!mem)
803 goto err_out_pp;
804 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
805
806 rc = ata_pad_alloc(ap, dev);
807 if (rc)
808 goto err_out_priv;
809
810 /* First item in chunk of DMA memory:
811 * 32-slot command request table (CRQB), 32 bytes each in size
812 */
813 pp->crqb = mem;
814 pp->crqb_dma = mem_dma;
815 mem += MV_CRQB_Q_SZ;
816 mem_dma += MV_CRQB_Q_SZ;
817
818 /* Second item:
819 * 32-slot command response table (CRPB), 8 bytes each in size
820 */
821 pp->crpb = mem;
822 pp->crpb_dma = mem_dma;
823 mem += MV_CRPB_Q_SZ;
824 mem_dma += MV_CRPB_Q_SZ;
825
826 /* Third item:
827 * Table of scatter-gather descriptors (ePRD), 16 bytes each
828 */
829 pp->sg_tbl = mem;
830 pp->sg_tbl_dma = mem_dma;
831
832 writelfl(EDMA_CFG_Q_DEPTH | EDMA_CFG_RD_BRST_EXT |
833 EDMA_CFG_WR_BUFF_LEN, port_mmio + EDMA_CFG_OFS);
834
835 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
836 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
837 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
838
839 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
840 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
841
842 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
843 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
844 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
845
846 pp->req_producer = pp->rsp_consumer = 0;
847
848 /* Don't turn on EDMA here...do it before DMA commands only. Else
849 * we'll be unable to send non-data, PIO, etc due to restricted access
850 * to shadow regs.
851 */
852 ap->private_data = pp;
853 return 0;
854
855 err_out_priv:
856 mv_priv_free(pp, dev);
857 err_out_pp:
858 kfree(pp);
859 err_out:
860 return rc;
861 }
862
863 /**
864 * mv_port_stop - Port specific cleanup/stop routine.
865 * @ap: ATA channel to manipulate
866 *
867 * Stop DMA, cleanup port memory.
868 *
869 * LOCKING:
870 * This routine uses the host_set lock to protect the DMA stop.
871 */
872 static void mv_port_stop(struct ata_port *ap)
873 {
874 struct device *dev = ap->host_set->dev;
875 struct mv_port_priv *pp = ap->private_data;
876 unsigned long flags;
877
878 spin_lock_irqsave(&ap->host_set->lock, flags);
879 mv_stop_dma(ap);
880 spin_unlock_irqrestore(&ap->host_set->lock, flags);
881
882 ap->private_data = NULL;
883 ata_pad_free(ap, dev);
884 mv_priv_free(pp, dev);
885 kfree(pp);
886 }
887
888 /**
889 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
890 * @qc: queued command whose SG list to source from
891 *
892 * Populate the SG list and mark the last entry.
893 *
894 * LOCKING:
895 * Inherited from caller.
896 */
897 static void mv_fill_sg(struct ata_queued_cmd *qc)
898 {
899 struct mv_port_priv *pp = qc->ap->private_data;
900 unsigned int i = 0;
901 struct scatterlist *sg;
902
903 ata_for_each_sg(sg, qc) {
904 dma_addr_t addr;
905 u32 sg_len, len, offset;
906
907 addr = sg_dma_address(sg);
908 sg_len = sg_dma_len(sg);
909
910 while (sg_len) {
911 offset = addr & MV_DMA_BOUNDARY;
912 len = sg_len;
913 if ((offset + sg_len) > 0x10000)
914 len = 0x10000 - offset;
915
916 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
917 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
918 pp->sg_tbl[i].flags_size = cpu_to_le32(len);
919
920 sg_len -= len;
921 addr += len;
922
923 if (!sg_len && ata_sg_is_last(sg, qc))
924 pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
925
926 i++;
927 }
928 }
929 }
930
931 static inline unsigned mv_inc_q_index(unsigned *index)
932 {
933 *index = (*index + 1) & MV_MAX_Q_DEPTH_MASK;
934 return *index;
935 }
936
937 static inline void mv_crqb_pack_cmd(u16 *cmdw, u8 data, u8 addr, unsigned last)
938 {
939 *cmdw = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
940 (last ? CRQB_CMD_LAST : 0);
941 }
942
943 /**
944 * mv_qc_prep - Host specific command preparation.
945 * @qc: queued command to prepare
946 *
947 * This routine simply redirects to the general purpose routine
948 * if command is not DMA. Else, it handles prep of the CRQB
949 * (command request block), does some sanity checking, and calls
950 * the SG load routine.
951 *
952 * LOCKING:
953 * Inherited from caller.
954 */
955 static void mv_qc_prep(struct ata_queued_cmd *qc)
956 {
957 struct ata_port *ap = qc->ap;
958 struct mv_port_priv *pp = ap->private_data;
959 u16 *cw;
960 struct ata_taskfile *tf;
961 u16 flags = 0;
962
963 if (ATA_PROT_DMA != qc->tf.protocol) {
964 return;
965 }
966
967 /* the req producer index should be the same as we remember it */
968 assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >>
969 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
970 pp->req_producer);
971
972 /* Fill in command request block
973 */
974 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
975 flags |= CRQB_FLAG_READ;
976 }
977 assert(MV_MAX_Q_DEPTH > qc->tag);
978 flags |= qc->tag << CRQB_TAG_SHIFT;
979
980 pp->crqb[pp->req_producer].sg_addr =
981 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
982 pp->crqb[pp->req_producer].sg_addr_hi =
983 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
984 pp->crqb[pp->req_producer].ctrl_flags = cpu_to_le16(flags);
985
986 cw = &pp->crqb[pp->req_producer].ata_cmd[0];
987 tf = &qc->tf;
988
989 /* Sadly, the CRQB cannot accomodate all registers--there are
990 * only 11 bytes...so we must pick and choose required
991 * registers based on the command. So, we drop feature and
992 * hob_feature for [RW] DMA commands, but they are needed for
993 * NCQ. NCQ will drop hob_nsect.
994 */
995 switch (tf->command) {
996 case ATA_CMD_READ:
997 case ATA_CMD_READ_EXT:
998 case ATA_CMD_WRITE:
999 case ATA_CMD_WRITE_EXT:
1000 case ATA_CMD_WRITE_FUA_EXT:
1001 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1002 break;
1003 #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
1004 case ATA_CMD_FPDMA_READ:
1005 case ATA_CMD_FPDMA_WRITE:
1006 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1007 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1008 break;
1009 #endif /* FIXME: remove this line when NCQ added */
1010 default:
1011 /* The only other commands EDMA supports in non-queued and
1012 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1013 * of which are defined/used by Linux. If we get here, this
1014 * driver needs work.
1015 *
1016 * FIXME: modify libata to give qc_prep a return value and
1017 * return error here.
1018 */
1019 BUG_ON(tf->command);
1020 break;
1021 }
1022 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1023 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1024 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1025 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1026 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1027 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1028 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1029 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1030 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1031
1032 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) {
1033 return;
1034 }
1035 mv_fill_sg(qc);
1036 }
1037
1038 /**
1039 * mv_qc_issue - Initiate a command to the host
1040 * @qc: queued command to start
1041 *
1042 * This routine simply redirects to the general purpose routine
1043 * if command is not DMA. Else, it sanity checks our local
1044 * caches of the request producer/consumer indices then enables
1045 * DMA and bumps the request producer index.
1046 *
1047 * LOCKING:
1048 * Inherited from caller.
1049 */
1050 static int mv_qc_issue(struct ata_queued_cmd *qc)
1051 {
1052 void __iomem *port_mmio = mv_ap_base(qc->ap);
1053 struct mv_port_priv *pp = qc->ap->private_data;
1054 u32 in_ptr;
1055
1056 if (ATA_PROT_DMA != qc->tf.protocol) {
1057 /* We're about to send a non-EDMA capable command to the
1058 * port. Turn off EDMA so there won't be problems accessing
1059 * shadow block, etc registers.
1060 */
1061 mv_stop_dma(qc->ap);
1062 return ata_qc_issue_prot(qc);
1063 }
1064
1065 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1066
1067 /* the req producer index should be the same as we remember it */
1068 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1069 pp->req_producer);
1070 /* until we do queuing, the queue should be empty at this point */
1071 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1072 ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >>
1073 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1074
1075 mv_inc_q_index(&pp->req_producer); /* now incr producer index */
1076
1077 mv_start_dma(port_mmio, pp);
1078
1079 /* and write the request in pointer to kick the EDMA to life */
1080 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
1081 in_ptr |= pp->req_producer << EDMA_REQ_Q_PTR_SHIFT;
1082 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1083
1084 return 0;
1085 }
1086
1087 /**
1088 * mv_get_crpb_status - get status from most recently completed cmd
1089 * @ap: ATA channel to manipulate
1090 *
1091 * This routine is for use when the port is in DMA mode, when it
1092 * will be using the CRPB (command response block) method of
1093 * returning command completion information. We assert indices
1094 * are good, grab status, and bump the response consumer index to
1095 * prove that we're up to date.
1096 *
1097 * LOCKING:
1098 * Inherited from caller.
1099 */
1100 static u8 mv_get_crpb_status(struct ata_port *ap)
1101 {
1102 void __iomem *port_mmio = mv_ap_base(ap);
1103 struct mv_port_priv *pp = ap->private_data;
1104 u32 out_ptr;
1105
1106 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1107
1108 /* the response consumer index should be the same as we remember it */
1109 assert(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1110 pp->rsp_consumer);
1111
1112 /* increment our consumer index... */
1113 pp->rsp_consumer = mv_inc_q_index(&pp->rsp_consumer);
1114
1115 /* and, until we do NCQ, there should only be 1 CRPB waiting */
1116 assert(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >>
1117 EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
1118 pp->rsp_consumer);
1119
1120 /* write out our inc'd consumer index so EDMA knows we're caught up */
1121 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
1122 out_ptr |= pp->rsp_consumer << EDMA_RSP_Q_PTR_SHIFT;
1123 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1124
1125 /* Return ATA status register for completed CRPB */
1126 return (pp->crpb[pp->rsp_consumer].flags >> CRPB_FLAG_STATUS_SHIFT);
1127 }
1128
1129 /**
1130 * mv_err_intr - Handle error interrupts on the port
1131 * @ap: ATA channel to manipulate
1132 *
1133 * In most cases, just clear the interrupt and move on. However,
1134 * some cases require an eDMA reset, which is done right before
1135 * the COMRESET in mv_phy_reset(). The SERR case requires a
1136 * clear of pending errors in the SATA SERROR register. Finally,
1137 * if the port disabled DMA, update our cached copy to match.
1138 *
1139 * LOCKING:
1140 * Inherited from caller.
1141 */
1142 static void mv_err_intr(struct ata_port *ap)
1143 {
1144 void __iomem *port_mmio = mv_ap_base(ap);
1145 u32 edma_err_cause, serr = 0;
1146
1147 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1148
1149 if (EDMA_ERR_SERR & edma_err_cause) {
1150 serr = scr_read(ap, SCR_ERROR);
1151 scr_write_flush(ap, SCR_ERROR, serr);
1152 }
1153 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1154 struct mv_port_priv *pp = ap->private_data;
1155 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1156 }
1157 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
1158 "SERR: 0x%08x\n", ap->id, edma_err_cause, serr);
1159
1160 /* Clear EDMA now that SERR cleanup done */
1161 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1162
1163 /* check for fatal here and recover if needed */
1164 if (EDMA_ERR_FATAL & edma_err_cause) {
1165 mv_stop_and_reset(ap);
1166 }
1167 }
1168
1169 /**
1170 * mv_host_intr - Handle all interrupts on the given host controller
1171 * @host_set: host specific structure
1172 * @relevant: port error bits relevant to this host controller
1173 * @hc: which host controller we're to look at
1174 *
1175 * Read then write clear the HC interrupt status then walk each
1176 * port connected to the HC and see if it needs servicing. Port
1177 * success ints are reported in the HC interrupt status reg, the
1178 * port error ints are reported in the higher level main
1179 * interrupt status register and thus are passed in via the
1180 * 'relevant' argument.
1181 *
1182 * LOCKING:
1183 * Inherited from caller.
1184 */
1185 static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
1186 unsigned int hc)
1187 {
1188 void __iomem *mmio = host_set->mmio_base;
1189 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1190 struct ata_port *ap;
1191 struct ata_queued_cmd *qc;
1192 u32 hc_irq_cause;
1193 int shift, port, port0, hard_port, handled;
1194 unsigned int err_mask;
1195 u8 ata_status = 0;
1196
1197 if (hc == 0) {
1198 port0 = 0;
1199 } else {
1200 port0 = MV_PORTS_PER_HC;
1201 }
1202
1203 /* we'll need the HC success int register in most cases */
1204 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1205 if (hc_irq_cause) {
1206 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1207 }
1208
1209 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1210 hc,relevant,hc_irq_cause);
1211
1212 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
1213 ap = host_set->ports[port];
1214 hard_port = port & MV_PORT_MASK; /* range 0-3 */
1215 handled = 0; /* ensure ata_status is set if handled++ */
1216
1217 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1218 /* new CRPB on the queue; just one at a time until NCQ
1219 */
1220 ata_status = mv_get_crpb_status(ap);
1221 handled++;
1222 } else if ((DEV_IRQ << hard_port) & hc_irq_cause) {
1223 /* received ATA IRQ; read the status reg to clear INTRQ
1224 */
1225 ata_status = readb((void __iomem *)
1226 ap->ioaddr.status_addr);
1227 handled++;
1228 }
1229
1230 if (ap &&
1231 (ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR)))
1232 continue;
1233
1234 err_mask = ac_err_mask(ata_status);
1235
1236 shift = port << 1; /* (port * 2) */
1237 if (port >= MV_PORTS_PER_HC) {
1238 shift++; /* skip bit 8 in the HC Main IRQ reg */
1239 }
1240 if ((PORT0_ERR << shift) & relevant) {
1241 mv_err_intr(ap);
1242 err_mask |= AC_ERR_OTHER;
1243 handled++;
1244 }
1245
1246 if (handled && ap) {
1247 qc = ata_qc_from_tag(ap, ap->active_tag);
1248 if (NULL != qc) {
1249 VPRINTK("port %u IRQ found for qc, "
1250 "ata_status 0x%x\n", port,ata_status);
1251 /* mark qc status appropriately */
1252 if (!(qc->tf.ctl & ATA_NIEN)) {
1253 qc->err_mask |= err_mask;
1254 ata_qc_complete(qc);
1255 }
1256 }
1257 }
1258 }
1259 VPRINTK("EXIT\n");
1260 }
1261
1262 /**
1263 * mv_interrupt -
1264 * @irq: unused
1265 * @dev_instance: private data; in this case the host structure
1266 * @regs: unused
1267 *
1268 * Read the read only register to determine if any host
1269 * controllers have pending interrupts. If so, call lower level
1270 * routine to handle. Also check for PCI errors which are only
1271 * reported here.
1272 *
1273 * LOCKING:
1274 * This routine holds the host_set lock while processing pending
1275 * interrupts.
1276 */
1277 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
1278 struct pt_regs *regs)
1279 {
1280 struct ata_host_set *host_set = dev_instance;
1281 unsigned int hc, handled = 0, n_hcs;
1282 void __iomem *mmio = host_set->mmio_base;
1283 u32 irq_stat;
1284
1285 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
1286
1287 /* check the cases where we either have nothing pending or have read
1288 * a bogus register value which can indicate HW removal or PCI fault
1289 */
1290 if (!irq_stat || (0xffffffffU == irq_stat)) {
1291 return IRQ_NONE;
1292 }
1293
1294 n_hcs = mv_get_hc_count(host_set->ports[0]->flags);
1295 spin_lock(&host_set->lock);
1296
1297 for (hc = 0; hc < n_hcs; hc++) {
1298 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1299 if (relevant) {
1300 mv_host_intr(host_set, relevant, hc);
1301 handled++;
1302 }
1303 }
1304 if (PCI_ERR & irq_stat) {
1305 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1306 readl(mmio + PCI_IRQ_CAUSE_OFS));
1307
1308 DPRINTK("All regs @ PCI error\n");
1309 mv_dump_all_regs(mmio, -1, to_pci_dev(host_set->dev));
1310
1311 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1312 handled++;
1313 }
1314 spin_unlock(&host_set->lock);
1315
1316 return IRQ_RETVAL(handled);
1317 }
1318
1319 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1320 {
1321 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1322 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
1323
1324 return hc_mmio + ofs;
1325 }
1326
1327 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1328 {
1329 unsigned int ofs;
1330
1331 switch (sc_reg_in) {
1332 case SCR_STATUS:
1333 case SCR_ERROR:
1334 case SCR_CONTROL:
1335 ofs = sc_reg_in * sizeof(u32);
1336 break;
1337 default:
1338 ofs = 0xffffffffU;
1339 break;
1340 }
1341 return ofs;
1342 }
1343
1344 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
1345 {
1346 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1347 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1348
1349 if (ofs != 0xffffffffU)
1350 return readl(mmio + ofs);
1351 else
1352 return (u32) ofs;
1353 }
1354
1355 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1356 {
1357 void __iomem *mmio = mv5_phy_base(ap->host_set->mmio_base, ap->port_no);
1358 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1359
1360 if (ofs != 0xffffffffU)
1361 writelfl(val, mmio + ofs);
1362 }
1363
1364 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1365 {
1366 u8 rev_id;
1367 int early_5080;
1368
1369 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1370
1371 early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
1372
1373 if (!early_5080) {
1374 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1375 tmp |= (1 << 0);
1376 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1377 }
1378
1379 mv_reset_pci_bus(pdev, mmio);
1380 }
1381
1382 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1383 {
1384 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1385 }
1386
1387 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
1388 void __iomem *mmio)
1389 {
1390 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1391 u32 tmp;
1392
1393 tmp = readl(phy_mmio + MV5_PHY_MODE);
1394
1395 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1396 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
1397 }
1398
1399 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1400 {
1401 u32 tmp;
1402
1403 writel(0, mmio + MV_GPIO_PORT_CTL);
1404
1405 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1406
1407 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1408 tmp |= ~(1 << 0);
1409 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1410 }
1411
1412 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1413 unsigned int port)
1414 {
1415 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1416 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1417 u32 tmp;
1418 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1419
1420 if (fix_apm_sq) {
1421 tmp = readl(phy_mmio + MV5_LT_MODE);
1422 tmp |= (1 << 19);
1423 writel(tmp, phy_mmio + MV5_LT_MODE);
1424
1425 tmp = readl(phy_mmio + MV5_PHY_CTL);
1426 tmp &= ~0x3;
1427 tmp |= 0x1;
1428 writel(tmp, phy_mmio + MV5_PHY_CTL);
1429 }
1430
1431 tmp = readl(phy_mmio + MV5_PHY_MODE);
1432 tmp &= ~mask;
1433 tmp |= hpriv->signal[port].pre;
1434 tmp |= hpriv->signal[port].amps;
1435 writel(tmp, phy_mmio + MV5_PHY_MODE);
1436 }
1437
1438
1439 #undef ZERO
1440 #define ZERO(reg) writel(0, port_mmio + (reg))
1441 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1442 unsigned int port)
1443 {
1444 void __iomem *port_mmio = mv_port_base(mmio, port);
1445
1446 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1447
1448 mv_channel_reset(hpriv, mmio, port);
1449
1450 ZERO(0x028); /* command */
1451 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1452 ZERO(0x004); /* timer */
1453 ZERO(0x008); /* irq err cause */
1454 ZERO(0x00c); /* irq err mask */
1455 ZERO(0x010); /* rq bah */
1456 ZERO(0x014); /* rq inp */
1457 ZERO(0x018); /* rq outp */
1458 ZERO(0x01c); /* respq bah */
1459 ZERO(0x024); /* respq outp */
1460 ZERO(0x020); /* respq inp */
1461 ZERO(0x02c); /* test control */
1462 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1463 }
1464 #undef ZERO
1465
1466 #define ZERO(reg) writel(0, hc_mmio + (reg))
1467 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1468 unsigned int hc)
1469 {
1470 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1471 u32 tmp;
1472
1473 ZERO(0x00c);
1474 ZERO(0x010);
1475 ZERO(0x014);
1476 ZERO(0x018);
1477
1478 tmp = readl(hc_mmio + 0x20);
1479 tmp &= 0x1c1c1c1c;
1480 tmp |= 0x03030303;
1481 writel(tmp, hc_mmio + 0x20);
1482 }
1483 #undef ZERO
1484
1485 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1486 unsigned int n_hc)
1487 {
1488 unsigned int hc, port;
1489
1490 for (hc = 0; hc < n_hc; hc++) {
1491 for (port = 0; port < MV_PORTS_PER_HC; port++)
1492 mv5_reset_hc_port(hpriv, mmio,
1493 (hc * MV_PORTS_PER_HC) + port);
1494
1495 mv5_reset_one_hc(hpriv, mmio, hc);
1496 }
1497
1498 return 0;
1499 }
1500
1501 #undef ZERO
1502 #define ZERO(reg) writel(0, mmio + (reg))
1503 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1504 {
1505 u32 tmp;
1506
1507 tmp = readl(mmio + MV_PCI_MODE);
1508 tmp &= 0xff00ffff;
1509 writel(tmp, mmio + MV_PCI_MODE);
1510
1511 ZERO(MV_PCI_DISC_TIMER);
1512 ZERO(MV_PCI_MSI_TRIGGER);
1513 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1514 ZERO(HC_MAIN_IRQ_MASK_OFS);
1515 ZERO(MV_PCI_SERR_MASK);
1516 ZERO(PCI_IRQ_CAUSE_OFS);
1517 ZERO(PCI_IRQ_MASK_OFS);
1518 ZERO(MV_PCI_ERR_LOW_ADDRESS);
1519 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
1520 ZERO(MV_PCI_ERR_ATTRIBUTE);
1521 ZERO(MV_PCI_ERR_COMMAND);
1522 }
1523 #undef ZERO
1524
1525 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1526 {
1527 u32 tmp;
1528
1529 mv5_reset_flash(hpriv, mmio);
1530
1531 tmp = readl(mmio + MV_GPIO_PORT_CTL);
1532 tmp &= 0x3;
1533 tmp |= (1 << 5) | (1 << 6);
1534 writel(tmp, mmio + MV_GPIO_PORT_CTL);
1535 }
1536
1537 /**
1538 * mv6_reset_hc - Perform the 6xxx global soft reset
1539 * @mmio: base address of the HBA
1540 *
1541 * This routine only applies to 6xxx parts.
1542 *
1543 * LOCKING:
1544 * Inherited from caller.
1545 */
1546 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1547 unsigned int n_hc)
1548 {
1549 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
1550 int i, rc = 0;
1551 u32 t;
1552
1553 /* Following procedure defined in PCI "main command and status
1554 * register" table.
1555 */
1556 t = readl(reg);
1557 writel(t | STOP_PCI_MASTER, reg);
1558
1559 for (i = 0; i < 1000; i++) {
1560 udelay(1);
1561 t = readl(reg);
1562 if (PCI_MASTER_EMPTY & t) {
1563 break;
1564 }
1565 }
1566 if (!(PCI_MASTER_EMPTY & t)) {
1567 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
1568 rc = 1;
1569 goto done;
1570 }
1571
1572 /* set reset */
1573 i = 5;
1574 do {
1575 writel(t | GLOB_SFT_RST, reg);
1576 t = readl(reg);
1577 udelay(1);
1578 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
1579
1580 if (!(GLOB_SFT_RST & t)) {
1581 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
1582 rc = 1;
1583 goto done;
1584 }
1585
1586 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
1587 i = 5;
1588 do {
1589 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
1590 t = readl(reg);
1591 udelay(1);
1592 } while ((GLOB_SFT_RST & t) && (i-- > 0));
1593
1594 if (GLOB_SFT_RST & t) {
1595 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
1596 rc = 1;
1597 }
1598 done:
1599 return rc;
1600 }
1601
1602 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
1603 void __iomem *mmio)
1604 {
1605 void __iomem *port_mmio;
1606 u32 tmp;
1607
1608 tmp = readl(mmio + MV_RESET_CFG);
1609 if ((tmp & (1 << 0)) == 0) {
1610 hpriv->signal[idx].amps = 0x7 << 8;
1611 hpriv->signal[idx].pre = 0x1 << 5;
1612 return;
1613 }
1614
1615 port_mmio = mv_port_base(mmio, idx);
1616 tmp = readl(port_mmio + PHY_MODE2);
1617
1618 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
1619 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
1620 }
1621
1622 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1623 {
1624 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
1625 }
1626
1627 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1628 unsigned int port)
1629 {
1630 void __iomem *port_mmio = mv_port_base(mmio, port);
1631
1632 u32 hp_flags = hpriv->hp_flags;
1633 int fix_phy_mode2 =
1634 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1635 int fix_phy_mode4 =
1636 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1637 u32 m2, tmp;
1638
1639 if (fix_phy_mode2) {
1640 m2 = readl(port_mmio + PHY_MODE2);
1641 m2 &= ~(1 << 16);
1642 m2 |= (1 << 31);
1643 writel(m2, port_mmio + PHY_MODE2);
1644
1645 udelay(200);
1646
1647 m2 = readl(port_mmio + PHY_MODE2);
1648 m2 &= ~((1 << 16) | (1 << 31));
1649 writel(m2, port_mmio + PHY_MODE2);
1650
1651 udelay(200);
1652 }
1653
1654 /* who knows what this magic does */
1655 tmp = readl(port_mmio + PHY_MODE3);
1656 tmp &= ~0x7F800000;
1657 tmp |= 0x2A800000;
1658 writel(tmp, port_mmio + PHY_MODE3);
1659
1660 if (fix_phy_mode4) {
1661 u32 m4;
1662
1663 m4 = readl(port_mmio + PHY_MODE4);
1664
1665 if (hp_flags & MV_HP_ERRATA_60X1B2)
1666 tmp = readl(port_mmio + 0x310);
1667
1668 m4 = (m4 & ~(1 << 1)) | (1 << 0);
1669
1670 writel(m4, port_mmio + PHY_MODE4);
1671
1672 if (hp_flags & MV_HP_ERRATA_60X1B2)
1673 writel(tmp, port_mmio + 0x310);
1674 }
1675
1676 /* Revert values of pre-emphasis and signal amps to the saved ones */
1677 m2 = readl(port_mmio + PHY_MODE2);
1678
1679 m2 &= ~MV_M2_PREAMP_MASK;
1680 m2 |= hpriv->signal[port].amps;
1681 m2 |= hpriv->signal[port].pre;
1682 m2 &= ~(1 << 16);
1683
1684 writel(m2, port_mmio + PHY_MODE2);
1685 }
1686
1687 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1688 unsigned int port_no)
1689 {
1690 void __iomem *port_mmio = mv_port_base(mmio, port_no);
1691
1692 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1693
1694 if (IS_60XX(hpriv)) {
1695 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
1696 ifctl |= (1 << 12) | (1 << 7);
1697 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
1698 }
1699
1700 udelay(25); /* allow reset propagation */
1701
1702 /* Spec never mentions clearing the bit. Marvell's driver does
1703 * clear the bit, however.
1704 */
1705 writelfl(0, port_mmio + EDMA_CMD_OFS);
1706
1707 hpriv->ops->phy_errata(hpriv, mmio, port_no);
1708
1709 if (IS_50XX(hpriv))
1710 mdelay(1);
1711 }
1712
1713 static void mv_stop_and_reset(struct ata_port *ap)
1714 {
1715 struct mv_host_priv *hpriv = ap->host_set->private_data;
1716 void __iomem *mmio = ap->host_set->mmio_base;
1717
1718 mv_stop_dma(ap);
1719
1720 mv_channel_reset(hpriv, mmio, ap->port_no);
1721
1722 __mv_phy_reset(ap, 0);
1723 }
1724
1725 static inline void __msleep(unsigned int msec, int can_sleep)
1726 {
1727 if (can_sleep)
1728 msleep(msec);
1729 else
1730 mdelay(msec);
1731 }
1732
1733 /**
1734 * __mv_phy_reset - Perform eDMA reset followed by COMRESET
1735 * @ap: ATA channel to manipulate
1736 *
1737 * Part of this is taken from __sata_phy_reset and modified to
1738 * not sleep since this routine gets called from interrupt level.
1739 *
1740 * LOCKING:
1741 * Inherited from caller. This is coded to safe to call at
1742 * interrupt level, i.e. it does not sleep.
1743 */
1744 static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
1745 {
1746 struct mv_port_priv *pp = ap->private_data;
1747 struct mv_host_priv *hpriv = ap->host_set->private_data;
1748 void __iomem *port_mmio = mv_ap_base(ap);
1749 struct ata_taskfile tf;
1750 struct ata_device *dev = &ap->device[0];
1751 unsigned long timeout;
1752 int retry = 5;
1753 u32 sstatus;
1754
1755 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1756
1757 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1758 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1759 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1760
1761 /* Issue COMRESET via SControl */
1762 comreset_retry:
1763 scr_write_flush(ap, SCR_CONTROL, 0x301);
1764 __msleep(1, can_sleep);
1765
1766 scr_write_flush(ap, SCR_CONTROL, 0x300);
1767 __msleep(20, can_sleep);
1768
1769 timeout = jiffies + msecs_to_jiffies(200);
1770 do {
1771 sstatus = scr_read(ap, SCR_STATUS) & 0x3;
1772 if ((sstatus == 3) || (sstatus == 0))
1773 break;
1774
1775 __msleep(1, can_sleep);
1776 } while (time_before(jiffies, timeout));
1777
1778 /* work around errata */
1779 if (IS_60XX(hpriv) &&
1780 (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
1781 (retry-- > 0))
1782 goto comreset_retry;
1783
1784 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1785 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1786 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1787
1788 if (sata_dev_present(ap)) {
1789 ata_port_probe(ap);
1790 } else {
1791 printk(KERN_INFO "ata%u: no device found (phy stat %08x)\n",
1792 ap->id, scr_read(ap, SCR_STATUS));
1793 ata_port_disable(ap);
1794 return;
1795 }
1796 ap->cbl = ATA_CBL_SATA;
1797
1798 /* even after SStatus reflects that device is ready,
1799 * it seems to take a while for link to be fully
1800 * established (and thus Status no longer 0x80/0x7F),
1801 * so we poll a bit for that, here.
1802 */
1803 retry = 20;
1804 while (1) {
1805 u8 drv_stat = ata_check_status(ap);
1806 if ((drv_stat != 0x80) && (drv_stat != 0x7f))
1807 break;
1808 __msleep(500, can_sleep);
1809 if (retry-- <= 0)
1810 break;
1811 }
1812
1813 tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr);
1814 tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr);
1815 tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr);
1816 tf.nsect = readb((void __iomem *) ap->ioaddr.nsect_addr);
1817
1818 dev->class = ata_dev_classify(&tf);
1819 if (!ata_dev_present(dev)) {
1820 VPRINTK("Port disabled post-sig: No device present.\n");
1821 ata_port_disable(ap);
1822 }
1823
1824 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1825
1826 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1827
1828 VPRINTK("EXIT\n");
1829 }
1830
1831 static void mv_phy_reset(struct ata_port *ap)
1832 {
1833 __mv_phy_reset(ap, 1);
1834 }
1835
1836 /**
1837 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
1838 * @ap: ATA channel to manipulate
1839 *
1840 * Intent is to clear all pending error conditions, reset the
1841 * chip/bus, fail the command, and move on.
1842 *
1843 * LOCKING:
1844 * This routine holds the host_set lock while failing the command.
1845 */
1846 static void mv_eng_timeout(struct ata_port *ap)
1847 {
1848 struct ata_queued_cmd *qc;
1849 unsigned long flags;
1850
1851 printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id);
1852 DPRINTK("All regs @ start of eng_timeout\n");
1853 mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no,
1854 to_pci_dev(ap->host_set->dev));
1855
1856 qc = ata_qc_from_tag(ap, ap->active_tag);
1857 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
1858 ap->host_set->mmio_base, ap, qc, qc->scsicmd,
1859 &qc->scsicmd->cmnd);
1860
1861 mv_err_intr(ap);
1862 mv_stop_and_reset(ap);
1863
1864 if (!qc) {
1865 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
1866 ap->id);
1867 } else {
1868 /* hack alert! We cannot use the supplied completion
1869 * function from inside the ->eh_strategy_handler() thread.
1870 * libata is the only user of ->eh_strategy_handler() in
1871 * any kernel, so the default scsi_done() assumes it is
1872 * not being called from the SCSI EH.
1873 */
1874 spin_lock_irqsave(&ap->host_set->lock, flags);
1875 qc->scsidone = scsi_finish_command;
1876 qc->err_mask |= AC_ERR_OTHER;
1877 ata_qc_complete(qc);
1878 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1879 }
1880 }
1881
1882 /**
1883 * mv_port_init - Perform some early initialization on a single port.
1884 * @port: libata data structure storing shadow register addresses
1885 * @port_mmio: base address of the port
1886 *
1887 * Initialize shadow register mmio addresses, clear outstanding
1888 * interrupts on the port, and unmask interrupts for the future
1889 * start of the port.
1890 *
1891 * LOCKING:
1892 * Inherited from caller.
1893 */
1894 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
1895 {
1896 unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS;
1897 unsigned serr_ofs;
1898
1899 /* PIO related setup
1900 */
1901 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
1902 port->error_addr =
1903 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
1904 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
1905 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
1906 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
1907 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
1908 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
1909 port->status_addr =
1910 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
1911 /* special case: control/altstatus doesn't have ATA_REG_ address */
1912 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
1913
1914 /* unused: */
1915 port->cmd_addr = port->bmdma_addr = port->scr_addr = 0;
1916
1917 /* Clear any currently outstanding port interrupt conditions */
1918 serr_ofs = mv_scr_offset(SCR_ERROR);
1919 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
1920 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1921
1922 /* unmask all EDMA error interrupts */
1923 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
1924
1925 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
1926 readl(port_mmio + EDMA_CFG_OFS),
1927 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
1928 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
1929 }
1930
1931 static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
1932 unsigned int board_idx)
1933 {
1934 u8 rev_id;
1935 u32 hp_flags = hpriv->hp_flags;
1936
1937 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1938
1939 switch(board_idx) {
1940 case chip_5080:
1941 hpriv->ops = &mv5xxx_ops;
1942 hp_flags |= MV_HP_50XX;
1943
1944 switch (rev_id) {
1945 case 0x1:
1946 hp_flags |= MV_HP_ERRATA_50XXB0;
1947 break;
1948 case 0x3:
1949 hp_flags |= MV_HP_ERRATA_50XXB2;
1950 break;
1951 default:
1952 dev_printk(KERN_WARNING, &pdev->dev,
1953 "Applying 50XXB2 workarounds to unknown rev\n");
1954 hp_flags |= MV_HP_ERRATA_50XXB2;
1955 break;
1956 }
1957 break;
1958
1959 case chip_504x:
1960 case chip_508x:
1961 hpriv->ops = &mv5xxx_ops;
1962 hp_flags |= MV_HP_50XX;
1963
1964 switch (rev_id) {
1965 case 0x0:
1966 hp_flags |= MV_HP_ERRATA_50XXB0;
1967 break;
1968 case 0x3:
1969 hp_flags |= MV_HP_ERRATA_50XXB2;
1970 break;
1971 default:
1972 dev_printk(KERN_WARNING, &pdev->dev,
1973 "Applying B2 workarounds to unknown rev\n");
1974 hp_flags |= MV_HP_ERRATA_50XXB2;
1975 break;
1976 }
1977 break;
1978
1979 case chip_604x:
1980 case chip_608x:
1981 hpriv->ops = &mv6xxx_ops;
1982
1983 switch (rev_id) {
1984 case 0x7:
1985 hp_flags |= MV_HP_ERRATA_60X1B2;
1986 break;
1987 case 0x9:
1988 hp_flags |= MV_HP_ERRATA_60X1C0;
1989 break;
1990 default:
1991 dev_printk(KERN_WARNING, &pdev->dev,
1992 "Applying B2 workarounds to unknown rev\n");
1993 hp_flags |= MV_HP_ERRATA_60X1B2;
1994 break;
1995 }
1996 break;
1997
1998 default:
1999 printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
2000 return 1;
2001 }
2002
2003 hpriv->hp_flags = hp_flags;
2004
2005 return 0;
2006 }
2007
2008 /**
2009 * mv_init_host - Perform some early initialization of the host.
2010 * @pdev: host PCI device
2011 * @probe_ent: early data struct representing the host
2012 *
2013 * If possible, do an early global reset of the host. Then do
2014 * our port init and clear/unmask all/relevant host interrupts.
2015 *
2016 * LOCKING:
2017 * Inherited from caller.
2018 */
2019 static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
2020 unsigned int board_idx)
2021 {
2022 int rc = 0, n_hc, port, hc;
2023 void __iomem *mmio = probe_ent->mmio_base;
2024 struct mv_host_priv *hpriv = probe_ent->private_data;
2025
2026 /* global interrupt mask */
2027 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2028
2029 rc = mv_chip_id(pdev, hpriv, board_idx);
2030 if (rc)
2031 goto done;
2032
2033 n_hc = mv_get_hc_count(probe_ent->host_flags);
2034 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
2035
2036 for (port = 0; port < probe_ent->n_ports; port++)
2037 hpriv->ops->read_preamp(hpriv, port, mmio);
2038
2039 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
2040 if (rc)
2041 goto done;
2042
2043 hpriv->ops->reset_flash(hpriv, mmio);
2044 hpriv->ops->reset_bus(pdev, mmio);
2045 hpriv->ops->enable_leds(hpriv, mmio);
2046
2047 for (port = 0; port < probe_ent->n_ports; port++) {
2048 if (IS_60XX(hpriv)) {
2049 void __iomem *port_mmio = mv_port_base(mmio, port);
2050
2051 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
2052 ifctl |= (1 << 12);
2053 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2054 }
2055
2056 hpriv->ops->phy_errata(hpriv, mmio, port);
2057 }
2058
2059 for (port = 0; port < probe_ent->n_ports; port++) {
2060 void __iomem *port_mmio = mv_port_base(mmio, port);
2061 mv_port_init(&probe_ent->port[port], port_mmio);
2062 }
2063
2064 for (hc = 0; hc < n_hc; hc++) {
2065 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2066
2067 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2068 "(before clear)=0x%08x\n", hc,
2069 readl(hc_mmio + HC_CFG_OFS),
2070 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2071
2072 /* Clear any currently outstanding hc interrupt conditions */
2073 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
2074 }
2075
2076 /* Clear any currently outstanding host interrupt conditions */
2077 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
2078
2079 /* and unmask interrupt generation for host regs */
2080 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
2081 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
2082
2083 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2084 "PCI int cause/mask=0x%08x/0x%08x\n",
2085 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
2086 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
2087 readl(mmio + PCI_IRQ_CAUSE_OFS),
2088 readl(mmio + PCI_IRQ_MASK_OFS));
2089
2090 done:
2091 return rc;
2092 }
2093
2094 /**
2095 * mv_print_info - Dump key info to kernel log for perusal.
2096 * @probe_ent: early data struct representing the host
2097 *
2098 * FIXME: complete this.
2099 *
2100 * LOCKING:
2101 * Inherited from caller.
2102 */
2103 static void mv_print_info(struct ata_probe_ent *probe_ent)
2104 {
2105 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
2106 struct mv_host_priv *hpriv = probe_ent->private_data;
2107 u8 rev_id, scc;
2108 const char *scc_s;
2109
2110 /* Use this to determine the HW stepping of the chip so we know
2111 * what errata to workaround
2112 */
2113 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2114
2115 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
2116 if (scc == 0)
2117 scc_s = "SCSI";
2118 else if (scc == 0x01)
2119 scc_s = "RAID";
2120 else
2121 scc_s = "unknown";
2122
2123 dev_printk(KERN_INFO, &pdev->dev,
2124 "%u slots %u ports %s mode IRQ via %s\n",
2125 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
2126 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
2127 }
2128
2129 /**
2130 * mv_init_one - handle a positive probe of a Marvell host
2131 * @pdev: PCI device found
2132 * @ent: PCI device ID entry for the matched host
2133 *
2134 * LOCKING:
2135 * Inherited from caller.
2136 */
2137 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2138 {
2139 static int printed_version = 0;
2140 struct ata_probe_ent *probe_ent = NULL;
2141 struct mv_host_priv *hpriv;
2142 unsigned int board_idx = (unsigned int)ent->driver_data;
2143 void __iomem *mmio_base;
2144 int pci_dev_busy = 0, rc;
2145
2146 if (!printed_version++)
2147 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
2148
2149 rc = pci_enable_device(pdev);
2150 if (rc) {
2151 return rc;
2152 }
2153
2154 rc = pci_request_regions(pdev, DRV_NAME);
2155 if (rc) {
2156 pci_dev_busy = 1;
2157 goto err_out;
2158 }
2159
2160 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
2161 if (probe_ent == NULL) {
2162 rc = -ENOMEM;
2163 goto err_out_regions;
2164 }
2165
2166 memset(probe_ent, 0, sizeof(*probe_ent));
2167 probe_ent->dev = pci_dev_to_dev(pdev);
2168 INIT_LIST_HEAD(&probe_ent->node);
2169
2170 mmio_base = pci_iomap(pdev, MV_PRIMARY_BAR, 0);
2171 if (mmio_base == NULL) {
2172 rc = -ENOMEM;
2173 goto err_out_free_ent;
2174 }
2175
2176 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
2177 if (!hpriv) {
2178 rc = -ENOMEM;
2179 goto err_out_iounmap;
2180 }
2181 memset(hpriv, 0, sizeof(*hpriv));
2182
2183 probe_ent->sht = mv_port_info[board_idx].sht;
2184 probe_ent->host_flags = mv_port_info[board_idx].host_flags;
2185 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
2186 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
2187 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
2188
2189 probe_ent->irq = pdev->irq;
2190 probe_ent->irq_flags = SA_SHIRQ;
2191 probe_ent->mmio_base = mmio_base;
2192 probe_ent->private_data = hpriv;
2193
2194 /* initialize adapter */
2195 rc = mv_init_host(pdev, probe_ent, board_idx);
2196 if (rc) {
2197 goto err_out_hpriv;
2198 }
2199
2200 /* Enable interrupts */
2201 if (msi && pci_enable_msi(pdev) == 0) {
2202 hpriv->hp_flags |= MV_HP_FLAG_MSI;
2203 } else {
2204 pci_intx(pdev, 1);
2205 }
2206
2207 mv_dump_pci_cfg(pdev, 0x68);
2208 mv_print_info(probe_ent);
2209
2210 if (ata_device_add(probe_ent) == 0) {
2211 rc = -ENODEV; /* No devices discovered */
2212 goto err_out_dev_add;
2213 }
2214
2215 kfree(probe_ent);
2216 return 0;
2217
2218 err_out_dev_add:
2219 if (MV_HP_FLAG_MSI & hpriv->hp_flags) {
2220 pci_disable_msi(pdev);
2221 } else {
2222 pci_intx(pdev, 0);
2223 }
2224 err_out_hpriv:
2225 kfree(hpriv);
2226 err_out_iounmap:
2227 pci_iounmap(pdev, mmio_base);
2228 err_out_free_ent:
2229 kfree(probe_ent);
2230 err_out_regions:
2231 pci_release_regions(pdev);
2232 err_out:
2233 if (!pci_dev_busy) {
2234 pci_disable_device(pdev);
2235 }
2236
2237 return rc;
2238 }
2239
2240 static int __init mv_init(void)
2241 {
2242 return pci_module_init(&mv_pci_driver);
2243 }
2244
2245 static void __exit mv_exit(void)
2246 {
2247 pci_unregister_driver(&mv_pci_driver);
2248 }
2249
2250 MODULE_AUTHOR("Brett Russ");
2251 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
2252 MODULE_LICENSE("GPL");
2253 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
2254 MODULE_VERSION(DRV_VERSION);
2255
2256 module_param(msi, int, 0444);
2257 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
2258
2259 module_init(mv_init);
2260 module_exit(mv_exit);
Support for the Chinese Samsung S3C2440 based development boards