2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
7 * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
10 #include <linux/hardirq.h>
11 #include <linux/init.h>
12 #include <linux/highmem.h>
13 #include <linux/kernel.h>
14 #include <linux/linkage.h>
15 #include <linux/sched.h>
17 #include <linux/bitops.h>
19 #include <asm/bcache.h>
20 #include <asm/bootinfo.h>
21 #include <asm/cache.h>
22 #include <asm/cacheops.h>
24 #include <asm/cpu-features.h>
27 #include <asm/pgtable.h>
28 #include <asm/r4kcache.h>
29 #include <asm/sections.h>
30 #include <asm/system.h>
31 #include <asm/mmu_context.h>
33 #include <asm/cacheflush.h> /* for run_uncached() */
37 * Special Variant of smp_call_function for use by cache functions:
40 * o collapses to normal function call on UP kernels
41 * o collapses to normal function call on systems with a single shared
44 static inline void r4k_on_each_cpu(void (*func
) (void *info
), void *info
,
49 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
50 smp_call_function(func
, info
, retry
, wait
);
59 static unsigned long icache_size __read_mostly
;
60 static unsigned long dcache_size __read_mostly
;
61 static unsigned long scache_size __read_mostly
;
64 * Dummy cache handling routines for machines without boardcaches
66 static void cache_noop(void) {}
68 static struct bcache_ops no_sc_ops
= {
69 .bc_enable
= (void *)cache_noop
,
70 .bc_disable
= (void *)cache_noop
,
71 .bc_wback_inv
= (void *)cache_noop
,
72 .bc_inv
= (void *)cache_noop
75 struct bcache_ops
*bcops
= &no_sc_ops
;
77 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x00002010)
78 #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x00002020)
80 #define R4600_HIT_CACHEOP_WAR_IMPL \
82 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
83 *(volatile unsigned long *)CKSEG1; \
84 if (R4600_V1_HIT_CACHEOP_WAR) \
85 __asm__ __volatile__("nop;nop;nop;nop"); \
88 static void (*r4k_blast_dcache_page
)(unsigned long addr
);
90 static inline void r4k_blast_dcache_page_dc32(unsigned long addr
)
92 R4600_HIT_CACHEOP_WAR_IMPL
;
93 blast_dcache32_page(addr
);
96 static void __init
r4k_blast_dcache_page_setup(void)
98 unsigned long dc_lsize
= cpu_dcache_line_size();
101 r4k_blast_dcache_page
= (void *)cache_noop
;
102 else if (dc_lsize
== 16)
103 r4k_blast_dcache_page
= blast_dcache16_page
;
104 else if (dc_lsize
== 32)
105 r4k_blast_dcache_page
= r4k_blast_dcache_page_dc32
;
108 static void (* r4k_blast_dcache_page_indexed
)(unsigned long addr
);
110 static void __init
r4k_blast_dcache_page_indexed_setup(void)
112 unsigned long dc_lsize
= cpu_dcache_line_size();
115 r4k_blast_dcache_page_indexed
= (void *)cache_noop
;
116 else if (dc_lsize
== 16)
117 r4k_blast_dcache_page_indexed
= blast_dcache16_page_indexed
;
118 else if (dc_lsize
== 32)
119 r4k_blast_dcache_page_indexed
= blast_dcache32_page_indexed
;
122 static void (* r4k_blast_dcache
)(void);
124 static void __init
r4k_blast_dcache_setup(void)
126 unsigned long dc_lsize
= cpu_dcache_line_size();
129 r4k_blast_dcache
= (void *)cache_noop
;
130 else if (dc_lsize
== 16)
131 r4k_blast_dcache
= blast_dcache16
;
132 else if (dc_lsize
== 32)
133 r4k_blast_dcache
= blast_dcache32
;
136 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
137 #define JUMP_TO_ALIGN(order) \
138 __asm__ __volatile__( \
140 ".align\t" #order "\n\t" \
143 #define CACHE32_UNROLL32_ALIGN JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
144 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
146 static inline void blast_r4600_v1_icache32(void)
150 local_irq_save(flags
);
152 local_irq_restore(flags
);
155 static inline void tx49_blast_icache32(void)
157 unsigned long start
= INDEX_BASE
;
158 unsigned long end
= start
+ current_cpu_data
.icache
.waysize
;
159 unsigned long ws_inc
= 1UL << current_cpu_data
.icache
.waybit
;
160 unsigned long ws_end
= current_cpu_data
.icache
.ways
<<
161 current_cpu_data
.icache
.waybit
;
162 unsigned long ws
, addr
;
164 CACHE32_UNROLL32_ALIGN2
;
165 /* I'm in even chunk. blast odd chunks */
166 for (ws
= 0; ws
< ws_end
; ws
+= ws_inc
)
167 for (addr
= start
+ 0x400; addr
< end
; addr
+= 0x400 * 2)
168 cache32_unroll32(addr
|ws
, Index_Invalidate_I
);
169 CACHE32_UNROLL32_ALIGN
;
170 /* I'm in odd chunk. blast even chunks */
171 for (ws
= 0; ws
< ws_end
; ws
+= ws_inc
)
172 for (addr
= start
; addr
< end
; addr
+= 0x400 * 2)
173 cache32_unroll32(addr
|ws
, Index_Invalidate_I
);
176 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page
)
180 local_irq_save(flags
);
181 blast_icache32_page_indexed(page
);
182 local_irq_restore(flags
);
185 static inline void tx49_blast_icache32_page_indexed(unsigned long page
)
187 unsigned long indexmask
= current_cpu_data
.icache
.waysize
- 1;
188 unsigned long start
= INDEX_BASE
+ (page
& indexmask
);
189 unsigned long end
= start
+ PAGE_SIZE
;
190 unsigned long ws_inc
= 1UL << current_cpu_data
.icache
.waybit
;
191 unsigned long ws_end
= current_cpu_data
.icache
.ways
<<
192 current_cpu_data
.icache
.waybit
;
193 unsigned long ws
, addr
;
195 CACHE32_UNROLL32_ALIGN2
;
196 /* I'm in even chunk. blast odd chunks */
197 for (ws
= 0; ws
< ws_end
; ws
+= ws_inc
)
198 for (addr
= start
+ 0x400; addr
< end
; addr
+= 0x400 * 2)
199 cache32_unroll32(addr
|ws
, Index_Invalidate_I
);
200 CACHE32_UNROLL32_ALIGN
;
201 /* I'm in odd chunk. blast even chunks */
202 for (ws
= 0; ws
< ws_end
; ws
+= ws_inc
)
203 for (addr
= start
; addr
< end
; addr
+= 0x400 * 2)
204 cache32_unroll32(addr
|ws
, Index_Invalidate_I
);
207 static void (* r4k_blast_icache_page
)(unsigned long addr
);
209 static void __init
r4k_blast_icache_page_setup(void)
211 unsigned long ic_lsize
= cpu_icache_line_size();
214 r4k_blast_icache_page
= (void *)cache_noop
;
215 else if (ic_lsize
== 16)
216 r4k_blast_icache_page
= blast_icache16_page
;
217 else if (ic_lsize
== 32)
218 r4k_blast_icache_page
= blast_icache32_page
;
219 else if (ic_lsize
== 64)
220 r4k_blast_icache_page
= blast_icache64_page
;
224 static void (* r4k_blast_icache_page_indexed
)(unsigned long addr
);
226 static void __init
r4k_blast_icache_page_indexed_setup(void)
228 unsigned long ic_lsize
= cpu_icache_line_size();
231 r4k_blast_icache_page_indexed
= (void *)cache_noop
;
232 else if (ic_lsize
== 16)
233 r4k_blast_icache_page_indexed
= blast_icache16_page_indexed
;
234 else if (ic_lsize
== 32) {
235 if (R4600_V1_INDEX_ICACHEOP_WAR
&& cpu_is_r4600_v1_x())
236 r4k_blast_icache_page_indexed
=
237 blast_icache32_r4600_v1_page_indexed
;
238 else if (TX49XX_ICACHE_INDEX_INV_WAR
)
239 r4k_blast_icache_page_indexed
=
240 tx49_blast_icache32_page_indexed
;
242 r4k_blast_icache_page_indexed
=
243 blast_icache32_page_indexed
;
244 } else if (ic_lsize
== 64)
245 r4k_blast_icache_page_indexed
= blast_icache64_page_indexed
;
248 static void (* r4k_blast_icache
)(void);
250 static void __init
r4k_blast_icache_setup(void)
252 unsigned long ic_lsize
= cpu_icache_line_size();
255 r4k_blast_icache
= (void *)cache_noop
;
256 else if (ic_lsize
== 16)
257 r4k_blast_icache
= blast_icache16
;
258 else if (ic_lsize
== 32) {
259 if (R4600_V1_INDEX_ICACHEOP_WAR
&& cpu_is_r4600_v1_x())
260 r4k_blast_icache
= blast_r4600_v1_icache32
;
261 else if (TX49XX_ICACHE_INDEX_INV_WAR
)
262 r4k_blast_icache
= tx49_blast_icache32
;
264 r4k_blast_icache
= blast_icache32
;
265 } else if (ic_lsize
== 64)
266 r4k_blast_icache
= blast_icache64
;
269 static void (* r4k_blast_scache_page
)(unsigned long addr
);
271 static void __init
r4k_blast_scache_page_setup(void)
273 unsigned long sc_lsize
= cpu_scache_line_size();
275 if (scache_size
== 0)
276 r4k_blast_scache_page
= (void *)cache_noop
;
277 else if (sc_lsize
== 16)
278 r4k_blast_scache_page
= blast_scache16_page
;
279 else if (sc_lsize
== 32)
280 r4k_blast_scache_page
= blast_scache32_page
;
281 else if (sc_lsize
== 64)
282 r4k_blast_scache_page
= blast_scache64_page
;
283 else if (sc_lsize
== 128)
284 r4k_blast_scache_page
= blast_scache128_page
;
287 static void (* r4k_blast_scache_page_indexed
)(unsigned long addr
);
289 static void __init
r4k_blast_scache_page_indexed_setup(void)
291 unsigned long sc_lsize
= cpu_scache_line_size();
293 if (scache_size
== 0)
294 r4k_blast_scache_page_indexed
= (void *)cache_noop
;
295 else if (sc_lsize
== 16)
296 r4k_blast_scache_page_indexed
= blast_scache16_page_indexed
;
297 else if (sc_lsize
== 32)
298 r4k_blast_scache_page_indexed
= blast_scache32_page_indexed
;
299 else if (sc_lsize
== 64)
300 r4k_blast_scache_page_indexed
= blast_scache64_page_indexed
;
301 else if (sc_lsize
== 128)
302 r4k_blast_scache_page_indexed
= blast_scache128_page_indexed
;
305 static void (* r4k_blast_scache
)(void);
307 static void __init
r4k_blast_scache_setup(void)
309 unsigned long sc_lsize
= cpu_scache_line_size();
311 if (scache_size
== 0)
312 r4k_blast_scache
= (void *)cache_noop
;
313 else if (sc_lsize
== 16)
314 r4k_blast_scache
= blast_scache16
;
315 else if (sc_lsize
== 32)
316 r4k_blast_scache
= blast_scache32
;
317 else if (sc_lsize
== 64)
318 r4k_blast_scache
= blast_scache64
;
319 else if (sc_lsize
== 128)
320 r4k_blast_scache
= blast_scache128
;
323 static inline void local_r4k___flush_cache_all(void * args
)
325 #if defined(CONFIG_CPU_LOONGSON2)
332 switch (current_cpu_type()) {
344 static void r4k___flush_cache_all(void)
346 r4k_on_each_cpu(local_r4k___flush_cache_all
, NULL
, 1, 1);
349 static inline int has_valid_asid(const struct mm_struct
*mm
)
351 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
354 for_each_online_cpu(i
)
355 if (cpu_context(i
, mm
))
360 return cpu_context(smp_processor_id(), mm
);
364 static inline void local_r4k_flush_cache_range(void * args
)
366 struct vm_area_struct
*vma
= args
;
368 if (!(has_valid_asid(vma
->vm_mm
)))
374 static void r4k_flush_cache_range(struct vm_area_struct
*vma
,
375 unsigned long start
, unsigned long end
)
377 if (!cpu_has_dc_aliases
)
380 r4k_on_each_cpu(local_r4k_flush_cache_range
, vma
, 1, 1);
383 static inline void local_r4k_flush_cache_mm(void * args
)
385 struct mm_struct
*mm
= args
;
387 if (!has_valid_asid(mm
))
391 * Kludge alert. For obscure reasons R4000SC and R4400SC go nuts if we
392 * only flush the primary caches but R10000 and R12000 behave sane ...
393 * R4000SC and R4400SC indexed S-cache ops also invalidate primary
394 * caches, so we can bail out early.
396 if (current_cpu_type() == CPU_R4000SC
||
397 current_cpu_type() == CPU_R4000MC
||
398 current_cpu_type() == CPU_R4400SC
||
399 current_cpu_type() == CPU_R4400MC
) {
407 static void r4k_flush_cache_mm(struct mm_struct
*mm
)
409 if (!cpu_has_dc_aliases
)
412 r4k_on_each_cpu(local_r4k_flush_cache_mm
, mm
, 1, 1);
415 struct flush_cache_page_args
{
416 struct vm_area_struct
*vma
;
421 static inline void local_r4k_flush_cache_page(void *args
)
423 struct flush_cache_page_args
*fcp_args
= args
;
424 struct vm_area_struct
*vma
= fcp_args
->vma
;
425 unsigned long addr
= fcp_args
->addr
;
426 struct page
*page
= pfn_to_page(fcp_args
->pfn
);
427 int exec
= vma
->vm_flags
& VM_EXEC
;
428 struct mm_struct
*mm
= vma
->vm_mm
;
436 * If ownes no valid ASID yet, cannot possibly have gotten
437 * this page into the cache.
439 if (!has_valid_asid(mm
))
443 pgdp
= pgd_offset(mm
, addr
);
444 pudp
= pud_offset(pgdp
, addr
);
445 pmdp
= pmd_offset(pudp
, addr
);
446 ptep
= pte_offset(pmdp
, addr
);
449 * If the page isn't marked valid, the page cannot possibly be
452 if (!(pte_present(*ptep
)))
455 if ((mm
== current
->active_mm
) && (pte_val(*ptep
) & _PAGE_VALID
))
459 * Use kmap_coherent or kmap_atomic to do flushes for
460 * another ASID than the current one.
462 if (cpu_has_dc_aliases
)
463 vaddr
= kmap_coherent(page
, addr
);
465 vaddr
= kmap_atomic(page
, KM_USER0
);
466 addr
= (unsigned long)vaddr
;
469 if (cpu_has_dc_aliases
|| (exec
&& !cpu_has_ic_fills_f_dc
)) {
470 r4k_blast_dcache_page(addr
);
471 if (exec
&& !cpu_icache_snoops_remote_store
)
472 r4k_blast_scache_page(addr
);
475 if (vaddr
&& cpu_has_vtag_icache
&& mm
== current
->active_mm
) {
476 int cpu
= smp_processor_id();
478 if (cpu_context(cpu
, mm
) != 0)
479 drop_mmu_context(mm
, cpu
);
481 r4k_blast_icache_page(addr
);
485 if (cpu_has_dc_aliases
)
488 kunmap_atomic(vaddr
, KM_USER0
);
492 static void r4k_flush_cache_page(struct vm_area_struct
*vma
,
493 unsigned long addr
, unsigned long pfn
)
495 struct flush_cache_page_args args
;
501 r4k_on_each_cpu(local_r4k_flush_cache_page
, &args
, 1, 1);
504 static inline void local_r4k_flush_data_cache_page(void * addr
)
506 r4k_blast_dcache_page((unsigned long) addr
);
509 static void r4k_flush_data_cache_page(unsigned long addr
)
512 local_r4k_flush_data_cache_page((void *)addr
);
514 r4k_on_each_cpu(local_r4k_flush_data_cache_page
, (void *) addr
,
518 struct flush_icache_range_args
{
523 static inline void local_r4k_flush_icache_range(void *args
)
525 struct flush_icache_range_args
*fir_args
= args
;
526 unsigned long start
= fir_args
->start
;
527 unsigned long end
= fir_args
->end
;
529 if (!cpu_has_ic_fills_f_dc
) {
530 if (end
- start
>= dcache_size
) {
533 R4600_HIT_CACHEOP_WAR_IMPL
;
534 protected_blast_dcache_range(start
, end
);
537 if (!cpu_icache_snoops_remote_store
&& scache_size
) {
538 if (end
- start
> scache_size
)
541 protected_blast_scache_range(start
, end
);
545 if (end
- start
> icache_size
)
548 protected_blast_icache_range(start
, end
);
551 static void r4k_flush_icache_range(unsigned long start
, unsigned long end
)
553 struct flush_icache_range_args args
;
558 r4k_on_each_cpu(local_r4k_flush_icache_range
, &args
, 1, 1);
559 instruction_hazard();
562 #ifdef CONFIG_DMA_NONCOHERENT
564 static void r4k_dma_cache_wback_inv(unsigned long addr
, unsigned long size
)
566 /* Catch bad driver code */
569 if (cpu_has_inclusive_pcaches
) {
570 if (size
>= scache_size
)
573 blast_scache_range(addr
, addr
+ size
);
578 * Either no secondary cache or the available caches don't have the
579 * subset property so we have to flush the primary caches
582 if (size
>= dcache_size
) {
585 R4600_HIT_CACHEOP_WAR_IMPL
;
586 blast_dcache_range(addr
, addr
+ size
);
589 bc_wback_inv(addr
, size
);
592 static void r4k_dma_cache_inv(unsigned long addr
, unsigned long size
)
594 /* Catch bad driver code */
597 if (cpu_has_inclusive_pcaches
) {
598 if (size
>= scache_size
)
601 blast_scache_range(addr
, addr
+ size
);
605 if (size
>= dcache_size
) {
608 R4600_HIT_CACHEOP_WAR_IMPL
;
609 blast_dcache_range(addr
, addr
+ size
);
614 #endif /* CONFIG_DMA_NONCOHERENT */
617 * While we're protected against bad userland addresses we don't care
618 * very much about what happens in that case. Usually a segmentation
619 * fault will dump the process later on anyway ...
621 static void local_r4k_flush_cache_sigtramp(void * arg
)
623 unsigned long ic_lsize
= cpu_icache_line_size();
624 unsigned long dc_lsize
= cpu_dcache_line_size();
625 unsigned long sc_lsize
= cpu_scache_line_size();
626 unsigned long addr
= (unsigned long) arg
;
628 R4600_HIT_CACHEOP_WAR_IMPL
;
630 protected_writeback_dcache_line(addr
& ~(dc_lsize
- 1));
631 if (!cpu_icache_snoops_remote_store
&& scache_size
)
632 protected_writeback_scache_line(addr
& ~(sc_lsize
- 1));
634 protected_flush_icache_line(addr
& ~(ic_lsize
- 1));
635 if (MIPS4K_ICACHE_REFILL_WAR
) {
636 __asm__
__volatile__ (
651 : "i" (Hit_Invalidate_I
));
653 if (MIPS_CACHE_SYNC_WAR
)
654 __asm__
__volatile__ ("sync");
657 static void r4k_flush_cache_sigtramp(unsigned long addr
)
659 r4k_on_each_cpu(local_r4k_flush_cache_sigtramp
, (void *) addr
, 1, 1);
662 static void r4k_flush_icache_all(void)
664 if (cpu_has_vtag_icache
)
668 static inline void rm7k_erratum31(void)
670 const unsigned long ic_lsize
= 32;
673 /* RM7000 erratum #31. The icache is screwed at startup. */
677 for (addr
= INDEX_BASE
; addr
<= INDEX_BASE
+ 4096; addr
+= ic_lsize
) {
678 __asm__
__volatile__ (
682 "cache\t%1, 0(%0)\n\t"
683 "cache\t%1, 0x1000(%0)\n\t"
684 "cache\t%1, 0x2000(%0)\n\t"
685 "cache\t%1, 0x3000(%0)\n\t"
686 "cache\t%2, 0(%0)\n\t"
687 "cache\t%2, 0x1000(%0)\n\t"
688 "cache\t%2, 0x2000(%0)\n\t"
689 "cache\t%2, 0x3000(%0)\n\t"
690 "cache\t%1, 0(%0)\n\t"
691 "cache\t%1, 0x1000(%0)\n\t"
692 "cache\t%1, 0x2000(%0)\n\t"
693 "cache\t%1, 0x3000(%0)\n\t"
696 : "r" (addr
), "i" (Index_Store_Tag_I
), "i" (Fill
));
700 static char *way_string
[] __initdata
= { NULL
, "direct mapped", "2-way",
701 "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
704 static void __init
probe_pcache(void)
706 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
707 unsigned int config
= read_c0_config();
708 unsigned int prid
= read_c0_prid();
709 unsigned long config1
;
712 switch (c
->cputype
) {
713 case CPU_R4600
: /* QED style two way caches? */
717 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
718 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
720 c
->icache
.waybit
= __ffs(icache_size
/2);
722 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
723 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
725 c
->dcache
.waybit
= __ffs(dcache_size
/2);
727 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
732 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
733 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
737 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
738 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
740 c
->dcache
.waybit
= 0;
742 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
746 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
747 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
751 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
752 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
754 c
->dcache
.waybit
= 0;
756 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
757 c
->options
|= MIPS_CPU_PREFETCH
;
767 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
768 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
770 c
->icache
.waybit
= 0; /* doesn't matter */
772 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
773 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
775 c
->dcache
.waybit
= 0; /* does not matter */
777 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
783 icache_size
= 1 << (12 + ((config
& R10K_CONF_IC
) >> 29));
784 c
->icache
.linesz
= 64;
786 c
->icache
.waybit
= 0;
788 dcache_size
= 1 << (12 + ((config
& R10K_CONF_DC
) >> 26));
789 c
->dcache
.linesz
= 32;
791 c
->dcache
.waybit
= 0;
793 c
->options
|= MIPS_CPU_PREFETCH
;
797 write_c0_config(config
& ~VR41_CONF_P4K
);
799 /* Workaround for cache instruction bug of VR4131 */
800 if (c
->processor_id
== 0x0c80U
|| c
->processor_id
== 0x0c81U
||
801 c
->processor_id
== 0x0c82U
) {
802 config
|= 0x00400000U
;
803 if (c
->processor_id
== 0x0c80U
)
804 config
|= VR41_CONF_BP
;
805 write_c0_config(config
);
807 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
809 icache_size
= 1 << (10 + ((config
& CONF_IC
) >> 9));
810 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
812 c
->icache
.waybit
= __ffs(icache_size
/2);
814 dcache_size
= 1 << (10 + ((config
& CONF_DC
) >> 6));
815 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
817 c
->dcache
.waybit
= __ffs(dcache_size
/2);
826 icache_size
= 1 << (10 + ((config
& CONF_IC
) >> 9));
827 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
829 c
->icache
.waybit
= 0; /* doesn't matter */
831 dcache_size
= 1 << (10 + ((config
& CONF_DC
) >> 6));
832 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
834 c
->dcache
.waybit
= 0; /* does not matter */
836 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
843 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
844 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
846 c
->icache
.waybit
= __ffs(icache_size
/ c
->icache
.ways
);
848 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
849 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
851 c
->dcache
.waybit
= __ffs(dcache_size
/ c
->dcache
.ways
);
853 #if !defined(CONFIG_SMP) || !defined(RM9000_CDEX_SMP_WAR)
854 c
->options
|= MIPS_CPU_CACHE_CDEX_P
;
856 c
->options
|= MIPS_CPU_PREFETCH
;
860 icache_size
= 1 << (12 + ((config
& CONF_IC
) >> 9));
861 c
->icache
.linesz
= 16 << ((config
& CONF_IB
) >> 5);
866 c
->icache
.waybit
= 0;
868 dcache_size
= 1 << (12 + ((config
& CONF_DC
) >> 6));
869 c
->dcache
.linesz
= 16 << ((config
& CONF_DB
) >> 4);
874 c
->dcache
.waybit
= 0;
878 if (!(config
& MIPS_CONF_M
))
879 panic("Don't know how to probe P-caches on this cpu.");
882 * So we seem to be a MIPS32 or MIPS64 CPU
883 * So let's probe the I-cache ...
885 config1
= read_c0_config1();
887 if ((lsize
= ((config1
>> 19) & 7)))
888 c
->icache
.linesz
= 2 << lsize
;
890 c
->icache
.linesz
= lsize
;
891 c
->icache
.sets
= 64 << ((config1
>> 22) & 7);
892 c
->icache
.ways
= 1 + ((config1
>> 16) & 7);
894 icache_size
= c
->icache
.sets
*
897 c
->icache
.waybit
= __ffs(icache_size
/c
->icache
.ways
);
899 if (config
& 0x8) /* VI bit */
900 c
->icache
.flags
|= MIPS_CACHE_VTAG
;
903 * Now probe the MIPS32 / MIPS64 data cache.
907 if ((lsize
= ((config1
>> 10) & 7)))
908 c
->dcache
.linesz
= 2 << lsize
;
910 c
->dcache
.linesz
= lsize
;
911 c
->dcache
.sets
= 64 << ((config1
>> 13) & 7);
912 c
->dcache
.ways
= 1 + ((config1
>> 7) & 7);
914 dcache_size
= c
->dcache
.sets
*
917 c
->dcache
.waybit
= __ffs(dcache_size
/c
->dcache
.ways
);
919 c
->options
|= MIPS_CPU_PREFETCH
;
924 * Processor configuration sanity check for the R4000SC erratum
925 * #5. With page sizes larger than 32kB there is no possibility
926 * to get a VCE exception anymore so we don't care about this
927 * misconfiguration. The case is rather theoretical anyway;
928 * presumably no vendor is shipping his hardware in the "bad"
931 if ((prid
& 0xff00) == PRID_IMP_R4000
&& (prid
& 0xff) < 0x40 &&
932 !(config
& CONF_SC
) && c
->icache
.linesz
!= 16 &&
934 panic("Improper R4000SC processor configuration detected");
936 /* compute a couple of other cache variables */
937 c
->icache
.waysize
= icache_size
/ c
->icache
.ways
;
938 c
->dcache
.waysize
= dcache_size
/ c
->dcache
.ways
;
940 c
->icache
.sets
= c
->icache
.linesz
?
941 icache_size
/ (c
->icache
.linesz
* c
->icache
.ways
) : 0;
942 c
->dcache
.sets
= c
->dcache
.linesz
?
943 dcache_size
/ (c
->dcache
.linesz
* c
->dcache
.ways
) : 0;
946 * R10000 and R12000 P-caches are odd in a positive way. They're 32kB
947 * 2-way virtually indexed so normally would suffer from aliases. So
948 * normally they'd suffer from aliases but magic in the hardware deals
949 * with that for us so we don't need to take care ourselves.
951 switch (c
->cputype
) {
956 c
->dcache
.flags
|= MIPS_CACHE_PINDEX
;
967 if ((read_c0_config7() & (1 << 16))) {
968 /* effectively physically indexed dcache,
969 thus no virtual aliases. */
970 c
->dcache
.flags
|= MIPS_CACHE_PINDEX
;
974 if (c
->dcache
.waysize
> PAGE_SIZE
)
975 c
->dcache
.flags
|= MIPS_CACHE_ALIASES
;
978 switch (c
->cputype
) {
981 * Some older 20Kc chips doesn't have the 'VI' bit in
982 * the config register.
984 c
->icache
.flags
|= MIPS_CACHE_VTAG
;
992 c
->icache
.flags
|= MIPS_CACHE_IC_F_DC
;
996 #ifdef CONFIG_CPU_LOONGSON2
998 * LOONGSON2 has 4 way icache, but when using indexed cache op,
999 * one op will act on all 4 ways
1004 printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1006 cpu_has_vtag_icache
? "VIVT" : "VIPT",
1007 way_string
[c
->icache
.ways
], c
->icache
.linesz
);
1009 printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1010 dcache_size
>> 10, way_string
[c
->dcache
.ways
],
1011 (c
->dcache
.flags
& MIPS_CACHE_PINDEX
) ? "PIPT" : "VIPT",
1012 (c
->dcache
.flags
& MIPS_CACHE_ALIASES
) ?
1013 "cache aliases" : "no aliases",
1018 * If you even _breathe_ on this function, look at the gcc output and make sure
1019 * it does not pop things on and off the stack for the cache sizing loop that
1020 * executes in KSEG1 space or else you will crash and burn badly. You have
1023 static int __init
probe_scache(void)
1025 unsigned long flags
, addr
, begin
, end
, pow2
;
1026 unsigned int config
= read_c0_config();
1027 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1030 if (config
& CONF_SC
)
1033 begin
= (unsigned long) &_stext
;
1034 begin
&= ~((4 * 1024 * 1024) - 1);
1035 end
= begin
+ (4 * 1024 * 1024);
1038 * This is such a bitch, you'd think they would make it easy to do
1039 * this. Away you daemons of stupidity!
1041 local_irq_save(flags
);
1043 /* Fill each size-multiple cache line with a valid tag. */
1045 for (addr
= begin
; addr
< end
; addr
= (begin
+ pow2
)) {
1046 unsigned long *p
= (unsigned long *) addr
;
1047 __asm__
__volatile__("nop" : : "r" (*p
)); /* whee... */
1051 /* Load first line with zero (therefore invalid) tag. */
1054 __asm__
__volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1055 cache_op(Index_Store_Tag_I
, begin
);
1056 cache_op(Index_Store_Tag_D
, begin
);
1057 cache_op(Index_Store_Tag_SD
, begin
);
1059 /* Now search for the wrap around point. */
1060 pow2
= (128 * 1024);
1062 for (addr
= begin
+ (128 * 1024); addr
< end
; addr
= begin
+ pow2
) {
1063 cache_op(Index_Load_Tag_SD
, addr
);
1064 __asm__
__volatile__("nop; nop; nop; nop;"); /* hazard... */
1065 if (!read_c0_taglo())
1069 local_irq_restore(flags
);
1073 c
->scache
.linesz
= 16 << ((config
& R4K_CONF_SB
) >> 22);
1075 c
->dcache
.waybit
= 0; /* does not matter */
1080 #if defined(CONFIG_CPU_LOONGSON2)
1081 static void __init
loongson2_sc_init(void)
1083 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1085 scache_size
= 512*1024;
1086 c
->scache
.linesz
= 32;
1088 c
->scache
.waybit
= 0;
1089 c
->scache
.waysize
= scache_size
/ (c
->scache
.ways
);
1090 c
->scache
.sets
= scache_size
/ (c
->scache
.linesz
* c
->scache
.ways
);
1091 pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1092 scache_size
>> 10, way_string
[c
->scache
.ways
], c
->scache
.linesz
);
1094 c
->options
|= MIPS_CPU_INCLUSIVE_CACHES
;
1098 extern int r5k_sc_init(void);
1099 extern int rm7k_sc_init(void);
1100 extern int mips_sc_init(void);
1102 static void __init
setup_scache(void)
1104 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1105 unsigned int config
= read_c0_config();
1109 * Do the probing thing on R4000SC and R4400SC processors. Other
1110 * processors don't have a S-cache that would be relevant to the
1111 * Linux memory managment.
1113 switch (c
->cputype
) {
1118 sc_present
= run_uncached(probe_scache
);
1120 c
->options
|= MIPS_CPU_CACHE_CDEX_S
;
1126 scache_size
= 0x80000 << ((config
& R10K_CONF_SS
) >> 16);
1127 c
->scache
.linesz
= 64 << ((config
>> 13) & 1);
1129 c
->scache
.waybit
= 0;
1135 #ifdef CONFIG_R5000_CPU_SCACHE
1142 #ifdef CONFIG_RM7000_CPU_SCACHE
1147 #if defined(CONFIG_CPU_LOONGSON2)
1149 loongson2_sc_init();
1154 if (c
->isa_level
== MIPS_CPU_ISA_M32R1
||
1155 c
->isa_level
== MIPS_CPU_ISA_M32R2
||
1156 c
->isa_level
== MIPS_CPU_ISA_M64R1
||
1157 c
->isa_level
== MIPS_CPU_ISA_M64R2
) {
1158 #ifdef CONFIG_MIPS_CPU_SCACHE
1159 if (mips_sc_init ()) {
1160 scache_size
= c
->scache
.ways
* c
->scache
.sets
* c
->scache
.linesz
;
1161 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1163 way_string
[c
->scache
.ways
], c
->scache
.linesz
);
1166 if (!(c
->scache
.flags
& MIPS_CACHE_NOT_PRESENT
))
1167 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1177 /* compute a couple of other cache variables */
1178 c
->scache
.waysize
= scache_size
/ c
->scache
.ways
;
1180 c
->scache
.sets
= scache_size
/ (c
->scache
.linesz
* c
->scache
.ways
);
1182 printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1183 scache_size
>> 10, way_string
[c
->scache
.ways
], c
->scache
.linesz
);
1185 c
->options
|= MIPS_CPU_INCLUSIVE_CACHES
;
1188 void au1x00_fixup_config_od(void)
1191 * c0_config.od (bit 19) was write only (and read as 0)
1192 * on the early revisions of Alchemy SOCs. It disables the bus
1193 * transaction overlapping and needs to be set to fix various errata.
1195 switch (read_c0_prid()) {
1196 case 0x00030100: /* Au1000 DA */
1197 case 0x00030201: /* Au1000 HA */
1198 case 0x00030202: /* Au1000 HB */
1199 case 0x01030200: /* Au1500 AB */
1201 * Au1100 errata actually keeps silence about this bit, so we set it
1202 * just in case for those revisions that require it to be set according
1203 * to arch/mips/au1000/common/cputable.c
1205 case 0x02030200: /* Au1100 AB */
1206 case 0x02030201: /* Au1100 BA */
1207 case 0x02030202: /* Au1100 BC */
1208 set_c0_config(1 << 19);
1213 static void __init
coherency_setup(void)
1215 change_c0_config(CONF_CM_CMASK
, CONF_CM_DEFAULT
);
1218 * c0_status.cu=0 specifies that updates by the sc instruction use
1219 * the coherency mode specified by the TLB; 1 means cachable
1220 * coherent update on write will be used. Not all processors have
1221 * this bit and; some wire it to zero, others like Toshiba had the
1222 * silly idea of putting something else there ...
1224 switch (current_cpu_type()) {
1231 clear_c0_config(CONF_CU
);
1234 * We need to catch the early Alchemy SOCs with
1235 * the write-only co_config.od bit and set it back to one...
1237 case CPU_AU1000
: /* rev. DA, HA, HB */
1238 case CPU_AU1100
: /* rev. AB, BA, BC ?? */
1239 case CPU_AU1500
: /* rev. AB */
1240 au1x00_fixup_config_od();
1245 void __init
r4k_cache_init(void)
1247 extern void build_clear_page(void);
1248 extern void build_copy_page(void);
1249 extern char __weak except_vec2_generic
;
1250 extern char __weak except_vec2_sb1
;
1251 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
1253 switch (c
->cputype
) {
1256 set_uncached_handler(0x100, &except_vec2_sb1
, 0x80);
1260 set_uncached_handler(0x100, &except_vec2_generic
, 0x80);
1267 r4k_blast_dcache_page_setup();
1268 r4k_blast_dcache_page_indexed_setup();
1269 r4k_blast_dcache_setup();
1270 r4k_blast_icache_page_setup();
1271 r4k_blast_icache_page_indexed_setup();
1272 r4k_blast_icache_setup();
1273 r4k_blast_scache_page_setup();
1274 r4k_blast_scache_page_indexed_setup();
1275 r4k_blast_scache_setup();
1278 * Some MIPS32 and MIPS64 processors have physically indexed caches.
1279 * This code supports virtually indexed processors and will be
1280 * unnecessarily inefficient on physically indexed processors.
1282 if (c
->dcache
.linesz
)
1283 shm_align_mask
= max_t( unsigned long,
1284 c
->dcache
.sets
* c
->dcache
.linesz
- 1,
1287 shm_align_mask
= PAGE_SIZE
-1;
1288 flush_cache_all
= cache_noop
;
1289 __flush_cache_all
= r4k___flush_cache_all
;
1290 flush_cache_mm
= r4k_flush_cache_mm
;
1291 flush_cache_page
= r4k_flush_cache_page
;
1292 flush_cache_range
= r4k_flush_cache_range
;
1294 flush_cache_sigtramp
= r4k_flush_cache_sigtramp
;
1295 flush_icache_all
= r4k_flush_icache_all
;
1296 local_flush_data_cache_page
= local_r4k_flush_data_cache_page
;
1297 flush_data_cache_page
= r4k_flush_data_cache_page
;
1298 flush_icache_range
= r4k_flush_icache_range
;
1300 #ifdef CONFIG_DMA_NONCOHERENT
1301 _dma_cache_wback_inv
= r4k_dma_cache_wback_inv
;
1302 _dma_cache_wback
= r4k_dma_cache_wback_inv
;
1303 _dma_cache_inv
= r4k_dma_cache_inv
;
1308 local_r4k___flush_cache_all(NULL
);