arch/sparc64/kernel/cpu.c

   1 /* cpu.c: Dinky routines to look for the kind of Sparc cpu
   2  *        we are on.
   3  *
   4  * Copyright (C) 1996, 2007 David S. Miller (davem@davemloft.net)
   5  */
   6
   7 #include <linux/kernel.h>
   8 #include <linux/init.h>
   9 #include <linux/sched.h>
  10 #include <linux/smp.h>
  11 #include <asm/asi.h>
  12 #include <asm/system.h>
  13 #include <asm/fpumacro.h>
  14 #include <asm/cpudata.h>
  15 #include <asm/spitfire.h>
  16 #include <asm/oplib.h>
  17
  18 DEFINE_PER_CPU(cpuinfo_sparc, __cpu_data) = { 0 };
  19
  20 struct cpu_iu_info {
  21   short manuf;
  22   short impl;
  23   char* cpu_name;   /* should be enough I hope... */
  24 };
  25
  26 struct cpu_fp_info {
  27   short manuf;
  28   short impl;
  29   char fpu_vers;
  30   char* fp_name;
  31 };
  32
  33 struct cpu_fp_info linux_sparc_fpu[] = {
  34   { 0x17, 0x10, 0, "UltraSparc I integrated FPU"},
  35   { 0x22, 0x10, 0, "UltraSparc I integrated FPU"},
  36   { 0x17, 0x11, 0, "UltraSparc II integrated FPU"},
  37   { 0x17, 0x12, 0, "UltraSparc IIi integrated FPU"},
  38   { 0x17, 0x13, 0, "UltraSparc IIe integrated FPU"},
  39   { 0x3e, 0x14, 0, "UltraSparc III integrated FPU"},
  40   { 0x3e, 0x15, 0, "UltraSparc III+ integrated FPU"},
  41   { 0x3e, 0x16, 0, "UltraSparc IIIi integrated FPU"},
  42   { 0x3e, 0x18, 0, "UltraSparc IV integrated FPU"},
  43   { 0x3e, 0x19, 0, "UltraSparc IV+ integrated FPU"},
  44   { 0x3e, 0x22, 0, "UltraSparc IIIi+ integrated FPU"},
  45 };
  46
  47 #define NSPARCFPU  ARRAY_SIZE(linux_sparc_fpu)
  48
  49 struct cpu_iu_info linux_sparc_chips[] = {
  50   { 0x17, 0x10, "TI UltraSparc I   (SpitFire)"},
  51   { 0x22, 0x10, "TI UltraSparc I   (SpitFire)"},
  52   { 0x17, 0x11, "TI UltraSparc II  (BlackBird)"},
  53   { 0x17, 0x12, "TI UltraSparc IIi (Sabre)"},
  54   { 0x17, 0x13, "TI UltraSparc IIe (Hummingbird)"},
  55   { 0x3e, 0x14, "TI UltraSparc III (Cheetah)"},
  56   { 0x3e, 0x15, "TI UltraSparc III+ (Cheetah+)"},
  57   { 0x3e, 0x16, "TI UltraSparc IIIi (Jalapeno)"},
  58   { 0x3e, 0x18, "TI UltraSparc IV (Jaguar)"},
  59   { 0x3e, 0x19, "TI UltraSparc IV+ (Panther)"},
  60   { 0x3e, 0x22, "TI UltraSparc IIIi+ (Serrano)"},
  61 };
  62
  63 #define NSPARCCHIPS  ARRAY_SIZE(linux_sparc_chips)
  64
  65 char *sparc_cpu_type;
  66 char *sparc_fpu_type;
  67
  68 unsigned int fsr_storage;
  69
  70 static void __init sun4v_cpu_probe(void)
  71 {
  72         switch (sun4v_chip_type) {
  73         case SUN4V_CHIP_NIAGARA1:
  74                 sparc_cpu_type = "UltraSparc T1 (Niagara)";
  75                 sparc_fpu_type = "UltraSparc T1 integrated FPU";
  76                 break;
  77
  78         case SUN4V_CHIP_NIAGARA2:
  79                 sparc_cpu_type = "UltraSparc T2 (Niagara2)";
  80                 sparc_fpu_type = "UltraSparc T2 integrated FPU";
  81                 break;
  82
  83         default:
  84                 printk(KERN_WARNING "CPU: Unknown sun4v cpu type [%s]\n",
  85                        prom_cpu_compatible);
  86                 sparc_cpu_type = "Unknown SUN4V CPU";
  87                 sparc_fpu_type = "Unknown SUN4V FPU";
  88                 break;
  89         }
  90 }
  91
  92 void __init cpu_probe(void)
  93 {
  94         unsigned long ver, fpu_vers, manuf, impl, fprs;
  95         int i;
  96
  97         if (tlb_type == hypervisor)
  98                 return sun4v_cpu_probe();
  99
 100         fprs = fprs_read();
 101         fprs_write(FPRS_FEF);
 102         __asm__ __volatile__ ("rdpr %%ver, %0; stx %%fsr, [%1]"
 103                               : "=&r" (ver)
 104                               : "r" (&fpu_vers));
 105         fprs_write(fprs);
 106
 107         manuf = ((ver >> 48) & 0xffff);
 108         impl = ((ver >> 32) & 0xffff);
 109
 110         fpu_vers = ((fpu_vers >> 17) & 0x7);
 111
 112 retry:
 113         for (i = 0; i < NSPARCCHIPS; i++) {
 114                 if (linux_sparc_chips[i].manuf == manuf) {
 115                         if (linux_sparc_chips[i].impl == impl) {
 116                                 sparc_cpu_type =
 117                                         linux_sparc_chips[i].cpu_name;
 118                                 break;
 119                         }
 120                 }
 121         }
 122
 123         if (i == NSPARCCHIPS) {
 124                 /* Maybe it is a cheetah+ derivative, report it as cheetah+
 125                  * in that case until we learn the real names.
 126                  */
 127                 if (manuf == 0x3e &&
 128                     impl > 0x15) {
 129                         impl = 0x15;
 130                         goto retry;
 131                 } else {
 132                         printk("DEBUG: manuf[%lx] impl[%lx]\n",
 133                                manuf, impl);
 134                 }
 135                 sparc_cpu_type = "Unknown CPU";
 136         }
 137
 138         for (i = 0; i < NSPARCFPU; i++) {
 139                 if (linux_sparc_fpu[i].manuf == manuf &&
 140                     linux_sparc_fpu[i].impl == impl) {
 141                         if (linux_sparc_fpu[i].fpu_vers == fpu_vers) {
 142                                 sparc_fpu_type =
 143                                         linux_sparc_fpu[i].fp_name;
 144                                 break;
 145                         }
 146                 }
 147         }
 148
 149         if (i == NSPARCFPU) {
 150                 printk("DEBUG: manuf[%lx] impl[%lx] fsr.vers[%lx]\n",
 151                        manuf, impl, fpu_vers);
 152                 sparc_fpu_type = "Unknown FPU";
 153         }
 154 }