arch/x86/kernel/cpu/common.c

   1 #include <linux/init.h>
   2 #include <linux/kernel.h>
   3 #include <linux/sched.h>
   4 #include <linux/string.h>
   5 #include <linux/bootmem.h>
   6 #include <linux/bitops.h>
   7 #include <linux/module.h>
   8 #include <linux/kgdb.h>
   9 #include <linux/topology.h>
  10 #include <linux/delay.h>
  11 #include <linux/smp.h>
  12 #include <linux/percpu.h>
  13 #include <asm/i387.h>
  14 #include <asm/msr.h>
  15 #include <asm/io.h>
  16 #include <asm/linkage.h>
  17 #include <asm/mmu_context.h>
  18 #include <asm/mtrr.h>
  19 #include <asm/mce.h>
  20 #include <asm/pat.h>
  21 #include <asm/asm.h>
  22 #include <asm/numa.h>
  23 #ifdef CONFIG_X86_LOCAL_APIC
  24 #include <asm/mpspec.h>
  25 #include <asm/apic.h>
  26 #include <mach_apic.h>
  27 #include <asm/genapic.h>
  28 #endif
  29
  30 #include <asm/pda.h>
  31 #include <asm/pgtable.h>
  32 #include <asm/processor.h>
  33 #include <asm/desc.h>
  34 #include <asm/atomic.h>
  35 #include <asm/proto.h>
  36 #include <asm/sections.h>
  37 #include <asm/setup.h>
  38
  39 #include "cpu.h"
  40
  41 static struct cpu_dev *this_cpu __cpuinitdata;
  42
  43 #ifdef CONFIG_X86_64
  44 /* We need valid kernel segments for data and code in long mode too
  45  * IRET will check the segment types  kkeil 2000/10/28
  46  * Also sysret mandates a special GDT layout
  47  */
  48 /* The TLS descriptors are currently at a different place compared to i386.
  49    Hopefully nobody expects them at a fixed place (Wine?) */
  50 DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
  51         [GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
  52         [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
  53         [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
  54         [GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
  55         [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
  56         [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
  57 } };
  58 #else
  59 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
  60         [GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
  61         [GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
  62         [GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
  63         [GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
  64         /*
  65          * Segments used for calling PnP BIOS have byte granularity.
  66          * They code segments and data segments have fixed 64k limits,
  67          * the transfer segment sizes are set at run time.
  68          */
  69         /* 32-bit code */
  70         [GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
  71         /* 16-bit code */
  72         [GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
  73         /* 16-bit data */
  74         [GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
  75         /* 16-bit data */
  76         [GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
  77         /* 16-bit data */
  78         [GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
  79         /*
  80          * The APM segments have byte granularity and their bases
  81          * are set at run time.  All have 64k limits.
  82          */
  83         /* 32-bit code */
  84         [GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
  85         /* 16-bit code */
  86         [GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
  87         /* data */
  88         [GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
  89
  90         [GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
  91         [GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } },
  92 } };
  93 #endif
  94 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
  95
  96 #ifdef CONFIG_X86_32
  97 static int cachesize_override __cpuinitdata = -1;
  98 static int disable_x86_serial_nr __cpuinitdata = 1;
  99
 100 static int __init cachesize_setup(char *str)
 101 {
 102         get_option(&str, &cachesize_override);
 103         return 1;
 104 }
 105 __setup("cachesize=", cachesize_setup);
 106
 107 /*
 108  * Naming convention should be: <Name> [(<Codename>)]
 109  * This table only is used unless init_<vendor>() below doesn't set it;
 110  * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
 111  *
 112  */
 113
 114 /* Look up CPU names by table lookup. */
 115 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
 116 {
 117         struct cpu_model_info *info;
 118
 119         if (c->x86_model >= 16)
 120                 return NULL;    /* Range check */
 121
 122         if (!this_cpu)
 123                 return NULL;
 124
 125         info = this_cpu->c_models;
 126
 127         while (info && info->family) {
 128                 if (info->family == c->x86)
 129                         return info->model_names[c->x86_model];
 130                 info++;
 131         }
 132         return NULL;            /* Not found */
 133 }
 134
 135 static int __init x86_fxsr_setup(char *s)
 136 {
 137         setup_clear_cpu_cap(X86_FEATURE_FXSR);
 138         setup_clear_cpu_cap(X86_FEATURE_XMM);
 139         return 1;
 140 }
 141 __setup("nofxsr", x86_fxsr_setup);
 142
 143 static int __init x86_sep_setup(char *s)
 144 {
 145         setup_clear_cpu_cap(X86_FEATURE_SEP);
 146         return 1;
 147 }
 148 __setup("nosep", x86_sep_setup);
 149
 150 /* Standard macro to see if a specific flag is changeable */
 151 static inline int flag_is_changeable_p(u32 flag)
 152 {
 153         u32 f1, f2;
 154
 155         asm("pushfl\n\t"
 156             "pushfl\n\t"
 157             "popl %0\n\t"
 158             "movl %0,%1\n\t"
 159             "xorl %2,%0\n\t"
 160             "pushl %0\n\t"
 161             "popfl\n\t"
 162             "pushfl\n\t"
 163             "popl %0\n\t"
 164             "popfl\n\t"
 165             : "=&r" (f1), "=&r" (f2)
 166             : "ir" (flag));
 167
 168         return ((f1^f2) & flag) != 0;
 169 }
 170
 171 /* Probe for the CPUID instruction */
 172 static int __cpuinit have_cpuid_p(void)
 173 {
 174         return flag_is_changeable_p(X86_EFLAGS_ID);
 175 }
 176
 177 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
 178 {
 179         if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
 180                 /* Disable processor serial number */
 181                 unsigned long lo, hi;
 182                 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
 183                 lo |= 0x200000;
 184                 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
 185                 printk(KERN_NOTICE "CPU serial number disabled.\n");
 186                 clear_cpu_cap(c, X86_FEATURE_PN);
 187
 188                 /* Disabling the serial number may affect the cpuid level */
 189                 c->cpuid_level = cpuid_eax(0);
 190         }
 191 }
 192
 193 static int __init x86_serial_nr_setup(char *s)
 194 {
 195         disable_x86_serial_nr = 0;
 196         return 1;
 197 }
 198 __setup("serialnumber", x86_serial_nr_setup);
 199 #else
 200 /* Probe for the CPUID instruction */
 201 static inline int have_cpuid_p(void)
 202 {
 203         return 1;
 204 }
 205 #endif
 206
 207 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
 208
 209 /* Current gdt points %fs at the "master" per-cpu area: after this,
 210  * it's on the real one. */
 211 void switch_to_new_gdt(void)
 212 {
 213         struct desc_ptr gdt_descr;
 214
 215         gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
 216         gdt_descr.size = GDT_SIZE - 1;
 217         load_gdt(&gdt_descr);
 218 #ifdef CONFIG_X86_32
 219         asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
 220 #endif
 221 }
 222
 223 static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
 224
 225 static void __cpuinit default_init(struct cpuinfo_x86 *c)
 226 {
 227 #ifdef CONFIG_X86_64
 228         display_cacheinfo(c);
 229 #else
 230         /* Not much we can do here... */
 231         /* Check if at least it has cpuid */
 232         if (c->cpuid_level == -1) {
 233                 /* No cpuid. It must be an ancient CPU */
 234                 if (c->x86 == 4)
 235                         strcpy(c->x86_model_id, "486");
 236                 else if (c->x86 == 3)
 237                         strcpy(c->x86_model_id, "386");
 238         }
 239 #endif
 240 }
 241
 242 static struct cpu_dev __cpuinitdata default_cpu = {
 243         .c_init = default_init,
 244         .c_vendor = "Unknown",
 245         .c_x86_vendor = X86_VENDOR_UNKNOWN,
 246 };
 247
 248 int __cpuinit get_model_name(struct cpuinfo_x86 *c)
 249 {
 250         unsigned int *v;
 251         char *p, *q;
 252
 253         if (c->extended_cpuid_level < 0x80000004)
 254                 return 0;
 255
 256         v = (unsigned int *) c->x86_model_id;
 257         cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
 258         cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
 259         cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
 260         c->x86_model_id[48] = 0;
 261
 262         /* Intel chips right-justify this string for some dumb reason;
 263            undo that brain damage */
 264         p = q = &c->x86_model_id[0];
 265         while (*p == ' ')
 266              p++;
 267         if (p != q) {
 268              while (*p)
 269                   *q++ = *p++;
 270              while (q <= &c->x86_model_id[48])
 271                   *q++ = '\0';  /* Zero-pad the rest */
 272         }
 273
 274         return 1;
 275 }
 276
 277 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
 278 {
 279         unsigned int n, dummy, ebx, ecx, edx, l2size;
 280
 281         n = c->extended_cpuid_level;
 282
 283         if (n >= 0x80000005) {
 284                 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
 285                 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
 286                                 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
 287                 c->x86_cache_size = (ecx>>24) + (edx>>24);
 288 #ifdef CONFIG_X86_64
 289                 /* On K8 L1 TLB is inclusive, so don't count it */
 290                 c->x86_tlbsize = 0;
 291 #endif
 292         }
 293
 294         if (n < 0x80000006)     /* Some chips just has a large L1. */
 295                 return;
 296
 297         cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
 298         l2size = ecx >> 16;
 299
 300 #ifdef CONFIG_X86_64
 301         c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
 302 #else
 303         /* do processor-specific cache resizing */
 304         if (this_cpu->c_size_cache)
 305                 l2size = this_cpu->c_size_cache(c, l2size);
 306
 307         /* Allow user to override all this if necessary. */
 308         if (cachesize_override != -1)
 309                 l2size = cachesize_override;
 310
 311         if (l2size == 0)
 312                 return;         /* Again, no L2 cache is possible */
 313 #endif
 314
 315         c->x86_cache_size = l2size;
 316
 317         printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
 318                         l2size, ecx & 0xFF);
 319 }
 320
 321 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
 322 {
 323 #ifdef CONFIG_X86_HT
 324         u32 eax, ebx, ecx, edx;
 325         int index_msb, core_bits;
 326
 327         if (!cpu_has(c, X86_FEATURE_HT))
 328                 return;
 329
 330         if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
 331                 goto out;
 332
 333         if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
 334                 return;
 335
 336         cpuid(1, &eax, &ebx, &ecx, &edx);
 337
 338         smp_num_siblings = (ebx & 0xff0000) >> 16;
 339
 340         if (smp_num_siblings == 1) {
 341                 printk(KERN_INFO  "CPU: Hyper-Threading is disabled\n");
 342         } else if (smp_num_siblings > 1) {
 343
 344                 if (smp_num_siblings > NR_CPUS) {
 345                         printk(KERN_WARNING "CPU: Unsupported number of siblings %d",
 346                                         smp_num_siblings);
 347                         smp_num_siblings = 1;
 348                         return;
 349                 }
 350
 351                 index_msb = get_count_order(smp_num_siblings);
 352 #ifdef CONFIG_X86_64
 353                 c->phys_proc_id = phys_pkg_id(index_msb);
 354 #else
 355                 c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb);
 356 #endif
 357
 358                 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
 359
 360                 index_msb = get_count_order(smp_num_siblings);
 361
 362                 core_bits = get_count_order(c->x86_max_cores);
 363
 364 #ifdef CONFIG_X86_64
 365                 c->cpu_core_id = phys_pkg_id(index_msb) &
 366                                                ((1 << core_bits) - 1);
 367 #else
 368                 c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) &
 369                                                ((1 << core_bits) - 1);
 370 #endif
 371         }
 372
 373 out:
 374         if ((c->x86_max_cores * smp_num_siblings) > 1) {
 375                 printk(KERN_INFO  "CPU: Physical Processor ID: %d\n",
 376                        c->phys_proc_id);
 377                 printk(KERN_INFO  "CPU: Processor Core ID: %d\n",
 378                        c->cpu_core_id);
 379         }
 380 #endif
 381 }
 382
 383 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
 384 {
 385         char *v = c->x86_vendor_id;
 386         int i;
 387         static int printed;
 388
 389         for (i = 0; i < X86_VENDOR_NUM; i++) {
 390                 if (!cpu_devs[i])
 391                         break;
 392
 393                 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
 394                     (cpu_devs[i]->c_ident[1] &&
 395                      !strcmp(v, cpu_devs[i]->c_ident[1]))) {
 396                         this_cpu = cpu_devs[i];
 397                         c->x86_vendor = this_cpu->c_x86_vendor;
 398                         return;
 399                 }
 400         }
 401
 402         if (!printed) {
 403                 printed++;
 404                 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
 405                 printk(KERN_ERR "CPU: Your system may be unstable.\n");
 406         }
 407
 408         c->x86_vendor = X86_VENDOR_UNKNOWN;
 409         this_cpu = &default_cpu;
 410 }
 411
 412 void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
 413 {
 414         /* Get vendor name */
 415         cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
 416               (unsigned int *)&c->x86_vendor_id[0],
 417               (unsigned int *)&c->x86_vendor_id[8],
 418               (unsigned int *)&c->x86_vendor_id[4]);
 419
 420         c->x86 = 4;
 421         /* Intel-defined flags: level 0x00000001 */
 422         if (c->cpuid_level >= 0x00000001) {
 423                 u32 junk, tfms, cap0, misc;
 424                 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
 425                 c->x86 = (tfms >> 8) & 0xf;
 426                 c->x86_model = (tfms >> 4) & 0xf;
 427                 c->x86_mask = tfms & 0xf;
 428                 if (c->x86 == 0xf)
 429                         c->x86 += (tfms >> 20) & 0xff;
 430                 if (c->x86 >= 0x6)
 431                         c->x86_model += ((tfms >> 16) & 0xf) << 4;
 432                 if (cap0 & (1<<19)) {
 433                         c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
 434                         c->x86_cache_alignment = c->x86_clflush_size;
 435                 }
 436         }
 437 }
 438
 439 static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
 440 {
 441         u32 tfms, xlvl;
 442         u32 ebx;
 443
 444         /* Intel-defined flags: level 0x00000001 */
 445         if (c->cpuid_level >= 0x00000001) {
 446                 u32 capability, excap;
 447                 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
 448                 c->x86_capability[0] = capability;
 449                 c->x86_capability[4] = excap;
 450         }
 451
 452         /* AMD-defined flags: level 0x80000001 */
 453         xlvl = cpuid_eax(0x80000000);
 454         c->extended_cpuid_level = xlvl;
 455         if ((xlvl & 0xffff0000) == 0x80000000) {
 456                 if (xlvl >= 0x80000001) {
 457                         c->x86_capability[1] = cpuid_edx(0x80000001);
 458                         c->x86_capability[6] = cpuid_ecx(0x80000001);
 459                 }
 460         }
 461
 462 #ifdef CONFIG_X86_64
 463         /* Transmeta-defined flags: level 0x80860001 */
 464         xlvl = cpuid_eax(0x80860000);
 465         if ((xlvl & 0xffff0000) == 0x80860000) {
 466                 /* Don't set x86_cpuid_level here for now to not confuse. */
 467                 if (xlvl >= 0x80860001)
 468                         c->x86_capability[2] = cpuid_edx(0x80860001);
 469         }
 470
 471         if (c->extended_cpuid_level >= 0x80000007)
 472                 c->x86_power = cpuid_edx(0x80000007);
 473
 474         if (c->extended_cpuid_level >= 0x80000008) {
 475                 u32 eax = cpuid_eax(0x80000008);
 476
 477                 c->x86_virt_bits = (eax >> 8) & 0xff;
 478                 c->x86_phys_bits = eax & 0xff;
 479         }
 480 #endif
 481 }
 482 /*
 483  * Do minimum CPU detection early.
 484  * Fields really needed: vendor, cpuid_level, family, model, mask,
 485  * cache alignment.
 486  * The others are not touched to avoid unwanted side effects.
 487  *
 488  * WARNING: this function is only called on the BP.  Don't add code here
 489  * that is supposed to run on all CPUs.
 490  */
 491 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
 492 {
 493         c->x86_clflush_size = 32;
 494         c->x86_cache_alignment = c->x86_clflush_size;
 495
 496         if (!have_cpuid_p())
 497                 return;
 498
 499         memset(&c->x86_capability, 0, sizeof c->x86_capability);
 500
 501         c->extended_cpuid_level = 0;
 502
 503         cpu_detect(c);
 504
 505         get_cpu_vendor(c);
 506
 507         get_cpu_cap(c);
 508
 509         if (this_cpu->c_early_init)
 510                 this_cpu->c_early_init(c);
 511
 512         validate_pat_support(c);
 513 }
 514
 515 void __init early_cpu_init(void)
 516 {
 517         struct cpu_dev **cdev;
 518         int count = 0;
 519
 520         printk("KERNEL supported cpus:\n");
 521         for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
 522                 struct cpu_dev *cpudev = *cdev;
 523                 unsigned int j;
 524
 525                 if (count >= X86_VENDOR_NUM)
 526                         break;
 527                 cpu_devs[count] = cpudev;
 528                 count++;
 529
 530                 for (j = 0; j < 2; j++) {
 531                         if (!cpudev->c_ident[j])
 532                                 continue;
 533                         printk("  %s %s\n", cpudev->c_vendor,
 534                                 cpudev->c_ident[j]);
 535                 }
 536         }
 537
 538         early_identify_cpu(&boot_cpu_data);
 539 }
 540
 541 /*
 542  * The NOPL instruction is supposed to exist on all CPUs with
 543  * family >= 6, unfortunately, that's not true in practice because
 544  * of early VIA chips and (more importantly) broken virtualizers that
 545  * are not easy to detect.  Hence, probe for it based on first
 546  * principles.
 547  */
 548 static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
 549 {
 550         const u32 nopl_signature = 0x888c53b1; /* Random number */
 551         u32 has_nopl = nopl_signature;
 552
 553         clear_cpu_cap(c, X86_FEATURE_NOPL);
 554         if (c->x86 >= 6) {
 555                 asm volatile("\n"
 556                              "1:      .byte 0x0f,0x1f,0xc0\n" /* nopl %eax */
 557                              "2:\n"
 558                              "        .section .fixup,\"ax\"\n"
 559                              "3:      xor %0,%0\n"
 560                              "        jmp 2b\n"
 561                              "        .previous\n"
 562                              _ASM_EXTABLE(1b,3b)
 563                              : "+a" (has_nopl));
 564
 565                 if (has_nopl == nopl_signature)
 566                         set_cpu_cap(c, X86_FEATURE_NOPL);
 567         }
 568 }
 569
 570 static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
 571 {
 572         if (!have_cpuid_p())
 573                 return;
 574
 575         c->extended_cpuid_level = 0;
 576
 577         cpu_detect(c);
 578
 579         get_cpu_vendor(c);
 580
 581         get_cpu_cap(c);
 582
 583         if (c->cpuid_level >= 0x00000001) {
 584                 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
 585 #ifdef CONFIG_X86_HT
 586                 c->apicid = phys_pkg_id(c->initial_apicid, 0);
 587                 c->phys_proc_id = c->initial_apicid;
 588 #else
 589                 c->apicid = c->initial_apicid;
 590 #endif
 591         }
 592
 593         if (c->extended_cpuid_level >= 0x80000004)
 594                 get_model_name(c); /* Default name */
 595
 596         init_scattered_cpuid_features(c);
 597         detect_nopl(c);
 598 }
 599
 600 /*
 601  * This does the hard work of actually picking apart the CPU stuff...
 602  */
 603 static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
 604 {
 605         int i;
 606
 607         c->loops_per_jiffy = loops_per_jiffy;
 608         c->x86_cache_size = -1;
 609         c->x86_vendor = X86_VENDOR_UNKNOWN;
 610         c->cpuid_level = -1;    /* CPUID not detected */
 611         c->x86_model = c->x86_mask = 0; /* So far unknown... */
 612         c->x86_vendor_id[0] = '\0'; /* Unset */
 613         c->x86_model_id[0] = '\0';  /* Unset */
 614         c->x86_max_cores = 1;
 615         c->x86_clflush_size = 32;
 616         memset(&c->x86_capability, 0, sizeof c->x86_capability);
 617
 618         if (!have_cpuid_p()) {
 619                 /*
 620                  * First of all, decide if this is a 486 or higher
 621                  * It's a 486 if we can modify the AC flag
 622                  */
 623                 if (flag_is_changeable_p(X86_EFLAGS_AC))
 624                         c->x86 = 4;
 625                 else
 626                         c->x86 = 3;
 627         }
 628
 629         generic_identify(c);
 630
 631         if (this_cpu->c_identify)
 632                 this_cpu->c_identify(c);
 633
 634         /*
 635          * Vendor-specific initialization.  In this section we
 636          * canonicalize the feature flags, meaning if there are
 637          * features a certain CPU supports which CPUID doesn't
 638          * tell us, CPUID claiming incorrect flags, or other bugs,
 639          * we handle them here.
 640          *
 641          * At the end of this section, c->x86_capability better
 642          * indicate the features this CPU genuinely supports!
 643          */
 644         if (this_cpu->c_init)
 645                 this_cpu->c_init(c);
 646
 647         /* Disable the PN if appropriate */
 648         squash_the_stupid_serial_number(c);
 649
 650         /*
 651          * The vendor-specific functions might have changed features.  Now
 652          * we do "generic changes."
 653          */
 654
 655         /* If the model name is still unset, do table lookup. */
 656         if (!c->x86_model_id[0]) {
 657                 char *p;
 658                 p = table_lookup_model(c);
 659                 if (p)
 660                         strcpy(c->x86_model_id, p);
 661                 else
 662                         /* Last resort... */
 663                         sprintf(c->x86_model_id, "%02x/%02x",
 664                                 c->x86, c->x86_model);
 665         }
 666
 667         /*
 668          * On SMP, boot_cpu_data holds the common feature set between
 669          * all CPUs; so make sure that we indicate which features are
 670          * common between the CPUs.  The first time this routine gets
 671          * executed, c == &boot_cpu_data.
 672          */
 673         if (c != &boot_cpu_data) {
 674                 /* AND the already accumulated flags with these */
 675                 for (i = 0; i < NCAPINTS; i++)
 676                         boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
 677         }
 678
 679         /* Clear all flags overriden by options */
 680         for (i = 0; i < NCAPINTS; i++)
 681                 c->x86_capability[i] &= ~cleared_cpu_caps[i];
 682
 683         /* Init Machine Check Exception if available. */
 684         mcheck_init(c);
 685
 686         select_idle_routine(c);
 687 }
 688
 689 void __init identify_boot_cpu(void)
 690 {
 691         identify_cpu(&boot_cpu_data);
 692         sysenter_setup();
 693         enable_sep_cpu();
 694 }
 695
 696 void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
 697 {
 698         BUG_ON(c == &boot_cpu_data);
 699         identify_cpu(c);
 700         enable_sep_cpu();
 701         mtrr_ap_init();
 702 }
 703
 704 struct msr_range {
 705         unsigned min;
 706         unsigned max;
 707 };
 708
 709 static struct msr_range msr_range_array[] __cpuinitdata = {
 710         { 0x00000000, 0x00000418},
 711         { 0xc0000000, 0xc000040b},
 712         { 0xc0010000, 0xc0010142},
 713         { 0xc0011000, 0xc001103b},
 714 };
 715
 716 static void __cpuinit print_cpu_msr(void)
 717 {
 718         unsigned index;
 719         u64 val;
 720         int i;
 721         unsigned index_min, index_max;
 722
 723         for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
 724                 index_min = msr_range_array[i].min;
 725                 index_max = msr_range_array[i].max;
 726                 for (index = index_min; index < index_max; index++) {
 727                         if (rdmsrl_amd_safe(index, &val))
 728                                 continue;
 729                         printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
 730                 }
 731         }
 732 }
 733
 734 static int show_msr __cpuinitdata;
 735 static __init int setup_show_msr(char *arg)
 736 {
 737         int num;
 738
 739         get_option(&arg, &num);
 740
 741         if (num > 0)
 742                 show_msr = num;
 743         return 1;
 744 }
 745 __setup("show_msr=", setup_show_msr);
 746
 747 static __init int setup_noclflush(char *arg)
 748 {
 749         setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
 750         return 1;
 751 }
 752 __setup("noclflush", setup_noclflush);
 753
 754 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
 755 {
 756         char *vendor = NULL;
 757
 758         if (c->x86_vendor < X86_VENDOR_NUM)
 759                 vendor = this_cpu->c_vendor;
 760         else if (c->cpuid_level >= 0)
 761                 vendor = c->x86_vendor_id;
 762
 763         if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
 764                 printk(KERN_CONT "%s ", vendor);
 765
 766         if (c->x86_model_id[0])
 767                 printk(KERN_CONT "%s", c->x86_model_id);
 768         else
 769                 printk(KERN_CONT "%d86", c->x86);
 770
 771         if (c->x86_mask || c->cpuid_level >= 0)
 772                 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
 773         else
 774                 printk(KERN_CONT "\n");
 775
 776 #ifdef CONFIG_SMP
 777         if (c->cpu_index < show_msr)
 778                 print_cpu_msr();
 779 #else
 780         if (show_msr)
 781                 print_cpu_msr();
 782 #endif
 783 }
 784
 785 static __init int setup_disablecpuid(char *arg)
 786 {
 787         int bit;
 788         if (get_option(&arg, &bit) && bit < NCAPINTS*32)
 789                 setup_clear_cpu_cap(bit);
 790         else
 791                 return 0;
 792         return 1;
 793 }
 794 __setup("clearcpuid=", setup_disablecpuid);
 795
 796 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
 797
 798 #ifdef CONFIG_X86_64
 799 struct x8664_pda **_cpu_pda __read_mostly;
 800 EXPORT_SYMBOL(_cpu_pda);
 801
 802 struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };
 803
 804 char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss;
 805
 806 unsigned long __supported_pte_mask __read_mostly = ~0UL;
 807 EXPORT_SYMBOL_GPL(__supported_pte_mask);
 808
 809 static int do_not_nx __cpuinitdata;
 810
 811 /* noexec=on|off
 812 Control non executable mappings for 64bit processes.
 813
 814 on      Enable(default)
 815 off     Disable
 816 */
 817 static int __init nonx_setup(char *str)
 818 {
 819         if (!str)
 820                 return -EINVAL;
 821         if (!strncmp(str, "on", 2)) {
 822                 __supported_pte_mask |= _PAGE_NX;
 823                 do_not_nx = 0;
 824         } else if (!strncmp(str, "off", 3)) {
 825                 do_not_nx = 1;
 826                 __supported_pte_mask &= ~_PAGE_NX;
 827         }
 828         return 0;
 829 }
 830 early_param("noexec", nonx_setup);
 831
 832 int force_personality32;
 833
 834 /* noexec32=on|off
 835 Control non executable heap for 32bit processes.
 836 To control the stack too use noexec=off
 837
 838 on      PROT_READ does not imply PROT_EXEC for 32bit processes (default)
 839 off     PROT_READ implies PROT_EXEC
 840 */
 841 static int __init nonx32_setup(char *str)
 842 {
 843         if (!strcmp(str, "on"))
 844                 force_personality32 &= ~READ_IMPLIES_EXEC;
 845         else if (!strcmp(str, "off"))
 846                 force_personality32 |= READ_IMPLIES_EXEC;
 847         return 1;
 848 }
 849 __setup("noexec32=", nonx32_setup);
 850
 851 void pda_init(int cpu)
 852 {
 853         struct x8664_pda *pda = cpu_pda(cpu);
 854
 855         /* Setup up data that may be needed in __get_free_pages early */
 856         loadsegment(fs, 0);
 857         loadsegment(gs, 0);
 858         /* Memory clobbers used to order PDA accessed */
 859         mb();
 860         wrmsrl(MSR_GS_BASE, pda);
 861         mb();
 862
 863         pda->cpunumber = cpu;
 864         pda->irqcount = -1;
 865         pda->kernelstack = (unsigned long)stack_thread_info() -
 866                                  PDA_STACKOFFSET + THREAD_SIZE;
 867         pda->active_mm = &init_mm;
 868         pda->mmu_state = 0;
 869
 870         if (cpu == 0) {
 871                 /* others are initialized in smpboot.c */
 872                 pda->pcurrent = &init_task;
 873                 pda->irqstackptr = boot_cpu_stack;
 874                 pda->irqstackptr += IRQSTACKSIZE - 64;
 875         } else {
 876                 if (!pda->irqstackptr) {
 877                         pda->irqstackptr = (char *)
 878                                 __get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER);
 879                         if (!pda->irqstackptr)
 880                                 panic("cannot allocate irqstack for cpu %d",
 881                                       cpu);
 882                         pda->irqstackptr += IRQSTACKSIZE - 64;
 883                 }
 884
 885                 if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE)
 886                         pda->nodenumber = cpu_to_node(cpu);
 887         }
 888 }
 889
 890 char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ +
 891                            DEBUG_STKSZ] __page_aligned_bss;
 892
 893 extern asmlinkage void ignore_sysret(void);
 894
 895 /* May not be marked __init: used by software suspend */
 896 void syscall_init(void)
 897 {
 898         /*
 899          * LSTAR and STAR live in a bit strange symbiosis.
 900          * They both write to the same internal register. STAR allows to
 901          * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
 902          */
 903         wrmsrl(MSR_STAR,  ((u64)__USER32_CS)<<48  | ((u64)__KERNEL_CS)<<32);
 904         wrmsrl(MSR_LSTAR, system_call);
 905         wrmsrl(MSR_CSTAR, ignore_sysret);
 906
 907 #ifdef CONFIG_IA32_EMULATION
 908         syscall32_cpu_init();
 909 #endif
 910
 911         /* Flags to clear on syscall */
 912         wrmsrl(MSR_SYSCALL_MASK,
 913                X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
 914 }
 915
 916 void __cpuinit check_efer(void)
 917 {
 918         unsigned long efer;
 919
 920         rdmsrl(MSR_EFER, efer);
 921         if (!(efer & EFER_NX) || do_not_nx)
 922                 __supported_pte_mask &= ~_PAGE_NX;
 923 }
 924
 925 unsigned long kernel_eflags;
 926
 927 /*
 928  * Copies of the original ist values from the tss are only accessed during
 929  * debugging, no special alignment required.
 930  */
 931 DEFINE_PER_CPU(struct orig_ist, orig_ist);
 932
 933 #else
 934
 935 /* Make sure %fs is initialized properly in idle threads */
 936 struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
 937 {
 938         memset(regs, 0, sizeof(struct pt_regs));
 939         regs->fs = __KERNEL_PERCPU;
 940         return regs;
 941 }
 942 #endif
 943
 944 /*
 945  * cpu_init() initializes state that is per-CPU. Some data is already
 946  * initialized (naturally) in the bootstrap process, such as the GDT
 947  * and IDT. We reload them nevertheless, this function acts as a
 948  * 'CPU state barrier', nothing should get across.
 949  * A lot of state is already set up in PDA init for 64 bit
 950  */
 951 #ifdef CONFIG_X86_64
 952 void __cpuinit cpu_init(void)
 953 {
 954         int cpu = stack_smp_processor_id();
 955         struct tss_struct *t = &per_cpu(init_tss, cpu);
 956         struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
 957         unsigned long v;
 958         char *estacks = NULL;
 959         struct task_struct *me;
 960         int i;
 961
 962         /* CPU 0 is initialised in head64.c */
 963         if (cpu != 0)
 964                 pda_init(cpu);
 965         else
 966                 estacks = boot_exception_stacks;
 967
 968         me = current;
 969
 970         if (cpu_test_and_set(cpu, cpu_initialized))
 971                 panic("CPU#%d already initialized!\n", cpu);
 972
 973         printk(KERN_INFO "Initializing CPU#%d\n", cpu);
 974
 975         clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
 976
 977         /*
 978          * Initialize the per-CPU GDT with the boot GDT,
 979          * and set up the GDT descriptor:
 980          */
 981
 982         switch_to_new_gdt();
 983         load_idt((const struct desc_ptr *)&idt_descr);
 984
 985         memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
 986         syscall_init();
 987
 988         wrmsrl(MSR_FS_BASE, 0);
 989         wrmsrl(MSR_KERNEL_GS_BASE, 0);
 990         barrier();
 991
 992         check_efer();
 993         if (cpu != 0 && x2apic)
 994                 enable_x2apic();
 995
 996         /*
 997          * set up and load the per-CPU TSS
 998          */
 999         if (!orig_ist->ist[0]) {
1000                 static const unsigned int order[N_EXCEPTION_STACKS] = {
1001                   [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER,
1002                   [DEBUG_STACK - 1] = DEBUG_STACK_ORDER
1003                 };
1004                 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1005                         if (cpu) {
1006                                 estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]);
1007                                 if (!estacks)
1008                                         panic("Cannot allocate exception "
1009                                               "stack %ld %d\n", v, cpu);
1010                         }
1011                         estacks += PAGE_SIZE << order[v];
1012                         orig_ist->ist[v] = t->x86_tss.ist[v] =
1013                                         (unsigned long)estacks;
1014                 }
1015         }
1016
1017         t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1018         /*
1019          * <= is required because the CPU will access up to
1020          * 8 bits beyond the end of the IO permission bitmap.
1021          */
1022         for (i = 0; i <= IO_BITMAP_LONGS; i++)
1023                 t->io_bitmap[i] = ~0UL;
1024
1025         atomic_inc(&init_mm.mm_count);
1026         me->active_mm = &init_mm;
1027         if (me->mm)
1028                 BUG();
1029         enter_lazy_tlb(&init_mm, me);
1030
1031         load_sp0(t, &current->thread);
1032         set_tss_desc(cpu, t);
1033         load_TR_desc();
1034         load_LDT(&init_mm.context);
1035
1036 #ifdef CONFIG_KGDB
1037         /*
1038          * If the kgdb is connected no debug regs should be altered.  This
1039          * is only applicable when KGDB and a KGDB I/O module are built
1040          * into the kernel and you are using early debugging with
1041          * kgdbwait. KGDB will control the kernel HW breakpoint registers.
1042          */
1043         if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
1044                 arch_kgdb_ops.correct_hw_break();
1045         else {
1046 #endif
1047         /*
1048          * Clear all 6 debug registers:
1049          */
1050
1051         set_debugreg(0UL, 0);
1052         set_debugreg(0UL, 1);
1053         set_debugreg(0UL, 2);
1054         set_debugreg(0UL, 3);
1055         set_debugreg(0UL, 6);
1056         set_debugreg(0UL, 7);
1057 #ifdef CONFIG_KGDB
1058         /* If the kgdb is connected no debug regs should be altered. */
1059         }
1060 #endif
1061
1062         fpu_init();
1063
1064         raw_local_save_flags(kernel_eflags);
1065
1066         if (is_uv_system())
1067                 uv_cpu_init();
1068 }
1069
1070 #else
1071
1072 void __cpuinit cpu_init(void)
1073 {
1074         int cpu = smp_processor_id();
1075         struct task_struct *curr = current;
1076         struct tss_struct *t = &per_cpu(init_tss, cpu);
1077         struct thread_struct *thread = &curr->thread;
1078
1079         if (cpu_test_and_set(cpu, cpu_initialized)) {
1080                 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1081                 for (;;) local_irq_enable();
1082         }
1083
1084         printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1085
1086         if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1087                 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1088
1089         load_idt(&idt_descr);
1090         switch_to_new_gdt();
1091
1092         /*
1093          * Set up and load the per-CPU TSS and LDT
1094          */
1095         atomic_inc(&init_mm.mm_count);
1096         curr->active_mm = &init_mm;
1097         if (curr->mm)
1098                 BUG();
1099         enter_lazy_tlb(&init_mm, curr);
1100
1101         load_sp0(t, thread);
1102         set_tss_desc(cpu, t);
1103         load_TR_desc();
1104         load_LDT(&init_mm.context);
1105
1106 #ifdef CONFIG_DOUBLEFAULT
1107         /* Set up doublefault TSS pointer in the GDT */
1108         __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1109 #endif
1110
1111         /* Clear %gs. */
1112         asm volatile ("mov %0, %%gs" : : "r" (0));
1113
1114         /* Clear all 6 debug registers: */
1115         set_debugreg(0, 0);
1116         set_debugreg(0, 1);
1117         set_debugreg(0, 2);
1118         set_debugreg(0, 3);
1119         set_debugreg(0, 6);
1120         set_debugreg(0, 7);
1121
1122         /*
1123          * Force FPU initialization:
1124          */
1125         if (cpu_has_xsave)
1126                 current_thread_info()->status = TS_XSAVE;
1127         else
1128                 current_thread_info()->status = 0;
1129         clear_used_math();
1130         mxcsr_feature_mask_init();
1131
1132         /*
1133          * Boot processor to setup the FP and extended state context info.
1134          */
1135         if (!smp_processor_id())
1136                 init_thread_xstate();
1137
1138         xsave_init();
1139 }
1140
1141 #ifdef CONFIG_HOTPLUG_CPU
1142 void __cpuinit cpu_uninit(void)
1143 {
1144         int cpu = raw_smp_processor_id();
1145         cpu_clear(cpu, cpu_initialized);
1146
1147         /* lazy TLB state */
1148         per_cpu(cpu_tlbstate, cpu).state = 0;
1149         per_cpu(cpu_tlbstate, cpu).active_mm = &init_mm;
1150 }
1151 #endif
1152
1153 #endif