x86_64: fix incorrect comments
[linux-2.6/mini2440.git] / arch / x86 / include / asm / i387.h
blob63d185087d91ff21821a92f831bf86b6fbae499b
1 /*
2 * Copyright (C) 1994 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 * x86-64 work by Andi Kleen 2002
8 */
10 #ifndef _ASM_X86_I387_H
11 #define _ASM_X86_I387_H
13 #include <linux/sched.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/regset.h>
16 #include <linux/hardirq.h>
17 #include <asm/asm.h>
18 #include <asm/processor.h>
19 #include <asm/sigcontext.h>
20 #include <asm/user.h>
21 #include <asm/uaccess.h>
22 #include <asm/xsave.h>
24 extern unsigned int sig_xstate_size;
25 extern void fpu_init(void);
26 extern void mxcsr_feature_mask_init(void);
27 extern int init_fpu(struct task_struct *child);
28 extern asmlinkage void math_state_restore(void);
29 extern void init_thread_xstate(void);
30 extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
32 extern user_regset_active_fn fpregs_active, xfpregs_active;
33 extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get;
34 extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set;
36 extern struct _fpx_sw_bytes fx_sw_reserved;
37 #ifdef CONFIG_IA32_EMULATION
38 extern unsigned int sig_xstate_ia32_size;
39 extern struct _fpx_sw_bytes fx_sw_reserved_ia32;
40 struct _fpstate_ia32;
41 struct _xstate_ia32;
42 extern int save_i387_xstate_ia32(void __user *buf);
43 extern int restore_i387_xstate_ia32(void __user *buf);
44 #endif
46 #define X87_FSW_ES (1 << 7) /* Exception Summary */
48 #ifdef CONFIG_X86_64
50 /* Ignore delayed exceptions from user space */
51 static inline void tolerant_fwait(void)
53 asm volatile("1: fwait\n"
54 "2:\n"
55 _ASM_EXTABLE(1b, 2b));
58 static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
60 int err;
62 asm volatile("1: rex64/fxrstor (%[fx])\n\t"
63 "2:\n"
64 ".section .fixup,\"ax\"\n"
65 "3: movl $-1,%[err]\n"
66 " jmp 2b\n"
67 ".previous\n"
68 _ASM_EXTABLE(1b, 3b)
69 : [err] "=r" (err)
70 #if 0 /* See comment in fxsave() below. */
71 : [fx] "r" (fx), "m" (*fx), "0" (0));
72 #else
73 : [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
74 #endif
75 return err;
78 /* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
79 is pending. Clear the x87 state here by setting it to fixed
80 values. The kernel data segment can be sometimes 0 and sometimes
81 new user value. Both should be ok.
82 Use the PDA as safe address because it should be already in L1. */
83 static inline void clear_fpu_state(struct task_struct *tsk)
85 struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
86 struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
89 * xsave header may indicate the init state of the FP.
91 if ((task_thread_info(tsk)->status & TS_XSAVE) &&
92 !(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
93 return;
95 if (unlikely(fx->swd & X87_FSW_ES))
96 asm volatile("fnclex");
97 alternative_input(ASM_NOP8 ASM_NOP2,
98 " emms\n" /* clear stack tags */
99 " fildl %%gs:0", /* load to clear state */
100 X86_FEATURE_FXSAVE_LEAK);
103 static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
105 int err;
107 asm volatile("1: rex64/fxsave (%[fx])\n\t"
108 "2:\n"
109 ".section .fixup,\"ax\"\n"
110 "3: movl $-1,%[err]\n"
111 " jmp 2b\n"
112 ".previous\n"
113 _ASM_EXTABLE(1b, 3b)
114 : [err] "=r" (err), "=m" (*fx)
115 #if 0 /* See comment in fxsave() below. */
116 : [fx] "r" (fx), "0" (0));
117 #else
118 : [fx] "cdaSDb" (fx), "0" (0));
119 #endif
120 if (unlikely(err) &&
121 __clear_user(fx, sizeof(struct i387_fxsave_struct)))
122 err = -EFAULT;
123 /* No need to clear here because the caller clears USED_MATH */
124 return err;
127 static inline void fxsave(struct task_struct *tsk)
129 /* Using "rex64; fxsave %0" is broken because, if the memory operand
130 uses any extended registers for addressing, a second REX prefix
131 will be generated (to the assembler, rex64 followed by semicolon
132 is a separate instruction), and hence the 64-bitness is lost. */
133 #if 0
134 /* Using "fxsaveq %0" would be the ideal choice, but is only supported
135 starting with gas 2.16. */
136 __asm__ __volatile__("fxsaveq %0"
137 : "=m" (tsk->thread.xstate->fxsave));
138 #elif 0
139 /* Using, as a workaround, the properly prefixed form below isn't
140 accepted by any binutils version so far released, complaining that
141 the same type of prefix is used twice if an extended register is
142 needed for addressing (fix submitted to mainline 2005-11-21). */
143 __asm__ __volatile__("rex64/fxsave %0"
144 : "=m" (tsk->thread.xstate->fxsave));
145 #else
146 /* This, however, we can work around by forcing the compiler to select
147 an addressing mode that doesn't require extended registers. */
148 __asm__ __volatile__("rex64/fxsave (%1)"
149 : "=m" (tsk->thread.xstate->fxsave)
150 : "cdaSDb" (&tsk->thread.xstate->fxsave));
151 #endif
154 static inline void __save_init_fpu(struct task_struct *tsk)
156 if (task_thread_info(tsk)->status & TS_XSAVE)
157 xsave(tsk);
158 else
159 fxsave(tsk);
161 clear_fpu_state(tsk);
162 task_thread_info(tsk)->status &= ~TS_USEDFPU;
165 #else /* CONFIG_X86_32 */
167 #ifdef CONFIG_MATH_EMULATION
168 extern void finit_task(struct task_struct *tsk);
169 #else
170 static inline void finit_task(struct task_struct *tsk)
173 #endif
175 static inline void tolerant_fwait(void)
177 asm volatile("fnclex ; fwait");
180 /* perform fxrstor iff the processor has extended states, otherwise frstor */
181 static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
184 * The "nop" is needed to make the instructions the same
185 * length.
187 alternative_input(
188 "nop ; frstor %1",
189 "fxrstor %1",
190 X86_FEATURE_FXSR,
191 "m" (*fx));
193 return 0;
196 /* We need a safe address that is cheap to find and that is already
197 in L1 during context switch. The best choices are unfortunately
198 different for UP and SMP */
199 #ifdef CONFIG_SMP
200 #define safe_address (__per_cpu_offset[0])
201 #else
202 #define safe_address (kstat_cpu(0).cpustat.user)
203 #endif
206 * These must be called with preempt disabled
208 static inline void __save_init_fpu(struct task_struct *tsk)
210 if (task_thread_info(tsk)->status & TS_XSAVE) {
211 struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
212 struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
214 xsave(tsk);
217 * xsave header may indicate the init state of the FP.
219 if (!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
220 goto end;
222 if (unlikely(fx->swd & X87_FSW_ES))
223 asm volatile("fnclex");
226 * we can do a simple return here or be paranoid :)
228 goto clear_state;
231 /* Use more nops than strictly needed in case the compiler
232 varies code */
233 alternative_input(
234 "fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
235 "fxsave %[fx]\n"
236 "bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
237 X86_FEATURE_FXSR,
238 [fx] "m" (tsk->thread.xstate->fxsave),
239 [fsw] "m" (tsk->thread.xstate->fxsave.swd) : "memory");
240 clear_state:
241 /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
242 is pending. Clear the x87 state here by setting it to fixed
243 values. safe_address is a random variable that should be in L1 */
244 alternative_input(
245 GENERIC_NOP8 GENERIC_NOP2,
246 "emms\n\t" /* clear stack tags */
247 "fildl %[addr]", /* set F?P to defined value */
248 X86_FEATURE_FXSAVE_LEAK,
249 [addr] "m" (safe_address));
250 end:
251 task_thread_info(tsk)->status &= ~TS_USEDFPU;
254 #endif /* CONFIG_X86_64 */
256 static inline int restore_fpu_checking(struct task_struct *tsk)
258 if (task_thread_info(tsk)->status & TS_XSAVE)
259 return xrstor_checking(&tsk->thread.xstate->xsave);
260 else
261 return fxrstor_checking(&tsk->thread.xstate->fxsave);
265 * Signal frame handlers...
267 extern int save_i387_xstate(void __user *buf);
268 extern int restore_i387_xstate(void __user *buf);
270 static inline void __unlazy_fpu(struct task_struct *tsk)
272 if (task_thread_info(tsk)->status & TS_USEDFPU) {
273 __save_init_fpu(tsk);
274 stts();
275 } else
276 tsk->fpu_counter = 0;
279 static inline void __clear_fpu(struct task_struct *tsk)
281 if (task_thread_info(tsk)->status & TS_USEDFPU) {
282 tolerant_fwait();
283 task_thread_info(tsk)->status &= ~TS_USEDFPU;
284 stts();
288 static inline void kernel_fpu_begin(void)
290 struct thread_info *me = current_thread_info();
291 preempt_disable();
292 if (me->status & TS_USEDFPU)
293 __save_init_fpu(me->task);
294 else
295 clts();
298 static inline void kernel_fpu_end(void)
300 stts();
301 preempt_enable();
305 * Some instructions like VIA's padlock instructions generate a spurious
306 * DNA fault but don't modify SSE registers. And these instructions
307 * get used from interrupt context aswell. To prevent these kernel instructions
308 * in interrupt context interact wrongly with other user/kernel fpu usage, we
309 * should use them only in the context of irq_ts_save/restore()
311 static inline int irq_ts_save(void)
314 * If we are in process context, we are ok to take a spurious DNA fault.
315 * Otherwise, doing clts() in process context require pre-emption to
316 * be disabled or some heavy lifting like kernel_fpu_begin()
318 if (!in_interrupt())
319 return 0;
321 if (read_cr0() & X86_CR0_TS) {
322 clts();
323 return 1;
326 return 0;
329 static inline void irq_ts_restore(int TS_state)
331 if (TS_state)
332 stts();
335 #ifdef CONFIG_X86_64
337 static inline void save_init_fpu(struct task_struct *tsk)
339 __save_init_fpu(tsk);
340 stts();
343 #define unlazy_fpu __unlazy_fpu
344 #define clear_fpu __clear_fpu
346 #else /* CONFIG_X86_32 */
349 * These disable preemption on their own and are safe
351 static inline void save_init_fpu(struct task_struct *tsk)
353 preempt_disable();
354 __save_init_fpu(tsk);
355 stts();
356 preempt_enable();
359 static inline void unlazy_fpu(struct task_struct *tsk)
361 preempt_disable();
362 __unlazy_fpu(tsk);
363 preempt_enable();
366 static inline void clear_fpu(struct task_struct *tsk)
368 preempt_disable();
369 __clear_fpu(tsk);
370 preempt_enable();
373 #endif /* CONFIG_X86_64 */
376 * i387 state interaction
378 static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
380 if (cpu_has_fxsr) {
381 return tsk->thread.xstate->fxsave.cwd;
382 } else {
383 return (unsigned short)tsk->thread.xstate->fsave.cwd;
387 static inline unsigned short get_fpu_swd(struct task_struct *tsk)
389 if (cpu_has_fxsr) {
390 return tsk->thread.xstate->fxsave.swd;
391 } else {
392 return (unsigned short)tsk->thread.xstate->fsave.swd;
396 static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
398 if (cpu_has_xmm) {
399 return tsk->thread.xstate->fxsave.mxcsr;
400 } else {
401 return MXCSR_DEFAULT;
405 #endif /* _ASM_X86_I387_H */