arch/blackfin/kernel/reboot.c

   1 /*
   2  * arch/blackfin/kernel/reboot.c - handle shutdown/reboot
   3  *
   4  * Copyright 2004-2007 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <linux/interrupt.h>
  10 #include <asm/bfin-global.h>
  11 #include <asm/reboot.h>
  12 #include <asm/system.h>
  13 #include <asm/bfrom.h>
  14
  15 /* A system soft reset makes external memory unusable so force
  16  * this function into L1.  We use the compiler ssync here rather
  17  * than SSYNC() because it's safe (no interrupts and such) and
  18  * we save some L1.  We do not need to force sanity in the SYSCR
  19  * register as the BMODE selection bit is cleared by the soft
  20  * reset while the Core B bit (on dual core parts) is cleared by
  21  * the core reset.
  22  */
  23 __attribute__((l1_text))
  24 static void _bfin_reset(void)
  25 {
  26         /* Wait for completion of "system" events such as cache line
  27          * line fills so that we avoid infinite stalls later on as
  28          * much as possible.  This code is in L1, so it won't trigger
  29          * any such event after this point in time.
  30          */
  31         __builtin_bfin_ssync();
  32
  33         while (1) {
  34                 /* Initiate System software reset. */
  35                 bfin_write_SWRST(0x7);
  36
  37                 /* Due to the way reset is handled in the hardware, we need
  38                  * to delay for 10 SCLKS.  The only reliable way to do this is
  39                  * to calculate the CCLK/SCLK ratio and multiply 10.  For now,
  40                  * we'll assume worse case which is a 1:15 ratio.
  41                  */
  42                 asm(
  43                         "LSETUP (1f, 1f) LC0 = %0\n"
  44                         "1: nop;"
  45                         :
  46                         : "a" (15 * 10)
  47                         : "LC0", "LB0", "LT0"
  48                 );
  49
  50                 /* Clear System software reset */
  51                 bfin_write_SWRST(0);
  52
  53                 /* Wait for the SWRST write to complete.  Cannot rely on SSYNC
  54                  * though as the System state is all reset now.
  55                  */
  56                 asm(
  57                         "LSETUP (1f, 1f) LC1 = %0\n"
  58                         "1: nop;"
  59                         :
  60                         : "a" (15 * 1)
  61                         : "LC1", "LB1", "LT1"
  62                 );
  63
  64                 /* Issue core reset */
  65                 asm("raise 1");
  66         }
  67 }
  68
  69 static void bfin_reset(void)
  70 {
  71         if (ANOMALY_05000353 || ANOMALY_05000386)
  72                 _bfin_reset();
  73         else
  74                 /* the bootrom checks to see how it was reset and will
  75                  * automatically perform a software reset for us when
  76                  * it starts executing boot
  77                  */
  78                 asm("raise 1;");
  79 }
  80
  81 __attribute__((weak))
  82 void native_machine_restart(char *cmd)
  83 {
  84 }
  85
  86 void machine_restart(char *cmd)
  87 {
  88         native_machine_restart(cmd);
  89         local_irq_disable();
  90         if (smp_processor_id())
  91                 smp_call_function((void *)bfin_reset, 0, 1);
  92         else
  93                 bfin_reset();
  94 }
  95
  96 __attribute__((weak))
  97 void native_machine_halt(void)
  98 {
  99         idle_with_irq_disabled();
 100 }
 101
 102 void machine_halt(void)
 103 {
 104         native_machine_halt();
 105 }
 106
 107 __attribute__((weak))
 108 void native_machine_power_off(void)
 109 {
 110         idle_with_irq_disabled();
 111 }
 112
 113 void machine_power_off(void)
 114 {
 115         native_machine_power_off();
 116 }