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VM, x86, PAT: Change is_linear_pfn_mapping to not use vm_pgoff
[linux-2.6/mini2440.git] / arch / x86 / kvm / x86_emulate.c
blobd174db7a3370d9e80f6c1b93f2960a40b5b1cc43
1 /******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 *
13 * Avi Kivity <avi@qumranet.com>
14 * Yaniv Kamay <yaniv@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
20 */
21
22 #ifndef __KERNEL__
23 #include <stdio.h>
24 #include <stdint.h>
25 #include <public/xen.h>
26 #define DPRINTF(_f, _a ...) printf(_f , ## _a)
27 #else
28 #include <linux/kvm_host.h>
29 #include "kvm_cache_regs.h"
30 #define DPRINTF(x...) do {} while (0)
31 #endif
32 #include <linux/module.h>
33 #include <asm/kvm_x86_emulate.h>
34
35 /*
36 * Opcode effective-address decode tables.
37 * Note that we only emulate instructions that have at least one memory
38 * operand (excluding implicit stack references). We assume that stack
39 * references and instruction fetches will never occur in special memory
40 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
41 * not be handled.
42 */
43
44 /* Operand sizes: 8-bit operands or specified/overridden size. */
45 #define ByteOp (1<<0) /* 8-bit operands. */
46 /* Destination operand type. */
47 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
48 #define DstReg (2<<1) /* Register operand. */
49 #define DstMem (3<<1) /* Memory operand. */
50 #define DstAcc (4<<1) /* Destination Accumulator */
51 #define DstMask (7<<1)
52 /* Source operand type. */
53 #define SrcNone (0<<4) /* No source operand. */
54 #define SrcImplicit (0<<4) /* Source operand is implicit in the opcode. */
55 #define SrcReg (1<<4) /* Register operand. */
56 #define SrcMem (2<<4) /* Memory operand. */
57 #define SrcMem16 (3<<4) /* Memory operand (16-bit). */
58 #define SrcMem32 (4<<4) /* Memory operand (32-bit). */
59 #define SrcImm (5<<4) /* Immediate operand. */
60 #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
61 #define SrcOne (7<<4) /* Implied '1' */
62 #define SrcMask (7<<4)
63 /* Generic ModRM decode. */
64 #define ModRM (1<<7)
65 /* Destination is only written; never read. */
66 #define Mov (1<<8)
67 #define BitOp (1<<9)
68 #define MemAbs (1<<10) /* Memory operand is absolute displacement */
69 #define String (1<<12) /* String instruction (rep capable) */
70 #define Stack (1<<13) /* Stack instruction (push/pop) */
71 #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
72 #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
73 #define GroupMask 0xff /* Group number stored in bits 0:7 */
74 /* Source 2 operand type */
75 #define Src2None (0<<29)
76 #define Src2CL (1<<29)
77 #define Src2ImmByte (2<<29)
78 #define Src2One (3<<29)
79 #define Src2Mask (7<<29)
80
81 enum {
82 Group1_80, Group1_81, Group1_82, Group1_83,
83 Group1A, Group3_Byte, Group3, Group4, Group5, Group7,
84 };
85
86 static u32 opcode_table[256] = {
87 /* 0x00 - 0x07 */
88 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
89 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
90 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm, 0, 0,
91 /* 0x08 - 0x0F */
92 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
93 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
94 0, 0, 0, 0,
95 /* 0x10 - 0x17 */
96 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
97 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
98 0, 0, 0, 0,
99 /* 0x18 - 0x1F */
100 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
101 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
102 0, 0, 0, 0,
103 /* 0x20 - 0x27 */
104 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
105 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
106 DstAcc | SrcImmByte, DstAcc | SrcImm, 0, 0,
107 /* 0x28 - 0x2F */
108 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
109 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
110 0, 0, 0, 0,
111 /* 0x30 - 0x37 */
112 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
113 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
114 0, 0, 0, 0,
115 /* 0x38 - 0x3F */
116 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
117 ByteOp | DstReg | SrcMem | ModRM, DstReg | SrcMem | ModRM,
118 ByteOp | DstAcc | SrcImm, DstAcc | SrcImm,
119 0, 0,
120 /* 0x40 - 0x47 */
121 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
122 /* 0x48 - 0x4F */
123 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
124 /* 0x50 - 0x57 */
125 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
126 SrcReg | Stack, SrcReg | Stack, SrcReg | Stack, SrcReg | Stack,
127 /* 0x58 - 0x5F */
128 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
129 DstReg | Stack, DstReg | Stack, DstReg | Stack, DstReg | Stack,
130 /* 0x60 - 0x67 */
131 0, 0, 0, DstReg | SrcMem32 | ModRM | Mov /* movsxd (x86/64) */ ,
132 0, 0, 0, 0,
133 /* 0x68 - 0x6F */
134 SrcImm | Mov | Stack, 0, SrcImmByte | Mov | Stack, 0,
135 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* insb, insw/insd */
136 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps, /* outsb, outsw/outsd */
137 /* 0x70 - 0x77 */
138 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
139 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
140 /* 0x78 - 0x7F */
141 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
142 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
143 /* 0x80 - 0x87 */
144 Group | Group1_80, Group | Group1_81,
145 Group | Group1_82, Group | Group1_83,
146 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
147 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM,
148 /* 0x88 - 0x8F */
149 ByteOp | DstMem | SrcReg | ModRM | Mov, DstMem | SrcReg | ModRM | Mov,
150 ByteOp | DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
151 DstMem | SrcReg | ModRM | Mov, ModRM | DstReg,
152 DstReg | SrcMem | ModRM | Mov, Group | Group1A,
153 /* 0x90 - 0x97 */
154 DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg, DstReg,
155 /* 0x98 - 0x9F */
156 0, 0, 0, 0, ImplicitOps | Stack, ImplicitOps | Stack, 0, 0,
157 /* 0xA0 - 0xA7 */
158 ByteOp | DstReg | SrcMem | Mov | MemAbs, DstReg | SrcMem | Mov | MemAbs,
159 ByteOp | DstMem | SrcReg | Mov | MemAbs, DstMem | SrcReg | Mov | MemAbs,
160 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
161 ByteOp | ImplicitOps | String, ImplicitOps | String,
162 /* 0xA8 - 0xAF */
163 0, 0, ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
164 ByteOp | ImplicitOps | Mov | String, ImplicitOps | Mov | String,
165 ByteOp | ImplicitOps | String, ImplicitOps | String,
166 /* 0xB0 - 0xB7 */
167 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
168 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
169 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
170 ByteOp | DstReg | SrcImm | Mov, ByteOp | DstReg | SrcImm | Mov,
171 /* 0xB8 - 0xBF */
172 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
173 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
174 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
175 DstReg | SrcImm | Mov, DstReg | SrcImm | Mov,
176 /* 0xC0 - 0xC7 */
177 ByteOp | DstMem | SrcImm | ModRM, DstMem | SrcImmByte | ModRM,
178 0, ImplicitOps | Stack, 0, 0,
179 ByteOp | DstMem | SrcImm | ModRM | Mov, DstMem | SrcImm | ModRM | Mov,
180 /* 0xC8 - 0xCF */
181 0, 0, 0, 0, 0, 0, 0, 0,
182 /* 0xD0 - 0xD7 */
183 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
184 ByteOp | DstMem | SrcImplicit | ModRM, DstMem | SrcImplicit | ModRM,
185 0, 0, 0, 0,
186 /* 0xD8 - 0xDF */
187 0, 0, 0, 0, 0, 0, 0, 0,
188 /* 0xE0 - 0xE7 */
189 0, 0, 0, 0,
190 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
191 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
192 /* 0xE8 - 0xEF */
193 ImplicitOps | Stack, SrcImm | ImplicitOps,
194 ImplicitOps, SrcImmByte | ImplicitOps,
195 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
196 SrcNone | ByteOp | ImplicitOps, SrcNone | ImplicitOps,
197 /* 0xF0 - 0xF7 */
198 0, 0, 0, 0,
199 ImplicitOps, ImplicitOps, Group | Group3_Byte, Group | Group3,
200 /* 0xF8 - 0xFF */
201 ImplicitOps, 0, ImplicitOps, ImplicitOps,
202 ImplicitOps, ImplicitOps, Group | Group4, Group | Group5,
203 };
204
205 static u32 twobyte_table[256] = {
206 /* 0x00 - 0x0F */
207 0, Group | GroupDual | Group7, 0, 0, 0, 0, ImplicitOps, 0,
208 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps | ModRM, 0, 0,
209 /* 0x10 - 0x1F */
210 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps | ModRM, 0, 0, 0, 0, 0, 0, 0,
211 /* 0x20 - 0x2F */
212 ModRM | ImplicitOps, ModRM, ModRM | ImplicitOps, ModRM, 0, 0, 0, 0,
213 0, 0, 0, 0, 0, 0, 0, 0,
214 /* 0x30 - 0x3F */
215 ImplicitOps, 0, ImplicitOps, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
216 /* 0x40 - 0x47 */
217 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
218 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
219 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
220 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
221 /* 0x48 - 0x4F */
222 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
223 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
224 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
225 DstReg | SrcMem | ModRM | Mov, DstReg | SrcMem | ModRM | Mov,
226 /* 0x50 - 0x5F */
227 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
228 /* 0x60 - 0x6F */
229 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
230 /* 0x70 - 0x7F */
231 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
232 /* 0x80 - 0x8F */
233 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
234 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
235 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
236 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
237 /* 0x90 - 0x9F */
238 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
239 /* 0xA0 - 0xA7 */
240 0, 0, 0, DstMem | SrcReg | ModRM | BitOp,
241 DstMem | SrcReg | Src2ImmByte | ModRM,
242 DstMem | SrcReg | Src2CL | ModRM, 0, 0,
243 /* 0xA8 - 0xAF */
244 0, 0, 0, DstMem | SrcReg | ModRM | BitOp,
245 DstMem | SrcReg | Src2ImmByte | ModRM,
246 DstMem | SrcReg | Src2CL | ModRM,
247 ModRM, 0,
248 /* 0xB0 - 0xB7 */
249 ByteOp | DstMem | SrcReg | ModRM, DstMem | SrcReg | ModRM, 0,
250 DstMem | SrcReg | ModRM | BitOp,
251 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
252 DstReg | SrcMem16 | ModRM | Mov,
253 /* 0xB8 - 0xBF */
254 0, 0, DstMem | SrcImmByte | ModRM, DstMem | SrcReg | ModRM | BitOp,
255 0, 0, ByteOp | DstReg | SrcMem | ModRM | Mov,
256 DstReg | SrcMem16 | ModRM | Mov,
257 /* 0xC0 - 0xCF */
258 0, 0, 0, DstMem | SrcReg | ModRM | Mov, 0, 0, 0, ImplicitOps | ModRM,
259 0, 0, 0, 0, 0, 0, 0, 0,
260 /* 0xD0 - 0xDF */
261 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
262 /* 0xE0 - 0xEF */
263 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
264 /* 0xF0 - 0xFF */
265 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
266 };
267
268 static u32 group_table[] = {
269 [Group1_80*8] =
270 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
271 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
272 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
273 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
274 [Group1_81*8] =
275 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
276 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
277 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
278 DstMem | SrcImm | ModRM, DstMem | SrcImm | ModRM,
279 [Group1_82*8] =
280 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
281 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
282 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
283 ByteOp | DstMem | SrcImm | ModRM, ByteOp | DstMem | SrcImm | ModRM,
284 [Group1_83*8] =
285 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
286 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
287 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
288 DstMem | SrcImmByte | ModRM, DstMem | SrcImmByte | ModRM,
289 [Group1A*8] =
290 DstMem | SrcNone | ModRM | Mov | Stack, 0, 0, 0, 0, 0, 0, 0,
291 [Group3_Byte*8] =
292 ByteOp | SrcImm | DstMem | ModRM, 0,
293 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
294 0, 0, 0, 0,
295 [Group3*8] =
296 DstMem | SrcImm | ModRM, 0,
297 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
298 0, 0, 0, 0,
299 [Group4*8] =
300 ByteOp | DstMem | SrcNone | ModRM, ByteOp | DstMem | SrcNone | ModRM,
301 0, 0, 0, 0, 0, 0,
302 [Group5*8] =
303 DstMem | SrcNone | ModRM, DstMem | SrcNone | ModRM,
304 SrcMem | ModRM | Stack, 0,
305 SrcMem | ModRM | Stack, 0, SrcMem | ModRM | Stack, 0,
306 [Group7*8] =
307 0, 0, ModRM | SrcMem, ModRM | SrcMem,
308 SrcNone | ModRM | DstMem | Mov, 0,
309 SrcMem16 | ModRM | Mov, SrcMem | ModRM | ByteOp,
310 };
311
312 static u32 group2_table[] = {
313 [Group7*8] =
314 SrcNone | ModRM, 0, 0, SrcNone | ModRM,
315 SrcNone | ModRM | DstMem | Mov, 0,
316 SrcMem16 | ModRM | Mov, 0,
317 };
318
319 /* EFLAGS bit definitions. */
320 #define EFLG_OF (1<<11)
321 #define EFLG_DF (1<<10)
322 #define EFLG_SF (1<<7)
323 #define EFLG_ZF (1<<6)
324 #define EFLG_AF (1<<4)
325 #define EFLG_PF (1<<2)
326 #define EFLG_CF (1<<0)
327
328 /*
329 * Instruction emulation:
330 * Most instructions are emulated directly via a fragment of inline assembly
331 * code. This allows us to save/restore EFLAGS and thus very easily pick up
332 * any modified flags.
333 */
334
335 #if defined(CONFIG_X86_64)
336 #define _LO32 "k" /* force 32-bit operand */
337 #define _STK "%%rsp" /* stack pointer */
338 #elif defined(__i386__)
339 #define _LO32 "" /* force 32-bit operand */
340 #define _STK "%%esp" /* stack pointer */
341 #endif
342
343 /*
344 * These EFLAGS bits are restored from saved value during emulation, and
345 * any changes are written back to the saved value after emulation.
346 */
347 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
348
349 /* Before executing instruction: restore necessary bits in EFLAGS. */
350 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
351 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
352 "movl %"_sav",%"_LO32 _tmp"; " \
353 "push %"_tmp"; " \
354 "push %"_tmp"; " \
355 "movl %"_msk",%"_LO32 _tmp"; " \
356 "andl %"_LO32 _tmp",("_STK"); " \
357 "pushf; " \
358 "notl %"_LO32 _tmp"; " \
359 "andl %"_LO32 _tmp",("_STK"); " \
360 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
361 "pop %"_tmp"; " \
362 "orl %"_LO32 _tmp",("_STK"); " \
363 "popf; " \
364 "pop %"_sav"; "
365
366 /* After executing instruction: write-back necessary bits in EFLAGS. */
367 #define _POST_EFLAGS(_sav, _msk, _tmp) \
368 /* _sav |= EFLAGS & _msk; */ \
369 "pushf; " \
370 "pop %"_tmp"; " \
371 "andl %"_msk",%"_LO32 _tmp"; " \
372 "orl %"_LO32 _tmp",%"_sav"; "
373
374 #ifdef CONFIG_X86_64
375 #define ON64(x) x
376 #else
377 #define ON64(x)
378 #endif
379
380 #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix) \
381 do { \
382 __asm__ __volatile__ ( \
383 _PRE_EFLAGS("0", "4", "2") \
384 _op _suffix " %"_x"3,%1; " \
385 _POST_EFLAGS("0", "4", "2") \
386 : "=m" (_eflags), "=m" ((_dst).val), \
387 "=&r" (_tmp) \
388 : _y ((_src).val), "i" (EFLAGS_MASK)); \
389 } while (0)
390
391
392 /* Raw emulation: instruction has two explicit operands. */
393 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
394 do { \
395 unsigned long _tmp; \
396 \
397 switch ((_dst).bytes) { \
398 case 2: \
399 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w"); \
400 break; \
401 case 4: \
402 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l"); \
403 break; \
404 case 8: \
405 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q")); \
406 break; \
407 } \
408 } while (0)
409
410 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
411 do { \
412 unsigned long _tmp; \
413 switch ((_dst).bytes) { \
414 case 1: \
415 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b"); \
416 break; \
417 default: \
418 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
419 _wx, _wy, _lx, _ly, _qx, _qy); \
420 break; \
421 } \
422 } while (0)
423
424 /* Source operand is byte-sized and may be restricted to just %cl. */
425 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
426 __emulate_2op(_op, _src, _dst, _eflags, \
427 "b", "c", "b", "c", "b", "c", "b", "c")
428
429 /* Source operand is byte, word, long or quad sized. */
430 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
431 __emulate_2op(_op, _src, _dst, _eflags, \
432 "b", "q", "w", "r", _LO32, "r", "", "r")
433
434 /* Source operand is word, long or quad sized. */
435 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
436 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
437 "w", "r", _LO32, "r", "", "r")
438
439 /* Instruction has three operands and one operand is stored in ECX register */
440 #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
441 do { \
442 unsigned long _tmp; \
443 _type _clv = (_cl).val; \
444 _type _srcv = (_src).val; \
445 _type _dstv = (_dst).val; \
446 \
447 __asm__ __volatile__ ( \
448 _PRE_EFLAGS("0", "5", "2") \
449 _op _suffix " %4,%1 \n" \
450 _POST_EFLAGS("0", "5", "2") \
451 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
452 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
453 ); \
454 \
455 (_cl).val = (unsigned long) _clv; \
456 (_src).val = (unsigned long) _srcv; \
457 (_dst).val = (unsigned long) _dstv; \
458 } while (0)
459
460 #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
461 do { \
462 switch ((_dst).bytes) { \
463 case 2: \
464 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
465 "w", unsigned short); \
466 break; \
467 case 4: \
468 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
469 "l", unsigned int); \
470 break; \
471 case 8: \
472 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
473 "q", unsigned long)); \
474 break; \
475 } \
476 } while (0)
477
478 #define __emulate_1op(_op, _dst, _eflags, _suffix) \
479 do { \
480 unsigned long _tmp; \
481 \
482 __asm__ __volatile__ ( \
483 _PRE_EFLAGS("0", "3", "2") \
484 _op _suffix " %1; " \
485 _POST_EFLAGS("0", "3", "2") \
486 : "=m" (_eflags), "+m" ((_dst).val), \
487 "=&r" (_tmp) \
488 : "i" (EFLAGS_MASK)); \
489 } while (0)
490
491 /* Instruction has only one explicit operand (no source operand). */
492 #define emulate_1op(_op, _dst, _eflags) \
493 do { \
494 switch ((_dst).bytes) { \
495 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
496 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
497 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
498 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
499 } \
500 } while (0)
501
502 /* Fetch next part of the instruction being emulated. */
503 #define insn_fetch(_type, _size, _eip) \
504 ({ unsigned long _x; \
505 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
506 if (rc != 0) \
507 goto done; \
508 (_eip) += (_size); \
509 (_type)_x; \
510 })
511
512 static inline unsigned long ad_mask(struct decode_cache *c)
513 {
514 return (1UL << (c->ad_bytes << 3)) - 1;
515 }
516
517 /* Access/update address held in a register, based on addressing mode. */
518 static inline unsigned long
519 address_mask(struct decode_cache *c, unsigned long reg)
520 {
521 if (c->ad_bytes == sizeof(unsigned long))
522 return reg;
523 else
524 return reg & ad_mask(c);
525 }
526
527 static inline unsigned long
528 register_address(struct decode_cache *c, unsigned long base, unsigned long reg)
529 {
530 return base + address_mask(c, reg);
531 }
532
533 static inline void
534 register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
535 {
536 if (c->ad_bytes == sizeof(unsigned long))
537 *reg += inc;
538 else
539 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
540 }
541
542 static inline void jmp_rel(struct decode_cache *c, int rel)
543 {
544 register_address_increment(c, &c->eip, rel);
545 }
546
547 static void set_seg_override(struct decode_cache *c, int seg)
548 {
549 c->has_seg_override = true;
550 c->seg_override = seg;
551 }
552
553 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
554 {
555 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
556 return 0;
557
558 return kvm_x86_ops->get_segment_base(ctxt->vcpu, seg);
559 }
560
561 static unsigned long seg_override_base(struct x86_emulate_ctxt *ctxt,
562 struct decode_cache *c)
563 {
564 if (!c->has_seg_override)
565 return 0;
566
567 return seg_base(ctxt, c->seg_override);
568 }
569
570 static unsigned long es_base(struct x86_emulate_ctxt *ctxt)
571 {
572 return seg_base(ctxt, VCPU_SREG_ES);
573 }
574
575 static unsigned long ss_base(struct x86_emulate_ctxt *ctxt)
576 {
577 return seg_base(ctxt, VCPU_SREG_SS);
578 }
579
580 static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
581 struct x86_emulate_ops *ops,
582 unsigned long linear, u8 *dest)
583 {
584 struct fetch_cache *fc = &ctxt->decode.fetch;
585 int rc;
586 int size;
587
588 if (linear < fc->start || linear >= fc->end) {
589 size = min(15UL, PAGE_SIZE - offset_in_page(linear));
590 rc = ops->read_std(linear, fc->data, size, ctxt->vcpu);
591 if (rc)
592 return rc;
593 fc->start = linear;
594 fc->end = linear + size;
595 }
596 *dest = fc->data[linear - fc->start];
597 return 0;
598 }
599
600 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
601 struct x86_emulate_ops *ops,
602 unsigned long eip, void *dest, unsigned size)
603 {
604 int rc = 0;
605
606 eip += ctxt->cs_base;
607 while (size--) {
608 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
609 if (rc)
610 return rc;
611 }
612 return 0;
613 }
614
615 /*
616 * Given the 'reg' portion of a ModRM byte, and a register block, return a
617 * pointer into the block that addresses the relevant register.
618 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
619 */
620 static void *decode_register(u8 modrm_reg, unsigned long *regs,
621 int highbyte_regs)
622 {
623 void *p;
624
625 p = &regs[modrm_reg];
626 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
627 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
628 return p;
629 }
630
631 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
632 struct x86_emulate_ops *ops,
633 void *ptr,
634 u16 *size, unsigned long *address, int op_bytes)
635 {
636 int rc;
637
638 if (op_bytes == 2)
639 op_bytes = 3;
640 *address = 0;
641 rc = ops->read_std((unsigned long)ptr, (unsigned long *)size, 2,
642 ctxt->vcpu);
643 if (rc)
644 return rc;
645 rc = ops->read_std((unsigned long)ptr + 2, address, op_bytes,
646 ctxt->vcpu);
647 return rc;
648 }
649
650 static int test_cc(unsigned int condition, unsigned int flags)
651 {
652 int rc = 0;
653
654 switch ((condition & 15) >> 1) {
655 case 0: /* o */
656 rc |= (flags & EFLG_OF);
657 break;
658 case 1: /* b/c/nae */
659 rc |= (flags & EFLG_CF);
660 break;
661 case 2: /* z/e */
662 rc |= (flags & EFLG_ZF);
663 break;
664 case 3: /* be/na */
665 rc |= (flags & (EFLG_CF|EFLG_ZF));
666 break;
667 case 4: /* s */
668 rc |= (flags & EFLG_SF);
669 break;
670 case 5: /* p/pe */
671 rc |= (flags & EFLG_PF);
672 break;
673 case 7: /* le/ng */
674 rc |= (flags & EFLG_ZF);
675 /* fall through */
676 case 6: /* l/nge */
677 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
678 break;
679 }
680
681 /* Odd condition identifiers (lsb == 1) have inverted sense. */
682 return (!!rc ^ (condition & 1));
683 }
684
685 static void decode_register_operand(struct operand *op,
686 struct decode_cache *c,
687 int inhibit_bytereg)
688 {
689 unsigned reg = c->modrm_reg;
690 int highbyte_regs = c->rex_prefix == 0;
691
692 if (!(c->d & ModRM))
693 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
694 op->type = OP_REG;
695 if ((c->d & ByteOp) && !inhibit_bytereg) {
696 op->ptr = decode_register(reg, c->regs, highbyte_regs);
697 op->val = *(u8 *)op->ptr;
698 op->bytes = 1;
699 } else {
700 op->ptr = decode_register(reg, c->regs, 0);
701 op->bytes = c->op_bytes;
702 switch (op->bytes) {
703 case 2:
704 op->val = *(u16 *)op->ptr;
705 break;
706 case 4:
707 op->val = *(u32 *)op->ptr;
708 break;
709 case 8:
710 op->val = *(u64 *) op->ptr;
711 break;
712 }
713 }
714 op->orig_val = op->val;
715 }
716
717 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
718 struct x86_emulate_ops *ops)
719 {
720 struct decode_cache *c = &ctxt->decode;
721 u8 sib;
722 int index_reg = 0, base_reg = 0, scale;
723 int rc = 0;
724
725 if (c->rex_prefix) {
726 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
727 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
728 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
729 }
730
731 c->modrm = insn_fetch(u8, 1, c->eip);
732 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
733 c->modrm_reg |= (c->modrm & 0x38) >> 3;
734 c->modrm_rm |= (c->modrm & 0x07);
735 c->modrm_ea = 0;
736 c->use_modrm_ea = 1;
737
738 if (c->modrm_mod == 3) {
739 c->modrm_ptr = decode_register(c->modrm_rm,
740 c->regs, c->d & ByteOp);
741 c->modrm_val = *(unsigned long *)c->modrm_ptr;
742 return rc;
743 }
744
745 if (c->ad_bytes == 2) {
746 unsigned bx = c->regs[VCPU_REGS_RBX];
747 unsigned bp = c->regs[VCPU_REGS_RBP];
748 unsigned si = c->regs[VCPU_REGS_RSI];
749 unsigned di = c->regs[VCPU_REGS_RDI];
750
751 /* 16-bit ModR/M decode. */
752 switch (c->modrm_mod) {
753 case 0:
754 if (c->modrm_rm == 6)
755 c->modrm_ea += insn_fetch(u16, 2, c->eip);
756 break;
757 case 1:
758 c->modrm_ea += insn_fetch(s8, 1, c->eip);
759 break;
760 case 2:
761 c->modrm_ea += insn_fetch(u16, 2, c->eip);
762 break;
763 }
764 switch (c->modrm_rm) {
765 case 0:
766 c->modrm_ea += bx + si;
767 break;
768 case 1:
769 c->modrm_ea += bx + di;
770 break;
771 case 2:
772 c->modrm_ea += bp + si;
773 break;
774 case 3:
775 c->modrm_ea += bp + di;
776 break;
777 case 4:
778 c->modrm_ea += si;
779 break;
780 case 5:
781 c->modrm_ea += di;
782 break;
783 case 6:
784 if (c->modrm_mod != 0)
785 c->modrm_ea += bp;
786 break;
787 case 7:
788 c->modrm_ea += bx;
789 break;
790 }
791 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
792 (c->modrm_rm == 6 && c->modrm_mod != 0))
793 if (!c->has_seg_override)
794 set_seg_override(c, VCPU_SREG_SS);
795 c->modrm_ea = (u16)c->modrm_ea;
796 } else {
797 /* 32/64-bit ModR/M decode. */
798 if ((c->modrm_rm & 7) == 4) {
799 sib = insn_fetch(u8, 1, c->eip);
800 index_reg |= (sib >> 3) & 7;
801 base_reg |= sib & 7;
802 scale = sib >> 6;
803
804 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
805 c->modrm_ea += insn_fetch(s32, 4, c->eip);
806 else
807 c->modrm_ea += c->regs[base_reg];
808 if (index_reg != 4)
809 c->modrm_ea += c->regs[index_reg] << scale;
810 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
811 if (ctxt->mode == X86EMUL_MODE_PROT64)
812 c->rip_relative = 1;
813 } else
814 c->modrm_ea += c->regs[c->modrm_rm];
815 switch (c->modrm_mod) {
816 case 0:
817 if (c->modrm_rm == 5)
818 c->modrm_ea += insn_fetch(s32, 4, c->eip);
819 break;
820 case 1:
821 c->modrm_ea += insn_fetch(s8, 1, c->eip);
822 break;
823 case 2:
824 c->modrm_ea += insn_fetch(s32, 4, c->eip);
825 break;
826 }
827 }
828 done:
829 return rc;
830 }
831
832 static int decode_abs(struct x86_emulate_ctxt *ctxt,
833 struct x86_emulate_ops *ops)
834 {
835 struct decode_cache *c = &ctxt->decode;
836 int rc = 0;
837
838 switch (c->ad_bytes) {
839 case 2:
840 c->modrm_ea = insn_fetch(u16, 2, c->eip);
841 break;
842 case 4:
843 c->modrm_ea = insn_fetch(u32, 4, c->eip);
844 break;
845 case 8:
846 c->modrm_ea = insn_fetch(u64, 8, c->eip);
847 break;
848 }
849 done:
850 return rc;
851 }
852
853 int
854 x86_decode_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
855 {
856 struct decode_cache *c = &ctxt->decode;
857 int rc = 0;
858 int mode = ctxt->mode;
859 int def_op_bytes, def_ad_bytes, group;
860
861 /* Shadow copy of register state. Committed on successful emulation. */
862
863 memset(c, 0, sizeof(struct decode_cache));
864 c->eip = kvm_rip_read(ctxt->vcpu);
865 ctxt->cs_base = seg_base(ctxt, VCPU_SREG_CS);
866 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
867
868 switch (mode) {
869 case X86EMUL_MODE_REAL:
870 case X86EMUL_MODE_PROT16:
871 def_op_bytes = def_ad_bytes = 2;
872 break;
873 case X86EMUL_MODE_PROT32:
874 def_op_bytes = def_ad_bytes = 4;
875 break;
876 #ifdef CONFIG_X86_64
877 case X86EMUL_MODE_PROT64:
878 def_op_bytes = 4;
879 def_ad_bytes = 8;
880 break;
881 #endif
882 default:
883 return -1;
884 }
885
886 c->op_bytes = def_op_bytes;
887 c->ad_bytes = def_ad_bytes;
888
889 /* Legacy prefixes. */
890 for (;;) {
891 switch (c->b = insn_fetch(u8, 1, c->eip)) {
892 case 0x66: /* operand-size override */
893 /* switch between 2/4 bytes */
894 c->op_bytes = def_op_bytes ^ 6;
895 break;
896 case 0x67: /* address-size override */
897 if (mode == X86EMUL_MODE_PROT64)
898 /* switch between 4/8 bytes */
899 c->ad_bytes = def_ad_bytes ^ 12;
900 else
901 /* switch between 2/4 bytes */
902 c->ad_bytes = def_ad_bytes ^ 6;
903 break;
904 case 0x26: /* ES override */
905 case 0x2e: /* CS override */
906 case 0x36: /* SS override */
907 case 0x3e: /* DS override */
908 set_seg_override(c, (c->b >> 3) & 3);
909 break;
910 case 0x64: /* FS override */
911 case 0x65: /* GS override */
912 set_seg_override(c, c->b & 7);
913 break;
914 case 0x40 ... 0x4f: /* REX */
915 if (mode != X86EMUL_MODE_PROT64)
916 goto done_prefixes;
917 c->rex_prefix = c->b;
918 continue;
919 case 0xf0: /* LOCK */
920 c->lock_prefix = 1;
921 break;
922 case 0xf2: /* REPNE/REPNZ */
923 c->rep_prefix = REPNE_PREFIX;
924 break;
925 case 0xf3: /* REP/REPE/REPZ */
926 c->rep_prefix = REPE_PREFIX;
927 break;
928 default:
929 goto done_prefixes;
930 }
931
932 /* Any legacy prefix after a REX prefix nullifies its effect. */
933
934 c->rex_prefix = 0;
935 }
936
937 done_prefixes:
938
939 /* REX prefix. */
940 if (c->rex_prefix)
941 if (c->rex_prefix & 8)
942 c->op_bytes = 8; /* REX.W */
943
944 /* Opcode byte(s). */
945 c->d = opcode_table[c->b];
946 if (c->d == 0) {
947 /* Two-byte opcode? */
948 if (c->b == 0x0f) {
949 c->twobyte = 1;
950 c->b = insn_fetch(u8, 1, c->eip);
951 c->d = twobyte_table[c->b];
952 }
953 }
954
955 if (c->d & Group) {
956 group = c->d & GroupMask;
957 c->modrm = insn_fetch(u8, 1, c->eip);
958 --c->eip;
959
960 group = (group << 3) + ((c->modrm >> 3) & 7);
961 if ((c->d & GroupDual) && (c->modrm >> 6) == 3)
962 c->d = group2_table[group];
963 else
964 c->d = group_table[group];
965 }
966
967 /* Unrecognised? */
968 if (c->d == 0) {
969 DPRINTF("Cannot emulate %02x\n", c->b);
970 return -1;
971 }
972
973 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
974 c->op_bytes = 8;
975
976 /* ModRM and SIB bytes. */
977 if (c->d & ModRM)
978 rc = decode_modrm(ctxt, ops);
979 else if (c->d & MemAbs)
980 rc = decode_abs(ctxt, ops);
981 if (rc)
982 goto done;
983
984 if (!c->has_seg_override)
985 set_seg_override(c, VCPU_SREG_DS);
986
987 if (!(!c->twobyte && c->b == 0x8d))
988 c->modrm_ea += seg_override_base(ctxt, c);
989
990 if (c->ad_bytes != 8)
991 c->modrm_ea = (u32)c->modrm_ea;
992 /*
993 * Decode and fetch the source operand: register, memory
994 * or immediate.
995 */
996 switch (c->d & SrcMask) {
997 case SrcNone:
998 break;
999 case SrcReg:
1000 decode_register_operand(&c->src, c, 0);
1001 break;
1002 case SrcMem16:
1003 c->src.bytes = 2;
1004 goto srcmem_common;
1005 case SrcMem32:
1006 c->src.bytes = 4;
1007 goto srcmem_common;
1008 case SrcMem:
1009 c->src.bytes = (c->d & ByteOp) ? 1 :
1010 c->op_bytes;
1011 /* Don't fetch the address for invlpg: it could be unmapped. */
1012 if (c->twobyte && c->b == 0x01 && c->modrm_reg == 7)
1013 break;
1014 srcmem_common:
1015 /*
1016 * For instructions with a ModR/M byte, switch to register
1017 * access if Mod = 3.
1018 */
1019 if ((c->d & ModRM) && c->modrm_mod == 3) {
1020 c->src.type = OP_REG;
1021 c->src.val = c->modrm_val;
1022 c->src.ptr = c->modrm_ptr;
1023 break;
1024 }
1025 c->src.type = OP_MEM;
1026 break;
1027 case SrcImm:
1028 c->src.type = OP_IMM;
1029 c->src.ptr = (unsigned long *)c->eip;
1030 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1031 if (c->src.bytes == 8)
1032 c->src.bytes = 4;
1033 /* NB. Immediates are sign-extended as necessary. */
1034 switch (c->src.bytes) {
1035 case 1:
1036 c->src.val = insn_fetch(s8, 1, c->eip);
1037 break;
1038 case 2:
1039 c->src.val = insn_fetch(s16, 2, c->eip);
1040 break;
1041 case 4:
1042 c->src.val = insn_fetch(s32, 4, c->eip);
1043 break;
1044 }
1045 break;
1046 case SrcImmByte:
1047 c->src.type = OP_IMM;
1048 c->src.ptr = (unsigned long *)c->eip;
1049 c->src.bytes = 1;
1050 c->src.val = insn_fetch(s8, 1, c->eip);
1051 break;
1052 case SrcOne:
1053 c->src.bytes = 1;
1054 c->src.val = 1;
1055 break;
1056 }
1057
1058 /*
1059 * Decode and fetch the second source operand: register, memory
1060 * or immediate.
1061 */
1062 switch (c->d & Src2Mask) {
1063 case Src2None:
1064 break;
1065 case Src2CL:
1066 c->src2.bytes = 1;
1067 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
1068 break;
1069 case Src2ImmByte:
1070 c->src2.type = OP_IMM;
1071 c->src2.ptr = (unsigned long *)c->eip;
1072 c->src2.bytes = 1;
1073 c->src2.val = insn_fetch(u8, 1, c->eip);
1074 break;
1075 case Src2One:
1076 c->src2.bytes = 1;
1077 c->src2.val = 1;
1078 break;
1079 }
1080
1081 /* Decode and fetch the destination operand: register or memory. */
1082 switch (c->d & DstMask) {
1083 case ImplicitOps:
1084 /* Special instructions do their own operand decoding. */
1085 return 0;
1086 case DstReg:
1087 decode_register_operand(&c->dst, c,
1088 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
1089 break;
1090 case DstMem:
1091 if ((c->d & ModRM) && c->modrm_mod == 3) {
1092 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1093 c->dst.type = OP_REG;
1094 c->dst.val = c->dst.orig_val = c->modrm_val;
1095 c->dst.ptr = c->modrm_ptr;
1096 break;
1097 }
1098 c->dst.type = OP_MEM;
1099 break;
1100 case DstAcc:
1101 c->dst.type = OP_REG;
1102 c->dst.bytes = c->op_bytes;
1103 c->dst.ptr = &c->regs[VCPU_REGS_RAX];
1104 switch (c->op_bytes) {
1105 case 1:
1106 c->dst.val = *(u8 *)c->dst.ptr;
1107 break;
1108 case 2:
1109 c->dst.val = *(u16 *)c->dst.ptr;
1110 break;
1111 case 4:
1112 c->dst.val = *(u32 *)c->dst.ptr;
1113 break;
1114 }
1115 c->dst.orig_val = c->dst.val;
1116 break;
1117 }
1118
1119 if (c->rip_relative)
1120 c->modrm_ea += c->eip;
1121
1122 done:
1123 return (rc == X86EMUL_UNHANDLEABLE) ? -1 : 0;
1124 }
1125
1126 static inline void emulate_push(struct x86_emulate_ctxt *ctxt)
1127 {
1128 struct decode_cache *c = &ctxt->decode;
1129
1130 c->dst.type = OP_MEM;
1131 c->dst.bytes = c->op_bytes;
1132 c->dst.val = c->src.val;
1133 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1134 c->dst.ptr = (void *) register_address(c, ss_base(ctxt),
1135 c->regs[VCPU_REGS_RSP]);
1136 }
1137
1138 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1139 struct x86_emulate_ops *ops)
1140 {
1141 struct decode_cache *c = &ctxt->decode;
1142 int rc;
1143
1144 rc = ops->read_emulated(register_address(c, ss_base(ctxt),
1145 c->regs[VCPU_REGS_RSP]),
1146 &c->src.val, c->src.bytes, ctxt->vcpu);
1147 if (rc != 0)
1148 return rc;
1149
1150 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.bytes);
1151 return rc;
1152 }
1153
1154 static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1155 struct x86_emulate_ops *ops)
1156 {
1157 struct decode_cache *c = &ctxt->decode;
1158 int rc;
1159
1160 c->src.bytes = c->dst.bytes;
1161 rc = emulate_pop(ctxt, ops);
1162 if (rc != 0)
1163 return rc;
1164 c->dst.val = c->src.val;
1165 return 0;
1166 }
1167
1168 static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1169 {
1170 struct decode_cache *c = &ctxt->decode;
1171 switch (c->modrm_reg) {
1172 case 0: /* rol */
1173 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1174 break;
1175 case 1: /* ror */
1176 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1177 break;
1178 case 2: /* rcl */
1179 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1180 break;
1181 case 3: /* rcr */
1182 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1183 break;
1184 case 4: /* sal/shl */
1185 case 6: /* sal/shl */
1186 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1187 break;
1188 case 5: /* shr */
1189 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1190 break;
1191 case 7: /* sar */
1192 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1193 break;
1194 }
1195 }
1196
1197 static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1198 struct x86_emulate_ops *ops)
1199 {
1200 struct decode_cache *c = &ctxt->decode;
1201 int rc = 0;
1202
1203 switch (c->modrm_reg) {
1204 case 0 ... 1: /* test */
1205 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1206 break;
1207 case 2: /* not */
1208 c->dst.val = ~c->dst.val;
1209 break;
1210 case 3: /* neg */
1211 emulate_1op("neg", c->dst, ctxt->eflags);
1212 break;
1213 default:
1214 DPRINTF("Cannot emulate %02x\n", c->b);
1215 rc = X86EMUL_UNHANDLEABLE;
1216 break;
1217 }
1218 return rc;
1219 }
1220
1221 static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
1222 struct x86_emulate_ops *ops)
1223 {
1224 struct decode_cache *c = &ctxt->decode;
1225
1226 switch (c->modrm_reg) {
1227 case 0: /* inc */
1228 emulate_1op("inc", c->dst, ctxt->eflags);
1229 break;
1230 case 1: /* dec */
1231 emulate_1op("dec", c->dst, ctxt->eflags);
1232 break;
1233 case 2: /* call near abs */ {
1234 long int old_eip;
1235 old_eip = c->eip;
1236 c->eip = c->src.val;
1237 c->src.val = old_eip;
1238 emulate_push(ctxt);
1239 break;
1240 }
1241 case 4: /* jmp abs */
1242 c->eip = c->src.val;
1243 break;
1244 case 6: /* push */
1245 emulate_push(ctxt);
1246 break;
1247 }
1248 return 0;
1249 }
1250
1251 static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1252 struct x86_emulate_ops *ops,
1253 unsigned long memop)
1254 {
1255 struct decode_cache *c = &ctxt->decode;
1256 u64 old, new;
1257 int rc;
1258
1259 rc = ops->read_emulated(memop, &old, 8, ctxt->vcpu);
1260 if (rc != 0)
1261 return rc;
1262
1263 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1264 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1265
1266 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1267 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1268 ctxt->eflags &= ~EFLG_ZF;
1269
1270 } else {
1271 new = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1272 (u32) c->regs[VCPU_REGS_RBX];
1273
1274 rc = ops->cmpxchg_emulated(memop, &old, &new, 8, ctxt->vcpu);
1275 if (rc != 0)
1276 return rc;
1277 ctxt->eflags |= EFLG_ZF;
1278 }
1279 return 0;
1280 }
1281
1282 static inline int writeback(struct x86_emulate_ctxt *ctxt,
1283 struct x86_emulate_ops *ops)
1284 {
1285 int rc;
1286 struct decode_cache *c = &ctxt->decode;
1287
1288 switch (c->dst.type) {
1289 case OP_REG:
1290 /* The 4-byte case *is* correct:
1291 * in 64-bit mode we zero-extend.
1292 */
1293 switch (c->dst.bytes) {
1294 case 1:
1295 *(u8 *)c->dst.ptr = (u8)c->dst.val;
1296 break;
1297 case 2:
1298 *(u16 *)c->dst.ptr = (u16)c->dst.val;
1299 break;
1300 case 4:
1301 *c->dst.ptr = (u32)c->dst.val;
1302 break; /* 64b: zero-ext */
1303 case 8:
1304 *c->dst.ptr = c->dst.val;
1305 break;
1306 }
1307 break;
1308 case OP_MEM:
1309 if (c->lock_prefix)
1310 rc = ops->cmpxchg_emulated(
1311 (unsigned long)c->dst.ptr,
1312 &c->dst.orig_val,
1313 &c->dst.val,
1314 c->dst.bytes,
1315 ctxt->vcpu);
1316 else
1317 rc = ops->write_emulated(
1318 (unsigned long)c->dst.ptr,
1319 &c->dst.val,
1320 c->dst.bytes,
1321 ctxt->vcpu);
1322 if (rc != 0)
1323 return rc;
1324 break;
1325 case OP_NONE:
1326 /* no writeback */
1327 break;
1328 default:
1329 break;
1330 }
1331 return 0;
1332 }
1333
1334 int
1335 x86_emulate_insn(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1336 {
1337 unsigned long memop = 0;
1338 u64 msr_data;
1339 unsigned long saved_eip = 0;
1340 struct decode_cache *c = &ctxt->decode;
1341 unsigned int port;
1342 int io_dir_in;
1343 int rc = 0;
1344
1345 /* Shadow copy of register state. Committed on successful emulation.
1346 * NOTE: we can copy them from vcpu as x86_decode_insn() doesn't
1347 * modify them.
1348 */
1349
1350 memcpy(c->regs, ctxt->vcpu->arch.regs, sizeof c->regs);
1351 saved_eip = c->eip;
1352
1353 if (((c->d & ModRM) && (c->modrm_mod != 3)) || (c->d & MemAbs))
1354 memop = c->modrm_ea;
1355
1356 if (c->rep_prefix && (c->d & String)) {
1357 /* All REP prefixes have the same first termination condition */
1358 if (c->regs[VCPU_REGS_RCX] == 0) {
1359 kvm_rip_write(ctxt->vcpu, c->eip);
1360 goto done;
1361 }
1362 /* The second termination condition only applies for REPE
1363 * and REPNE. Test if the repeat string operation prefix is
1364 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
1365 * corresponding termination condition according to:
1366 * - if REPE/REPZ and ZF = 0 then done
1367 * - if REPNE/REPNZ and ZF = 1 then done
1368 */
1369 if ((c->b == 0xa6) || (c->b == 0xa7) ||
1370 (c->b == 0xae) || (c->b == 0xaf)) {
1371 if ((c->rep_prefix == REPE_PREFIX) &&
1372 ((ctxt->eflags & EFLG_ZF) == 0)) {
1373 kvm_rip_write(ctxt->vcpu, c->eip);
1374 goto done;
1375 }
1376 if ((c->rep_prefix == REPNE_PREFIX) &&
1377 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF)) {
1378 kvm_rip_write(ctxt->vcpu, c->eip);
1379 goto done;
1380 }
1381 }
1382 c->regs[VCPU_REGS_RCX]--;
1383 c->eip = kvm_rip_read(ctxt->vcpu);
1384 }
1385
1386 if (c->src.type == OP_MEM) {
1387 c->src.ptr = (unsigned long *)memop;
1388 c->src.val = 0;
1389 rc = ops->read_emulated((unsigned long)c->src.ptr,
1390 &c->src.val,
1391 c->src.bytes,
1392 ctxt->vcpu);
1393 if (rc != 0)
1394 goto done;
1395 c->src.orig_val = c->src.val;
1396 }
1397
1398 if ((c->d & DstMask) == ImplicitOps)
1399 goto special_insn;
1400
1401
1402 if (c->dst.type == OP_MEM) {
1403 c->dst.ptr = (unsigned long *)memop;
1404 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1405 c->dst.val = 0;
1406 if (c->d & BitOp) {
1407 unsigned long mask = ~(c->dst.bytes * 8 - 1);
1408
1409 c->dst.ptr = (void *)c->dst.ptr +
1410 (c->src.val & mask) / 8;
1411 }
1412 if (!(c->d & Mov) &&
1413 /* optimisation - avoid slow emulated read */
1414 ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1415 &c->dst.val,
1416 c->dst.bytes, ctxt->vcpu)) != 0))
1417 goto done;
1418 }
1419 c->dst.orig_val = c->dst.val;
1420
1421 special_insn:
1422
1423 if (c->twobyte)
1424 goto twobyte_insn;
1425
1426 switch (c->b) {
1427 case 0x00 ... 0x05:
1428 add: /* add */
1429 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
1430 break;
1431 case 0x08 ... 0x0d:
1432 or: /* or */
1433 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
1434 break;
1435 case 0x10 ... 0x15:
1436 adc: /* adc */
1437 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
1438 break;
1439 case 0x18 ... 0x1d:
1440 sbb: /* sbb */
1441 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
1442 break;
1443 case 0x20 ... 0x25:
1444 and: /* and */
1445 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
1446 break;
1447 case 0x28 ... 0x2d:
1448 sub: /* sub */
1449 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
1450 break;
1451 case 0x30 ... 0x35:
1452 xor: /* xor */
1453 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
1454 break;
1455 case 0x38 ... 0x3d:
1456 cmp: /* cmp */
1457 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1458 break;
1459 case 0x40 ... 0x47: /* inc r16/r32 */
1460 emulate_1op("inc", c->dst, ctxt->eflags);
1461 break;
1462 case 0x48 ... 0x4f: /* dec r16/r32 */
1463 emulate_1op("dec", c->dst, ctxt->eflags);
1464 break;
1465 case 0x50 ... 0x57: /* push reg */
1466 emulate_push(ctxt);
1467 break;
1468 case 0x58 ... 0x5f: /* pop reg */
1469 pop_instruction:
1470 c->src.bytes = c->op_bytes;
1471 rc = emulate_pop(ctxt, ops);
1472 if (rc != 0)
1473 goto done;
1474 c->dst.val = c->src.val;
1475 break;
1476 case 0x63: /* movsxd */
1477 if (ctxt->mode != X86EMUL_MODE_PROT64)
1478 goto cannot_emulate;
1479 c->dst.val = (s32) c->src.val;
1480 break;
1481 case 0x68: /* push imm */
1482 case 0x6a: /* push imm8 */
1483 emulate_push(ctxt);
1484 break;
1485 case 0x6c: /* insb */
1486 case 0x6d: /* insw/insd */
1487 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1488 1,
1489 (c->d & ByteOp) ? 1 : c->op_bytes,
1490 c->rep_prefix ?
1491 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
1492 (ctxt->eflags & EFLG_DF),
1493 register_address(c, es_base(ctxt),
1494 c->regs[VCPU_REGS_RDI]),
1495 c->rep_prefix,
1496 c->regs[VCPU_REGS_RDX]) == 0) {
1497 c->eip = saved_eip;
1498 return -1;
1499 }
1500 return 0;
1501 case 0x6e: /* outsb */
1502 case 0x6f: /* outsw/outsd */
1503 if (kvm_emulate_pio_string(ctxt->vcpu, NULL,
1504 0,
1505 (c->d & ByteOp) ? 1 : c->op_bytes,
1506 c->rep_prefix ?
1507 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1,
1508 (ctxt->eflags & EFLG_DF),
1509 register_address(c,
1510 seg_override_base(ctxt, c),
1511 c->regs[VCPU_REGS_RSI]),
1512 c->rep_prefix,
1513 c->regs[VCPU_REGS_RDX]) == 0) {
1514 c->eip = saved_eip;
1515 return -1;
1516 }
1517 return 0;
1518 case 0x70 ... 0x7f: /* jcc (short) */ {
1519 int rel = insn_fetch(s8, 1, c->eip);
1520
1521 if (test_cc(c->b, ctxt->eflags))
1522 jmp_rel(c, rel);
1523 break;
1524 }
1525 case 0x80 ... 0x83: /* Grp1 */
1526 switch (c->modrm_reg) {
1527 case 0:
1528 goto add;
1529 case 1:
1530 goto or;
1531 case 2:
1532 goto adc;
1533 case 3:
1534 goto sbb;
1535 case 4:
1536 goto and;
1537 case 5:
1538 goto sub;
1539 case 6:
1540 goto xor;
1541 case 7:
1542 goto cmp;
1543 }
1544 break;
1545 case 0x84 ... 0x85:
1546 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1547 break;
1548 case 0x86 ... 0x87: /* xchg */
1549 xchg:
1550 /* Write back the register source. */
1551 switch (c->dst.bytes) {
1552 case 1:
1553 *(u8 *) c->src.ptr = (u8) c->dst.val;
1554 break;
1555 case 2:
1556 *(u16 *) c->src.ptr = (u16) c->dst.val;
1557 break;
1558 case 4:
1559 *c->src.ptr = (u32) c->dst.val;
1560 break; /* 64b reg: zero-extend */
1561 case 8:
1562 *c->src.ptr = c->dst.val;
1563 break;
1564 }
1565 /*
1566 * Write back the memory destination with implicit LOCK
1567 * prefix.
1568 */
1569 c->dst.val = c->src.val;
1570 c->lock_prefix = 1;
1571 break;
1572 case 0x88 ... 0x8b: /* mov */
1573 goto mov;
1574 case 0x8c: { /* mov r/m, sreg */
1575 struct kvm_segment segreg;
1576
1577 if (c->modrm_reg <= 5)
1578 kvm_get_segment(ctxt->vcpu, &segreg, c->modrm_reg);
1579 else {
1580 printk(KERN_INFO "0x8c: Invalid segreg in modrm byte 0x%02x\n",
1581 c->modrm);
1582 goto cannot_emulate;
1583 }
1584 c->dst.val = segreg.selector;
1585 break;
1586 }
1587 case 0x8d: /* lea r16/r32, m */
1588 c->dst.val = c->modrm_ea;
1589 break;
1590 case 0x8e: { /* mov seg, r/m16 */
1591 uint16_t sel;
1592 int type_bits;
1593 int err;
1594
1595 sel = c->src.val;
1596 if (c->modrm_reg <= 5) {
1597 type_bits = (c->modrm_reg == 1) ? 9 : 1;
1598 err = kvm_load_segment_descriptor(ctxt->vcpu, sel,
1599 type_bits, c->modrm_reg);
1600 } else {
1601 printk(KERN_INFO "Invalid segreg in modrm byte 0x%02x\n",
1602 c->modrm);
1603 goto cannot_emulate;
1604 }
1605
1606 if (err < 0)
1607 goto cannot_emulate;
1608
1609 c->dst.type = OP_NONE; /* Disable writeback. */
1610 break;
1611 }
1612 case 0x8f: /* pop (sole member of Grp1a) */
1613 rc = emulate_grp1a(ctxt, ops);
1614 if (rc != 0)
1615 goto done;
1616 break;
1617 case 0x90: /* nop / xchg r8,rax */
1618 if (!(c->rex_prefix & 1)) { /* nop */
1619 c->dst.type = OP_NONE;
1620 break;
1621 }
1622 case 0x91 ... 0x97: /* xchg reg,rax */
1623 c->src.type = c->dst.type = OP_REG;
1624 c->src.bytes = c->dst.bytes = c->op_bytes;
1625 c->src.ptr = (unsigned long *) &c->regs[VCPU_REGS_RAX];
1626 c->src.val = *(c->src.ptr);
1627 goto xchg;
1628 case 0x9c: /* pushf */
1629 c->src.val = (unsigned long) ctxt->eflags;
1630 emulate_push(ctxt);
1631 break;
1632 case 0x9d: /* popf */
1633 c->dst.type = OP_REG;
1634 c->dst.ptr = (unsigned long *) &ctxt->eflags;
1635 c->dst.bytes = c->op_bytes;
1636 goto pop_instruction;
1637 case 0xa0 ... 0xa1: /* mov */
1638 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1639 c->dst.val = c->src.val;
1640 break;
1641 case 0xa2 ... 0xa3: /* mov */
1642 c->dst.val = (unsigned long)c->regs[VCPU_REGS_RAX];
1643 break;
1644 case 0xa4 ... 0xa5: /* movs */
1645 c->dst.type = OP_MEM;
1646 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1647 c->dst.ptr = (unsigned long *)register_address(c,
1648 es_base(ctxt),
1649 c->regs[VCPU_REGS_RDI]);
1650 if ((rc = ops->read_emulated(register_address(c,
1651 seg_override_base(ctxt, c),
1652 c->regs[VCPU_REGS_RSI]),
1653 &c->dst.val,
1654 c->dst.bytes, ctxt->vcpu)) != 0)
1655 goto done;
1656 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
1657 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1658 : c->dst.bytes);
1659 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
1660 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1661 : c->dst.bytes);
1662 break;
1663 case 0xa6 ... 0xa7: /* cmps */
1664 c->src.type = OP_NONE; /* Disable writeback. */
1665 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1666 c->src.ptr = (unsigned long *)register_address(c,
1667 seg_override_base(ctxt, c),
1668 c->regs[VCPU_REGS_RSI]);
1669 if ((rc = ops->read_emulated((unsigned long)c->src.ptr,
1670 &c->src.val,
1671 c->src.bytes,
1672 ctxt->vcpu)) != 0)
1673 goto done;
1674
1675 c->dst.type = OP_NONE; /* Disable writeback. */
1676 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1677 c->dst.ptr = (unsigned long *)register_address(c,
1678 es_base(ctxt),
1679 c->regs[VCPU_REGS_RDI]);
1680 if ((rc = ops->read_emulated((unsigned long)c->dst.ptr,
1681 &c->dst.val,
1682 c->dst.bytes,
1683 ctxt->vcpu)) != 0)
1684 goto done;
1685
1686 DPRINTF("cmps: mem1=0x%p mem2=0x%p\n", c->src.ptr, c->dst.ptr);
1687
1688 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
1689
1690 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
1691 (ctxt->eflags & EFLG_DF) ? -c->src.bytes
1692 : c->src.bytes);
1693 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
1694 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1695 : c->dst.bytes);
1696
1697 break;
1698 case 0xaa ... 0xab: /* stos */
1699 c->dst.type = OP_MEM;
1700 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1701 c->dst.ptr = (unsigned long *)register_address(c,
1702 es_base(ctxt),
1703 c->regs[VCPU_REGS_RDI]);
1704 c->dst.val = c->regs[VCPU_REGS_RAX];
1705 register_address_increment(c, &c->regs[VCPU_REGS_RDI],
1706 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1707 : c->dst.bytes);
1708 break;
1709 case 0xac ... 0xad: /* lods */
1710 c->dst.type = OP_REG;
1711 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
1712 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
1713 if ((rc = ops->read_emulated(register_address(c,
1714 seg_override_base(ctxt, c),
1715 c->regs[VCPU_REGS_RSI]),
1716 &c->dst.val,
1717 c->dst.bytes,
1718 ctxt->vcpu)) != 0)
1719 goto done;
1720 register_address_increment(c, &c->regs[VCPU_REGS_RSI],
1721 (ctxt->eflags & EFLG_DF) ? -c->dst.bytes
1722 : c->dst.bytes);
1723 break;
1724 case 0xae ... 0xaf: /* scas */
1725 DPRINTF("Urk! I don't handle SCAS.\n");
1726 goto cannot_emulate;
1727 case 0xb0 ... 0xbf: /* mov r, imm */
1728 goto mov;
1729 case 0xc0 ... 0xc1:
1730 emulate_grp2(ctxt);
1731 break;
1732 case 0xc3: /* ret */
1733 c->dst.type = OP_REG;
1734 c->dst.ptr = &c->eip;
1735 c->dst.bytes = c->op_bytes;
1736 goto pop_instruction;
1737 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1738 mov:
1739 c->dst.val = c->src.val;
1740 break;
1741 case 0xd0 ... 0xd1: /* Grp2 */
1742 c->src.val = 1;
1743 emulate_grp2(ctxt);
1744 break;
1745 case 0xd2 ... 0xd3: /* Grp2 */
1746 c->src.val = c->regs[VCPU_REGS_RCX];
1747 emulate_grp2(ctxt);
1748 break;
1749 case 0xe4: /* inb */
1750 case 0xe5: /* in */
1751 port = insn_fetch(u8, 1, c->eip);
1752 io_dir_in = 1;
1753 goto do_io;
1754 case 0xe6: /* outb */
1755 case 0xe7: /* out */
1756 port = insn_fetch(u8, 1, c->eip);
1757 io_dir_in = 0;
1758 goto do_io;
1759 case 0xe8: /* call (near) */ {
1760 long int rel;
1761 switch (c->op_bytes) {
1762 case 2:
1763 rel = insn_fetch(s16, 2, c->eip);
1764 break;
1765 case 4:
1766 rel = insn_fetch(s32, 4, c->eip);
1767 break;
1768 default:
1769 DPRINTF("Call: Invalid op_bytes\n");
1770 goto cannot_emulate;
1771 }
1772 c->src.val = (unsigned long) c->eip;
1773 jmp_rel(c, rel);
1774 c->op_bytes = c->ad_bytes;
1775 emulate_push(ctxt);
1776 break;
1777 }
1778 case 0xe9: /* jmp rel */
1779 goto jmp;
1780 case 0xea: /* jmp far */ {
1781 uint32_t eip;
1782 uint16_t sel;
1783
1784 switch (c->op_bytes) {
1785 case 2:
1786 eip = insn_fetch(u16, 2, c->eip);
1787 break;
1788 case 4:
1789 eip = insn_fetch(u32, 4, c->eip);
1790 break;
1791 default:
1792 DPRINTF("jmp far: Invalid op_bytes\n");
1793 goto cannot_emulate;
1794 }
1795 sel = insn_fetch(u16, 2, c->eip);
1796 if (kvm_load_segment_descriptor(ctxt->vcpu, sel, 9, VCPU_SREG_CS) < 0) {
1797 DPRINTF("jmp far: Failed to load CS descriptor\n");
1798 goto cannot_emulate;
1799 }
1800
1801 c->eip = eip;
1802 break;
1803 }
1804 case 0xeb:
1805 jmp: /* jmp rel short */
1806 jmp_rel(c, c->src.val);
1807 c->dst.type = OP_NONE; /* Disable writeback. */
1808 break;
1809 case 0xec: /* in al,dx */
1810 case 0xed: /* in (e/r)ax,dx */
1811 port = c->regs[VCPU_REGS_RDX];
1812 io_dir_in = 1;
1813 goto do_io;
1814 case 0xee: /* out al,dx */
1815 case 0xef: /* out (e/r)ax,dx */
1816 port = c->regs[VCPU_REGS_RDX];
1817 io_dir_in = 0;
1818 do_io: if (kvm_emulate_pio(ctxt->vcpu, NULL, io_dir_in,
1819 (c->d & ByteOp) ? 1 : c->op_bytes,
1820 port) != 0) {
1821 c->eip = saved_eip;
1822 goto cannot_emulate;
1823 }
1824 break;
1825 case 0xf4: /* hlt */
1826 ctxt->vcpu->arch.halt_request = 1;
1827 break;
1828 case 0xf5: /* cmc */
1829 /* complement carry flag from eflags reg */
1830 ctxt->eflags ^= EFLG_CF;
1831 c->dst.type = OP_NONE; /* Disable writeback. */
1832 break;
1833 case 0xf6 ... 0xf7: /* Grp3 */
1834 rc = emulate_grp3(ctxt, ops);
1835 if (rc != 0)
1836 goto done;
1837 break;
1838 case 0xf8: /* clc */
1839 ctxt->eflags &= ~EFLG_CF;
1840 c->dst.type = OP_NONE; /* Disable writeback. */
1841 break;
1842 case 0xfa: /* cli */
1843 ctxt->eflags &= ~X86_EFLAGS_IF;
1844 c->dst.type = OP_NONE; /* Disable writeback. */
1845 break;
1846 case 0xfb: /* sti */
1847 ctxt->eflags |= X86_EFLAGS_IF;
1848 c->dst.type = OP_NONE; /* Disable writeback. */
1849 break;
1850 case 0xfc: /* cld */
1851 ctxt->eflags &= ~EFLG_DF;
1852 c->dst.type = OP_NONE; /* Disable writeback. */
1853 break;
1854 case 0xfd: /* std */
1855 ctxt->eflags |= EFLG_DF;
1856 c->dst.type = OP_NONE; /* Disable writeback. */
1857 break;
1858 case 0xfe ... 0xff: /* Grp4/Grp5 */
1859 rc = emulate_grp45(ctxt, ops);
1860 if (rc != 0)
1861 goto done;
1862 break;
1863 }
1864
1865 writeback:
1866 rc = writeback(ctxt, ops);
1867 if (rc != 0)
1868 goto done;
1869
1870 /* Commit shadow register state. */
1871 memcpy(ctxt->vcpu->arch.regs, c->regs, sizeof c->regs);
1872 kvm_rip_write(ctxt->vcpu, c->eip);
1873
1874 done:
1875 if (rc == X86EMUL_UNHANDLEABLE) {
1876 c->eip = saved_eip;
1877 return -1;
1878 }
1879 return 0;
1880
1881 twobyte_insn:
1882 switch (c->b) {
1883 case 0x01: /* lgdt, lidt, lmsw */
1884 switch (c->modrm_reg) {
1885 u16 size;
1886 unsigned long address;
1887
1888 case 0: /* vmcall */
1889 if (c->modrm_mod != 3 || c->modrm_rm != 1)
1890 goto cannot_emulate;
1891
1892 rc = kvm_fix_hypercall(ctxt->vcpu);
1893 if (rc)
1894 goto done;
1895
1896 /* Let the processor re-execute the fixed hypercall */
1897 c->eip = kvm_rip_read(ctxt->vcpu);
1898 /* Disable writeback. */
1899 c->dst.type = OP_NONE;
1900 break;
1901 case 2: /* lgdt */
1902 rc = read_descriptor(ctxt, ops, c->src.ptr,
1903 &size, &address, c->op_bytes);
1904 if (rc)
1905 goto done;
1906 realmode_lgdt(ctxt->vcpu, size, address);
1907 /* Disable writeback. */
1908 c->dst.type = OP_NONE;
1909 break;
1910 case 3: /* lidt/vmmcall */
1911 if (c->modrm_mod == 3 && c->modrm_rm == 1) {
1912 rc = kvm_fix_hypercall(ctxt->vcpu);
1913 if (rc)
1914 goto done;
1915 kvm_emulate_hypercall(ctxt->vcpu);
1916 } else {
1917 rc = read_descriptor(ctxt, ops, c->src.ptr,
1918 &size, &address,
1919 c->op_bytes);
1920 if (rc)
1921 goto done;
1922 realmode_lidt(ctxt->vcpu, size, address);
1923 }
1924 /* Disable writeback. */
1925 c->dst.type = OP_NONE;
1926 break;
1927 case 4: /* smsw */
1928 c->dst.bytes = 2;
1929 c->dst.val = realmode_get_cr(ctxt->vcpu, 0);
1930 break;
1931 case 6: /* lmsw */
1932 realmode_lmsw(ctxt->vcpu, (u16)c->src.val,
1933 &ctxt->eflags);
1934 c->dst.type = OP_NONE;
1935 break;
1936 case 7: /* invlpg*/
1937 emulate_invlpg(ctxt->vcpu, memop);
1938 /* Disable writeback. */
1939 c->dst.type = OP_NONE;
1940 break;
1941 default:
1942 goto cannot_emulate;
1943 }
1944 break;
1945 case 0x06:
1946 emulate_clts(ctxt->vcpu);
1947 c->dst.type = OP_NONE;
1948 break;
1949 case 0x08: /* invd */
1950 case 0x09: /* wbinvd */
1951 case 0x0d: /* GrpP (prefetch) */
1952 case 0x18: /* Grp16 (prefetch/nop) */
1953 c->dst.type = OP_NONE;
1954 break;
1955 case 0x20: /* mov cr, reg */
1956 if (c->modrm_mod != 3)
1957 goto cannot_emulate;
1958 c->regs[c->modrm_rm] =
1959 realmode_get_cr(ctxt->vcpu, c->modrm_reg);
1960 c->dst.type = OP_NONE; /* no writeback */
1961 break;
1962 case 0x21: /* mov from dr to reg */
1963 if (c->modrm_mod != 3)
1964 goto cannot_emulate;
1965 rc = emulator_get_dr(ctxt, c->modrm_reg, &c->regs[c->modrm_rm]);
1966 if (rc)
1967 goto cannot_emulate;
1968 c->dst.type = OP_NONE; /* no writeback */
1969 break;
1970 case 0x22: /* mov reg, cr */
1971 if (c->modrm_mod != 3)
1972 goto cannot_emulate;
1973 realmode_set_cr(ctxt->vcpu,
1974 c->modrm_reg, c->modrm_val, &ctxt->eflags);
1975 c->dst.type = OP_NONE;
1976 break;
1977 case 0x23: /* mov from reg to dr */
1978 if (c->modrm_mod != 3)
1979 goto cannot_emulate;
1980 rc = emulator_set_dr(ctxt, c->modrm_reg,
1981 c->regs[c->modrm_rm]);
1982 if (rc)
1983 goto cannot_emulate;
1984 c->dst.type = OP_NONE; /* no writeback */
1985 break;
1986 case 0x30:
1987 /* wrmsr */
1988 msr_data = (u32)c->regs[VCPU_REGS_RAX]
1989 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
1990 rc = kvm_set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data);
1991 if (rc) {
1992 kvm_inject_gp(ctxt->vcpu, 0);
1993 c->eip = kvm_rip_read(ctxt->vcpu);
1994 }
1995 rc = X86EMUL_CONTINUE;
1996 c->dst.type = OP_NONE;
1997 break;
1998 case 0x32:
1999 /* rdmsr */
2000 rc = kvm_get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data);
2001 if (rc) {
2002 kvm_inject_gp(ctxt->vcpu, 0);
2003 c->eip = kvm_rip_read(ctxt->vcpu);
2004 } else {
2005 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
2006 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
2007 }
2008 rc = X86EMUL_CONTINUE;
2009 c->dst.type = OP_NONE;
2010 break;
2011 case 0x40 ... 0x4f: /* cmov */
2012 c->dst.val = c->dst.orig_val = c->src.val;
2013 if (!test_cc(c->b, ctxt->eflags))
2014 c->dst.type = OP_NONE; /* no writeback */
2015 break;
2016 case 0x80 ... 0x8f: /* jnz rel, etc*/ {
2017 long int rel;
2018
2019 switch (c->op_bytes) {
2020 case 2:
2021 rel = insn_fetch(s16, 2, c->eip);
2022 break;
2023 case 4:
2024 rel = insn_fetch(s32, 4, c->eip);
2025 break;
2026 case 8:
2027 rel = insn_fetch(s64, 8, c->eip);
2028 break;
2029 default:
2030 DPRINTF("jnz: Invalid op_bytes\n");
2031 goto cannot_emulate;
2032 }
2033 if (test_cc(c->b, ctxt->eflags))
2034 jmp_rel(c, rel);
2035 c->dst.type = OP_NONE;
2036 break;
2037 }
2038 case 0xa3:
2039 bt: /* bt */
2040 c->dst.type = OP_NONE;
2041 /* only subword offset */
2042 c->src.val &= (c->dst.bytes << 3) - 1;
2043 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
2044 break;
2045 case 0xa4: /* shld imm8, r, r/m */
2046 case 0xa5: /* shld cl, r, r/m */
2047 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
2048 break;
2049 case 0xab:
2050 bts: /* bts */
2051 /* only subword offset */
2052 c->src.val &= (c->dst.bytes << 3) - 1;
2053 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
2054 break;
2055 case 0xac: /* shrd imm8, r, r/m */
2056 case 0xad: /* shrd cl, r, r/m */
2057 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
2058 break;
2059 case 0xae: /* clflush */
2060 break;
2061 case 0xb0 ... 0xb1: /* cmpxchg */
2062 /*
2063 * Save real source value, then compare EAX against
2064 * destination.
2065 */
2066 c->src.orig_val = c->src.val;
2067 c->src.val = c->regs[VCPU_REGS_RAX];
2068 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
2069 if (ctxt->eflags & EFLG_ZF) {
2070 /* Success: write back to memory. */
2071 c->dst.val = c->src.orig_val;
2072 } else {
2073 /* Failure: write the value we saw to EAX. */
2074 c->dst.type = OP_REG;
2075 c->dst.ptr = (unsigned long *)&c->regs[VCPU_REGS_RAX];
2076 }
2077 break;
2078 case 0xb3:
2079 btr: /* btr */
2080 /* only subword offset */
2081 c->src.val &= (c->dst.bytes << 3) - 1;
2082 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
2083 break;
2084 case 0xb6 ... 0xb7: /* movzx */
2085 c->dst.bytes = c->op_bytes;
2086 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
2087 : (u16) c->src.val;
2088 break;
2089 case 0xba: /* Grp8 */
2090 switch (c->modrm_reg & 3) {
2091 case 0:
2092 goto bt;
2093 case 1:
2094 goto bts;
2095 case 2:
2096 goto btr;
2097 case 3:
2098 goto btc;
2099 }
2100 break;
2101 case 0xbb:
2102 btc: /* btc */
2103 /* only subword offset */
2104 c->src.val &= (c->dst.bytes << 3) - 1;
2105 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
2106 break;
2107 case 0xbe ... 0xbf: /* movsx */
2108 c->dst.bytes = c->op_bytes;
2109 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
2110 (s16) c->src.val;
2111 break;
2112 case 0xc3: /* movnti */
2113 c->dst.bytes = c->op_bytes;
2114 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
2115 (u64) c->src.val;
2116 break;
2117 case 0xc7: /* Grp9 (cmpxchg8b) */
2118 rc = emulate_grp9(ctxt, ops, memop);
2119 if (rc != 0)
2120 goto done;
2121 c->dst.type = OP_NONE;
2122 break;
2123 }
2124 goto writeback;
2125
2126 cannot_emulate:
2127 DPRINTF("Cannot emulate %02x\n", c->b);
2128 c->eip = saved_eip;
2129 return -1;
2130 }
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