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e1000e: write protect ICHx NVM to prevent malicious write/erase
[linux-2.6/mini2440.git] / drivers / net / r8169.c
blob0f6f9747d255f08065570a108b28db7f33e33bb6
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26
27 #include <asm/system.h>
28 #include <asm/io.h>
29 #include <asm/irq.h>
30
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
34
35 #ifdef RTL8169_DEBUG
36 #define assert(expr) \
37 if (!(expr)) { \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__FUNCTION__,__LINE__); \
40 }
41 #define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
43 #else
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...) do {} while (0)
46 #endif /* RTL8169_DEBUG */
47
48 #define R8169_MSG_DEFAULT \
49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
50
51 #define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
55 static const int max_interrupt_work = 20;
56
57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
59 static const int multicast_filter_limit = 32;
60
61 /* MAC address length */
62 #define MAC_ADDR_LEN 6
63
64 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
65 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
66 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
68 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
69 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
70 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
71
72 #define R8169_REGS_SIZE 256
73 #define R8169_NAPI_WEIGHT 64
74 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
75 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
76 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
77 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
78 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
79
80 #define RTL8169_TX_TIMEOUT (6*HZ)
81 #define RTL8169_PHY_TIMEOUT (10*HZ)
82
83 /* write/read MMIO register */
84 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
85 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
86 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
87 #define RTL_R8(reg) readb (ioaddr + (reg))
88 #define RTL_R16(reg) readw (ioaddr + (reg))
89 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
90
91 enum mac_version {
92 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
93 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
94 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
95 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
96 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
97 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
98 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
99 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
100 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
101 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
102 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
103 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
104 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
105 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
106 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
107 RTL_GIGA_MAC_VER_20 = 0x14 // 8168C
108 };
109
110 #define _R(NAME,MAC,MASK) \
111 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
112
113 static const struct {
114 const char *name;
115 u8 mac_version;
116 u32 RxConfigMask; /* Clears the bits supported by this chip */
117 } rtl_chip_info[] = {
118 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
119 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
120 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
121 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
122 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
123 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
124 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
125 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
126 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
127 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
128 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
129 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
130 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
131 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
132 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
133 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880) // PCI-E
134 };
135 #undef _R
136
137 enum cfg_version {
138 RTL_CFG_0 = 0x00,
139 RTL_CFG_1,
140 RTL_CFG_2
141 };
142
143 static void rtl_hw_start_8169(struct net_device *);
144 static void rtl_hw_start_8168(struct net_device *);
145 static void rtl_hw_start_8101(struct net_device *);
146
147 static struct pci_device_id rtl8169_pci_tbl[] = {
148 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
149 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
150 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
151 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
152 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
153 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
154 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
155 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
156 { PCI_VENDOR_ID_LINKSYS, 0x1032,
157 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
158 { 0x0001, 0x8168,
159 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
160 {0,},
161 };
162
163 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
164
165 static int rx_copybreak = 200;
166 static int use_dac;
167 static struct {
168 u32 msg_enable;
169 } debug = { -1 };
170
171 enum rtl_registers {
172 MAC0 = 0, /* Ethernet hardware address. */
173 MAC4 = 4,
174 MAR0 = 8, /* Multicast filter. */
175 CounterAddrLow = 0x10,
176 CounterAddrHigh = 0x14,
177 TxDescStartAddrLow = 0x20,
178 TxDescStartAddrHigh = 0x24,
179 TxHDescStartAddrLow = 0x28,
180 TxHDescStartAddrHigh = 0x2c,
181 FLASH = 0x30,
182 ERSR = 0x36,
183 ChipCmd = 0x37,
184 TxPoll = 0x38,
185 IntrMask = 0x3c,
186 IntrStatus = 0x3e,
187 TxConfig = 0x40,
188 RxConfig = 0x44,
189 RxMissed = 0x4c,
190 Cfg9346 = 0x50,
191 Config0 = 0x51,
192 Config1 = 0x52,
193 Config2 = 0x53,
194 Config3 = 0x54,
195 Config4 = 0x55,
196 Config5 = 0x56,
197 MultiIntr = 0x5c,
198 PHYAR = 0x60,
199 TBICSR = 0x64,
200 TBI_ANAR = 0x68,
201 TBI_LPAR = 0x6a,
202 PHYstatus = 0x6c,
203 RxMaxSize = 0xda,
204 CPlusCmd = 0xe0,
205 IntrMitigate = 0xe2,
206 RxDescAddrLow = 0xe4,
207 RxDescAddrHigh = 0xe8,
208 EarlyTxThres = 0xec,
209 FuncEvent = 0xf0,
210 FuncEventMask = 0xf4,
211 FuncPresetState = 0xf8,
212 FuncForceEvent = 0xfc,
213 };
214
215 enum rtl_register_content {
216 /* InterruptStatusBits */
217 SYSErr = 0x8000,
218 PCSTimeout = 0x4000,
219 SWInt = 0x0100,
220 TxDescUnavail = 0x0080,
221 RxFIFOOver = 0x0040,
222 LinkChg = 0x0020,
223 RxOverflow = 0x0010,
224 TxErr = 0x0008,
225 TxOK = 0x0004,
226 RxErr = 0x0002,
227 RxOK = 0x0001,
228
229 /* RxStatusDesc */
230 RxFOVF = (1 << 23),
231 RxRWT = (1 << 22),
232 RxRES = (1 << 21),
233 RxRUNT = (1 << 20),
234 RxCRC = (1 << 19),
235
236 /* ChipCmdBits */
237 CmdReset = 0x10,
238 CmdRxEnb = 0x08,
239 CmdTxEnb = 0x04,
240 RxBufEmpty = 0x01,
241
242 /* TXPoll register p.5 */
243 HPQ = 0x80, /* Poll cmd on the high prio queue */
244 NPQ = 0x40, /* Poll cmd on the low prio queue */
245 FSWInt = 0x01, /* Forced software interrupt */
246
247 /* Cfg9346Bits */
248 Cfg9346_Lock = 0x00,
249 Cfg9346_Unlock = 0xc0,
250
251 /* rx_mode_bits */
252 AcceptErr = 0x20,
253 AcceptRunt = 0x10,
254 AcceptBroadcast = 0x08,
255 AcceptMulticast = 0x04,
256 AcceptMyPhys = 0x02,
257 AcceptAllPhys = 0x01,
258
259 /* RxConfigBits */
260 RxCfgFIFOShift = 13,
261 RxCfgDMAShift = 8,
262
263 /* TxConfigBits */
264 TxInterFrameGapShift = 24,
265 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
266
267 /* Config1 register p.24 */
268 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
269 PMEnable = (1 << 0), /* Power Management Enable */
270
271 /* Config2 register p. 25 */
272 PCI_Clock_66MHz = 0x01,
273 PCI_Clock_33MHz = 0x00,
274
275 /* Config3 register p.25 */
276 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
277 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
278
279 /* Config5 register p.27 */
280 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
281 MWF = (1 << 5), /* Accept Multicast wakeup frame */
282 UWF = (1 << 4), /* Accept Unicast wakeup frame */
283 LanWake = (1 << 1), /* LanWake enable/disable */
284 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
285
286 /* TBICSR p.28 */
287 TBIReset = 0x80000000,
288 TBILoopback = 0x40000000,
289 TBINwEnable = 0x20000000,
290 TBINwRestart = 0x10000000,
291 TBILinkOk = 0x02000000,
292 TBINwComplete = 0x01000000,
293
294 /* CPlusCmd p.31 */
295 PktCntrDisable = (1 << 7), // 8168
296 RxVlan = (1 << 6),
297 RxChkSum = (1 << 5),
298 PCIDAC = (1 << 4),
299 PCIMulRW = (1 << 3),
300 INTT_0 = 0x0000, // 8168
301 INTT_1 = 0x0001, // 8168
302 INTT_2 = 0x0002, // 8168
303 INTT_3 = 0x0003, // 8168
304
305 /* rtl8169_PHYstatus */
306 TBI_Enable = 0x80,
307 TxFlowCtrl = 0x40,
308 RxFlowCtrl = 0x20,
309 _1000bpsF = 0x10,
310 _100bps = 0x08,
311 _10bps = 0x04,
312 LinkStatus = 0x02,
313 FullDup = 0x01,
314
315 /* _TBICSRBit */
316 TBILinkOK = 0x02000000,
317
318 /* DumpCounterCommand */
319 CounterDump = 0x8,
320 };
321
322 enum desc_status_bit {
323 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
324 RingEnd = (1 << 30), /* End of descriptor ring */
325 FirstFrag = (1 << 29), /* First segment of a packet */
326 LastFrag = (1 << 28), /* Final segment of a packet */
327
328 /* Tx private */
329 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
330 MSSShift = 16, /* MSS value position */
331 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
332 IPCS = (1 << 18), /* Calculate IP checksum */
333 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
334 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
335 TxVlanTag = (1 << 17), /* Add VLAN tag */
336
337 /* Rx private */
338 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
339 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
340
341 #define RxProtoUDP (PID1)
342 #define RxProtoTCP (PID0)
343 #define RxProtoIP (PID1 | PID0)
344 #define RxProtoMask RxProtoIP
345
346 IPFail = (1 << 16), /* IP checksum failed */
347 UDPFail = (1 << 15), /* UDP/IP checksum failed */
348 TCPFail = (1 << 14), /* TCP/IP checksum failed */
349 RxVlanTag = (1 << 16), /* VLAN tag available */
350 };
351
352 #define RsvdMask 0x3fffc000
353
354 struct TxDesc {
355 __le32 opts1;
356 __le32 opts2;
357 __le64 addr;
358 };
359
360 struct RxDesc {
361 __le32 opts1;
362 __le32 opts2;
363 __le64 addr;
364 };
365
366 struct ring_info {
367 struct sk_buff *skb;
368 u32 len;
369 u8 __pad[sizeof(void *) - sizeof(u32)];
370 };
371
372 enum features {
373 RTL_FEATURE_WOL = (1 << 0),
374 RTL_FEATURE_MSI = (1 << 1),
375 };
376
377 struct rtl8169_private {
378 void __iomem *mmio_addr; /* memory map physical address */
379 struct pci_dev *pci_dev; /* Index of PCI device */
380 struct net_device *dev;
381 struct napi_struct napi;
382 spinlock_t lock; /* spin lock flag */
383 u32 msg_enable;
384 int chipset;
385 int mac_version;
386 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
387 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
388 u32 dirty_rx;
389 u32 dirty_tx;
390 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
391 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
392 dma_addr_t TxPhyAddr;
393 dma_addr_t RxPhyAddr;
394 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
395 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
396 unsigned align;
397 unsigned rx_buf_sz;
398 struct timer_list timer;
399 u16 cp_cmd;
400 u16 intr_event;
401 u16 napi_event;
402 u16 intr_mask;
403 int phy_auto_nego_reg;
404 int phy_1000_ctrl_reg;
405 #ifdef CONFIG_R8169_VLAN
406 struct vlan_group *vlgrp;
407 #endif
408 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
409 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
410 void (*phy_reset_enable)(void __iomem *);
411 void (*hw_start)(struct net_device *);
412 unsigned int (*phy_reset_pending)(void __iomem *);
413 unsigned int (*link_ok)(void __iomem *);
414 struct delayed_work task;
415 unsigned features;
416 };
417
418 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
419 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
420 module_param(rx_copybreak, int, 0);
421 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
422 module_param(use_dac, int, 0);
423 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
424 module_param_named(debug, debug.msg_enable, int, 0);
425 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
426 MODULE_LICENSE("GPL");
427 MODULE_VERSION(RTL8169_VERSION);
428
429 static int rtl8169_open(struct net_device *dev);
430 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
431 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
432 static int rtl8169_init_ring(struct net_device *dev);
433 static void rtl_hw_start(struct net_device *dev);
434 static int rtl8169_close(struct net_device *dev);
435 static void rtl_set_rx_mode(struct net_device *dev);
436 static void rtl8169_tx_timeout(struct net_device *dev);
437 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
438 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
439 void __iomem *, u32 budget);
440 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
441 static void rtl8169_down(struct net_device *dev);
442 static void rtl8169_rx_clear(struct rtl8169_private *tp);
443 static int rtl8169_poll(struct napi_struct *napi, int budget);
444
445 static const unsigned int rtl8169_rx_config =
446 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
447
448 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
449 {
450 int i;
451
452 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
453
454 for (i = 20; i > 0; i--) {
455 /*
456 * Check if the RTL8169 has completed writing to the specified
457 * MII register.
458 */
459 if (!(RTL_R32(PHYAR) & 0x80000000))
460 break;
461 udelay(25);
462 }
463 }
464
465 static int mdio_read(void __iomem *ioaddr, int reg_addr)
466 {
467 int i, value = -1;
468
469 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
470
471 for (i = 20; i > 0; i--) {
472 /*
473 * Check if the RTL8169 has completed retrieving data from
474 * the specified MII register.
475 */
476 if (RTL_R32(PHYAR) & 0x80000000) {
477 value = RTL_R32(PHYAR) & 0xffff;
478 break;
479 }
480 udelay(25);
481 }
482 return value;
483 }
484
485 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
486 {
487 RTL_W16(IntrMask, 0x0000);
488
489 RTL_W16(IntrStatus, 0xffff);
490 }
491
492 static void rtl8169_asic_down(void __iomem *ioaddr)
493 {
494 RTL_W8(ChipCmd, 0x00);
495 rtl8169_irq_mask_and_ack(ioaddr);
496 RTL_R16(CPlusCmd);
497 }
498
499 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
500 {
501 return RTL_R32(TBICSR) & TBIReset;
502 }
503
504 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
505 {
506 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
507 }
508
509 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
510 {
511 return RTL_R32(TBICSR) & TBILinkOk;
512 }
513
514 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
515 {
516 return RTL_R8(PHYstatus) & LinkStatus;
517 }
518
519 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
520 {
521 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
522 }
523
524 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
525 {
526 unsigned int val;
527
528 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
529 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
530 }
531
532 static void rtl8169_check_link_status(struct net_device *dev,
533 struct rtl8169_private *tp,
534 void __iomem *ioaddr)
535 {
536 unsigned long flags;
537
538 spin_lock_irqsave(&tp->lock, flags);
539 if (tp->link_ok(ioaddr)) {
540 netif_carrier_on(dev);
541 if (netif_msg_ifup(tp))
542 printk(KERN_INFO PFX "%s: link up\n", dev->name);
543 } else {
544 if (netif_msg_ifdown(tp))
545 printk(KERN_INFO PFX "%s: link down\n", dev->name);
546 netif_carrier_off(dev);
547 }
548 spin_unlock_irqrestore(&tp->lock, flags);
549 }
550
551 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
552 {
553 struct rtl8169_private *tp = netdev_priv(dev);
554 void __iomem *ioaddr = tp->mmio_addr;
555 u8 options;
556
557 wol->wolopts = 0;
558
559 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
560 wol->supported = WAKE_ANY;
561
562 spin_lock_irq(&tp->lock);
563
564 options = RTL_R8(Config1);
565 if (!(options & PMEnable))
566 goto out_unlock;
567
568 options = RTL_R8(Config3);
569 if (options & LinkUp)
570 wol->wolopts |= WAKE_PHY;
571 if (options & MagicPacket)
572 wol->wolopts |= WAKE_MAGIC;
573
574 options = RTL_R8(Config5);
575 if (options & UWF)
576 wol->wolopts |= WAKE_UCAST;
577 if (options & BWF)
578 wol->wolopts |= WAKE_BCAST;
579 if (options & MWF)
580 wol->wolopts |= WAKE_MCAST;
581
582 out_unlock:
583 spin_unlock_irq(&tp->lock);
584 }
585
586 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
587 {
588 struct rtl8169_private *tp = netdev_priv(dev);
589 void __iomem *ioaddr = tp->mmio_addr;
590 unsigned int i;
591 static struct {
592 u32 opt;
593 u16 reg;
594 u8 mask;
595 } cfg[] = {
596 { WAKE_ANY, Config1, PMEnable },
597 { WAKE_PHY, Config3, LinkUp },
598 { WAKE_MAGIC, Config3, MagicPacket },
599 { WAKE_UCAST, Config5, UWF },
600 { WAKE_BCAST, Config5, BWF },
601 { WAKE_MCAST, Config5, MWF },
602 { WAKE_ANY, Config5, LanWake }
603 };
604
605 spin_lock_irq(&tp->lock);
606
607 RTL_W8(Cfg9346, Cfg9346_Unlock);
608
609 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
610 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
611 if (wol->wolopts & cfg[i].opt)
612 options |= cfg[i].mask;
613 RTL_W8(cfg[i].reg, options);
614 }
615
616 RTL_W8(Cfg9346, Cfg9346_Lock);
617
618 if (wol->wolopts)
619 tp->features |= RTL_FEATURE_WOL;
620 else
621 tp->features &= ~RTL_FEATURE_WOL;
622
623 spin_unlock_irq(&tp->lock);
624
625 return 0;
626 }
627
628 static void rtl8169_get_drvinfo(struct net_device *dev,
629 struct ethtool_drvinfo *info)
630 {
631 struct rtl8169_private *tp = netdev_priv(dev);
632
633 strcpy(info->driver, MODULENAME);
634 strcpy(info->version, RTL8169_VERSION);
635 strcpy(info->bus_info, pci_name(tp->pci_dev));
636 }
637
638 static int rtl8169_get_regs_len(struct net_device *dev)
639 {
640 return R8169_REGS_SIZE;
641 }
642
643 static int rtl8169_set_speed_tbi(struct net_device *dev,
644 u8 autoneg, u16 speed, u8 duplex)
645 {
646 struct rtl8169_private *tp = netdev_priv(dev);
647 void __iomem *ioaddr = tp->mmio_addr;
648 int ret = 0;
649 u32 reg;
650
651 reg = RTL_R32(TBICSR);
652 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
653 (duplex == DUPLEX_FULL)) {
654 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
655 } else if (autoneg == AUTONEG_ENABLE)
656 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
657 else {
658 if (netif_msg_link(tp)) {
659 printk(KERN_WARNING "%s: "
660 "incorrect speed setting refused in TBI mode\n",
661 dev->name);
662 }
663 ret = -EOPNOTSUPP;
664 }
665
666 return ret;
667 }
668
669 static int rtl8169_set_speed_xmii(struct net_device *dev,
670 u8 autoneg, u16 speed, u8 duplex)
671 {
672 struct rtl8169_private *tp = netdev_priv(dev);
673 void __iomem *ioaddr = tp->mmio_addr;
674 int auto_nego, giga_ctrl;
675
676 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
677 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
678 ADVERTISE_100HALF | ADVERTISE_100FULL);
679 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
680 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
681
682 if (autoneg == AUTONEG_ENABLE) {
683 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
684 ADVERTISE_100HALF | ADVERTISE_100FULL);
685 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
686 } else {
687 if (speed == SPEED_10)
688 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
689 else if (speed == SPEED_100)
690 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
691 else if (speed == SPEED_1000)
692 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
693
694 if (duplex == DUPLEX_HALF)
695 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
696
697 if (duplex == DUPLEX_FULL)
698 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
699
700 /* This tweak comes straight from Realtek's driver. */
701 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
702 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
703 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
704 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
705 }
706 }
707
708 /* The 8100e/8101e do Fast Ethernet only. */
709 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
710 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
711 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
712 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
713 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
714 netif_msg_link(tp)) {
715 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
716 dev->name);
717 }
718 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
719 }
720
721 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
722
723 if ((tp->mac_version == RTL_GIGA_MAC_VER_12) ||
724 (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
725 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
726 mdio_write(ioaddr, 0x1f, 0x0000);
727 mdio_write(ioaddr, 0x0e, 0x0000);
728 }
729
730 tp->phy_auto_nego_reg = auto_nego;
731 tp->phy_1000_ctrl_reg = giga_ctrl;
732
733 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
734 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
735 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
736 return 0;
737 }
738
739 static int rtl8169_set_speed(struct net_device *dev,
740 u8 autoneg, u16 speed, u8 duplex)
741 {
742 struct rtl8169_private *tp = netdev_priv(dev);
743 int ret;
744
745 ret = tp->set_speed(dev, autoneg, speed, duplex);
746
747 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
748 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
749
750 return ret;
751 }
752
753 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
754 {
755 struct rtl8169_private *tp = netdev_priv(dev);
756 unsigned long flags;
757 int ret;
758
759 spin_lock_irqsave(&tp->lock, flags);
760 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
761 spin_unlock_irqrestore(&tp->lock, flags);
762
763 return ret;
764 }
765
766 static u32 rtl8169_get_rx_csum(struct net_device *dev)
767 {
768 struct rtl8169_private *tp = netdev_priv(dev);
769
770 return tp->cp_cmd & RxChkSum;
771 }
772
773 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
774 {
775 struct rtl8169_private *tp = netdev_priv(dev);
776 void __iomem *ioaddr = tp->mmio_addr;
777 unsigned long flags;
778
779 spin_lock_irqsave(&tp->lock, flags);
780
781 if (data)
782 tp->cp_cmd |= RxChkSum;
783 else
784 tp->cp_cmd &= ~RxChkSum;
785
786 RTL_W16(CPlusCmd, tp->cp_cmd);
787 RTL_R16(CPlusCmd);
788
789 spin_unlock_irqrestore(&tp->lock, flags);
790
791 return 0;
792 }
793
794 #ifdef CONFIG_R8169_VLAN
795
796 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
797 struct sk_buff *skb)
798 {
799 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
800 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
801 }
802
803 static void rtl8169_vlan_rx_register(struct net_device *dev,
804 struct vlan_group *grp)
805 {
806 struct rtl8169_private *tp = netdev_priv(dev);
807 void __iomem *ioaddr = tp->mmio_addr;
808 unsigned long flags;
809
810 spin_lock_irqsave(&tp->lock, flags);
811 tp->vlgrp = grp;
812 if (tp->vlgrp)
813 tp->cp_cmd |= RxVlan;
814 else
815 tp->cp_cmd &= ~RxVlan;
816 RTL_W16(CPlusCmd, tp->cp_cmd);
817 RTL_R16(CPlusCmd);
818 spin_unlock_irqrestore(&tp->lock, flags);
819 }
820
821 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
822 struct sk_buff *skb)
823 {
824 u32 opts2 = le32_to_cpu(desc->opts2);
825 struct vlan_group *vlgrp = tp->vlgrp;
826 int ret;
827
828 if (vlgrp && (opts2 & RxVlanTag)) {
829 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
830 ret = 0;
831 } else
832 ret = -1;
833 desc->opts2 = 0;
834 return ret;
835 }
836
837 #else /* !CONFIG_R8169_VLAN */
838
839 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
840 struct sk_buff *skb)
841 {
842 return 0;
843 }
844
845 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
846 struct sk_buff *skb)
847 {
848 return -1;
849 }
850
851 #endif
852
853 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
854 {
855 struct rtl8169_private *tp = netdev_priv(dev);
856 void __iomem *ioaddr = tp->mmio_addr;
857 u32 status;
858
859 cmd->supported =
860 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
861 cmd->port = PORT_FIBRE;
862 cmd->transceiver = XCVR_INTERNAL;
863
864 status = RTL_R32(TBICSR);
865 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
866 cmd->autoneg = !!(status & TBINwEnable);
867
868 cmd->speed = SPEED_1000;
869 cmd->duplex = DUPLEX_FULL; /* Always set */
870 }
871
872 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
873 {
874 struct rtl8169_private *tp = netdev_priv(dev);
875 void __iomem *ioaddr = tp->mmio_addr;
876 u8 status;
877
878 cmd->supported = SUPPORTED_10baseT_Half |
879 SUPPORTED_10baseT_Full |
880 SUPPORTED_100baseT_Half |
881 SUPPORTED_100baseT_Full |
882 SUPPORTED_1000baseT_Full |
883 SUPPORTED_Autoneg |
884 SUPPORTED_TP;
885
886 cmd->autoneg = 1;
887 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
888
889 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
890 cmd->advertising |= ADVERTISED_10baseT_Half;
891 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
892 cmd->advertising |= ADVERTISED_10baseT_Full;
893 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
894 cmd->advertising |= ADVERTISED_100baseT_Half;
895 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
896 cmd->advertising |= ADVERTISED_100baseT_Full;
897 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
898 cmd->advertising |= ADVERTISED_1000baseT_Full;
899
900 status = RTL_R8(PHYstatus);
901
902 if (status & _1000bpsF)
903 cmd->speed = SPEED_1000;
904 else if (status & _100bps)
905 cmd->speed = SPEED_100;
906 else if (status & _10bps)
907 cmd->speed = SPEED_10;
908
909 if (status & TxFlowCtrl)
910 cmd->advertising |= ADVERTISED_Asym_Pause;
911 if (status & RxFlowCtrl)
912 cmd->advertising |= ADVERTISED_Pause;
913
914 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
915 DUPLEX_FULL : DUPLEX_HALF;
916 }
917
918 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
919 {
920 struct rtl8169_private *tp = netdev_priv(dev);
921 unsigned long flags;
922
923 spin_lock_irqsave(&tp->lock, flags);
924
925 tp->get_settings(dev, cmd);
926
927 spin_unlock_irqrestore(&tp->lock, flags);
928 return 0;
929 }
930
931 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
932 void *p)
933 {
934 struct rtl8169_private *tp = netdev_priv(dev);
935 unsigned long flags;
936
937 if (regs->len > R8169_REGS_SIZE)
938 regs->len = R8169_REGS_SIZE;
939
940 spin_lock_irqsave(&tp->lock, flags);
941 memcpy_fromio(p, tp->mmio_addr, regs->len);
942 spin_unlock_irqrestore(&tp->lock, flags);
943 }
944
945 static u32 rtl8169_get_msglevel(struct net_device *dev)
946 {
947 struct rtl8169_private *tp = netdev_priv(dev);
948
949 return tp->msg_enable;
950 }
951
952 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
953 {
954 struct rtl8169_private *tp = netdev_priv(dev);
955
956 tp->msg_enable = value;
957 }
958
959 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
960 "tx_packets",
961 "rx_packets",
962 "tx_errors",
963 "rx_errors",
964 "rx_missed",
965 "align_errors",
966 "tx_single_collisions",
967 "tx_multi_collisions",
968 "unicast",
969 "broadcast",
970 "multicast",
971 "tx_aborted",
972 "tx_underrun",
973 };
974
975 struct rtl8169_counters {
976 __le64 tx_packets;
977 __le64 rx_packets;
978 __le64 tx_errors;
979 __le32 rx_errors;
980 __le16 rx_missed;
981 __le16 align_errors;
982 __le32 tx_one_collision;
983 __le32 tx_multi_collision;
984 __le64 rx_unicast;
985 __le64 rx_broadcast;
986 __le32 rx_multicast;
987 __le16 tx_aborted;
988 __le16 tx_underun;
989 };
990
991 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
992 {
993 switch (sset) {
994 case ETH_SS_STATS:
995 return ARRAY_SIZE(rtl8169_gstrings);
996 default:
997 return -EOPNOTSUPP;
998 }
999 }
1000
1001 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1002 struct ethtool_stats *stats, u64 *data)
1003 {
1004 struct rtl8169_private *tp = netdev_priv(dev);
1005 void __iomem *ioaddr = tp->mmio_addr;
1006 struct rtl8169_counters *counters;
1007 dma_addr_t paddr;
1008 u32 cmd;
1009
1010 ASSERT_RTNL();
1011
1012 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1013 if (!counters)
1014 return;
1015
1016 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1017 cmd = (u64)paddr & DMA_32BIT_MASK;
1018 RTL_W32(CounterAddrLow, cmd);
1019 RTL_W32(CounterAddrLow, cmd | CounterDump);
1020
1021 while (RTL_R32(CounterAddrLow) & CounterDump) {
1022 if (msleep_interruptible(1))
1023 break;
1024 }
1025
1026 RTL_W32(CounterAddrLow, 0);
1027 RTL_W32(CounterAddrHigh, 0);
1028
1029 data[0] = le64_to_cpu(counters->tx_packets);
1030 data[1] = le64_to_cpu(counters->rx_packets);
1031 data[2] = le64_to_cpu(counters->tx_errors);
1032 data[3] = le32_to_cpu(counters->rx_errors);
1033 data[4] = le16_to_cpu(counters->rx_missed);
1034 data[5] = le16_to_cpu(counters->align_errors);
1035 data[6] = le32_to_cpu(counters->tx_one_collision);
1036 data[7] = le32_to_cpu(counters->tx_multi_collision);
1037 data[8] = le64_to_cpu(counters->rx_unicast);
1038 data[9] = le64_to_cpu(counters->rx_broadcast);
1039 data[10] = le32_to_cpu(counters->rx_multicast);
1040 data[11] = le16_to_cpu(counters->tx_aborted);
1041 data[12] = le16_to_cpu(counters->tx_underun);
1042
1043 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1044 }
1045
1046 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1047 {
1048 switch(stringset) {
1049 case ETH_SS_STATS:
1050 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1051 break;
1052 }
1053 }
1054
1055 static const struct ethtool_ops rtl8169_ethtool_ops = {
1056 .get_drvinfo = rtl8169_get_drvinfo,
1057 .get_regs_len = rtl8169_get_regs_len,
1058 .get_link = ethtool_op_get_link,
1059 .get_settings = rtl8169_get_settings,
1060 .set_settings = rtl8169_set_settings,
1061 .get_msglevel = rtl8169_get_msglevel,
1062 .set_msglevel = rtl8169_set_msglevel,
1063 .get_rx_csum = rtl8169_get_rx_csum,
1064 .set_rx_csum = rtl8169_set_rx_csum,
1065 .set_tx_csum = ethtool_op_set_tx_csum,
1066 .set_sg = ethtool_op_set_sg,
1067 .set_tso = ethtool_op_set_tso,
1068 .get_regs = rtl8169_get_regs,
1069 .get_wol = rtl8169_get_wol,
1070 .set_wol = rtl8169_set_wol,
1071 .get_strings = rtl8169_get_strings,
1072 .get_sset_count = rtl8169_get_sset_count,
1073 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1074 };
1075
1076 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1077 int bitnum, int bitval)
1078 {
1079 int val;
1080
1081 val = mdio_read(ioaddr, reg);
1082 val = (bitval == 1) ?
1083 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1084 mdio_write(ioaddr, reg, val & 0xffff);
1085 }
1086
1087 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1088 void __iomem *ioaddr)
1089 {
1090 /*
1091 * The driver currently handles the 8168Bf and the 8168Be identically
1092 * but they can be identified more specifically through the test below
1093 * if needed:
1094 *
1095 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1096 *
1097 * Same thing for the 8101Eb and the 8101Ec:
1098 *
1099 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1100 */
1101 const struct {
1102 u32 mask;
1103 u32 val;
1104 int mac_version;
1105 } mac_info[] = {
1106 /* 8168B family. */
1107 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1108 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1109 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1110 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
1111
1112 /* 8168B family. */
1113 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1114 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1115 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1116 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1117
1118 /* 8101 family. */
1119 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1120 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1121 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1122 /* FIXME: where did these entries come from ? -- FR */
1123 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1124 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1125
1126 /* 8110 family. */
1127 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1128 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1129 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1130 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1131 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1132 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1133
1134 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1135 }, *p = mac_info;
1136 u32 reg;
1137
1138 reg = RTL_R32(TxConfig);
1139 while ((reg & p->mask) != p->val)
1140 p++;
1141 tp->mac_version = p->mac_version;
1142
1143 if (p->mask == 0x00000000) {
1144 struct pci_dev *pdev = tp->pci_dev;
1145
1146 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1147 }
1148 }
1149
1150 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1151 {
1152 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1153 }
1154
1155 struct phy_reg {
1156 u16 reg;
1157 u16 val;
1158 };
1159
1160 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1161 {
1162 while (len-- > 0) {
1163 mdio_write(ioaddr, regs->reg, regs->val);
1164 regs++;
1165 }
1166 }
1167
1168 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1169 {
1170 struct {
1171 u16 regs[5]; /* Beware of bit-sign propagation */
1172 } phy_magic[5] = { {
1173 { 0x0000, //w 4 15 12 0
1174 0x00a1, //w 3 15 0 00a1
1175 0x0008, //w 2 15 0 0008
1176 0x1020, //w 1 15 0 1020
1177 0x1000 } },{ //w 0 15 0 1000
1178 { 0x7000, //w 4 15 12 7
1179 0xff41, //w 3 15 0 ff41
1180 0xde60, //w 2 15 0 de60
1181 0x0140, //w 1 15 0 0140
1182 0x0077 } },{ //w 0 15 0 0077
1183 { 0xa000, //w 4 15 12 a
1184 0xdf01, //w 3 15 0 df01
1185 0xdf20, //w 2 15 0 df20
1186 0xff95, //w 1 15 0 ff95
1187 0xfa00 } },{ //w 0 15 0 fa00
1188 { 0xb000, //w 4 15 12 b
1189 0xff41, //w 3 15 0 ff41
1190 0xde20, //w 2 15 0 de20
1191 0x0140, //w 1 15 0 0140
1192 0x00bb } },{ //w 0 15 0 00bb
1193 { 0xf000, //w 4 15 12 f
1194 0xdf01, //w 3 15 0 df01
1195 0xdf20, //w 2 15 0 df20
1196 0xff95, //w 1 15 0 ff95
1197 0xbf00 } //w 0 15 0 bf00
1198 }
1199 }, *p = phy_magic;
1200 unsigned int i;
1201
1202 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1203 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1204 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1205 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1206
1207 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1208 int val, pos = 4;
1209
1210 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1211 mdio_write(ioaddr, pos, val);
1212 while (--pos >= 0)
1213 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1214 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1215 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1216 }
1217 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1218 }
1219
1220 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1221 {
1222 struct phy_reg phy_reg_init[] = {
1223 { 0x1f, 0x0002 },
1224 { 0x01, 0x90d0 },
1225 { 0x1f, 0x0000 }
1226 };
1227
1228 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1229 }
1230
1231 static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
1232 {
1233 struct phy_reg phy_reg_init[] = {
1234 { 0x1f, 0x0000 },
1235 { 0x1d, 0x0f00 },
1236 { 0x1f, 0x0002 },
1237 { 0x0c, 0x1ec8 },
1238 { 0x1f, 0x0000 }
1239 };
1240
1241 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1242 }
1243
1244 static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
1245 {
1246 struct phy_reg phy_reg_init[] = {
1247 { 0x1f, 0x0001 },
1248 { 0x12, 0x2300 },
1249 { 0x1f, 0x0002 },
1250 { 0x00, 0x88d4 },
1251 { 0x01, 0x82b1 },
1252 { 0x03, 0x7002 },
1253 { 0x08, 0x9e30 },
1254 { 0x09, 0x01f0 },
1255 { 0x0a, 0x5500 },
1256 { 0x0c, 0x00c8 },
1257 { 0x1f, 0x0003 },
1258 { 0x12, 0xc096 },
1259 { 0x16, 0x000a },
1260 { 0x1f, 0x0000 }
1261 };
1262
1263 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1264 }
1265
1266 static void rtl8168cx_hw_phy_config(void __iomem *ioaddr)
1267 {
1268 struct phy_reg phy_reg_init[] = {
1269 { 0x1f, 0x0000 },
1270 { 0x12, 0x2300 },
1271 { 0x1f, 0x0003 },
1272 { 0x16, 0x0f0a },
1273 { 0x1f, 0x0000 },
1274 { 0x1f, 0x0002 },
1275 { 0x0c, 0x7eb8 },
1276 { 0x1f, 0x0000 }
1277 };
1278
1279 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1280 }
1281
1282 static void rtl_hw_phy_config(struct net_device *dev)
1283 {
1284 struct rtl8169_private *tp = netdev_priv(dev);
1285 void __iomem *ioaddr = tp->mmio_addr;
1286
1287 rtl8169_print_mac_version(tp);
1288
1289 switch (tp->mac_version) {
1290 case RTL_GIGA_MAC_VER_01:
1291 break;
1292 case RTL_GIGA_MAC_VER_02:
1293 case RTL_GIGA_MAC_VER_03:
1294 rtl8169s_hw_phy_config(ioaddr);
1295 break;
1296 case RTL_GIGA_MAC_VER_04:
1297 rtl8169sb_hw_phy_config(ioaddr);
1298 break;
1299 case RTL_GIGA_MAC_VER_18:
1300 rtl8168cp_hw_phy_config(ioaddr);
1301 break;
1302 case RTL_GIGA_MAC_VER_19:
1303 rtl8168c_hw_phy_config(ioaddr);
1304 break;
1305 case RTL_GIGA_MAC_VER_20:
1306 rtl8168cx_hw_phy_config(ioaddr);
1307 break;
1308 default:
1309 break;
1310 }
1311 }
1312
1313 static void rtl8169_phy_timer(unsigned long __opaque)
1314 {
1315 struct net_device *dev = (struct net_device *)__opaque;
1316 struct rtl8169_private *tp = netdev_priv(dev);
1317 struct timer_list *timer = &tp->timer;
1318 void __iomem *ioaddr = tp->mmio_addr;
1319 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1320
1321 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1322
1323 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1324 return;
1325
1326 spin_lock_irq(&tp->lock);
1327
1328 if (tp->phy_reset_pending(ioaddr)) {
1329 /*
1330 * A busy loop could burn quite a few cycles on nowadays CPU.
1331 * Let's delay the execution of the timer for a few ticks.
1332 */
1333 timeout = HZ/10;
1334 goto out_mod_timer;
1335 }
1336
1337 if (tp->link_ok(ioaddr))
1338 goto out_unlock;
1339
1340 if (netif_msg_link(tp))
1341 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1342
1343 tp->phy_reset_enable(ioaddr);
1344
1345 out_mod_timer:
1346 mod_timer(timer, jiffies + timeout);
1347 out_unlock:
1348 spin_unlock_irq(&tp->lock);
1349 }
1350
1351 static inline void rtl8169_delete_timer(struct net_device *dev)
1352 {
1353 struct rtl8169_private *tp = netdev_priv(dev);
1354 struct timer_list *timer = &tp->timer;
1355
1356 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1357 return;
1358
1359 del_timer_sync(timer);
1360 }
1361
1362 static inline void rtl8169_request_timer(struct net_device *dev)
1363 {
1364 struct rtl8169_private *tp = netdev_priv(dev);
1365 struct timer_list *timer = &tp->timer;
1366
1367 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1368 return;
1369
1370 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1371 }
1372
1373 #ifdef CONFIG_NET_POLL_CONTROLLER
1374 /*
1375 * Polling 'interrupt' - used by things like netconsole to send skbs
1376 * without having to re-enable interrupts. It's not called while
1377 * the interrupt routine is executing.
1378 */
1379 static void rtl8169_netpoll(struct net_device *dev)
1380 {
1381 struct rtl8169_private *tp = netdev_priv(dev);
1382 struct pci_dev *pdev = tp->pci_dev;
1383
1384 disable_irq(pdev->irq);
1385 rtl8169_interrupt(pdev->irq, dev);
1386 enable_irq(pdev->irq);
1387 }
1388 #endif
1389
1390 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1391 void __iomem *ioaddr)
1392 {
1393 iounmap(ioaddr);
1394 pci_release_regions(pdev);
1395 pci_disable_device(pdev);
1396 free_netdev(dev);
1397 }
1398
1399 static void rtl8169_phy_reset(struct net_device *dev,
1400 struct rtl8169_private *tp)
1401 {
1402 void __iomem *ioaddr = tp->mmio_addr;
1403 unsigned int i;
1404
1405 tp->phy_reset_enable(ioaddr);
1406 for (i = 0; i < 100; i++) {
1407 if (!tp->phy_reset_pending(ioaddr))
1408 return;
1409 msleep(1);
1410 }
1411 if (netif_msg_link(tp))
1412 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1413 }
1414
1415 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1416 {
1417 void __iomem *ioaddr = tp->mmio_addr;
1418
1419 rtl_hw_phy_config(dev);
1420
1421 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1422 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1423 RTL_W8(0x82, 0x01);
1424 }
1425
1426 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1427
1428 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1429 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1430
1431 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1432 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1433 RTL_W8(0x82, 0x01);
1434 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1435 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1436 }
1437
1438 rtl8169_phy_reset(dev, tp);
1439
1440 /*
1441 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1442 * only 8101. Don't panic.
1443 */
1444 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1445
1446 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1447 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1448 }
1449
1450 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1451 {
1452 void __iomem *ioaddr = tp->mmio_addr;
1453 u32 high;
1454 u32 low;
1455
1456 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1457 high = addr[4] | (addr[5] << 8);
1458
1459 spin_lock_irq(&tp->lock);
1460
1461 RTL_W8(Cfg9346, Cfg9346_Unlock);
1462 RTL_W32(MAC0, low);
1463 RTL_W32(MAC4, high);
1464 RTL_W8(Cfg9346, Cfg9346_Lock);
1465
1466 spin_unlock_irq(&tp->lock);
1467 }
1468
1469 static int rtl_set_mac_address(struct net_device *dev, void *p)
1470 {
1471 struct rtl8169_private *tp = netdev_priv(dev);
1472 struct sockaddr *addr = p;
1473
1474 if (!is_valid_ether_addr(addr->sa_data))
1475 return -EADDRNOTAVAIL;
1476
1477 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1478
1479 rtl_rar_set(tp, dev->dev_addr);
1480
1481 return 0;
1482 }
1483
1484 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1485 {
1486 struct rtl8169_private *tp = netdev_priv(dev);
1487 struct mii_ioctl_data *data = if_mii(ifr);
1488
1489 if (!netif_running(dev))
1490 return -ENODEV;
1491
1492 switch (cmd) {
1493 case SIOCGMIIPHY:
1494 data->phy_id = 32; /* Internal PHY */
1495 return 0;
1496
1497 case SIOCGMIIREG:
1498 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1499 return 0;
1500
1501 case SIOCSMIIREG:
1502 if (!capable(CAP_NET_ADMIN))
1503 return -EPERM;
1504 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1505 return 0;
1506 }
1507 return -EOPNOTSUPP;
1508 }
1509
1510 static const struct rtl_cfg_info {
1511 void (*hw_start)(struct net_device *);
1512 unsigned int region;
1513 unsigned int align;
1514 u16 intr_event;
1515 u16 napi_event;
1516 unsigned msi;
1517 } rtl_cfg_infos [] = {
1518 [RTL_CFG_0] = {
1519 .hw_start = rtl_hw_start_8169,
1520 .region = 1,
1521 .align = 0,
1522 .intr_event = SYSErr | LinkChg | RxOverflow |
1523 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1524 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1525 .msi = 0
1526 },
1527 [RTL_CFG_1] = {
1528 .hw_start = rtl_hw_start_8168,
1529 .region = 2,
1530 .align = 8,
1531 .intr_event = SYSErr | LinkChg | RxOverflow |
1532 TxErr | TxOK | RxOK | RxErr,
1533 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
1534 .msi = RTL_FEATURE_MSI
1535 },
1536 [RTL_CFG_2] = {
1537 .hw_start = rtl_hw_start_8101,
1538 .region = 2,
1539 .align = 8,
1540 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1541 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1542 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1543 .msi = RTL_FEATURE_MSI
1544 }
1545 };
1546
1547 /* Cfg9346_Unlock assumed. */
1548 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1549 const struct rtl_cfg_info *cfg)
1550 {
1551 unsigned msi = 0;
1552 u8 cfg2;
1553
1554 cfg2 = RTL_R8(Config2) & ~MSIEnable;
1555 if (cfg->msi) {
1556 if (pci_enable_msi(pdev)) {
1557 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1558 } else {
1559 cfg2 |= MSIEnable;
1560 msi = RTL_FEATURE_MSI;
1561 }
1562 }
1563 RTL_W8(Config2, cfg2);
1564 return msi;
1565 }
1566
1567 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1568 {
1569 if (tp->features & RTL_FEATURE_MSI) {
1570 pci_disable_msi(pdev);
1571 tp->features &= ~RTL_FEATURE_MSI;
1572 }
1573 }
1574
1575 static int __devinit
1576 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1577 {
1578 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1579 const unsigned int region = cfg->region;
1580 struct rtl8169_private *tp;
1581 struct net_device *dev;
1582 void __iomem *ioaddr;
1583 unsigned int i;
1584 int rc;
1585
1586 if (netif_msg_drv(&debug)) {
1587 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1588 MODULENAME, RTL8169_VERSION);
1589 }
1590
1591 dev = alloc_etherdev(sizeof (*tp));
1592 if (!dev) {
1593 if (netif_msg_drv(&debug))
1594 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
1595 rc = -ENOMEM;
1596 goto out;
1597 }
1598
1599 SET_NETDEV_DEV(dev, &pdev->dev);
1600 tp = netdev_priv(dev);
1601 tp->dev = dev;
1602 tp->pci_dev = pdev;
1603 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1604
1605 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1606 rc = pci_enable_device(pdev);
1607 if (rc < 0) {
1608 if (netif_msg_probe(tp))
1609 dev_err(&pdev->dev, "enable failure\n");
1610 goto err_out_free_dev_1;
1611 }
1612
1613 rc = pci_set_mwi(pdev);
1614 if (rc < 0)
1615 goto err_out_disable_2;
1616
1617 /* make sure PCI base addr 1 is MMIO */
1618 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
1619 if (netif_msg_probe(tp)) {
1620 dev_err(&pdev->dev,
1621 "region #%d not an MMIO resource, aborting\n",
1622 region);
1623 }
1624 rc = -ENODEV;
1625 goto err_out_mwi_3;
1626 }
1627
1628 /* check for weird/broken PCI region reporting */
1629 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
1630 if (netif_msg_probe(tp)) {
1631 dev_err(&pdev->dev,
1632 "Invalid PCI region size(s), aborting\n");
1633 }
1634 rc = -ENODEV;
1635 goto err_out_mwi_3;
1636 }
1637
1638 rc = pci_request_regions(pdev, MODULENAME);
1639 if (rc < 0) {
1640 if (netif_msg_probe(tp))
1641 dev_err(&pdev->dev, "could not request regions.\n");
1642 goto err_out_mwi_3;
1643 }
1644
1645 tp->cp_cmd = PCIMulRW | RxChkSum;
1646
1647 if ((sizeof(dma_addr_t) > 4) &&
1648 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1649 tp->cp_cmd |= PCIDAC;
1650 dev->features |= NETIF_F_HIGHDMA;
1651 } else {
1652 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1653 if (rc < 0) {
1654 if (netif_msg_probe(tp)) {
1655 dev_err(&pdev->dev,
1656 "DMA configuration failed.\n");
1657 }
1658 goto err_out_free_res_4;
1659 }
1660 }
1661
1662 pci_set_master(pdev);
1663
1664 /* ioremap MMIO region */
1665 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
1666 if (!ioaddr) {
1667 if (netif_msg_probe(tp))
1668 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1669 rc = -EIO;
1670 goto err_out_free_res_4;
1671 }
1672
1673 /* Unneeded ? Don't mess with Mrs. Murphy. */
1674 rtl8169_irq_mask_and_ack(ioaddr);
1675
1676 /* Soft reset the chip. */
1677 RTL_W8(ChipCmd, CmdReset);
1678
1679 /* Check that the chip has finished the reset. */
1680 for (i = 0; i < 100; i++) {
1681 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1682 break;
1683 msleep_interruptible(1);
1684 }
1685
1686 /* Identify chip attached to board */
1687 rtl8169_get_mac_version(tp, ioaddr);
1688
1689 rtl8169_print_mac_version(tp);
1690
1691 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1692 if (tp->mac_version == rtl_chip_info[i].mac_version)
1693 break;
1694 }
1695 if (i == ARRAY_SIZE(rtl_chip_info)) {
1696 /* Unknown chip: assume array element #0, original RTL-8169 */
1697 if (netif_msg_probe(tp)) {
1698 dev_printk(KERN_DEBUG, &pdev->dev,
1699 "unknown chip version, assuming %s\n",
1700 rtl_chip_info[0].name);
1701 }
1702 i = 0;
1703 }
1704 tp->chipset = i;
1705
1706 RTL_W8(Cfg9346, Cfg9346_Unlock);
1707 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1708 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1709 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
1710 RTL_W8(Cfg9346, Cfg9346_Lock);
1711
1712 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
1713 (RTL_R8(PHYstatus) & TBI_Enable)) {
1714 tp->set_speed = rtl8169_set_speed_tbi;
1715 tp->get_settings = rtl8169_gset_tbi;
1716 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1717 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1718 tp->link_ok = rtl8169_tbi_link_ok;
1719
1720 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1721 } else {
1722 tp->set_speed = rtl8169_set_speed_xmii;
1723 tp->get_settings = rtl8169_gset_xmii;
1724 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1725 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1726 tp->link_ok = rtl8169_xmii_link_ok;
1727
1728 dev->do_ioctl = rtl8169_ioctl;
1729 }
1730
1731 /* Get MAC address. FIXME: read EEPROM */
1732 for (i = 0; i < MAC_ADDR_LEN; i++)
1733 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1734 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1735
1736 dev->open = rtl8169_open;
1737 dev->hard_start_xmit = rtl8169_start_xmit;
1738 dev->get_stats = rtl8169_get_stats;
1739 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1740 dev->stop = rtl8169_close;
1741 dev->tx_timeout = rtl8169_tx_timeout;
1742 dev->set_multicast_list = rtl_set_rx_mode;
1743 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1744 dev->irq = pdev->irq;
1745 dev->base_addr = (unsigned long) ioaddr;
1746 dev->change_mtu = rtl8169_change_mtu;
1747 dev->set_mac_address = rtl_set_mac_address;
1748
1749 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1750
1751 #ifdef CONFIG_R8169_VLAN
1752 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1753 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1754 #endif
1755
1756 #ifdef CONFIG_NET_POLL_CONTROLLER
1757 dev->poll_controller = rtl8169_netpoll;
1758 #endif
1759
1760 tp->intr_mask = 0xffff;
1761 tp->mmio_addr = ioaddr;
1762 tp->align = cfg->align;
1763 tp->hw_start = cfg->hw_start;
1764 tp->intr_event = cfg->intr_event;
1765 tp->napi_event = cfg->napi_event;
1766
1767 init_timer(&tp->timer);
1768 tp->timer.data = (unsigned long) dev;
1769 tp->timer.function = rtl8169_phy_timer;
1770
1771 spin_lock_init(&tp->lock);
1772
1773 rc = register_netdev(dev);
1774 if (rc < 0)
1775 goto err_out_msi_5;
1776
1777 pci_set_drvdata(pdev, dev);
1778
1779 if (netif_msg_probe(tp)) {
1780 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1781
1782 printk(KERN_INFO "%s: %s at 0x%lx, "
1783 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1784 "XID %08x IRQ %d\n",
1785 dev->name,
1786 rtl_chip_info[tp->chipset].name,
1787 dev->base_addr,
1788 dev->dev_addr[0], dev->dev_addr[1],
1789 dev->dev_addr[2], dev->dev_addr[3],
1790 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
1791 }
1792
1793 rtl8169_init_phy(dev, tp);
1794
1795 out:
1796 return rc;
1797
1798 err_out_msi_5:
1799 rtl_disable_msi(pdev, tp);
1800 iounmap(ioaddr);
1801 err_out_free_res_4:
1802 pci_release_regions(pdev);
1803 err_out_mwi_3:
1804 pci_clear_mwi(pdev);
1805 err_out_disable_2:
1806 pci_disable_device(pdev);
1807 err_out_free_dev_1:
1808 free_netdev(dev);
1809 goto out;
1810 }
1811
1812 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1813 {
1814 struct net_device *dev = pci_get_drvdata(pdev);
1815 struct rtl8169_private *tp = netdev_priv(dev);
1816
1817 flush_scheduled_work();
1818
1819 unregister_netdev(dev);
1820 rtl_disable_msi(pdev, tp);
1821 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1822 pci_set_drvdata(pdev, NULL);
1823 }
1824
1825 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1826 struct net_device *dev)
1827 {
1828 unsigned int mtu = dev->mtu;
1829
1830 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1831 }
1832
1833 static int rtl8169_open(struct net_device *dev)
1834 {
1835 struct rtl8169_private *tp = netdev_priv(dev);
1836 struct pci_dev *pdev = tp->pci_dev;
1837 int retval = -ENOMEM;
1838
1839
1840 rtl8169_set_rxbufsize(tp, dev);
1841
1842 /*
1843 * Rx and Tx desscriptors needs 256 bytes alignment.
1844 * pci_alloc_consistent provides more.
1845 */
1846 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1847 &tp->TxPhyAddr);
1848 if (!tp->TxDescArray)
1849 goto out;
1850
1851 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1852 &tp->RxPhyAddr);
1853 if (!tp->RxDescArray)
1854 goto err_free_tx_0;
1855
1856 retval = rtl8169_init_ring(dev);
1857 if (retval < 0)
1858 goto err_free_rx_1;
1859
1860 INIT_DELAYED_WORK(&tp->task, NULL);
1861
1862 smp_mb();
1863
1864 retval = request_irq(dev->irq, rtl8169_interrupt,
1865 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
1866 dev->name, dev);
1867 if (retval < 0)
1868 goto err_release_ring_2;
1869
1870 napi_enable(&tp->napi);
1871
1872 rtl_hw_start(dev);
1873
1874 rtl8169_request_timer(dev);
1875
1876 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1877 out:
1878 return retval;
1879
1880 err_release_ring_2:
1881 rtl8169_rx_clear(tp);
1882 err_free_rx_1:
1883 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1884 tp->RxPhyAddr);
1885 err_free_tx_0:
1886 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1887 tp->TxPhyAddr);
1888 goto out;
1889 }
1890
1891 static void rtl8169_hw_reset(void __iomem *ioaddr)
1892 {
1893 /* Disable interrupts */
1894 rtl8169_irq_mask_and_ack(ioaddr);
1895
1896 /* Reset the chipset */
1897 RTL_W8(ChipCmd, CmdReset);
1898
1899 /* PCI commit */
1900 RTL_R8(ChipCmd);
1901 }
1902
1903 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
1904 {
1905 void __iomem *ioaddr = tp->mmio_addr;
1906 u32 cfg = rtl8169_rx_config;
1907
1908 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1909 RTL_W32(RxConfig, cfg);
1910
1911 /* Set DMA burst size and Interframe Gap Time */
1912 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1913 (InterFrameGap << TxInterFrameGapShift));
1914 }
1915
1916 static void rtl_hw_start(struct net_device *dev)
1917 {
1918 struct rtl8169_private *tp = netdev_priv(dev);
1919 void __iomem *ioaddr = tp->mmio_addr;
1920 unsigned int i;
1921
1922 /* Soft reset the chip. */
1923 RTL_W8(ChipCmd, CmdReset);
1924
1925 /* Check that the chip has finished the reset. */
1926 for (i = 0; i < 100; i++) {
1927 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1928 break;
1929 msleep_interruptible(1);
1930 }
1931
1932 tp->hw_start(dev);
1933
1934 netif_start_queue(dev);
1935 }
1936
1937
1938 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1939 void __iomem *ioaddr)
1940 {
1941 /*
1942 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1943 * register to be written before TxDescAddrLow to work.
1944 * Switching from MMIO to I/O access fixes the issue as well.
1945 */
1946 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1947 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1948 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1949 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1950 }
1951
1952 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1953 {
1954 u16 cmd;
1955
1956 cmd = RTL_R16(CPlusCmd);
1957 RTL_W16(CPlusCmd, cmd);
1958 return cmd;
1959 }
1960
1961 static void rtl_set_rx_max_size(void __iomem *ioaddr)
1962 {
1963 /* Low hurts. Let's disable the filtering. */
1964 RTL_W16(RxMaxSize, 16383);
1965 }
1966
1967 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1968 {
1969 struct {
1970 u32 mac_version;
1971 u32 clk;
1972 u32 val;
1973 } cfg2_info [] = {
1974 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1975 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1976 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1977 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1978 }, *p = cfg2_info;
1979 unsigned int i;
1980 u32 clk;
1981
1982 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1983 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
1984 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1985 RTL_W32(0x7c, p->val);
1986 break;
1987 }
1988 }
1989 }
1990
1991 static void rtl_hw_start_8169(struct net_device *dev)
1992 {
1993 struct rtl8169_private *tp = netdev_priv(dev);
1994 void __iomem *ioaddr = tp->mmio_addr;
1995 struct pci_dev *pdev = tp->pci_dev;
1996
1997 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1998 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1999 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2000 }
2001
2002 RTL_W8(Cfg9346, Cfg9346_Unlock);
2003 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2004 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2005 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2006 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2007 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2008
2009 RTL_W8(EarlyTxThres, EarlyTxThld);
2010
2011 rtl_set_rx_max_size(ioaddr);
2012
2013 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2014 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2015 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2016 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2017 rtl_set_rx_tx_config_registers(tp);
2018
2019 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2020
2021 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2022 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2023 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2024 "Bit-3 and bit-14 MUST be 1\n");
2025 tp->cp_cmd |= (1 << 14);
2026 }
2027
2028 RTL_W16(CPlusCmd, tp->cp_cmd);
2029
2030 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2031
2032 /*
2033 * Undocumented corner. Supposedly:
2034 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2035 */
2036 RTL_W16(IntrMitigate, 0x0000);
2037
2038 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2039
2040 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2041 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2042 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2043 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2044 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2045 rtl_set_rx_tx_config_registers(tp);
2046 }
2047
2048 RTL_W8(Cfg9346, Cfg9346_Lock);
2049
2050 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2051 RTL_R8(IntrMask);
2052
2053 RTL_W32(RxMissed, 0);
2054
2055 rtl_set_rx_mode(dev);
2056
2057 /* no early-rx interrupts */
2058 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2059
2060 /* Enable all known interrupts by setting the interrupt mask. */
2061 RTL_W16(IntrMask, tp->intr_event);
2062 }
2063
2064 static void rtl_hw_start_8168(struct net_device *dev)
2065 {
2066 struct rtl8169_private *tp = netdev_priv(dev);
2067 void __iomem *ioaddr = tp->mmio_addr;
2068 struct pci_dev *pdev = tp->pci_dev;
2069 u8 ctl;
2070
2071 RTL_W8(Cfg9346, Cfg9346_Unlock);
2072
2073 RTL_W8(EarlyTxThres, EarlyTxThld);
2074
2075 rtl_set_rx_max_size(ioaddr);
2076
2077 rtl_set_rx_tx_config_registers(tp);
2078
2079 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2080
2081 RTL_W16(CPlusCmd, tp->cp_cmd);
2082
2083 /* Tx performance tweak. */
2084 pci_read_config_byte(pdev, 0x69, &ctl);
2085 ctl = (ctl & ~0x70) | 0x50;
2086 pci_write_config_byte(pdev, 0x69, ctl);
2087
2088 RTL_W16(IntrMitigate, 0x5151);
2089
2090 /* Work around for RxFIFO overflow. */
2091 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2092 tp->intr_event |= RxFIFOOver | PCSTimeout;
2093 tp->intr_event &= ~RxOverflow;
2094 }
2095
2096 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2097
2098 RTL_W8(Cfg9346, Cfg9346_Lock);
2099
2100 RTL_R8(IntrMask);
2101
2102 RTL_W32(RxMissed, 0);
2103
2104 rtl_set_rx_mode(dev);
2105
2106 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2107
2108 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2109
2110 RTL_W16(IntrMask, tp->intr_event);
2111 }
2112
2113 static void rtl_hw_start_8101(struct net_device *dev)
2114 {
2115 struct rtl8169_private *tp = netdev_priv(dev);
2116 void __iomem *ioaddr = tp->mmio_addr;
2117 struct pci_dev *pdev = tp->pci_dev;
2118
2119 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2120 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2121 pci_write_config_word(pdev, 0x68, 0x00);
2122 pci_write_config_word(pdev, 0x69, 0x08);
2123 }
2124
2125 RTL_W8(Cfg9346, Cfg9346_Unlock);
2126
2127 RTL_W8(EarlyTxThres, EarlyTxThld);
2128
2129 rtl_set_rx_max_size(ioaddr);
2130
2131 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2132
2133 RTL_W16(CPlusCmd, tp->cp_cmd);
2134
2135 RTL_W16(IntrMitigate, 0x0000);
2136
2137 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2138
2139 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2140 rtl_set_rx_tx_config_registers(tp);
2141
2142 RTL_W8(Cfg9346, Cfg9346_Lock);
2143
2144 RTL_R8(IntrMask);
2145
2146 RTL_W32(RxMissed, 0);
2147
2148 rtl_set_rx_mode(dev);
2149
2150 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2151
2152 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2153
2154 RTL_W16(IntrMask, tp->intr_event);
2155 }
2156
2157 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2158 {
2159 struct rtl8169_private *tp = netdev_priv(dev);
2160 int ret = 0;
2161
2162 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2163 return -EINVAL;
2164
2165 dev->mtu = new_mtu;
2166
2167 if (!netif_running(dev))
2168 goto out;
2169
2170 rtl8169_down(dev);
2171
2172 rtl8169_set_rxbufsize(tp, dev);
2173
2174 ret = rtl8169_init_ring(dev);
2175 if (ret < 0)
2176 goto out;
2177
2178 napi_enable(&tp->napi);
2179
2180 rtl_hw_start(dev);
2181
2182 rtl8169_request_timer(dev);
2183
2184 out:
2185 return ret;
2186 }
2187
2188 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2189 {
2190 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
2191 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2192 }
2193
2194 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2195 struct sk_buff **sk_buff, struct RxDesc *desc)
2196 {
2197 struct pci_dev *pdev = tp->pci_dev;
2198
2199 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2200 PCI_DMA_FROMDEVICE);
2201 dev_kfree_skb(*sk_buff);
2202 *sk_buff = NULL;
2203 rtl8169_make_unusable_by_asic(desc);
2204 }
2205
2206 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2207 {
2208 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2209
2210 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2211 }
2212
2213 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2214 u32 rx_buf_sz)
2215 {
2216 desc->addr = cpu_to_le64(mapping);
2217 wmb();
2218 rtl8169_mark_to_asic(desc, rx_buf_sz);
2219 }
2220
2221 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2222 struct net_device *dev,
2223 struct RxDesc *desc, int rx_buf_sz,
2224 unsigned int align)
2225 {
2226 struct sk_buff *skb;
2227 dma_addr_t mapping;
2228 unsigned int pad;
2229
2230 pad = align ? align : NET_IP_ALIGN;
2231
2232 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2233 if (!skb)
2234 goto err_out;
2235
2236 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2237
2238 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2239 PCI_DMA_FROMDEVICE);
2240
2241 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2242 out:
2243 return skb;
2244
2245 err_out:
2246 rtl8169_make_unusable_by_asic(desc);
2247 goto out;
2248 }
2249
2250 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2251 {
2252 unsigned int i;
2253
2254 for (i = 0; i < NUM_RX_DESC; i++) {
2255 if (tp->Rx_skbuff[i]) {
2256 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2257 tp->RxDescArray + i);
2258 }
2259 }
2260 }
2261
2262 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2263 u32 start, u32 end)
2264 {
2265 u32 cur;
2266
2267 for (cur = start; end - cur != 0; cur++) {
2268 struct sk_buff *skb;
2269 unsigned int i = cur % NUM_RX_DESC;
2270
2271 WARN_ON((s32)(end - cur) < 0);
2272
2273 if (tp->Rx_skbuff[i])
2274 continue;
2275
2276 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2277 tp->RxDescArray + i,
2278 tp->rx_buf_sz, tp->align);
2279 if (!skb)
2280 break;
2281
2282 tp->Rx_skbuff[i] = skb;
2283 }
2284 return cur - start;
2285 }
2286
2287 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2288 {
2289 desc->opts1 |= cpu_to_le32(RingEnd);
2290 }
2291
2292 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2293 {
2294 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2295 }
2296
2297 static int rtl8169_init_ring(struct net_device *dev)
2298 {
2299 struct rtl8169_private *tp = netdev_priv(dev);
2300
2301 rtl8169_init_ring_indexes(tp);
2302
2303 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2304 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2305
2306 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2307 goto err_out;
2308
2309 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2310
2311 return 0;
2312
2313 err_out:
2314 rtl8169_rx_clear(tp);
2315 return -ENOMEM;
2316 }
2317
2318 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2319 struct TxDesc *desc)
2320 {
2321 unsigned int len = tx_skb->len;
2322
2323 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2324 desc->opts1 = 0x00;
2325 desc->opts2 = 0x00;
2326 desc->addr = 0x00;
2327 tx_skb->len = 0;
2328 }
2329
2330 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2331 {
2332 unsigned int i;
2333
2334 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2335 unsigned int entry = i % NUM_TX_DESC;
2336 struct ring_info *tx_skb = tp->tx_skb + entry;
2337 unsigned int len = tx_skb->len;
2338
2339 if (len) {
2340 struct sk_buff *skb = tx_skb->skb;
2341
2342 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2343 tp->TxDescArray + entry);
2344 if (skb) {
2345 dev_kfree_skb(skb);
2346 tx_skb->skb = NULL;
2347 }
2348 tp->dev->stats.tx_dropped++;
2349 }
2350 }
2351 tp->cur_tx = tp->dirty_tx = 0;
2352 }
2353
2354 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
2355 {
2356 struct rtl8169_private *tp = netdev_priv(dev);
2357
2358 PREPARE_DELAYED_WORK(&tp->task, task);
2359 schedule_delayed_work(&tp->task, 4);
2360 }
2361
2362 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2363 {
2364 struct rtl8169_private *tp = netdev_priv(dev);
2365 void __iomem *ioaddr = tp->mmio_addr;
2366
2367 synchronize_irq(dev->irq);
2368
2369 /* Wait for any pending NAPI task to complete */
2370 napi_disable(&tp->napi);
2371
2372 rtl8169_irq_mask_and_ack(ioaddr);
2373
2374 tp->intr_mask = 0xffff;
2375 RTL_W16(IntrMask, tp->intr_event);
2376 napi_enable(&tp->napi);
2377 }
2378
2379 static void rtl8169_reinit_task(struct work_struct *work)
2380 {
2381 struct rtl8169_private *tp =
2382 container_of(work, struct rtl8169_private, task.work);
2383 struct net_device *dev = tp->dev;
2384 int ret;
2385
2386 rtnl_lock();
2387
2388 if (!netif_running(dev))
2389 goto out_unlock;
2390
2391 rtl8169_wait_for_quiescence(dev);
2392 rtl8169_close(dev);
2393
2394 ret = rtl8169_open(dev);
2395 if (unlikely(ret < 0)) {
2396 if (net_ratelimit() && netif_msg_drv(tp)) {
2397 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
2398 " Rescheduling.\n", dev->name, ret);
2399 }
2400 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2401 }
2402
2403 out_unlock:
2404 rtnl_unlock();
2405 }
2406
2407 static void rtl8169_reset_task(struct work_struct *work)
2408 {
2409 struct rtl8169_private *tp =
2410 container_of(work, struct rtl8169_private, task.work);
2411 struct net_device *dev = tp->dev;
2412
2413 rtnl_lock();
2414
2415 if (!netif_running(dev))
2416 goto out_unlock;
2417
2418 rtl8169_wait_for_quiescence(dev);
2419
2420 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
2421 rtl8169_tx_clear(tp);
2422
2423 if (tp->dirty_rx == tp->cur_rx) {
2424 rtl8169_init_ring_indexes(tp);
2425 rtl_hw_start(dev);
2426 netif_wake_queue(dev);
2427 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2428 } else {
2429 if (net_ratelimit() && netif_msg_intr(tp)) {
2430 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
2431 dev->name);
2432 }
2433 rtl8169_schedule_work(dev, rtl8169_reset_task);
2434 }
2435
2436 out_unlock:
2437 rtnl_unlock();
2438 }
2439
2440 static void rtl8169_tx_timeout(struct net_device *dev)
2441 {
2442 struct rtl8169_private *tp = netdev_priv(dev);
2443
2444 rtl8169_hw_reset(tp->mmio_addr);
2445
2446 /* Let's wait a bit while any (async) irq lands on */
2447 rtl8169_schedule_work(dev, rtl8169_reset_task);
2448 }
2449
2450 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2451 u32 opts1)
2452 {
2453 struct skb_shared_info *info = skb_shinfo(skb);
2454 unsigned int cur_frag, entry;
2455 struct TxDesc * uninitialized_var(txd);
2456
2457 entry = tp->cur_tx;
2458 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2459 skb_frag_t *frag = info->frags + cur_frag;
2460 dma_addr_t mapping;
2461 u32 status, len;
2462 void *addr;
2463
2464 entry = (entry + 1) % NUM_TX_DESC;
2465
2466 txd = tp->TxDescArray + entry;
2467 len = frag->size;
2468 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2469 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2470
2471 /* anti gcc 2.95.3 bugware (sic) */
2472 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2473
2474 txd->opts1 = cpu_to_le32(status);
2475 txd->addr = cpu_to_le64(mapping);
2476
2477 tp->tx_skb[entry].len = len;
2478 }
2479
2480 if (cur_frag) {
2481 tp->tx_skb[entry].skb = skb;
2482 txd->opts1 |= cpu_to_le32(LastFrag);
2483 }
2484
2485 return cur_frag;
2486 }
2487
2488 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2489 {
2490 if (dev->features & NETIF_F_TSO) {
2491 u32 mss = skb_shinfo(skb)->gso_size;
2492
2493 if (mss)
2494 return LargeSend | ((mss & MSSMask) << MSSShift);
2495 }
2496 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2497 const struct iphdr *ip = ip_hdr(skb);
2498
2499 if (ip->protocol == IPPROTO_TCP)
2500 return IPCS | TCPCS;
2501 else if (ip->protocol == IPPROTO_UDP)
2502 return IPCS | UDPCS;
2503 WARN_ON(1); /* we need a WARN() */
2504 }
2505 return 0;
2506 }
2507
2508 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2509 {
2510 struct rtl8169_private *tp = netdev_priv(dev);
2511 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2512 struct TxDesc *txd = tp->TxDescArray + entry;
2513 void __iomem *ioaddr = tp->mmio_addr;
2514 dma_addr_t mapping;
2515 u32 status, len;
2516 u32 opts1;
2517 int ret = NETDEV_TX_OK;
2518
2519 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2520 if (netif_msg_drv(tp)) {
2521 printk(KERN_ERR
2522 "%s: BUG! Tx Ring full when queue awake!\n",
2523 dev->name);
2524 }
2525 goto err_stop;
2526 }
2527
2528 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2529 goto err_stop;
2530
2531 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2532
2533 frags = rtl8169_xmit_frags(tp, skb, opts1);
2534 if (frags) {
2535 len = skb_headlen(skb);
2536 opts1 |= FirstFrag;
2537 } else {
2538 len = skb->len;
2539
2540 if (unlikely(len < ETH_ZLEN)) {
2541 if (skb_padto(skb, ETH_ZLEN))
2542 goto err_update_stats;
2543 len = ETH_ZLEN;
2544 }
2545
2546 opts1 |= FirstFrag | LastFrag;
2547 tp->tx_skb[entry].skb = skb;
2548 }
2549
2550 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2551
2552 tp->tx_skb[entry].len = len;
2553 txd->addr = cpu_to_le64(mapping);
2554 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2555
2556 wmb();
2557
2558 /* anti gcc 2.95.3 bugware (sic) */
2559 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2560 txd->opts1 = cpu_to_le32(status);
2561
2562 dev->trans_start = jiffies;
2563
2564 tp->cur_tx += frags + 1;
2565
2566 smp_wmb();
2567
2568 RTL_W8(TxPoll, NPQ); /* set polling bit */
2569
2570 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2571 netif_stop_queue(dev);
2572 smp_rmb();
2573 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2574 netif_wake_queue(dev);
2575 }
2576
2577 out:
2578 return ret;
2579
2580 err_stop:
2581 netif_stop_queue(dev);
2582 ret = NETDEV_TX_BUSY;
2583 err_update_stats:
2584 dev->stats.tx_dropped++;
2585 goto out;
2586 }
2587
2588 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2589 {
2590 struct rtl8169_private *tp = netdev_priv(dev);
2591 struct pci_dev *pdev = tp->pci_dev;
2592 void __iomem *ioaddr = tp->mmio_addr;
2593 u16 pci_status, pci_cmd;
2594
2595 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2596 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2597
2598 if (netif_msg_intr(tp)) {
2599 printk(KERN_ERR
2600 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2601 dev->name, pci_cmd, pci_status);
2602 }
2603
2604 /*
2605 * The recovery sequence below admits a very elaborated explanation:
2606 * - it seems to work;
2607 * - I did not see what else could be done;
2608 * - it makes iop3xx happy.
2609 *
2610 * Feel free to adjust to your needs.
2611 */
2612 if (pdev->broken_parity_status)
2613 pci_cmd &= ~PCI_COMMAND_PARITY;
2614 else
2615 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2616
2617 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2618
2619 pci_write_config_word(pdev, PCI_STATUS,
2620 pci_status & (PCI_STATUS_DETECTED_PARITY |
2621 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2622 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2623
2624 /* The infamous DAC f*ckup only happens at boot time */
2625 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2626 if (netif_msg_intr(tp))
2627 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2628 tp->cp_cmd &= ~PCIDAC;
2629 RTL_W16(CPlusCmd, tp->cp_cmd);
2630 dev->features &= ~NETIF_F_HIGHDMA;
2631 }
2632
2633 rtl8169_hw_reset(ioaddr);
2634
2635 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2636 }
2637
2638 static void rtl8169_tx_interrupt(struct net_device *dev,
2639 struct rtl8169_private *tp,
2640 void __iomem *ioaddr)
2641 {
2642 unsigned int dirty_tx, tx_left;
2643
2644 dirty_tx = tp->dirty_tx;
2645 smp_rmb();
2646 tx_left = tp->cur_tx - dirty_tx;
2647
2648 while (tx_left > 0) {
2649 unsigned int entry = dirty_tx % NUM_TX_DESC;
2650 struct ring_info *tx_skb = tp->tx_skb + entry;
2651 u32 len = tx_skb->len;
2652 u32 status;
2653
2654 rmb();
2655 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2656 if (status & DescOwn)
2657 break;
2658
2659 dev->stats.tx_bytes += len;
2660 dev->stats.tx_packets++;
2661
2662 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2663
2664 if (status & LastFrag) {
2665 dev_kfree_skb_irq(tx_skb->skb);
2666 tx_skb->skb = NULL;
2667 }
2668 dirty_tx++;
2669 tx_left--;
2670 }
2671
2672 if (tp->dirty_tx != dirty_tx) {
2673 tp->dirty_tx = dirty_tx;
2674 smp_wmb();
2675 if (netif_queue_stopped(dev) &&
2676 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2677 netif_wake_queue(dev);
2678 }
2679 /*
2680 * 8168 hack: TxPoll requests are lost when the Tx packets are
2681 * too close. Let's kick an extra TxPoll request when a burst
2682 * of start_xmit activity is detected (if it is not detected,
2683 * it is slow enough). -- FR
2684 */
2685 smp_rmb();
2686 if (tp->cur_tx != dirty_tx)
2687 RTL_W8(TxPoll, NPQ);
2688 }
2689 }
2690
2691 static inline int rtl8169_fragmented_frame(u32 status)
2692 {
2693 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2694 }
2695
2696 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2697 {
2698 u32 opts1 = le32_to_cpu(desc->opts1);
2699 u32 status = opts1 & RxProtoMask;
2700
2701 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2702 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2703 ((status == RxProtoIP) && !(opts1 & IPFail)))
2704 skb->ip_summed = CHECKSUM_UNNECESSARY;
2705 else
2706 skb->ip_summed = CHECKSUM_NONE;
2707 }
2708
2709 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2710 struct rtl8169_private *tp, int pkt_size,
2711 dma_addr_t addr)
2712 {
2713 struct sk_buff *skb;
2714 bool done = false;
2715
2716 if (pkt_size >= rx_copybreak)
2717 goto out;
2718
2719 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
2720 if (!skb)
2721 goto out;
2722
2723 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2724 PCI_DMA_FROMDEVICE);
2725 skb_reserve(skb, NET_IP_ALIGN);
2726 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2727 *sk_buff = skb;
2728 done = true;
2729 out:
2730 return done;
2731 }
2732
2733 static int rtl8169_rx_interrupt(struct net_device *dev,
2734 struct rtl8169_private *tp,
2735 void __iomem *ioaddr, u32 budget)
2736 {
2737 unsigned int cur_rx, rx_left;
2738 unsigned int delta, count;
2739
2740 cur_rx = tp->cur_rx;
2741 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2742 rx_left = min(rx_left, budget);
2743
2744 for (; rx_left > 0; rx_left--, cur_rx++) {
2745 unsigned int entry = cur_rx % NUM_RX_DESC;
2746 struct RxDesc *desc = tp->RxDescArray + entry;
2747 u32 status;
2748
2749 rmb();
2750 status = le32_to_cpu(desc->opts1);
2751
2752 if (status & DescOwn)
2753 break;
2754 if (unlikely(status & RxRES)) {
2755 if (netif_msg_rx_err(tp)) {
2756 printk(KERN_INFO
2757 "%s: Rx ERROR. status = %08x\n",
2758 dev->name, status);
2759 }
2760 dev->stats.rx_errors++;
2761 if (status & (RxRWT | RxRUNT))
2762 dev->stats.rx_length_errors++;
2763 if (status & RxCRC)
2764 dev->stats.rx_crc_errors++;
2765 if (status & RxFOVF) {
2766 rtl8169_schedule_work(dev, rtl8169_reset_task);
2767 dev->stats.rx_fifo_errors++;
2768 }
2769 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2770 } else {
2771 struct sk_buff *skb = tp->Rx_skbuff[entry];
2772 dma_addr_t addr = le64_to_cpu(desc->addr);
2773 int pkt_size = (status & 0x00001FFF) - 4;
2774 struct pci_dev *pdev = tp->pci_dev;
2775
2776 /*
2777 * The driver does not support incoming fragmented
2778 * frames. They are seen as a symptom of over-mtu
2779 * sized frames.
2780 */
2781 if (unlikely(rtl8169_fragmented_frame(status))) {
2782 dev->stats.rx_dropped++;
2783 dev->stats.rx_length_errors++;
2784 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2785 continue;
2786 }
2787
2788 rtl8169_rx_csum(skb, desc);
2789
2790 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
2791 pci_dma_sync_single_for_device(pdev, addr,
2792 pkt_size, PCI_DMA_FROMDEVICE);
2793 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2794 } else {
2795 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
2796 PCI_DMA_FROMDEVICE);
2797 tp->Rx_skbuff[entry] = NULL;
2798 }
2799
2800 skb_put(skb, pkt_size);
2801 skb->protocol = eth_type_trans(skb, dev);
2802
2803 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2804 netif_receive_skb(skb);
2805
2806 dev->last_rx = jiffies;
2807 dev->stats.rx_bytes += pkt_size;
2808 dev->stats.rx_packets++;
2809 }
2810
2811 /* Work around for AMD plateform. */
2812 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
2813 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2814 desc->opts2 = 0;
2815 cur_rx++;
2816 }
2817 }
2818
2819 count = cur_rx - tp->cur_rx;
2820 tp->cur_rx = cur_rx;
2821
2822 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2823 if (!delta && count && netif_msg_intr(tp))
2824 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2825 tp->dirty_rx += delta;
2826
2827 /*
2828 * FIXME: until there is periodic timer to try and refill the ring,
2829 * a temporary shortage may definitely kill the Rx process.
2830 * - disable the asic to try and avoid an overflow and kick it again
2831 * after refill ?
2832 * - how do others driver handle this condition (Uh oh...).
2833 */
2834 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2835 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2836
2837 return count;
2838 }
2839
2840 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
2841 {
2842 struct net_device *dev = dev_instance;
2843 struct rtl8169_private *tp = netdev_priv(dev);
2844 void __iomem *ioaddr = tp->mmio_addr;
2845 int handled = 0;
2846 int status;
2847
2848 status = RTL_R16(IntrStatus);
2849
2850 /* hotplug/major error/no more work/shared irq */
2851 if ((status == 0xffff) || !status)
2852 goto out;
2853
2854 handled = 1;
2855
2856 if (unlikely(!netif_running(dev))) {
2857 rtl8169_asic_down(ioaddr);
2858 goto out;
2859 }
2860
2861 status &= tp->intr_mask;
2862 RTL_W16(IntrStatus,
2863 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2864
2865 if (!(status & tp->intr_event))
2866 goto out;
2867
2868 /* Work around for rx fifo overflow */
2869 if (unlikely(status & RxFIFOOver) &&
2870 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2871 netif_stop_queue(dev);
2872 rtl8169_tx_timeout(dev);
2873 goto out;
2874 }
2875
2876 if (unlikely(status & SYSErr)) {
2877 rtl8169_pcierr_interrupt(dev);
2878 goto out;
2879 }
2880
2881 if (status & LinkChg)
2882 rtl8169_check_link_status(dev, tp, ioaddr);
2883
2884 if (status & tp->napi_event) {
2885 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2886 tp->intr_mask = ~tp->napi_event;
2887
2888 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
2889 __netif_rx_schedule(dev, &tp->napi);
2890 else if (netif_msg_intr(tp)) {
2891 printk(KERN_INFO "%s: interrupt %04x in poll\n",
2892 dev->name, status);
2893 }
2894 }
2895 out:
2896 return IRQ_RETVAL(handled);
2897 }
2898
2899 static int rtl8169_poll(struct napi_struct *napi, int budget)
2900 {
2901 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
2902 struct net_device *dev = tp->dev;
2903 void __iomem *ioaddr = tp->mmio_addr;
2904 int work_done;
2905
2906 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
2907 rtl8169_tx_interrupt(dev, tp, ioaddr);
2908
2909 if (work_done < budget) {
2910 netif_rx_complete(dev, napi);
2911 tp->intr_mask = 0xffff;
2912 /*
2913 * 20040426: the barrier is not strictly required but the
2914 * behavior of the irq handler could be less predictable
2915 * without it. Btw, the lack of flush for the posted pci
2916 * write is safe - FR
2917 */
2918 smp_wmb();
2919 RTL_W16(IntrMask, tp->intr_event);
2920 }
2921
2922 return work_done;
2923 }
2924
2925 static void rtl8169_down(struct net_device *dev)
2926 {
2927 struct rtl8169_private *tp = netdev_priv(dev);
2928 void __iomem *ioaddr = tp->mmio_addr;
2929 unsigned int intrmask;
2930
2931 rtl8169_delete_timer(dev);
2932
2933 netif_stop_queue(dev);
2934
2935 napi_disable(&tp->napi);
2936
2937 core_down:
2938 spin_lock_irq(&tp->lock);
2939
2940 rtl8169_asic_down(ioaddr);
2941
2942 /* Update the error counts. */
2943 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
2944 RTL_W32(RxMissed, 0);
2945
2946 spin_unlock_irq(&tp->lock);
2947
2948 synchronize_irq(dev->irq);
2949
2950 /* Give a racing hard_start_xmit a few cycles to complete. */
2951 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
2952
2953 /*
2954 * And now for the 50k$ question: are IRQ disabled or not ?
2955 *
2956 * Two paths lead here:
2957 * 1) dev->close
2958 * -> netif_running() is available to sync the current code and the
2959 * IRQ handler. See rtl8169_interrupt for details.
2960 * 2) dev->change_mtu
2961 * -> rtl8169_poll can not be issued again and re-enable the
2962 * interruptions. Let's simply issue the IRQ down sequence again.
2963 *
2964 * No loop if hotpluged or major error (0xffff).
2965 */
2966 intrmask = RTL_R16(IntrMask);
2967 if (intrmask && (intrmask != 0xffff))
2968 goto core_down;
2969
2970 rtl8169_tx_clear(tp);
2971
2972 rtl8169_rx_clear(tp);
2973 }
2974
2975 static int rtl8169_close(struct net_device *dev)
2976 {
2977 struct rtl8169_private *tp = netdev_priv(dev);
2978 struct pci_dev *pdev = tp->pci_dev;
2979
2980 rtl8169_down(dev);
2981
2982 free_irq(dev->irq, dev);
2983
2984 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2985 tp->RxPhyAddr);
2986 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2987 tp->TxPhyAddr);
2988 tp->TxDescArray = NULL;
2989 tp->RxDescArray = NULL;
2990
2991 return 0;
2992 }
2993
2994 static void rtl_set_rx_mode(struct net_device *dev)
2995 {
2996 struct rtl8169_private *tp = netdev_priv(dev);
2997 void __iomem *ioaddr = tp->mmio_addr;
2998 unsigned long flags;
2999 u32 mc_filter[2]; /* Multicast hash filter */
3000 int rx_mode;
3001 u32 tmp = 0;
3002
3003 if (dev->flags & IFF_PROMISC) {
3004 /* Unconditionally log net taps. */
3005 if (netif_msg_link(tp)) {
3006 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3007 dev->name);
3008 }
3009 rx_mode =
3010 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3011 AcceptAllPhys;
3012 mc_filter[1] = mc_filter[0] = 0xffffffff;
3013 } else if ((dev->mc_count > multicast_filter_limit)
3014 || (dev->flags & IFF_ALLMULTI)) {
3015 /* Too many to filter perfectly -- accept all multicasts. */
3016 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3017 mc_filter[1] = mc_filter[0] = 0xffffffff;
3018 } else {
3019 struct dev_mc_list *mclist;
3020 unsigned int i;
3021
3022 rx_mode = AcceptBroadcast | AcceptMyPhys;
3023 mc_filter[1] = mc_filter[0] = 0;
3024 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3025 i++, mclist = mclist->next) {
3026 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3027 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3028 rx_mode |= AcceptMulticast;
3029 }
3030 }
3031
3032 spin_lock_irqsave(&tp->lock, flags);
3033
3034 tmp = rtl8169_rx_config | rx_mode |
3035 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3036
3037 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
3038 u32 data = mc_filter[0];
3039
3040 mc_filter[0] = swab32(mc_filter[1]);
3041 mc_filter[1] = swab32(data);
3042 }
3043
3044 RTL_W32(MAR0 + 0, mc_filter[0]);
3045 RTL_W32(MAR0 + 4, mc_filter[1]);
3046
3047 RTL_W32(RxConfig, tmp);
3048
3049 spin_unlock_irqrestore(&tp->lock, flags);
3050 }
3051
3052 /**
3053 * rtl8169_get_stats - Get rtl8169 read/write statistics
3054 * @dev: The Ethernet Device to get statistics for
3055 *
3056 * Get TX/RX statistics for rtl8169
3057 */
3058 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3059 {
3060 struct rtl8169_private *tp = netdev_priv(dev);
3061 void __iomem *ioaddr = tp->mmio_addr;
3062 unsigned long flags;
3063
3064 if (netif_running(dev)) {
3065 spin_lock_irqsave(&tp->lock, flags);
3066 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
3067 RTL_W32(RxMissed, 0);
3068 spin_unlock_irqrestore(&tp->lock, flags);
3069 }
3070
3071 return &dev->stats;
3072 }
3073
3074 #ifdef CONFIG_PM
3075
3076 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3077 {
3078 struct net_device *dev = pci_get_drvdata(pdev);
3079 struct rtl8169_private *tp = netdev_priv(dev);
3080 void __iomem *ioaddr = tp->mmio_addr;
3081
3082 if (!netif_running(dev))
3083 goto out_pci_suspend;
3084
3085 netif_device_detach(dev);
3086 netif_stop_queue(dev);
3087
3088 spin_lock_irq(&tp->lock);
3089
3090 rtl8169_asic_down(ioaddr);
3091
3092 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
3093 RTL_W32(RxMissed, 0);
3094
3095 spin_unlock_irq(&tp->lock);
3096
3097 out_pci_suspend:
3098 pci_save_state(pdev);
3099 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3100 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
3101 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3102
3103 return 0;
3104 }
3105
3106 static int rtl8169_resume(struct pci_dev *pdev)
3107 {
3108 struct net_device *dev = pci_get_drvdata(pdev);
3109
3110 pci_set_power_state(pdev, PCI_D0);
3111 pci_restore_state(pdev);
3112 pci_enable_wake(pdev, PCI_D0, 0);
3113
3114 if (!netif_running(dev))
3115 goto out;
3116
3117 netif_device_attach(dev);
3118
3119 rtl8169_schedule_work(dev, rtl8169_reset_task);
3120 out:
3121 return 0;
3122 }
3123
3124 #endif /* CONFIG_PM */
3125
3126 static struct pci_driver rtl8169_pci_driver = {
3127 .name = MODULENAME,
3128 .id_table = rtl8169_pci_tbl,
3129 .probe = rtl8169_init_one,
3130 .remove = __devexit_p(rtl8169_remove_one),
3131 #ifdef CONFIG_PM
3132 .suspend = rtl8169_suspend,
3133 .resume = rtl8169_resume,
3134 #endif
3135 };
3136
3137 static int __init rtl8169_init_module(void)
3138 {
3139 return pci_register_driver(&rtl8169_pci_driver);
3140 }
3141
3142 static void __exit rtl8169_cleanup_module(void)
3143 {
3144 pci_unregister_driver(&rtl8169_pci_driver);
3145 }
3146
3147 module_init(rtl8169_init_module);
3148 module_exit(rtl8169_cleanup_module);
Support for the Chinese Samsung S3C2440 based development boards