1 #include <linux/init.h>
2 #include <linux/kernel.h>
3 #include <linux/sched.h>
4 #include <linux/string.h>
5 #include <linux/bootmem.h>
6 #include <linux/bitops.h>
7 #include <linux/module.h>
8 #include <linux/kgdb.h>
9 #include <linux/topology.h>
10 #include <linux/delay.h>
11 #include <linux/smp.h>
12 #include <linux/percpu.h>
16 #include <asm/linkage.h>
17 #include <asm/mmu_context.h>
22 #ifdef CONFIG_X86_LOCAL_APIC
23 #include <asm/mpspec.h>
25 #include <mach_apic.h>
28 #include <asm/pgtable.h>
29 #include <asm/processor.h>
31 #include <asm/atomic.h>
32 #include <asm/proto.h>
33 #include <asm/sections.h>
34 #include <asm/setup.h>
35 #include <asm/genapic.h>
39 /* We need valid kernel segments for data and code in long mode too
40 * IRET will check the segment types kkeil 2000/10/28
41 * Also sysret mandates a special GDT layout
43 /* The TLS descriptors are currently at a different place compared to i386.
44 Hopefully nobody expects them at a fixed place (Wine?) */
45 DEFINE_PER_CPU(struct gdt_page
, gdt_page
) = { .gdt
= {
46 [GDT_ENTRY_KERNEL32_CS
] = { { { 0x0000ffff, 0x00cf9b00 } } },
47 [GDT_ENTRY_KERNEL_CS
] = { { { 0x0000ffff, 0x00af9b00 } } },
48 [GDT_ENTRY_KERNEL_DS
] = { { { 0x0000ffff, 0x00cf9300 } } },
49 [GDT_ENTRY_DEFAULT_USER32_CS
] = { { { 0x0000ffff, 0x00cffb00 } } },
50 [GDT_ENTRY_DEFAULT_USER_DS
] = { { { 0x0000ffff, 0x00cff300 } } },
51 [GDT_ENTRY_DEFAULT_USER_CS
] = { { { 0x0000ffff, 0x00affb00 } } },
53 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
55 __u32 cleared_cpu_caps
[NCAPINTS
] __cpuinitdata
;
57 /* Current gdt points %fs at the "master" per-cpu area: after this,
58 * it's on the real one. */
59 void switch_to_new_gdt(void)
61 struct desc_ptr gdt_descr
;
63 gdt_descr
.address
= (long)get_cpu_gdt_table(smp_processor_id());
64 gdt_descr
.size
= GDT_SIZE
- 1;
68 struct cpu_dev
*cpu_devs
[X86_VENDOR_NUM
] = {};
70 static void __cpuinit
default_init(struct cpuinfo_x86
*c
)
75 static struct cpu_dev __cpuinitdata default_cpu
= {
76 .c_init
= default_init
,
77 .c_vendor
= "Unknown",
79 static struct cpu_dev
*this_cpu __cpuinitdata
= &default_cpu
;
81 int __cpuinit
get_model_name(struct cpuinfo_x86
*c
)
85 if (c
->extended_cpuid_level
< 0x80000004)
88 v
= (unsigned int *) c
->x86_model_id
;
89 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
90 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
91 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
92 c
->x86_model_id
[48] = 0;
97 void __cpuinit
display_cacheinfo(struct cpuinfo_x86
*c
)
99 unsigned int n
, dummy
, ebx
, ecx
, edx
;
101 n
= c
->extended_cpuid_level
;
103 if (n
>= 0x80000005) {
104 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
105 printk(KERN_INFO
"CPU: L1 I Cache: %dK (%d bytes/line), "
106 "D cache %dK (%d bytes/line)\n",
107 edx
>>24, edx
&0xFF, ecx
>>24, ecx
&0xFF);
108 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
109 /* On K8 L1 TLB is inclusive, so don't count it */
113 if (n
>= 0x80000006) {
114 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
115 ecx
= cpuid_ecx(0x80000006);
116 c
->x86_cache_size
= ecx
>> 16;
117 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
119 printk(KERN_INFO
"CPU: L2 Cache: %dK (%d bytes/line)\n",
120 c
->x86_cache_size
, ecx
& 0xFF);
124 void __cpuinit
detect_ht(struct cpuinfo_x86
*c
)
127 u32 eax
, ebx
, ecx
, edx
;
128 int index_msb
, core_bits
;
130 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
133 if (!cpu_has(c
, X86_FEATURE_HT
))
135 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
138 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
140 if (smp_num_siblings
== 1) {
141 printk(KERN_INFO
"CPU: Hyper-Threading is disabled\n");
142 } else if (smp_num_siblings
> 1) {
144 if (smp_num_siblings
> NR_CPUS
) {
145 printk(KERN_WARNING
"CPU: Unsupported number of "
146 "siblings %d", smp_num_siblings
);
147 smp_num_siblings
= 1;
151 index_msb
= get_count_order(smp_num_siblings
);
152 c
->phys_proc_id
= phys_pkg_id(index_msb
);
154 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
156 index_msb
= get_count_order(smp_num_siblings
);
158 core_bits
= get_count_order(c
->x86_max_cores
);
160 c
->cpu_core_id
= phys_pkg_id(index_msb
) &
161 ((1 << core_bits
) - 1);
164 if ((c
->x86_max_cores
* smp_num_siblings
) > 1) {
165 printk(KERN_INFO
"CPU: Physical Processor ID: %d\n",
167 printk(KERN_INFO
"CPU: Processor Core ID: %d\n",
174 static void __cpuinit
get_cpu_vendor(struct cpuinfo_x86
*c
)
176 char *v
= c
->x86_vendor_id
;
180 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
182 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
183 (cpu_devs
[i
]->c_ident
[1] &&
184 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
186 this_cpu
= cpu_devs
[i
];
193 printk(KERN_ERR
"CPU: Vendor unknown, using generic init.\n");
194 printk(KERN_ERR
"CPU: Your system may be unstable.\n");
196 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
199 static void __init
early_cpu_support_print(void)
202 struct cpu_dev
*cpu_devx
;
204 printk("KERNEL supported cpus:\n");
205 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
206 cpu_devx
= cpu_devs
[i
];
209 for (j
= 0; j
< 2; j
++) {
210 if (!cpu_devx
->c_ident
[j
])
212 printk(" %s %s\n", cpu_devx
->c_vendor
,
213 cpu_devx
->c_ident
[j
]);
218 static void __cpuinit
early_identify_cpu(struct cpuinfo_x86
*c
);
220 void __init
early_cpu_init(void)
222 struct cpu_vendor_dev
*cvdev
;
224 for (cvdev
= __x86cpuvendor_start
;
225 cvdev
< __x86cpuvendor_end
;
227 cpu_devs
[cvdev
->vendor
] = cvdev
->cpu_dev
;
228 early_cpu_support_print();
229 early_identify_cpu(&boot_cpu_data
);
232 /* Do some early cpuid on the boot CPU to get some parameter that are
233 needed before check_bugs. Everything advanced is in identify_cpu
235 static void __cpuinit
early_identify_cpu(struct cpuinfo_x86
*c
)
239 c
->loops_per_jiffy
= loops_per_jiffy
;
240 c
->x86_cache_size
= -1;
241 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
242 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
243 c
->x86_vendor_id
[0] = '\0'; /* Unset */
244 c
->x86_model_id
[0] = '\0'; /* Unset */
245 c
->x86_clflush_size
= 64;
246 c
->x86_cache_alignment
= c
->x86_clflush_size
;
247 c
->x86_max_cores
= 1;
248 c
->x86_coreid_bits
= 0;
249 c
->extended_cpuid_level
= 0;
250 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
252 /* Get vendor name */
253 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
254 (unsigned int *)&c
->x86_vendor_id
[0],
255 (unsigned int *)&c
->x86_vendor_id
[8],
256 (unsigned int *)&c
->x86_vendor_id
[4]);
260 /* Initialize the standard set of capabilities */
261 /* Note that the vendor-specific code below might override */
263 /* Intel-defined flags: level 0x00000001 */
264 if (c
->cpuid_level
>= 0x00000001) {
266 cpuid(0x00000001, &tfms
, &misc
, &c
->x86_capability
[4],
267 &c
->x86_capability
[0]);
268 c
->x86
= (tfms
>> 8) & 0xf;
269 c
->x86_model
= (tfms
>> 4) & 0xf;
270 c
->x86_mask
= tfms
& 0xf;
272 c
->x86
+= (tfms
>> 20) & 0xff;
274 c
->x86_model
+= ((tfms
>> 16) & 0xF) << 4;
275 if (test_cpu_cap(c
, X86_FEATURE_CLFLSH
))
276 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
278 /* Have CPUID level 0 only - unheard of */
282 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xff;
284 c
->phys_proc_id
= c
->initial_apicid
;
286 /* AMD-defined flags: level 0x80000001 */
287 xlvl
= cpuid_eax(0x80000000);
288 c
->extended_cpuid_level
= xlvl
;
289 if ((xlvl
& 0xffff0000) == 0x80000000) {
290 if (xlvl
>= 0x80000001) {
291 c
->x86_capability
[1] = cpuid_edx(0x80000001);
292 c
->x86_capability
[6] = cpuid_ecx(0x80000001);
294 if (xlvl
>= 0x80000004)
295 get_model_name(c
); /* Default name */
298 /* Transmeta-defined flags: level 0x80860001 */
299 xlvl
= cpuid_eax(0x80860000);
300 if ((xlvl
& 0xffff0000) == 0x80860000) {
301 /* Don't set x86_cpuid_level here for now to not confuse. */
302 if (xlvl
>= 0x80860001)
303 c
->x86_capability
[2] = cpuid_edx(0x80860001);
306 if (c
->extended_cpuid_level
>= 0x80000007)
307 c
->x86_power
= cpuid_edx(0x80000007);
309 if (c
->extended_cpuid_level
>= 0x80000008) {
310 u32 eax
= cpuid_eax(0x80000008);
312 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
313 c
->x86_phys_bits
= eax
& 0xff;
316 if (c
->x86_vendor
!= X86_VENDOR_UNKNOWN
&&
317 cpu_devs
[c
->x86_vendor
]->c_early_init
)
318 cpu_devs
[c
->x86_vendor
]->c_early_init(c
);
320 validate_pat_support(c
);
324 * This does the hard work of actually picking apart the CPU stuff...
326 static void __cpuinit
identify_cpu(struct cpuinfo_x86
*c
)
330 early_identify_cpu(c
);
332 init_scattered_cpuid_features(c
);
334 c
->apicid
= phys_pkg_id(0);
337 * Vendor-specific initialization. In this section we
338 * canonicalize the feature flags, meaning if there are
339 * features a certain CPU supports which CPUID doesn't
340 * tell us, CPUID claiming incorrect flags, or other bugs,
341 * we handle them here.
343 * At the end of this section, c->x86_capability better
344 * indicate the features this CPU genuinely supports!
346 if (this_cpu
->c_init
)
352 * On SMP, boot_cpu_data holds the common feature set between
353 * all CPUs; so make sure that we indicate which features are
354 * common between the CPUs. The first time this routine gets
355 * executed, c == &boot_cpu_data.
357 if (c
!= &boot_cpu_data
) {
358 /* AND the already accumulated flags with these */
359 for (i
= 0; i
< NCAPINTS
; i
++)
360 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
363 /* Clear all flags overriden by options */
364 for (i
= 0; i
< NCAPINTS
; i
++)
365 c
->x86_capability
[i
] &= ~cleared_cpu_caps
[i
];
367 #ifdef CONFIG_X86_MCE
370 select_idle_routine(c
);
373 numa_add_cpu(smp_processor_id());
378 void __cpuinit
identify_boot_cpu(void)
380 identify_cpu(&boot_cpu_data
);
383 void __cpuinit
identify_secondary_cpu(struct cpuinfo_x86
*c
)
385 BUG_ON(c
== &boot_cpu_data
);
390 static __init
int setup_noclflush(char *arg
)
392 setup_clear_cpu_cap(X86_FEATURE_CLFLSH
);
395 __setup("noclflush", setup_noclflush
);
397 void __cpuinit
print_cpu_info(struct cpuinfo_x86
*c
)
399 if (c
->x86_model_id
[0])
400 printk(KERN_CONT
"%s", c
->x86_model_id
);
402 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
403 printk(KERN_CONT
" stepping %02x\n", c
->x86_mask
);
405 printk(KERN_CONT
"\n");
408 static __init
int setup_disablecpuid(char *arg
)
411 if (get_option(&arg
, &bit
) && bit
< NCAPINTS
*32)
412 setup_clear_cpu_cap(bit
);
417 __setup("clearcpuid=", setup_disablecpuid
);
419 cpumask_t cpu_initialized __cpuinitdata
= CPU_MASK_NONE
;
421 struct x8664_pda
**_cpu_pda __read_mostly
;
422 EXPORT_SYMBOL(_cpu_pda
);
424 struct desc_ptr idt_descr
= { 256 * 16 - 1, (unsigned long) idt_table
};
426 char boot_cpu_stack
[IRQSTACKSIZE
] __page_aligned_bss
;
428 unsigned long __supported_pte_mask __read_mostly
= ~0UL;
429 EXPORT_SYMBOL_GPL(__supported_pte_mask
);
431 static int do_not_nx __cpuinitdata
;
434 Control non executable mappings for 64bit processes.
439 static int __init
nonx_setup(char *str
)
443 if (!strncmp(str
, "on", 2)) {
444 __supported_pte_mask
|= _PAGE_NX
;
446 } else if (!strncmp(str
, "off", 3)) {
448 __supported_pte_mask
&= ~_PAGE_NX
;
452 early_param("noexec", nonx_setup
);
454 int force_personality32
;
457 Control non executable heap for 32bit processes.
458 To control the stack too use noexec=off
460 on PROT_READ does not imply PROT_EXEC for 32bit processes (default)
461 off PROT_READ implies PROT_EXEC
463 static int __init
nonx32_setup(char *str
)
465 if (!strcmp(str
, "on"))
466 force_personality32
&= ~READ_IMPLIES_EXEC
;
467 else if (!strcmp(str
, "off"))
468 force_personality32
|= READ_IMPLIES_EXEC
;
471 __setup("noexec32=", nonx32_setup
);
473 void pda_init(int cpu
)
475 struct x8664_pda
*pda
= cpu_pda(cpu
);
477 /* Setup up data that may be needed in __get_free_pages early */
480 /* Memory clobbers used to order PDA accessed */
482 wrmsrl(MSR_GS_BASE
, pda
);
485 pda
->cpunumber
= cpu
;
487 pda
->kernelstack
= (unsigned long)stack_thread_info() -
488 PDA_STACKOFFSET
+ THREAD_SIZE
;
489 pda
->active_mm
= &init_mm
;
493 /* others are initialized in smpboot.c */
494 pda
->pcurrent
= &init_task
;
495 pda
->irqstackptr
= boot_cpu_stack
;
496 pda
->irqstackptr
+= IRQSTACKSIZE
- 64;
498 if (!pda
->irqstackptr
) {
499 pda
->irqstackptr
= (char *)
500 __get_free_pages(GFP_ATOMIC
, IRQSTACK_ORDER
);
501 if (!pda
->irqstackptr
)
502 panic("cannot allocate irqstack for cpu %d",
504 pda
->irqstackptr
+= IRQSTACKSIZE
- 64;
507 if (pda
->nodenumber
== 0 && cpu_to_node(cpu
) != NUMA_NO_NODE
)
508 pda
->nodenumber
= cpu_to_node(cpu
);
512 char boot_exception_stacks
[(N_EXCEPTION_STACKS
- 1) * EXCEPTION_STKSZ
+
513 DEBUG_STKSZ
] __page_aligned_bss
;
515 extern asmlinkage
void ignore_sysret(void);
517 /* May not be marked __init: used by software suspend */
518 void syscall_init(void)
521 * LSTAR and STAR live in a bit strange symbiosis.
522 * They both write to the same internal register. STAR allows to
523 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
525 wrmsrl(MSR_STAR
, ((u64
)__USER32_CS
)<<48 | ((u64
)__KERNEL_CS
)<<32);
526 wrmsrl(MSR_LSTAR
, system_call
);
527 wrmsrl(MSR_CSTAR
, ignore_sysret
);
529 #ifdef CONFIG_IA32_EMULATION
530 syscall32_cpu_init();
533 /* Flags to clear on syscall */
534 wrmsrl(MSR_SYSCALL_MASK
,
535 X86_EFLAGS_TF
|X86_EFLAGS_DF
|X86_EFLAGS_IF
|X86_EFLAGS_IOPL
);
538 void __cpuinit
check_efer(void)
542 rdmsrl(MSR_EFER
, efer
);
543 if (!(efer
& EFER_NX
) || do_not_nx
)
544 __supported_pte_mask
&= ~_PAGE_NX
;
547 unsigned long kernel_eflags
;
550 * Copies of the original ist values from the tss are only accessed during
551 * debugging, no special alignment required.
553 DEFINE_PER_CPU(struct orig_ist
, orig_ist
);
556 * cpu_init() initializes state that is per-CPU. Some data is already
557 * initialized (naturally) in the bootstrap process, such as the GDT
558 * and IDT. We reload them nevertheless, this function acts as a
559 * 'CPU state barrier', nothing should get across.
560 * A lot of state is already set up in PDA init.
562 void __cpuinit
cpu_init(void)
564 int cpu
= stack_smp_processor_id();
565 struct tss_struct
*t
= &per_cpu(init_tss
, cpu
);
566 struct orig_ist
*orig_ist
= &per_cpu(orig_ist
, cpu
);
568 char *estacks
= NULL
;
569 struct task_struct
*me
;
572 /* CPU 0 is initialised in head64.c */
576 estacks
= boot_exception_stacks
;
580 if (cpu_test_and_set(cpu
, cpu_initialized
))
581 panic("CPU#%d already initialized!\n", cpu
);
583 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
585 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
588 * Initialize the per-CPU GDT with the boot GDT,
589 * and set up the GDT descriptor:
593 load_idt((const struct desc_ptr
*)&idt_descr
);
595 memset(me
->thread
.tls_array
, 0, GDT_ENTRY_TLS_ENTRIES
* 8);
598 wrmsrl(MSR_FS_BASE
, 0);
599 wrmsrl(MSR_KERNEL_GS_BASE
, 0);
603 if (cpu
!= 0 && x2apic
)
607 * set up and load the per-CPU TSS
609 for (v
= 0; v
< N_EXCEPTION_STACKS
; v
++) {
610 static const unsigned int order
[N_EXCEPTION_STACKS
] = {
611 [0 ... N_EXCEPTION_STACKS
- 1] = EXCEPTION_STACK_ORDER
,
612 [DEBUG_STACK
- 1] = DEBUG_STACK_ORDER
615 estacks
= (char *)__get_free_pages(GFP_ATOMIC
, order
[v
]);
617 panic("Cannot allocate exception stack %ld %d\n",
620 estacks
+= PAGE_SIZE
<< order
[v
];
621 orig_ist
->ist
[v
] = t
->x86_tss
.ist
[v
] = (unsigned long)estacks
;
624 t
->x86_tss
.io_bitmap_base
= offsetof(struct tss_struct
, io_bitmap
);
626 * <= is required because the CPU will access up to
627 * 8 bits beyond the end of the IO permission bitmap.
629 for (i
= 0; i
<= IO_BITMAP_LONGS
; i
++)
630 t
->io_bitmap
[i
] = ~0UL;
632 atomic_inc(&init_mm
.mm_count
);
633 me
->active_mm
= &init_mm
;
636 enter_lazy_tlb(&init_mm
, me
);
638 load_sp0(t
, ¤t
->thread
);
639 set_tss_desc(cpu
, t
);
641 load_LDT(&init_mm
.context
);
645 * If the kgdb is connected no debug regs should be altered. This
646 * is only applicable when KGDB and a KGDB I/O module are built
647 * into the kernel and you are using early debugging with
648 * kgdbwait. KGDB will control the kernel HW breakpoint registers.
650 if (kgdb_connected
&& arch_kgdb_ops
.correct_hw_break
)
651 arch_kgdb_ops
.correct_hw_break();
655 * Clear all 6 debug registers:
658 set_debugreg(0UL, 0);
659 set_debugreg(0UL, 1);
660 set_debugreg(0UL, 2);
661 set_debugreg(0UL, 3);
662 set_debugreg(0UL, 6);
663 set_debugreg(0UL, 7);
665 /* If the kgdb is connected no debug regs should be altered. */
671 raw_local_save_flags(kernel_eflags
);