2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/interrupt.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/kernel_stat.h>
25 #include <linux/sysdev.h>
26 #include <linux/ioport.h>
27 #include <linux/clockchips.h>
28 #include <linux/acpi_pmtmr.h>
29 #include <linux/module.h>
30 #include <linux/dmar.h>
32 #include <asm/atomic.h>
35 #include <asm/mpspec.h>
37 #include <asm/pgalloc.h>
40 #include <asm/proto.h>
41 #include <asm/timex.h>
43 #include <asm/i8259.h>
46 #include <mach_apic.h>
48 static int disable_apic_timer __cpuinitdata
;
49 static int apic_calibrate_pmtmr __initdata
;
54 /* x2apic enabled before OS handover */
55 int x2apic_preenabled
;
57 /* Local APIC timer works in C2 */
58 int local_apic_timer_c2_ok
;
59 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok
);
62 * Debug level, exported for io_apic.c
64 unsigned int apic_verbosity
;
66 /* Have we found an MP table */
69 static struct resource lapic_resource
= {
71 .flags
= IORESOURCE_MEM
| IORESOURCE_BUSY
,
74 static unsigned int calibration_result
;
76 static int lapic_next_event(unsigned long delta
,
77 struct clock_event_device
*evt
);
78 static void lapic_timer_setup(enum clock_event_mode mode
,
79 struct clock_event_device
*evt
);
80 static void lapic_timer_broadcast(cpumask_t mask
);
81 static void apic_pm_activate(void);
83 static struct clock_event_device lapic_clockevent
= {
85 .features
= CLOCK_EVT_FEAT_PERIODIC
| CLOCK_EVT_FEAT_ONESHOT
86 | CLOCK_EVT_FEAT_C3STOP
| CLOCK_EVT_FEAT_DUMMY
,
88 .set_mode
= lapic_timer_setup
,
89 .set_next_event
= lapic_next_event
,
90 .broadcast
= lapic_timer_broadcast
,
94 static DEFINE_PER_CPU(struct clock_event_device
, lapic_events
);
96 static unsigned long apic_phys
;
98 unsigned long mp_lapic_addr
;
100 unsigned int __cpuinitdata maxcpus
= NR_CPUS
;
102 * Get the LAPIC version
104 static inline int lapic_get_version(void)
106 return GET_APIC_VERSION(apic_read(APIC_LVR
));
110 * Check, if the APIC is integrated or a seperate chip
112 static inline int lapic_is_integrated(void)
118 * Check, whether this is a modern or a first generation APIC
120 static int modern_apic(void)
122 /* AMD systems use old APIC versions, so check the CPU */
123 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
124 boot_cpu_data
.x86
>= 0xf)
126 return lapic_get_version() >= 0x14;
129 void xapic_wait_icr_idle(void)
131 while (apic_read(APIC_ICR
) & APIC_ICR_BUSY
)
135 u32
safe_xapic_wait_icr_idle(void)
142 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
146 } while (timeout
++ < 1000);
151 void xapic_icr_write(u32 low
, u32 id
)
153 apic_write(APIC_ICR2
, id
<< 24);
154 apic_write(APIC_ICR
, low
);
157 u64
xapic_icr_read(void)
161 icr2
= apic_read(APIC_ICR2
);
162 icr1
= apic_read(APIC_ICR
);
164 return (icr1
| ((u64
)icr2
<< 32));
167 static struct apic_ops xapic_ops
= {
168 .read
= native_apic_mem_read
,
169 .write
= native_apic_mem_write
,
170 .icr_read
= xapic_icr_read
,
171 .icr_write
= xapic_icr_write
,
172 .wait_icr_idle
= xapic_wait_icr_idle
,
173 .safe_wait_icr_idle
= safe_xapic_wait_icr_idle
,
176 struct apic_ops __read_mostly
*apic_ops
= &xapic_ops
;
178 EXPORT_SYMBOL_GPL(apic_ops
);
180 static void x2apic_wait_icr_idle(void)
182 /* no need to wait for icr idle in x2apic */
186 static u32
safe_x2apic_wait_icr_idle(void)
188 /* no need to wait for icr idle in x2apic */
192 void x2apic_icr_write(u32 low
, u32 id
)
194 wrmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), ((__u64
) id
) << 32 | low
);
197 u64
x2apic_icr_read(void)
201 rdmsrl(APIC_BASE_MSR
+ (APIC_ICR
>> 4), val
);
205 static struct apic_ops x2apic_ops
= {
206 .read
= native_apic_msr_read
,
207 .write
= native_apic_msr_write
,
208 .icr_read
= x2apic_icr_read
,
209 .icr_write
= x2apic_icr_write
,
210 .wait_icr_idle
= x2apic_wait_icr_idle
,
211 .safe_wait_icr_idle
= safe_x2apic_wait_icr_idle
,
215 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
217 void __cpuinit
enable_NMI_through_LVT0(void)
221 /* unmask and set to NMI */
223 apic_write(APIC_LVT0
, v
);
227 * lapic_get_maxlvt - get the maximum number of local vector table entries
229 int lapic_get_maxlvt(void)
231 unsigned int v
, maxlvt
;
233 v
= apic_read(APIC_LVR
);
234 maxlvt
= GET_APIC_MAXLVT(v
);
239 * This function sets up the local APIC timer, with a timeout of
240 * 'clocks' APIC bus clock. During calibration we actually call
241 * this function twice on the boot CPU, once with a bogus timeout
242 * value, second time for real. The other (noncalibrating) CPUs
243 * call this function only once, with the real, calibrated value.
245 * We do reads before writes even if unnecessary, to get around the
246 * P5 APIC double write bug.
249 static void __setup_APIC_LVTT(unsigned int clocks
, int oneshot
, int irqen
)
251 unsigned int lvtt_value
, tmp_value
;
253 lvtt_value
= LOCAL_TIMER_VECTOR
;
255 lvtt_value
|= APIC_LVT_TIMER_PERIODIC
;
257 lvtt_value
|= APIC_LVT_MASKED
;
259 apic_write(APIC_LVTT
, lvtt_value
);
264 tmp_value
= apic_read(APIC_TDCR
);
265 apic_write(APIC_TDCR
, (tmp_value
266 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
270 apic_write(APIC_TMICT
, clocks
);
274 * Setup extended LVT, AMD specific (K8, family 10h)
276 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
277 * MCE interrupts are supported. Thus MCE offset must be set to 0.
280 #define APIC_EILVT_LVTOFF_MCE 0
281 #define APIC_EILVT_LVTOFF_IBS 1
283 static void setup_APIC_eilvt(u8 lvt_off
, u8 vector
, u8 msg_type
, u8 mask
)
285 unsigned long reg
= (lvt_off
<< 4) + APIC_EILVT0
;
286 unsigned int v
= (mask
<< 16) | (msg_type
<< 8) | vector
;
291 u8
setup_APIC_eilvt_mce(u8 vector
, u8 msg_type
, u8 mask
)
293 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE
, vector
, msg_type
, mask
);
294 return APIC_EILVT_LVTOFF_MCE
;
297 u8
setup_APIC_eilvt_ibs(u8 vector
, u8 msg_type
, u8 mask
)
299 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS
, vector
, msg_type
, mask
);
300 return APIC_EILVT_LVTOFF_IBS
;
304 * Program the next event, relative to now
306 static int lapic_next_event(unsigned long delta
,
307 struct clock_event_device
*evt
)
309 apic_write(APIC_TMICT
, delta
);
314 * Setup the lapic timer in periodic or oneshot mode
316 static void lapic_timer_setup(enum clock_event_mode mode
,
317 struct clock_event_device
*evt
)
322 /* Lapic used as dummy for broadcast ? */
323 if (evt
->features
& CLOCK_EVT_FEAT_DUMMY
)
326 local_irq_save(flags
);
329 case CLOCK_EVT_MODE_PERIODIC
:
330 case CLOCK_EVT_MODE_ONESHOT
:
331 __setup_APIC_LVTT(calibration_result
,
332 mode
!= CLOCK_EVT_MODE_PERIODIC
, 1);
334 case CLOCK_EVT_MODE_UNUSED
:
335 case CLOCK_EVT_MODE_SHUTDOWN
:
336 v
= apic_read(APIC_LVTT
);
337 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
338 apic_write(APIC_LVTT
, v
);
340 case CLOCK_EVT_MODE_RESUME
:
341 /* Nothing to do here */
345 local_irq_restore(flags
);
349 * Local APIC timer broadcast function
351 static void lapic_timer_broadcast(cpumask_t mask
)
354 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
359 * Setup the local APIC timer for this CPU. Copy the initilized values
360 * of the boot CPU and register the clock event in the framework.
362 static void setup_APIC_timer(void)
364 struct clock_event_device
*levt
= &__get_cpu_var(lapic_events
);
366 memcpy(levt
, &lapic_clockevent
, sizeof(*levt
));
367 levt
->cpumask
= cpumask_of_cpu(smp_processor_id());
369 clockevents_register_device(levt
);
373 * In this function we calibrate APIC bus clocks to the external
374 * timer. Unfortunately we cannot use jiffies and the timer irq
375 * to calibrate, since some later bootup code depends on getting
376 * the first irq? Ugh.
378 * We want to do the calibration only once since we
379 * want to have local timer irqs syncron. CPUs connected
380 * by the same APIC bus have the very same bus frequency.
381 * And we want to have irqs off anyways, no accidental
385 #define TICK_COUNT 100000000
387 static int __init
calibrate_APIC_clock(void)
389 unsigned apic
, apic_start
;
390 unsigned long tsc
, tsc_start
;
396 * Put whatever arbitrary (but long enough) timeout
397 * value into the APIC clock, we just want to get the
398 * counter running for calibration.
400 * No interrupt enable !
402 __setup_APIC_LVTT(250000000, 0, 0);
404 apic_start
= apic_read(APIC_TMCCT
);
405 #ifdef CONFIG_X86_PM_TIMER
406 if (apic_calibrate_pmtmr
&& pmtmr_ioport
) {
407 pmtimer_wait(5000); /* 5ms wait */
408 apic
= apic_read(APIC_TMCCT
);
409 result
= (apic_start
- apic
) * 1000L / 5;
416 apic
= apic_read(APIC_TMCCT
);
418 } while ((tsc
- tsc_start
) < TICK_COUNT
&&
419 (apic_start
- apic
) < TICK_COUNT
);
421 result
= (apic_start
- apic
) * 1000L * tsc_khz
/
427 printk(KERN_DEBUG
"APIC timer calibration result %d\n", result
);
429 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
430 result
/ 1000 / 1000, result
/ 1000 % 1000);
432 /* Calculate the scaled math multiplication factor */
433 lapic_clockevent
.mult
= div_sc(result
, NSEC_PER_SEC
,
434 lapic_clockevent
.shift
);
435 lapic_clockevent
.max_delta_ns
=
436 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent
);
437 lapic_clockevent
.min_delta_ns
=
438 clockevent_delta2ns(0xF, &lapic_clockevent
);
440 calibration_result
= result
/ HZ
;
443 * Do a sanity check on the APIC calibration result
445 if (calibration_result
< (1000000 / HZ
)) {
447 "APIC frequency too slow, disabling apic timer\n");
455 * Setup the boot APIC
457 * Calibrate and verify the result.
459 void __init
setup_boot_APIC_clock(void)
462 * The local apic timer can be disabled via the kernel commandline.
463 * Register the lapic timer as a dummy clock event source on SMP
464 * systems, so the broadcast mechanism is used. On UP systems simply
467 if (disable_apic_timer
) {
468 printk(KERN_INFO
"Disabling APIC timer\n");
469 /* No broadcast on UP ! */
470 if (num_possible_cpus() > 1) {
471 lapic_clockevent
.mult
= 1;
477 printk(KERN_INFO
"Using local APIC timer interrupts.\n");
478 if (calibrate_APIC_clock()) {
479 /* No broadcast on UP ! */
480 if (num_possible_cpus() > 1)
486 * If nmi_watchdog is set to IO_APIC, we need the
487 * PIT/HPET going. Otherwise register lapic as a dummy
490 if (nmi_watchdog
!= NMI_IO_APIC
)
491 lapic_clockevent
.features
&= ~CLOCK_EVT_FEAT_DUMMY
;
493 printk(KERN_WARNING
"APIC timer registered as dummy,"
494 " due to nmi_watchdog=%d!\n", nmi_watchdog
);
499 void __cpuinit
setup_secondary_APIC_clock(void)
505 * The guts of the apic timer interrupt
507 static void local_apic_timer_interrupt(void)
509 int cpu
= smp_processor_id();
510 struct clock_event_device
*evt
= &per_cpu(lapic_events
, cpu
);
513 * Normally we should not be here till LAPIC has been initialized but
514 * in some cases like kdump, its possible that there is a pending LAPIC
515 * timer interrupt from previous kernel's context and is delivered in
516 * new kernel the moment interrupts are enabled.
518 * Interrupts are enabled early and LAPIC is setup much later, hence
519 * its possible that when we get here evt->event_handler is NULL.
520 * Check for event_handler being NULL and discard the interrupt as
523 if (!evt
->event_handler
) {
525 "Spurious LAPIC timer interrupt on cpu %d\n", cpu
);
527 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN
, evt
);
532 * the NMI deadlock-detector uses this.
534 add_pda(apic_timer_irqs
, 1);
536 evt
->event_handler(evt
);
540 * Local APIC timer interrupt. This is the most natural way for doing
541 * local interrupts, but local timer interrupts can be emulated by
542 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
544 * [ if a single-CPU system runs an SMP kernel then we call the local
545 * interrupt as well. Thus we cannot inline the local irq ... ]
547 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
549 struct pt_regs
*old_regs
= set_irq_regs(regs
);
552 * NOTE! We'd better ACK the irq immediately,
553 * because timer handling can be slow.
557 * update_process_times() expects us to have done irq_enter().
558 * Besides, if we don't timer interrupts ignore the global
559 * interrupt lock, which is the WrongThing (tm) to do.
563 local_apic_timer_interrupt();
565 set_irq_regs(old_regs
);
568 int setup_profiling_timer(unsigned int multiplier
)
575 * Local APIC start and shutdown
579 * clear_local_APIC - shutdown the local APIC
581 * This is called, when a CPU is disabled and before rebooting, so the state of
582 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
583 * leftovers during boot.
585 void clear_local_APIC(void)
590 /* APIC hasn't been mapped yet */
594 maxlvt
= lapic_get_maxlvt();
596 * Masking an LVT entry can trigger a local APIC error
597 * if the vector is zero. Mask LVTERR first to prevent this.
600 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
601 apic_write(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
604 * Careful: we have to set masks only first to deassert
605 * any level-triggered sources.
607 v
= apic_read(APIC_LVTT
);
608 apic_write(APIC_LVTT
, v
| APIC_LVT_MASKED
);
609 v
= apic_read(APIC_LVT0
);
610 apic_write(APIC_LVT0
, v
| APIC_LVT_MASKED
);
611 v
= apic_read(APIC_LVT1
);
612 apic_write(APIC_LVT1
, v
| APIC_LVT_MASKED
);
614 v
= apic_read(APIC_LVTPC
);
615 apic_write(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
619 * Clean APIC state for other OSs:
621 apic_write(APIC_LVTT
, APIC_LVT_MASKED
);
622 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
623 apic_write(APIC_LVT1
, APIC_LVT_MASKED
);
625 apic_write(APIC_LVTERR
, APIC_LVT_MASKED
);
627 apic_write(APIC_LVTPC
, APIC_LVT_MASKED
);
628 apic_write(APIC_ESR
, 0);
633 * disable_local_APIC - clear and disable the local APIC
635 void disable_local_APIC(void)
642 * Disable APIC (implies clearing of registers
645 value
= apic_read(APIC_SPIV
);
646 value
&= ~APIC_SPIV_APIC_ENABLED
;
647 apic_write(APIC_SPIV
, value
);
650 void lapic_shutdown(void)
657 local_irq_save(flags
);
659 disable_local_APIC();
661 local_irq_restore(flags
);
665 * This is to verify that we're looking at a real local APIC.
666 * Check these against your board if the CPUs aren't getting
667 * started for no apparent reason.
669 int __init
verify_local_APIC(void)
671 unsigned int reg0
, reg1
;
674 * The version register is read-only in a real APIC.
676 reg0
= apic_read(APIC_LVR
);
677 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
678 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
679 reg1
= apic_read(APIC_LVR
);
680 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
683 * The two version reads above should print the same
684 * numbers. If the second one is different, then we
685 * poke at a non-APIC.
691 * Check if the version looks reasonably.
693 reg1
= GET_APIC_VERSION(reg0
);
694 if (reg1
== 0x00 || reg1
== 0xff)
696 reg1
= lapic_get_maxlvt();
697 if (reg1
< 0x02 || reg1
== 0xff)
701 * The ID register is read/write in a real APIC.
703 reg0
= apic_read(APIC_ID
);
704 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
705 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
706 reg1
= apic_read(APIC_ID
);
707 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
708 apic_write(APIC_ID
, reg0
);
709 if (reg1
!= (reg0
^ APIC_ID_MASK
))
713 * The next two are just to see if we have sane values.
714 * They're only really relevant if we're in Virtual Wire
715 * compatibility mode, but most boxes are anymore.
717 reg0
= apic_read(APIC_LVT0
);
718 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
719 reg1
= apic_read(APIC_LVT1
);
720 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
726 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
728 void __init
sync_Arb_IDs(void)
730 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
737 apic_wait_icr_idle();
739 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
740 apic_write(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
745 * An initial setup of the virtual wire mode.
747 void __init
init_bsp_APIC(void)
752 * Don't do the setup now if we have a SMP BIOS as the
753 * through-I/O-APIC virtual wire mode might be active.
755 if (smp_found_config
|| !cpu_has_apic
)
758 value
= apic_read(APIC_LVR
);
761 * Do not trust the local APIC being empty at bootup.
768 value
= apic_read(APIC_SPIV
);
769 value
&= ~APIC_VECTOR_MASK
;
770 value
|= APIC_SPIV_APIC_ENABLED
;
771 value
|= APIC_SPIV_FOCUS_DISABLED
;
772 value
|= SPURIOUS_APIC_VECTOR
;
773 apic_write(APIC_SPIV
, value
);
776 * Set up the virtual wire mode.
778 apic_write(APIC_LVT0
, APIC_DM_EXTINT
);
780 apic_write(APIC_LVT1
, value
);
784 * setup_local_APIC - setup the local APIC
786 void __cpuinit
setup_local_APIC(void)
792 value
= apic_read(APIC_LVR
);
794 BUILD_BUG_ON((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f);
797 * Double-check whether this APIC is really registered.
798 * This is meaningless in clustered apic mode, so we skip it.
800 if (!apic_id_registered())
804 * Intel recommends to set DFR, LDR and TPR before enabling
805 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
806 * document number 292116). So here it goes...
811 * Set Task Priority to 'accept all'. We never change this
814 value
= apic_read(APIC_TASKPRI
);
815 value
&= ~APIC_TPRI_MASK
;
816 apic_write(APIC_TASKPRI
, value
);
819 * After a crash, we no longer service the interrupts and a pending
820 * interrupt from previous kernel might still have ISR bit set.
822 * Most probably by now CPU has serviced that pending interrupt and
823 * it might not have done the ack_APIC_irq() because it thought,
824 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
825 * does not clear the ISR bit and cpu thinks it has already serivced
826 * the interrupt. Hence a vector might get locked. It was noticed
827 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
829 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
830 value
= apic_read(APIC_ISR
+ i
*0x10);
831 for (j
= 31; j
>= 0; j
--) {
838 * Now that we are all set up, enable the APIC
840 value
= apic_read(APIC_SPIV
);
841 value
&= ~APIC_VECTOR_MASK
;
845 value
|= APIC_SPIV_APIC_ENABLED
;
847 /* We always use processor focus */
850 * Set spurious IRQ vector
852 value
|= SPURIOUS_APIC_VECTOR
;
853 apic_write(APIC_SPIV
, value
);
858 * set up through-local-APIC on the BP's LINT0. This is not
859 * strictly necessary in pure symmetric-IO mode, but sometimes
860 * we delegate interrupts to the 8259A.
863 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
865 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
866 if (!smp_processor_id() && !value
) {
867 value
= APIC_DM_EXTINT
;
868 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
871 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
872 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
875 apic_write(APIC_LVT0
, value
);
878 * only the BP should see the LINT1 NMI signal, obviously.
880 if (!smp_processor_id())
883 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
884 apic_write(APIC_LVT1
, value
);
888 static void __cpuinit
lapic_setup_esr(void)
890 unsigned maxlvt
= lapic_get_maxlvt();
892 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
);
894 * spec says clear errors after enabling vector.
897 apic_write(APIC_ESR
, 0);
900 void __cpuinit
end_local_APIC_setup(void)
903 setup_apic_nmi_watchdog(NULL
);
907 void check_x2apic(void)
911 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
913 if (msr
& X2APIC_ENABLE
) {
914 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
915 x2apic_preenabled
= x2apic
= 1;
916 apic_ops
= &x2apic_ops
;
920 void enable_x2apic(void)
924 rdmsr(MSR_IA32_APICBASE
, msr
, msr2
);
925 if (!(msr
& X2APIC_ENABLE
)) {
926 printk("Enabling x2apic\n");
927 wrmsr(MSR_IA32_APICBASE
, msr
| X2APIC_ENABLE
, 0);
931 void enable_IR_x2apic(void)
933 #ifdef CONFIG_INTR_REMAP
940 if (!x2apic_preenabled
&& disable_x2apic
) {
942 "Skipped enabling x2apic and Interrupt-remapping "
943 "because of nox2apic\n");
947 if (x2apic_preenabled
&& disable_x2apic
)
948 panic("Bios already enabled x2apic, can't enforce nox2apic");
950 if (!x2apic_preenabled
&& skip_ioapic_setup
) {
952 "Skipped enabling x2apic and Interrupt-remapping "
953 "because of skipping io-apic setup\n");
957 ret
= dmar_table_init();
960 "dmar_table_init() failed with %d:\n", ret
);
962 if (x2apic_preenabled
)
963 panic("x2apic enabled by bios. But IR enabling failed");
966 "Not enabling x2apic,Intr-remapping\n");
970 local_irq_save(flags
);
972 save_mask_IO_APIC_setup();
974 ret
= enable_intr_remapping(1);
976 if (ret
&& x2apic_preenabled
) {
977 local_irq_restore(flags
);
978 panic("x2apic enabled by bios. But IR enabling failed");
986 apic_ops
= &x2apic_ops
;
994 restore_IO_APIC_setup();
996 reinit_intr_remapped_IO_APIC(x2apic_preenabled
);
999 local_irq_restore(flags
);
1002 if (!x2apic_preenabled
)
1004 "Enabled x2apic and interrupt-remapping\n");
1007 "Enabled Interrupt-remapping\n");
1010 "Failed to enable Interrupt-remapping and x2apic\n");
1012 if (!cpu_has_x2apic
)
1015 if (x2apic_preenabled
)
1016 panic("x2apic enabled prior OS handover,"
1017 " enable CONFIG_INTR_REMAP");
1019 printk(KERN_INFO
"Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1027 * Detect and enable local APICs on non-SMP boards.
1028 * Original code written by Keir Fraser.
1029 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1030 * not correctly set up (usually the APIC timer won't work etc.)
1032 static int __init
detect_init_APIC(void)
1034 if (!cpu_has_apic
) {
1035 printk(KERN_INFO
"No local APIC present\n");
1039 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
1040 boot_cpu_physical_apicid
= 0;
1044 void __init
early_init_lapic_mapping(void)
1046 unsigned long phys_addr
;
1049 * If no local APIC can be found then go out
1050 * : it means there is no mpatable and MADT
1052 if (!smp_found_config
)
1055 phys_addr
= mp_lapic_addr
;
1057 set_fixmap_nocache(FIX_APIC_BASE
, phys_addr
);
1058 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1059 APIC_BASE
, phys_addr
);
1062 * Fetch the APIC ID of the BSP in case we have a
1063 * default configuration (or the MP table is broken).
1065 boot_cpu_physical_apicid
= read_apic_id();
1069 * init_apic_mappings - initialize APIC mappings
1071 void __init
init_apic_mappings(void)
1074 boot_cpu_physical_apicid
= read_apic_id();
1079 * If no local APIC can be found then set up a fake all
1080 * zeroes page to simulate the local APIC and another
1081 * one for the IO-APIC.
1083 if (!smp_found_config
&& detect_init_APIC()) {
1084 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
1085 apic_phys
= __pa(apic_phys
);
1087 apic_phys
= mp_lapic_addr
;
1089 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
1090 apic_printk(APIC_VERBOSE
, "mapped APIC to %16lx (%16lx)\n",
1091 APIC_BASE
, apic_phys
);
1094 * Fetch the APIC ID of the BSP in case we have a
1095 * default configuration (or the MP table is broken).
1097 boot_cpu_physical_apicid
= read_apic_id();
1101 * This initializes the IO-APIC and APIC hardware if this is
1104 int __init
APIC_init_uniprocessor(void)
1107 printk(KERN_INFO
"Apic disabled\n");
1110 if (!cpu_has_apic
) {
1112 printk(KERN_INFO
"Apic disabled by BIOS\n");
1117 setup_apic_routing();
1119 verify_local_APIC();
1123 physid_set_mask_of_physid(boot_cpu_physical_apicid
, &phys_cpu_present_map
);
1124 apic_write(APIC_ID
, SET_APIC_ID(boot_cpu_physical_apicid
));
1129 * Now enable IO-APICs, actually call clear_IO_APIC
1130 * We need clear_IO_APIC before enabling vector on BP
1132 if (!skip_ioapic_setup
&& nr_ioapics
)
1135 if (!smp_found_config
|| skip_ioapic_setup
|| !nr_ioapics
)
1136 localise_nmi_watchdog();
1137 end_local_APIC_setup();
1139 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1143 setup_boot_APIC_clock();
1144 check_nmi_watchdog();
1149 * Local APIC interrupts
1153 * This interrupt should _never_ happen with our APIC/SMP architecture
1155 asmlinkage
void smp_spurious_interrupt(void)
1161 * Check if this really is a spurious interrupt and ACK it
1162 * if it is a vectored one. Just in case...
1163 * Spurious interrupts should not be ACKed.
1165 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1166 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1169 add_pda(irq_spurious_count
, 1);
1174 * This interrupt should never happen with our APIC/SMP architecture
1176 asmlinkage
void smp_error_interrupt(void)
1182 /* First tickle the hardware, only then report what went on. -- REW */
1183 v
= apic_read(APIC_ESR
);
1184 apic_write(APIC_ESR
, 0);
1185 v1
= apic_read(APIC_ESR
);
1187 atomic_inc(&irq_err_count
);
1189 /* Here is what the APIC error bits mean:
1192 2: Send accept error
1193 3: Receive accept error
1195 5: Send illegal vector
1196 6: Received illegal vector
1197 7: Illegal register address
1199 printk(KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1200 smp_processor_id(), v
, v1
);
1205 * * connect_bsp_APIC - attach the APIC to the interrupt system
1207 void __init
connect_bsp_APIC(void)
1212 void disconnect_bsp_APIC(int virt_wire_setup
)
1214 /* Go back to Virtual Wire compatibility mode */
1215 unsigned long value
;
1217 /* For the spurious interrupt use vector F, and enable it */
1218 value
= apic_read(APIC_SPIV
);
1219 value
&= ~APIC_VECTOR_MASK
;
1220 value
|= APIC_SPIV_APIC_ENABLED
;
1222 apic_write(APIC_SPIV
, value
);
1224 if (!virt_wire_setup
) {
1226 * For LVT0 make it edge triggered, active high,
1227 * external and enabled
1229 value
= apic_read(APIC_LVT0
);
1230 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1231 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1232 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1233 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1234 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
1235 apic_write(APIC_LVT0
, value
);
1238 apic_write(APIC_LVT0
, APIC_LVT_MASKED
);
1241 /* For LVT1 make it edge triggered, active high, nmi and enabled */
1242 value
= apic_read(APIC_LVT1
);
1243 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
1244 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
1245 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
1246 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
1247 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
1248 apic_write(APIC_LVT1
, value
);
1251 void __cpuinit
generic_processor_info(int apicid
, int version
)
1256 if (num_processors
>= NR_CPUS
) {
1257 printk(KERN_WARNING
"WARNING: NR_CPUS limit of %i reached."
1258 " Processor ignored.\n", NR_CPUS
);
1262 if (num_processors
>= maxcpus
) {
1263 printk(KERN_WARNING
"WARNING: maxcpus limit of %i reached."
1264 " Processor ignored.\n", maxcpus
);
1269 cpus_complement(tmp_map
, cpu_present_map
);
1270 cpu
= first_cpu(tmp_map
);
1272 physid_set(apicid
, phys_cpu_present_map
);
1273 if (apicid
== boot_cpu_physical_apicid
) {
1275 * x86_bios_cpu_apicid is required to have processors listed
1276 * in same order as logical cpu numbers. Hence the first
1277 * entry is BSP, and so on.
1281 if (apicid
> max_physical_apicid
)
1282 max_physical_apicid
= apicid
;
1284 /* are we being called early in kernel startup? */
1285 if (early_per_cpu_ptr(x86_cpu_to_apicid
)) {
1286 u16
*cpu_to_apicid
= early_per_cpu_ptr(x86_cpu_to_apicid
);
1287 u16
*bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1289 cpu_to_apicid
[cpu
] = apicid
;
1290 bios_cpu_apicid
[cpu
] = apicid
;
1292 per_cpu(x86_cpu_to_apicid
, cpu
) = apicid
;
1293 per_cpu(x86_bios_cpu_apicid
, cpu
) = apicid
;
1296 cpu_set(cpu
, cpu_possible_map
);
1297 cpu_set(cpu
, cpu_present_map
);
1300 int hard_smp_processor_id(void)
1302 return read_apic_id();
1311 /* 'active' is true if the local APIC was enabled by us and
1312 not the BIOS; this signifies that we are also responsible
1313 for disabling it before entering apm/acpi suspend */
1315 /* r/w apic fields */
1316 unsigned int apic_id
;
1317 unsigned int apic_taskpri
;
1318 unsigned int apic_ldr
;
1319 unsigned int apic_dfr
;
1320 unsigned int apic_spiv
;
1321 unsigned int apic_lvtt
;
1322 unsigned int apic_lvtpc
;
1323 unsigned int apic_lvt0
;
1324 unsigned int apic_lvt1
;
1325 unsigned int apic_lvterr
;
1326 unsigned int apic_tmict
;
1327 unsigned int apic_tdcr
;
1328 unsigned int apic_thmr
;
1331 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
1333 unsigned long flags
;
1336 if (!apic_pm_state
.active
)
1339 maxlvt
= lapic_get_maxlvt();
1341 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
1342 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
1343 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
1344 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
1345 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
1346 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
1348 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
1349 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
1350 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
1351 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
1352 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
1353 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
1354 #ifdef CONFIG_X86_MCE_INTEL
1356 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
1358 local_irq_save(flags
);
1359 disable_local_APIC();
1360 local_irq_restore(flags
);
1364 static int lapic_resume(struct sys_device
*dev
)
1367 unsigned long flags
;
1370 if (!apic_pm_state
.active
)
1373 maxlvt
= lapic_get_maxlvt();
1375 local_irq_save(flags
);
1377 rdmsr(MSR_IA32_APICBASE
, l
, h
);
1378 l
&= ~MSR_IA32_APICBASE_BASE
;
1379 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
1380 wrmsr(MSR_IA32_APICBASE
, l
, h
);
1384 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
1385 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
1386 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
1387 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
1388 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
1389 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
1390 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
1391 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
1392 #ifdef CONFIG_X86_MCE_INTEL
1394 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
1397 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
1398 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
1399 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
1400 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
1401 apic_write(APIC_ESR
, 0);
1402 apic_read(APIC_ESR
);
1403 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
1404 apic_write(APIC_ESR
, 0);
1405 apic_read(APIC_ESR
);
1406 local_irq_restore(flags
);
1410 static struct sysdev_class lapic_sysclass
= {
1412 .resume
= lapic_resume
,
1413 .suspend
= lapic_suspend
,
1416 static struct sys_device device_lapic
= {
1418 .cls
= &lapic_sysclass
,
1421 static void __cpuinit
apic_pm_activate(void)
1423 apic_pm_state
.active
= 1;
1426 static int __init
init_lapic_sysfs(void)
1432 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
1434 error
= sysdev_class_register(&lapic_sysclass
);
1436 error
= sysdev_register(&device_lapic
);
1439 device_initcall(init_lapic_sysfs
);
1441 #else /* CONFIG_PM */
1443 static void apic_pm_activate(void) { }
1445 #endif /* CONFIG_PM */
1448 * apic_is_clustered_box() -- Check if we can expect good TSC
1450 * Thus far, the major user of this is IBM's Summit2 series:
1452 * Clustered boxes may have unsynced TSC problems if they are
1453 * multi-chassis. Use available data to take a good guess.
1454 * If in doubt, go HPET.
1456 __cpuinit
int apic_is_clustered_box(void)
1458 int i
, clusters
, zeros
;
1460 u16
*bios_cpu_apicid
;
1461 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
1464 * there is not this kind of box with AMD CPU yet.
1465 * Some AMD box with quadcore cpu and 8 sockets apicid
1466 * will be [4, 0x23] or [8, 0x27] could be thought to
1467 * vsmp box still need checking...
1469 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
) && !is_vsmp_box())
1472 bios_cpu_apicid
= early_per_cpu_ptr(x86_bios_cpu_apicid
);
1473 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
1475 for (i
= 0; i
< NR_CPUS
; i
++) {
1476 /* are we being called early in kernel startup? */
1477 if (bios_cpu_apicid
) {
1478 id
= bios_cpu_apicid
[i
];
1480 else if (i
< nr_cpu_ids
) {
1482 id
= per_cpu(x86_bios_cpu_apicid
, i
);
1489 if (id
!= BAD_APICID
)
1490 __set_bit(APIC_CLUSTERID(id
), clustermap
);
1493 /* Problem: Partially populated chassis may not have CPUs in some of
1494 * the APIC clusters they have been allocated. Only present CPUs have
1495 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
1496 * Since clusters are allocated sequentially, count zeros only if
1497 * they are bounded by ones.
1501 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
1502 if (test_bit(i
, clustermap
)) {
1503 clusters
+= 1 + zeros
;
1509 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
1510 * not guaranteed to be synced between boards
1512 if (is_vsmp_box() && clusters
> 1)
1516 * If clusters > 2, then should be multi-chassis.
1517 * May have to revisit this when multi-core + hyperthreaded CPUs come
1518 * out, but AFAIK this will work even for them.
1520 return (clusters
> 2);
1523 static __init
int setup_nox2apic(char *str
)
1526 clear_cpu_cap(&boot_cpu_data
, X86_FEATURE_X2APIC
);
1529 early_param("nox2apic", setup_nox2apic
);
1533 * APIC command line parameters
1535 static int __init
apic_set_verbosity(char *str
)
1538 skip_ioapic_setup
= 0;
1542 if (strcmp("debug", str
) == 0)
1543 apic_verbosity
= APIC_DEBUG
;
1544 else if (strcmp("verbose", str
) == 0)
1545 apic_verbosity
= APIC_VERBOSE
;
1547 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
1548 " use apic=verbose or apic=debug\n", str
);
1554 early_param("apic", apic_set_verbosity
);
1556 static __init
int setup_disableapic(char *str
)
1559 setup_clear_cpu_cap(X86_FEATURE_APIC
);
1562 early_param("disableapic", setup_disableapic
);
1564 /* same as disableapic, for compatibility */
1565 static __init
int setup_nolapic(char *str
)
1567 return setup_disableapic(str
);
1569 early_param("nolapic", setup_nolapic
);
1571 static int __init
parse_lapic_timer_c2_ok(char *arg
)
1573 local_apic_timer_c2_ok
= 1;
1576 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok
);
1578 static __init
int setup_noapictimer(char *str
)
1580 if (str
[0] != ' ' && str
[0] != 0)
1582 disable_apic_timer
= 1;
1585 __setup("noapictimer", setup_noapictimer
);
1587 static __init
int setup_apicpmtimer(char *s
)
1589 apic_calibrate_pmtmr
= 1;
1593 __setup("apicpmtimer", setup_apicpmtimer
);
1595 static int __init
lapic_insert_resource(void)
1600 /* Put local APIC into the resource map. */
1601 lapic_resource
.start
= apic_phys
;
1602 lapic_resource
.end
= lapic_resource
.start
+ PAGE_SIZE
- 1;
1603 insert_resource(&iomem_resource
, &lapic_resource
);
1609 * need call insert after e820_reserve_resources()
1610 * that is using request_resource
1612 late_initcall(lapic_insert_resource
);