2 * Copyright (C) 2004, 2005 MIPS Technologies, Inc. All rights reserved.
11 #define LX_NODE_BASE 10
13 #define MIPS_CPU_RTLX_IRQ 0
15 #define RTLX_VERSION 2
16 #define RTLX_xID 0x12345600
17 #define RTLX_ID (RTLX_xID | RTLX_VERSION)
18 #define RTLX_CHANNELS 8
20 #define RTLX_CHANNEL_STDIO 0
21 #define RTLX_CHANNEL_DBG 1
22 #define RTLX_CHANNEL_SYSIO 2
24 extern int rtlx_open(int index
, int can_sleep
);
25 extern int rtlx_release(int index
);
26 extern ssize_t
rtlx_read(int index
, void __user
*buff
, size_t count
);
27 extern ssize_t
rtlx_write(int index
, const void __user
*buffer
, size_t count
);
28 extern unsigned int rtlx_read_poll(int index
, int can_sleep
);
29 extern unsigned int rtlx_write_poll(int index
);
33 RTLX_STATE_INITIALISED
,
34 RTLX_STATE_REMOTE_READY
,
38 #define RTLX_BUFFER_SIZE 1024
40 /* each channel supports read and write.
41 linux (vpe0) reads lx_buffer and writes rt_buffer
42 SP (vpe1) reads rt_buffer and writes lx_buffer
45 enum rtlx_state rt_state
;
46 enum rtlx_state lx_state
;
50 /* read and write indexes per buffer */
51 int rt_write
, rt_read
;
54 int lx_write
, lx_read
;
60 enum rtlx_state state
;
62 struct rtlx_channel channel
[RTLX_CHANNELS
];
65 #endif /* __ASM_RTLX_H_ */